A chip, a communication system and a communication method

Abstract

The present application provides a chip, a communication system, and a communication method. The communication method includes the following steps: the chip shakes hands with the opposite chip to establish a transmission link; when a data transmission error is detected, the transmission link is controlled to enter a repair state; in the repair state, data is repaired on the transmission link, and the matching parameters of the ports at both ends of the transmission link when the data transmission state is achieved are corrected; after the transmission link repair is completed, the transmission link is controlled to enter a low power consumption state. In the above scheme, by setting the repair state, the transmission link is repaired when a data transmission failure occurs, thereby improving the reliability of data transmission. In addition, during the repair, only the matching parameters corresponding to the data transmission are repaired, and there is no need to match the basic information of the two chips during the handshake again, thereby improving the repair effect.

Description

[0001] The present application claims priority to the Chinese patent application No. 202011066534.6 filed on September 30, 2020, and entitled "Chip, communication system and communication method", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, in particular to a chip, a communication system and a communication method. BACKGROUND

[0003] In recent years, the progress of industrial technology has greatly improved the level of port data transmission in the mobile device industry, and the mobile device industry has begun to widely apply high-speed data serial ports in terminal products. The physical layer port must face the challenge of higher and higher data transmission rates. Under the condition of high-speed data transmission, the working state of the port needs strict logical support.

[0004] At present, the environment of applying high-speed data serial ports in terminal products can be roughly divided into the following application scenarios: application processor-camera, application processor-display, storage, etc. Therefore, the high-speed data serial port needs to support multiple application scenarios. Due to the limitation of the application scenario, as the data transmission rate continues to increase, the possibility of various errors occurring in the data transmission link is getting larger and larger, which poses a great challenge to the stability of the transmission link. The existing data transmission technology cannot meet the demand. SUMMARY

[0005] The present application provides a chip, a communication system and a communication method, aiming to improve the reliability during communication.

[0006] In a first aspect, a communication method for communication transmission link switching in a communication system is provided. The method comprises the following steps: when a data transmission error is detected in a data transmission state, controlling both a sending port and a receiving port to enter a repair state, wherein the data transmission state comprises a high-speed data transmission state and a low-speed data transmission state, in the high-speed data transmission state, a data transmission rate is greater than or equal to 1 Gbps, the sending port is located at a master chip side, and the receiving port is located at a slave chip side which has a communication relationship with the master chip; in the repair state, performing data repair on the sending port and the receiving port, repairing parameters of the sending port to parameters when the sending port is in the data transmission state, and repairing parameters of the receiving port to parameters when the receiving port is in the data transmission state; after completing the data repair on the sending port and the receiving port, controlling both the sending port and the receiving port to enter a low-power consumption state or to enter the high-speed data transmission state again. In the above scheme, by setting the repair state, the transmission link is repaired when a data transmission fault occurs, and the reliability during data transmission is improved. In addition, during the repair, only the matching parameters corresponding to the data transmission are repaired, and there is no need to match the basic information of the two chips during handshaking again, and the repair efficiency is improved.

[0007] In a specific implementation, after detecting the data transmission error and before controlling both the sending port and the receiving port to enter the repair state, the method further comprises: controlling both the sending port and the receiving port to enter a low-power consumption state. The low-power consumption state is used as an intermediate state to facilitate state switching.

[0008] In a specific implementation, the controlling both the sending port and the receiving port to enter the repair state specifically means: controlling both the sending port and the receiving port to enter the repair state from the low-power consumption state. Both the ports at the two ends of the transmission link are repaired.

[0009] In a specific implementation, when the data transmission error is detected, both the sending port and the receiving port are controlled to enter the repair state, specifically: when the data transmission error is detected, the sending port is controlled to enter the repair state, and a repair control code stream is sent to the slave chip to make a protocol layer or a controller of the slave chip control the receiving port to enter the repair state according to the repair control code stream. Both the sending port and the receiving port are controlled to enter the repair state by the master chip.

[0010] In one specific implementation, the method further comprises: after the data repair is completed and before the sending port and the receiving port are both controlled to enter the low power consumption state, the method further comprises: confirming that the parameters of the sending port after the repair are the parameters when the sending port is in the data transmission state and the parameters of the receiving port are the parameters when the receiving port is in the data transmission state. The handshake process is added after the transmission link changes the parameter configuration, the accuracy of the repaired data transmission is preliminarily judged, and the robustness of the transmission link is improved.

[0011] In one specific implementation, before the high-speed data transmission state in which the data transmission error is detected, the sending port and the receiving port are both in the low power consumption state. The low power consumption state is used as an intermediate state to facilitate state switching.

[0012] In one specific implementation, the method further comprises: after the data transmission is completed, the sending port and the receiving port are both controlled to enter the low power consumption state to wait for the next state triggering condition. The low power consumption state is used to improve the intercommunication between the states of the state machine, the transmission link configuration process is reasonably arranged, and the conversion between any different states needs to be jumped at most twice.

[0013] In one specific implementation, the method further comprises: triggering the transmission link to enter a low-speed data transmission state and performing low-speed data transmission through a low-speed data control code stream; and after the low-speed data transmission is completed, the transmission link is controlled to enter the low power consumption state. The low power consumption state is used to improve the intercommunication between the states of the state machine, the transmission link configuration process is reasonably arranged, and the conversion between any different states needs to be jumped at most twice.

[0014] In one specific implementation, before the sending port and the receiving port are both first controlled to enter the low power consumption state, the method further comprises: a transmission link is established between the master chip and the slave chip, and port information exchange is performed, the port information exchange refers to that the master chip sends the port information of the sending port to the slave chip, and the slave chip sends the port information of the receiving port to the master chip; and after the port information exchange is completed, the sending port and the receiving port are both first controlled to enter the low power consumption state. State switching is facilitated.

[0015] In a second aspect, a communication method is provided, which comprises: detecting current parameters of a sending port and a receiving port before the sending port and the receiving port enter a data transmission state, and determining whether the current parameters of the sending port are consistent with parameters matched by the sending port when transmitting data at a target data transmission rate, and whether the current parameters of the receiving port are consistent with parameters matched by the receiving port when receiving data at the target data transmission rate, the sending port being located at a master chip side, and the receiving port being located at a slave chip side having a communication relationship with the master chip; when the current parameters of the sending port and the receiving port are inconsistent with the parameters matched by the sending port and the receiving port at the target data transmission rate, controlling the sending port and the receiving port to enter a rate switching state; in the rate switching state, switching the current parameters of the sending port to the parameters matched by the sending port when transmitting data at the target data transmission rate, and switching the current parameters of the receiving port to the parameters matched by the receiving port when receiving data at the target data transmission rate; and after the switching is completed, controlling the sending port and the receiving port to enter a low-power-consumption state. By matching the transmission link before data transmission, the reliability of data transmission is improved.

[0016] In a specific implementation, the method further comprises: after the current parameters of the sending port are switched to the parameters matched by the sending port when transmitting data at the target data transmission rate, and the current parameters of the receiving port are switched to the parameters matched by the receiving port when receiving data at the target data transmission rate, receiving a data transmission control code stream and controlling the transmission link to switch from the low-power-consumption state to a high-speed data transmission state or a low-speed data transmission state matched with the target data transmission rate, the high-speed data transmission rate being greater than the low-speed data transmission rate. The data transmission state is entered after the parameters are matched.

[0017] In a specific implementation, the method further comprises: during data transmission, when a data transmission rate changes, controlling the sending port and the receiving port to enter the low-power-consumption state, and to enter the rate switching state from the low-power-consumption state; in the rate switching state, switching the current parameters of the sending port to the parameters matched by the sending port when transmitting data at the changed data transmission rate, and switching the current parameters of the receiving port to the parameters matched by the receiving port when receiving data at the changed data transmission rate; and after the switching is completed, controlling the sending port and the receiving port to enter the low-power-consumption state.

[0018] In one specific implementation, the method further comprises: receiving a data transmission control code stream and controlling the transmission link to switch from the low power consumption state to a high speed data transmission state or a low speed data transmission state matching the target data transmission rate when the current parameters of the sending port are switched to the parameters matching the sending port when transmitting data at the changed data transmission rate and the current parameters of the receiving port are switched to the parameters matching the receiving port when receiving data at the changed data transmission rate.

[0019] In one specific implementation, the method further comprises: when a data transmission error is detected in the data transmission state, controlling the sending port and the receiving port to enter a repair state; wherein the data transmission state comprises a high speed data transmission state and a low speed data transmission state; in the repair state, performing data repair on the sending port and the receiving port, repairing the parameters of the sending port to the parameters when the sending port is in the data transmission state, and repairing the parameters of the receiving port to the parameters when the receiving port is in the data transmission state; after completing the data repair on the sending port and the receiving port, controlling the sending port and the receiving port to enter a low power consumption state or to enter the high speed data transmission state again. The reliability of the transmission link is improved.

[0020] In one specific implementation, after detecting the data transmission error and before controlling the sending port and the receiving port to enter the repair state, the method further comprises: controlling the sending port and the receiving port to enter a low power consumption state. The state switching is facilitated.

[0021] In a third aspect, a chip is provided, which comprises a first sending port and a first controller; the first controller is configured to control the first sending port to enter a repair state when a data transmission error is detected in a data transmission state; and send a repair control code stream to a peer chip to control a first receiving port of the peer chip to enter the repair state; wherein the data transmission state comprises a high-speed data transmission state and a low-speed data transmission state; the first controller is further configured to perform data repair on the first sending port in the repair state, and repair parameters of the first sending port to parameters when the first sending port is in the data transmission state; and the first controller is further configured to control the first sending port to enter a low-power state or the high-speed data transmission state again after completing the data repair on the first sending port; wherein the transmission rate of data in the high-speed data transmission state is greater than or equal to 1 Gbps. In the above scheme, by setting the repair state, the first sending port is repaired when a high-speed data transmission fault occurs, and the reliability of high-speed data transmission is improved. In addition, only the matching parameters corresponding to the high-speed data transmission are repaired during the repair, and the repair efficiency is improved.

[0022] In a specific implementation, the first controller is further configured to control the first sending port to enter a low-power state after detecting the data transmission error and before controlling the first sending port to enter the repair state. This facilitates state switching.

[0023] In a specific implementation, the first controller is further configured to confirm that the parameters of the first sending port after the repair are the parameters when the first sending port is in the data transmission state after completing the data repair and before controlling the first sending port to enter the low-power state. This improves the reliability of the transmission link.

[0024] In a specific implementation, the first controller is further configured to control the first sending port to enter a low-power state before the first sending port enters the high-speed data transmission state. This facilitates state switching.

[0025] In a specific implementation, the chip further comprises a second receiving port; the second receiving port is configured to receive port information of the first receiving port sent by a second sending port of the peer chip; and the first controller is further configured to control the first sending port to establish a transmission link with the first receiving port of the peer chip, and control the first sending port to send the port information of the first sending port to the first receiving port of the peer chip.

[0026] In a fourth aspect, a chip is provided, which includes a first receiving port and a second controller; the first receiving port is configured to receive a repair control code stream sent by a first sending port of a peer chip; the second controller is configured to control the first receiving port to enter a repair state according to the repair control code stream; wherein the repair control code stream is a repair control code stream generated by a first controller of the peer chip for controlling the first receiving port to switch to the repair state when a data transmission error is detected in a data transmission state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; the second controller is further configured to perform data repair on the first receiving port in the repair state, and repair parameters of the first receiving port to parameters when the first receiving port is in the data transmission state; the second controller is further configured to control the first receiving port to enter a low-power state or the high-speed data transmission state again after completing the data repair on the first receiving port; wherein in the high-speed data transmission state, the transmission rate of data is greater than or equal to 1 Gbps. The reliability of the transmission link is improved.

[0027] In a specific implementation, the second controller is further configured to control the first receiving port to enter a low-power state after detecting the data transmission error and before controlling the first receiving port to enter the repair state. The state switching is facilitated.

[0028] In a specific implementation, the second controller is further configured to confirm that the parameters of the first receiving port after the repair are the parameters when the first receiving port is in the data transmission state after completing the data repair and before controlling the first receiving port to enter the low-power state. The reliability of the transmission link is improved.

[0029] In a specific implementation, the second controller is further configured to control the first receiving port to enter a low-power state before the first receiving port enters the high-speed data transmission state. The state switching is facilitated.

[0030] In a specific implementation, a second sending port is further included; the second controller is further configured to control the first receiving port to establish a transmission link with the first sending port of the peer chip, and control the second sending port to send port information of the first receiving port to a second receiving port of the peer chip; the first receiving port is further configured to receive the port information of the first sending port sent by the first sending port of the peer chip.

[0031] In a fifth aspect, a chip is provided, which includes a first sending port and a first controller. The first controller is configured to detect a current parameter of the first sending port and determine whether the current parameter of the first sending port is consistent with a parameter matched by the first sending port when transmitting data at a target data transmission rate before the first sending port enters a data transmission state. The first controller is further configured to control the first sending port to enter a rate switching state when the current parameter of the first sending port is not consistent with the parameter matched by the first sending port at the target data transmission rate. The first controller is further configured to switch the current parameter of the first sending port to the parameter matched by the first sending port when transmitting data at the target data transmission rate in the rate switching state. The first controller is further configured to control the first sending port to send a control code stream to a first receiving port of a peer chip to control the first receiving port to enter the rate switching state. The first controller is further configured to control the first sending port to enter a low-power consumption state after the switching is completed. The reliability of a transmission link is improved.

[0032] In a specific implementation, the first controller is further configured to receive a data transmission control code stream and control the first sending port to switch from the low-power consumption state to a high-speed data transmission state or a low-speed data transmission state matched by the target data transmission rate after the current parameter of the first sending port is switched to the parameter matched by the first sending port when transmitting data at the target data transmission rate. The first controller is further configured to control the first sending port to send a control code stream to the first receiving port of the peer chip to control the first receiving port to switch to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate. The high-speed data transmission rate is greater than the low-speed data transmission rate.

[0033] In a specific implementation, the first controller is further configured to control the first sending port to enter the low-power consumption state and enter the rate switching state from the low-power consumption state when a data transmission rate changes during data transmission. The first controller is further configured to control the current parameter of the first sending port to be switched to a parameter matched by the first sending port when transmitting data at the changed data transmission rate in the rate switching state. The first controller is further configured to control the first sending port to send a control code stream to the first receiving port of the peer chip to control the first receiving port to enter the low-power consumption state and the rate switching state. The first controller is further configured to control the first sending port to enter the low-power consumption state after the switching is completed. The reliability of a transmission link is improved.

[0034] In one specific implementation, the first controller is further configured to receive a data transmission control code stream and control the first sending port to switch from the low power consumption state to a high speed data transmission state or a low speed data transmission state matching the target data transmission rate when the current parameters of the first sending port are switched to parameters matching the first sending port when transmitting data at the changed data transmission rate.

[0035] In one specific implementation, the first controller is further configured to control the first sending port to enter a repair state when a data transmission error is detected in a data transmission state; and send a repair control code stream to the peer chip to control the first receiving port of the peer chip to enter the repair state; wherein the data transmission state includes a high speed data transmission state and a low speed data transmission state; the first controller is further configured to perform data repair on the first sending port in the repair state, and repair the parameters of the first sending port to parameters when the first sending port is in the data transmission state; the first controller is further configured to control the first sending port to enter a low power consumption state or a high speed data transmission state again after completing the data repair on the first sending port. The reliability of the transmission link is improved.

[0036] In one specific implementation, the first controller is further configured to control the first sending port to enter a low power consumption state after detecting the data transmission error and before controlling the first sending port to enter the repair state. The state switching is facilitated.

[0037] In a sixth aspect, a chip is provided, which includes a first receiving port and a second controller, the first receiving port is configured to receive a control code stream sent by a peer chip to control the first receiving port to enter a rate switching state before the first receiving port enters a data transmission state; the second controller is configured to control the first receiving port to enter the rate switching state according to the control code stream controlling the first receiving port to enter the rate switching state; and control the first receiving port to enter the rate switching state according to the control code stream; the second controller is further configured to switch the current parameters of the first receiving port to parameters matching the first receiving port when transmitting data at a target data transmission rate in the rate switching state; the second controller is further configured to control the first receiving port to enter a low power consumption state after completing the switching. The reliability of the transmission link is improved.

[0038] In one specific implementation, the second controller is further configured to control the first receiving port to receive a control code stream for controlling the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state matching the target data transmission rate after the current parameters of the first receiving port are switched to parameters matching the first receiving port when transmitting data at the target data transmission rate, and control the first receiving port to switch from the low-power consumption state to the high-speed data transmission state or the low-speed data transmission state matching the target data transmission rate according to the control code stream; wherein the high-speed data transmission rate is greater than the low-speed data transmission rate.

[0039] In one specific implementation, during data transmission, when a data transmission rate changes, the first receiving port is configured to receive a control code stream sent by the opposite chip for controlling the first receiving port to enter a low-power consumption state and a rate switching state; the second controller is configured to control the first receiving port to enter the low-power consumption state and the rate switching state according to the control code stream for controlling the first receiving port to enter the low-power consumption state and the rate switching state; and control the first receiving port to enter the low-power consumption state and then enter the rate switching state according to the control code stream; the second controller is further configured to control the current parameters of the first receiving port to switch to parameters matching the first receiving port when transmitting data at the changed data transmission rate in the rate switching state; and the second controller is further configured to control the first receiving port to enter the low-power consumption state after the switching is completed.

[0040] In one specific implementation, the second controller is further configured to control the first receiving port to receive a control code stream for controlling the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state matching the target data transmission rate after the current parameters of the first receiving port are switched to parameters matching the first receiving port when transmitting data at the target data transmission rate, and control the first receiving port to switch from the low-power consumption state to the high-speed data transmission state or the low-speed data transmission state matching the target data transmission rate according to the control code stream.

[0041] In one specific implementation, the second controller is further configured to control the first receiving port to enter a repair state according to the repair control code stream; wherein the repair control code stream is a repair control code stream generated by the first controller of the opposite chip for controlling the first receiving port to switch to the repair state when a data transmission error is detected in the high-speed data transmission state.

[0042] The second controller is further configured to perform data repair on the first receiving port in the repair state, and repair parameters of the first receiving port to parameters when the first receiving port is in a data transmission state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state.

[0043] The second controller is further configured to control the first receiving port to enter a low-power state or the high-speed data transmission state again after completing the data repair on the first receiving port.

[0044] In a specific implementation, the second controller is further configured to control the first receiving port to enter a low-power state after detecting the data transmission error, and before controlling the first receiving port to enter the repair state.

[0045] In a seventh aspect, a communication system is provided, including a first chip and a second chip; wherein the first chip is any of the chips described above; the second chip is a peer chip of the first chip; and a transmission link is established between the first chip and the second chip. In the above scheme, by setting a repair state, the transmission link is repaired when a high-speed data transmission fault occurs, and the reliability of high-speed data transmission is improved. In addition, during repair, only matching parameters corresponding to high-speed data transmission are repaired, and there is no need to match the basic information of the two chips again when they are in a handshake state, and the repair efficiency is improved.

[0046] In an eighth aspect, a mobile terminal is provided, including a first chip and a second chip; wherein the first chip is any of the chips described above; the second chip is a peer chip of the first chip; and a transmission link is established between the first chip and the second chip. In the above scheme, by setting a repair state, the transmission link is repaired when a high-speed data transmission fault occurs, and the reliability of high-speed data transmission is improved. In addition, during repair, only matching parameters corresponding to high-speed data transmission are repaired, and there is no need to match the basic information of the two chips again when they are in a handshake state, and the repair efficiency is improved.

[0047] In a ninth aspect, an embodiment of the present application provides a signal processing module, the signal processing module comprising a processor configured to implement the method described in the first aspect or the second aspect. The signal processing module can further comprise a memory configured to store instructions and data. The memory is coupled to the processor, and when the processor executes the program instructions stored in the memory, the method described in the first aspect can be implemented. The signal processing module can further comprise a communication port configured to enable the apparatus to communicate with other devices, for example, the communication port can be a transceiver, a circuit, a bus, a module or other types of communication ports, and the other devices can be network devices or terminal devices.

[0048] In a specific implementation, the signal processing module comprises a memory configured to store program instructions, and a processor configured to invoke the instructions stored in the memory, so that the apparatus executes the method of the first aspect and any possible design of the first aspect.

[0049] In a tenth aspect, an embodiment of the present application further provides a computer readable storage medium comprising instructions, which, when executed on a computer, cause the computer to execute the method of the first aspect and any possible design of the first aspect, or the method of the second aspect and any possible design of the second aspect.

[0050] In an eleventh aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, cause the computer to execute the method of the first aspect and any possible design of the first aspect, or the method of the second aspect and any possible design of the second aspect.

[0051] In addition, the technical effects brought by any possible design of the ninth aspect to the eleventh aspect can be referred to the effects brought by different design manners in the method part, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 The communication method provided by the embodiments of the present application can be applied to the following scenarios in a terminal device;

[0053] Figure 2 The communication method provided by the embodiments of the present application can be applied to the following scenarios in a storage device;

[0054] Figure 3 A logic diagram of each state of the transmission link provided by the embodiments of the present application is shown;

[0055] Figure 4 A working mode management flow after the chip is powered on is shown;

[0056] Figure 5 A working mode management flow under high-speed data transmission provided by the embodiment of the application is shown;

[0057] Figure 6 A working mode management flow under low-speed data transmission provided by the embodiment of the application is shown;

[0058] Figure 7 A working mode management flow under ultra-low power consumption provided by the embodiment of the application is shown;

[0059] Figure 8 A communication system provided by the application is shown;

[0060] Figure 9 A working flow of a port in a LINK-STARTUP state under a communication system architecture is shown;

[0061] Figure 10 A working flow of a port in a SPEED-CHANGE state under a communication system architecture is shown;

[0062] Figure 11 A working flow of a port in a RECOVERY state under a communication system architecture is shown;

[0063] Figure 12 Another communication system provided by the application is shown;

[0064] Figure 13 A working flow of a port in a LINK-STARTUP state under a communication system architecture is shown;

[0065] Figure 14 A working flow of a port in a SPEED-CHANGE state under a communication system architecture is shown;

[0066] Figure 15 A working flow of a port in a RECOVERY state under a communication system architecture is shown;

[0067] Figure 16 A structure block diagram of a signal processing module provided by the embodiment of the application is shown. DETAILED DESCRIPTION

[0068] The embodiment of the application will be further described below in combination with the drawings.

[0069] Firstly, it is explained that the communication method provided by the embodiment of the application is a high-speed communication method, which is mainly applied to various transmission links requiring high-speed communication in terminal services. Common scenarios are, for example, a data communication transmission link between a processor and a camera of a terminal product such as a mobile phone or a tablet, a data communication transmission link between a processor and a display, a data communication transmission link between storage devices, etc.

[0070] Reference Figure 1 , Figure 1 The application embodiment provides a communication method which can be applied to a terminal device. The terminal device 200 includes a processor, a camera module, a display module, a radio frequency module, a storage module, and the like. The above-mentioned modules can be regarded as chips. Transmission links 201, 202, 203, and 204 represent transmission links between the processor and the camera module, the processor and the display module, the processor and the radio frequency module, and the processor and the storage module, respectively. The communication method provided by the application embodiment can be applied to low-power management of port working modes on both sides of data transmission links such as 201, 202, 203, and 204, to ensure stable and reliable transmission of data in a high-speed scenario.

[0071] It should be understood that in the application embodiment, the master chip, also called the local chip, refers to a chip used for sending data between two chips having a communication relationship. The slave chip, also called the opposite chip, refers to a chip used for receiving data between two chips having a communication relationship. Generally, each chip has the functions of data sending and receiving. When the chip is used for sending data, the chip can be referred to as a master chip or a local chip. Correspondingly, the chip located at the opposite end of the chip and used for receiving data can be referred to as a slave chip or an opposite chip. As described above, in the two chips having a communication relationship, one chip is not fixed as a master chip or a slave chip. Whether a particular chip is a master chip or a slave chip depends on whether it is used for sending data or receiving data. For example, taking the processor and the camera module as an example, when the processor sends data to the camera module, the processor is a master chip (a local chip), and the camera module is a slave chip (an opposite chip). When the camera module sends data to the processor, the camera module is a master chip (a local chip), and the processor is a slave chip (an opposite chip).

[0072] Reference Figure 2 , Figure 2 The application embodiment provides a communication method which can be applied to a terminal device. The terminal device 200 includes a processor, a camera module, a display module, a radio frequency module, a storage module, and the like. The above-mentioned modules can be regarded as chips. The transmission links 201, 202, 203, and 204 represent transmission links between the processor and the camera module, the processor and the display module, the processor and the radio frequency module, and the processor and the storage module, respectively. The communication method provided by the application embodiment can be applied to low-power management of port working modes on both sides of data transmission links such as 201, 202, 203, and 204, to ensure stable and reliable transmission of data in a high-speed scenario.

[0073] To facilitate understanding of several working states of the transmission link involved in the communication method provided by the application embodiment, the working states of the transmission link are described as follows. Figure 1The scenario of the local chip and the peer chip is shown. When the local chip and the peer chip establish a transmission link, the transmission link is formed by the sending port of the local chip, the receiving port of the peer chip and the link therebetween. It should be understood that the local chip and the peer chip each include a protocol layer and a physical layer, wherein the protocol layer is used to send data or control instructions to the physical layer, and the physical layer sends and processes data according to the instructions of the protocol layer. The sending port of the local chip and the receiving port of the peer chip are each a physical layer port.

[0074] The working mode management method of the high-speed data serial port provided in the embodiments of the present application is in the form of a state machine, as shown in Figure 3 Figure 3 Each state in the state machine corresponds to a working mode of the transmission link, and the transmission link includes the following working states: a DISABLED state, a PHY-INIT state, a LINK-STARTUP state, a LOW-POWER0 state, a LOW-POWER1 state, a TRANS0 state, a TRANS1 state, a RECOVERY state and a SPEED-CHANGE state. The functions of the transmission link in each state are defined in detail below. First, refer to Table 1, which shows the Chinese meanings corresponding to the English abbreviations of the various states.

[0075] Table 1

[0076]

[0077] It should be understood that in the various working modes of the transmission link, the sending port and the receiving port also correspondingly have the same working modes, and the parameters of the sending port and the receiving port are matched to be in the parameter requirements corresponding to different working modes, so that the transmission link is in different working modes. The above-mentioned several working modes are described in detail below.

[0078] DISABLED state:

[0079] This state represents the state when the chip is powered on and reset. This state can automatically enter after the chip is initially powered on, or can enter after being triggered by a trigger condition Trigger0 in any state.

[0080] During this state, the physical layer port is disabled for sending and receiving operations, and only when Trigger0 ends or is invalid, the PHY-INIT state is entered.

[0081] PHY-INIT state:

[0082] This state represents the state of port initialization, which can automatically enter after the DISABLED state ends, or can enter after being triggered by a trigger condition Trigger1 in any state.​

[0083] During this state, all the transmission link configurations and registers are restored to default values, and after the transmission link initialization is completed, the physical layer port is still disabled from transmitting and receiving operations, so that the physical layer is kept in an extremely low power consumption state, waiting for the trigger condition of entering LINK-STARTUP.

[0084] The trigger condition of entering LINK-STARTUP can come from the control of the upper layer chip or from the control code stream on the transmission link.

[0085] LINK-STARTUP state:

[0086] This state represents a state of establishing a reliable connection between physical layer ports. In this state, the physical layer port allows transmitting and receiving operations. The physical layer port in this state needs to determine the state of the transmission link, establish a link with the physical layer port at the other end of the transmission link, and exchange the basic information of the physical layer port.

[0087] The physical layer port in this state communicates at the lowest rate supported by the chip, and the operation at this rate is considered reliable. If the communication fails due to a timeout due to chip synchronization problems, the connection with the opposite chip is stopped, the upper layer is notified, and the PHY-INIT state is entered.

[0088] After the physical layer port establishes a reliable connection, it is triggered by the upper layer control or the control code stream on the transmission link to enter the condition of the LOW-POWER0 state.

[0089] LOW-POWER0 state:

[0090] This state represents a low power consumption state. The physical layer port in this state needs to save power consumption while not affecting the start-up time of data transmission. The physical layer port in this state does not perform parameter configuration and immediately enters the next state under the trigger condition of the upper layer control or the control code stream on the transmission link.

[0091] LOW-POWER1 state:

[0092] This state is an ultra-low power consumption state. During this state, the physical layer port keeps the current configuration and register values of the chip unchanged, and closes specific circuit modules. The physical layer port in this state does not perform transmitting and receiving operations, and under the trigger condition of the upper layer control or the control code stream on the transmission link, the corresponding circuit modules are reopened to enter the LOW-POWER0 state.

[0093] TRANS0 state:

[0094] This state is the low-speed data transmission state of the physical layer port. The port in this state transmits low-speed (less than 1 Gbps) data, and can support different low-speed gear positions. After the data transmission is completed, the physical layer port in this state will enter the LOW-POWER0 state.

[0095] TRANS1 state:

[0096] This state is the high-speed data transmission state of the physical layer port. The physical layer port in this state transmits high-speed large data, and can support different high-speed gear positions. Specifically, the data transmission rate is greater than or equal to 1 Gbps.

[0097] After the data transmission is completed, the physical layer port in this state will enter the LOW-POWER0 state, and will only enter the RECOVERY state when receiving upper layer control or control stream trigger condition on the transmission link.

[0098] RECOVERY state:

[0099] This state represents the data repair state of the physical layer port. When the data transmission link of the physical layer port has an error during data transmission, the port should enter the RECOVERY state to repair the corresponding data transmission link.

[0100] The physical layer port in this state can take appropriate repair measures according to different transmission error situations, and only performs data transmission related to repair, i.e., only repairs the corresponding matching parameters in the data transmission state, and does not process the basic configuration during the handshake establishment of the transmission link. After the configuration is completed, the physical layer port can send some handshake information to confirm that the transmission link is available again, and then enter the next state according to the upper layer control or control stream trigger on the transmission link.

[0101] SPEED-CHANGE state:

[0102] This state represents the data transmission rate switching state of the physical layer port. The physical layer port enters the SPEED-CHANGE state to change the rate configuration parameters of the port according to the indication of the upper layer.

[0103] The physical layer port in this state only performs data transmission related to speed switching. After the configuration is completed, the physical layer port needs to send some handshake information at the new rate to confirm that the transmission link is available again, and then return to the LOW-POWER0 state according to the upper layer control or control stream trigger on the transmission link.

[0104] Among the DISABLED state, the PHY-INIT state, the LINK-STARTUP state, the LOW-POWER0 state, the LOW-POWER1 state, the TRANS0 state, the TRANS1 state, the RECOVERY state and the SPEED-CHANGE state, the LOW-POWER0 state, the TRANS1 state and the RECOVERY state are the states mainly involved in the communication method provided by the embodiment of the present application, and the other states are optional states of the transmission link. In actual application, the optional states can be set according to requirements.

[0105] For the convenience of understanding the method provided by the embodiment of the present application, the communication method provided by the embodiment of the present application is described below in combination with specific drawings. The communication method provided by the embodiment of the present application is used to switch the working states of the transmission link. It should be understood that the working state of the transmission link corresponds to the working state of the transmitting port of the local chip and the receiving port of the opposite chip. When the transmission link has the above-mentioned working states, the corresponding transmitting port and receiving port also have the above-mentioned working states.

[0106] Firstly, the interface in the flowchart shown in Figures 4-7 in the flowchart refers to the transmitting port and / or the receiving port of the local chip and the opposite chip.

[0107] Referring to Figure 4 , the transmission link is established between the first chip and the second chip, and the port information is exchanged. The port information exchange means that the first chip sends the port information of the transmitting port to the second chip, and the second chip sends the port information of the receiving port to the first chip. After the port information exchange is completed, the transmitting port and the receiving port both enter the low-power state for the first time.

[0108] Exemplarily, Figure 4 the working mode management flow after the chip is powered on is shown. The power-on reset signal of the chip can be regarded as a kind of trigger condition Trigger0. Firstly, the first chip and the second chip handshake to establish the transmission link, and exchange the basic information of the ports at both ends of the transmission link. In the embodiment of the present application, the first chip is taken as the local chip, and the second chip is taken as the opposite chip. When the first chip is the local chip and the second chip is the opposite chip, the first chip has a transmitting port, and the second chip has a receiving port. When the transmission link is established, the transmitting port and the receiving port are the ports at both ends of the transmission link.

[0109] When the first chip is powered on and reset, the sending port of the first chip enters the DISABLED state from any previous state. After the power-on reset signal ends or fails, the sending port automatically enters the PHY-INIT state and performs initialization operations. After the initialization operation is completed, the sending port waits for the trigger condition to enter LINK-STARTUP in an extremely low power state. After receiving the trigger condition, the sending port enters the LINK-STARTUP state and attempts to establish a reliable link with the receiving port of the second chip. The first chip transmits the basic information of the sending port (such as capability information and version information) to the second chip, and the second chip transmits the basic information of the receiving port (such as capability information and version information) to the first chip.

[0110] If link establishment (transmission link establishment) fails, the transmitting port returns to the PHY-INIT state and re-initializes. If initialization is complete and the transmitting port and receiving port have completed reliable link establishment, they enter the LOW-POWER0 state under the trigger of the upper layer control or the control code stream on the transmission link, waiting for the trigger condition to enter the next state. The above-mentioned LOW-POWER0 state is an intermediate state. After the transmitting port and receiving port complete any data transmission work, the first chip can control the transmission link to enter the LOW-POWER0 state and wait for the trigger condition of the next state to reduce energy consumption.

[0111] refer to Figure 5 , Figure 5 The figure shows the working mode management process under high-speed data transmission. Before high-speed data transmission, the transmission link is in the LOW-POWER0 state, that is, the sending port and the receiving port are both in the low-power state before entering the high-speed data transmission state.

[0112] During high-speed data transmission, the transmission link can be triggered to enter a high-speed data transmission state via a high-speed data control stream, thereby performing high-speed data transmission. Specifically, the controller or protocol layer of the first chip triggers both the transmitting port and the receiving port to enter a high-speed data transmission state via the high-speed data control stream. High-speed data transmission refers to data transmission at a data transmission rate of the order of Gbps.

[0113] When a high-speed data transmission error is detected, the transmission link can be controlled to enter the repair state. For example, if an error occurs during data transmission, the transmission link can be triggered by upper-layer control or the control code stream on the transmission link to exit the TRANS1 state and enter the RECOVERY state directly, and the transmission link can be repaired in the RECOVERY state.

[0114] In the above process, the protocol layer of the first chip controls the sending port and the receiving port to enter the repair state; when detecting the high-speed data transmission error, the controller or the protocol layer of the first chip controls the sending port to enter the repair state and sends a repair control code stream to the second chip, so that the protocol layer or the controller of the second chip controls the receiving port to enter the repair state according to the repair control code stream. The above-mentioned control of the protocol layer of the first chip to control the receiving port to enter the repair state refers to the control of the second chip through the repair control code stream to make the receiving port enter the repair state, so that the sending port and the receiving port both enter the repair state.

[0115] After detecting the data transmission error and before controlling the sending port and the receiving port to enter the repair state, the sending port and the receiving port are controlled to enter a low-power state. Specifically, the sending port and the receiving port are controlled to enter the repair state from the low-power state.

[0116] In the repair state, the controller or the protocol layer of the first chip performs data repair (reset and repair) on the sending port and the receiving port, repairs the parameters of the sending port to the parameters when the sending port is in the high-speed data transmission state, and repairs the parameters of the receiving port to the parameters when the receiving port is in the high-speed data transmission state. In this state, the sending port and the receiving port can take corresponding repair measures according to different transmission error conditions, that is, only the corresponding matching parameters in the data transmission state are repaired, and the basic configuration during the handshake establishment of the transmission link is not involved. Taking reset as an example, the controller or the protocol layer of the first chip resets the parameters of the sending port to the parameters matched with the high-speed data transmission state. Similarly, the protocol layer or the controller of the second chip resets the parameters of the receiving port to the parameters matched with the high-speed data transmission state according to the related code stream sent by the first chip.

[0117] As an optional solution, after completing the transmission link repair, a handshake process is added to confirm that the parameters of the repaired sending port are the parameters when the sending port is in the high-speed data transmission state and the parameters of the receiving port are the parameters when the receiving port is in the high-speed data transmission state, so as to ensure the robustness of the transmission link.

[0118] If the data transmission is completed, the protocol layer or the controller of the first chip controls the transmission link to exit the TRANS1 state and enter the LOW-POWER0 state, and waits for a trigger condition to enter the next state.

[0119] As an optional solution, before entering the TRANS1 state, that is, before the sending port and the receiving port enter the data transmission state, the protocol layer or the controller of the first chip detects whether the transmission rate of the transmission link is consistent with the transmission rate of the target data.

[0120] For example, the current parameters of the sending port and the current parameters of the receiving port are detected, and it is determined whether the current parameters of the sending port are consistent with the parameters matched by the sending port when transmitting data at the target data transmission rate, and whether the current parameters of the receiving port are consistent with the parameters matched by the receiving port when receiving data at the target data transmission rate, i.e., whether the current parameters of the ports at both ends of the transmission link are consistent with the parameters matched by the ports at both ends of the transmission link when transmitting and receiving data at the target data transmission rate.

[0121] When the current parameters of the sending port and the receiving port are inconsistent with the parameters matched by the sending port and the receiving port at the target data transmission rate, the protocol layer or the controller of the first chip controls the sending port and the receiving port to enter the rate switching state. In the specific control, the protocol layer or the controller of the first chip controls the sending port to enter the low-power-consumption state, and after entering the low-power-consumption state, the sending port enters the rate switching state. In the above switching process, the protocol layer or the controller of the first chip controls the sending port to send a related switching control code stream to the receiving port of the second chip, and the protocol layer or the controller of the second chip controls the receiving port to enter the low-power-consumption state and then enter the rate switching state by receiving the related control code stream.

[0122] In the rate switching state, the protocol layer or the controller of the first chip switches the current parameters of the sending port to the parameters matched by the sending port when transmitting data at the target data transmission rate, and the protocol layer or the controller of the second chip switches the parameters of the receiving port to the parameters matched by the receiving port when receiving data at the target data transmission rate. After the switching is completed, the sending port and the receiving port enter the low-power-consumption state.

[0123] In addition, when the current parameters of the first sending port are consistent with the parameters matched by the first sending port when transmitting data at the target data transmission rate, and the current parameters of the receiving port are consistent with the parameters matched by the receiving port when receiving data at the target data transmission rate, the transmission link is controlled to switch from the low-power-consumption state to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate.

[0124] In the above process, the sending port needs to determine whether the data transmission rate supported by the current transmission link configuration is consistent with the target data transmission rate. If not, the sending port needs to enter the SPEED-CHANGE state to reconfigure the parameters of the transmission link to meet the target data transmission rate requirement. If the data transmission rate supported by the current transmission link configuration is consistent with the target data transmission rate, the sending port directly enters the TRANS1 state to perform high-speed data transmission under the triggering of the trigger condition (high-speed data control code stream). Similarly, the receiving port also performs corresponding operations.

[0125] In addition, when the data transmission rate changes during data transmission, the transmission link enters the low-power state, and then switches to the speed change state; the parameters of the ports at both ends of the transmission link are switched to the parameters matched with the data transmission rate after the change; and after the switching is completed, the sending port and the receiving port both enter the low-power state.

[0126] Specifically, if the transmission rate required by the transmitted data is different from the current transmission rate on the transmission link, the data transmission rate of the transmission link can be changed. For example, the sending port and the receiving port can be triggered to exit the TRANS1 state and enter the LOW-POWER0 state by the upper layer control or the control code stream on the transmission link, and then the sending port and the receiving port can be triggered to enter the SPEED-CHANGE state; in the SPEED-CHANGE state, the data parameters of the sending port and the receiving port are configured, i.e., the parameters of the ports at both ends of the transmission link are switched to the parameters corresponding to the transmission rate after the change, so as to adapt to the changed rate requirement. The above transmission rate switching during data transmission is the same as the transmission rate switching before entering the high-speed data transmission state, and will not be described in detail here.

[0127] Figure 6 The working mode management process under low-speed data transmission is shown. The transmission link can be triggered to enter the low-speed data transmission state by the low-speed data control code stream, and low-speed data transmission is performed; after the low-speed data transmission is completed, the transmission link enters the low-power state.

[0128] Before the transmission link performs low-speed data transmission, it is in the LOW-POWER0 state, and before entering the TRANS0 state, the sending port and the receiving port need to determine whether the data transmission rate supported by the current transmission link configuration is consistent with the transmission rate of the target data. If not, the transmission link needs to enter the SPEED-CHANGE state to reconfigure the transmission link parameters to meet the transmission rate requirement of the target data. If the data transmission rate supported by the current transmission link configuration is consistent with the transmission rate of the target data, the sending port and the receiving port directly enter the TRANS0 state under the triggering condition to perform low-speed data transmission. The process is similar to the related description in the above Figure 5

[0129] ​In the data transmission process, if the current transmission rate needs to be changed, the data transmission rate of the transmission link can be changed, the sending port and the receiving port are triggered to exit the TRANS0 state and enter the LOW-POWER0 state, and then the sending port and the receiving port are triggered to enter the SPEED-CHANGE state through upper layer control or control code stream on the transmission link. In the SPEED-CHANGE state, the data parameters of the sending port and the receiving port are configured, that is, the parameters of the ports at both ends of the transmission link are switched to the parameters corresponding to the transmission rate after the rate is changed, so as to adapt to the changed rate requirement. The process is similar to the related description in the above Figure 5 , and will not be repeated here.

[0130] In the data transmission process, if a data transmission error occurs, the transmission link can be controlled to enter the recovery state. For example, if an error occurs in the data transmission process, the transmission link can be triggered to exit the TRANS0 state and directly enter the RECOVERY state through upper layer control or control code stream on the transmission link, and the transmission link is repaired in the RECOVERY state. In the specific repair process, reference can be made to the related description in the above Figure 5 , and will not be repeated here.

[0131] If the data transmission is completed, the sending port and the receiving port exit the TRANS0 state and enter the LOW-POWER0 state, and wait for the trigger condition of the next state.

[0132] Figure 7 The working mode management flow under the ultra-low power consumption is shown. When no data transmission is performed, the transmission link enters the ultra-low power consumption state from the low power consumption state.

[0133] Specifically, the sending port and the receiving port are in the LOW-POWER0 state before entering the LOW-POWER1 state, and the sending port and the receiving port are triggered to exit the LOW-POWER0 state and enter the LOW-POWER1 state through upper layer control or control code stream on the transmission link. When the sending port and the receiving port need to exit the LOW-POWER1 state, the sending port is triggered to exit the LOW-POWER1 state and enter the LOW-POWER0 state through upper layer control or control code stream on the transmission link.

[0134] To facilitate understanding of the above communication method provided by the embodiments of the present application, the above several working states are described in conjunction with the communication system shown in Figure 8 .

[0135] Figure 8The shown communication system comprises a first chip 100 and a second chip 200, wherein the first chip 100 and the second chip 200 are opposite chips of another chip, and the first chip 100 and the second chip 200 have similar component structures.

[0136] Taking the first chip 100 as an example, the first chip 100 comprises a protocol layer and a physical layer structure. The protocol layer is responsible for sending upper-layer data information and control information, receiving data information and control information from other chips of the same level or upper-layer chips, and can control the physical layer. The physical layer of the first chip 100 comprises a sending module, a receiving module and a first controller 105. The sending module is used for sending data, the receiving module is used for receiving data, and the first controller 105 is used for controlling the sending module and the receiving module.

[0137] The sending module comprises a first data processing module 102 and a first sending port 101. The first data processing module 102 processes data information from the protocol layer into a data packet through operations such as encoding, scrambling, serial processing, etc., and then sends the data packet out through the first sending port 101.

[0138] The receiving module comprises a second data processing module 104 and a second receiving port 103. The second receiving port 103 receives a data packet from a transmission link, and the second data processing module 104 processes the data packet through operations such as decoding, descrambling, deserial processing, etc., and then transmits the data information and control information to the protocol layer, or indirectly controls the first controller 105 according to the control information.

[0139] The first controller 105 is directly controlled by the protocol layer, and can also accept indirect control from the receiving module, thereby realizing management of the sending module and the receiving module. The first controller 105 can realize management of data sending and receiving through management of the sending module and the receiving module.

[0140] The structure of the second chip 200 is similar to that of the first chip 100. The second sending port 201, the third data processing module 202, the first receiving port 203, the fourth data processing module 204, and the second controller 205 in the second chip 200 can refer to the related description of the same type of structure in the first chip 100. The second sending port 201 of the second chip 200 is connected with the second receiving port 103 of the first chip 100 to form a transmission link, and the first receiving port 203 of the second chip 200 is connected with the first sending port 101 of the first chip 100 to form a transmission link. When the transmission link is established, the above two transmission links are established synchronously. When the first sending port 101 and the first receiving port 203 establish the transmission link, the port information of the first receiving port can be sent to the second receiving port 103 through the second sending port 201, so as to realize the port information interaction between the first receiving port 203 and the first sending port 101. Similarly, when the second sending port 201 and the second receiving port 103 establish the transmission link, the port information of the second receiving port 103 can be sent to the first receiving port 203 through the first sending port 101.

[0141] The communication system provided by the embodiment of the application realizes the management of the transmission link of the communication system by managing the port working mode state machine. The transmission link between the first chip 100 and the second chip 200 of the communication system can be powered on, high-speed data transmission, low-speed data transmission, and ultra-low power consumption operation according to the working states described above.

[0142] In the communication system, the LINK-STARTUP state, the SPEED-CHANGE state, and the RECOVERY state of the first chip 100 are as follows:

[0143] Firstly, it is explained that the sending port in the following text refers to the first sending port 101 in the first chip 100, and the receiving port refers to the first receiving port 203 of the second chip 200.

[0144] Figure 9 The working flow of the port in the LINK-STARTUP state under the architecture of the communication system is shown. The first chip and the second chip handshake, establish the transmission link, and exchange the basic information of the ports at both ends of the transmission link (the first sending port and the first receiving port, and the second sending port and the first receiving port).

[0145] Specifically, after the first sending port is initialized, the protocol layer of the first chip controls the first sending port to enter a LINK-STARTUP state, and the first sending port sends a LINK-STARTUP control code stream to the first receiving port on the transmission link, and the LINK-STARTUP control code stream is used as a condition for triggering the first receiving port to enter the LINK-STARTUP state. The second controller of the second chip controls the first receiving port to enter the LINK-STARTUP state according to the received LINK-STARTUP control code stream. Similarly, the second sending port of the second chip sends a LINK-STARTUP control code stream to the second receiving port of the first chip, and the first controller of the first chip controls the second receiving port to enter the LINK-STARTUP state according to the received LINK-STARTUP control code stream.

[0146] When the first sending port enters the LINK-STARTUP state, the first sending port attempts to establish a link with the first receiving port and confirms the state of the transmission link by sending a link establishment related code stream on the transmission link; the second sending port attempts to establish a link with the second receiving port and confirms the state of the transmission link by sending a link establishment related code stream on the transmission link. The link establishment related code stream includes judgment information for establishing a reliable link of the transmission link and basic information that needs to be exchanged between the ports.

[0147] The first controller needs to judge whether a reliable link is established with the opposite port according to the link establishment related code streams sent and received by the first sending port and the second receiving port, and refresh the exchanged basic information in time. If it is judged that the port does not establish a reliable link, it is notified that the protocol layer fails to establish a link and returns to the PHY-INIT state; if it is judged that the first sending port and the second receiving port establish a reliable link with the opposite port, it is indicated that the link establishment is successful, the LINK-STARTUP state is ended, and the trigger condition of the next state is waited for. Similarly, the second controller also needs to perform the same operation as the first controller, which will not be described here.

[0148] After the transmission link is established, the transmission link can enter a low-power state through a trigger condition, and wait for the trigger condition of the next state.

[0149] Figure 10The working flow of the port in the SPEED-CHANGE state under the communication system architecture is shown. The first sending port and the first receiving port are in the LOW-POWER0 state before entering the SPEED-CHANGE state. After the protocol layer of the first chip sends the SPEED-CHANGE request, the first sending port enters the SPEED-CHANGE state and sends the SPEED-CHANGE control code stream on the transmission link between the first sending port and the first receiving port (i.e. sends the control code stream for entering the rate switching state to the first receiving port), and the SPEED-CHANGE control code stream is used as the condition for triggering the physical layer port (the first receiving port) of the opposite end to enter the SPEED-CHANGE state. The second controller controls the first receiving port to enter the SPEED-CHANGE state according to the SPEED-CHANGE control code stream received by the first receiving port.

[0150] After entering the SPEED-CHANGE state, the first sending port changes the current configuration parameter to the configuration parameter matched with the target data transmission rate (target rate) according to the request of the protocol layer or the target data in the SPEED-CHANGE control code stream. After the parameter configuration of the first sending port is completed, the rate switching related code stream is sent to the first receiving port at the target rate to attempt to communicate at the target rate. The rate switching related code stream includes but is not limited to the judgment information of the link rate switching success.

[0151] After the data transmission rate change is completed and the ports of the transmission link are matched, the sending code stream confirms the matching parameter of the transmission link corresponding to the target data. Taking the first chip as an example, the first sending port and the second receiving port need to judge whether the port can communicate with the first receiving port and the second sending port at the new rate according to the sent and received rate switching related code stream. If it is judged that the port cannot communicate, the protocol layer is informed that the rate switching fails and returns to the LOW-POWER0 state; if it is judged that the port can communicate at the transmission rate of the target data, it is indicated that the rate switching is successful, the SPEED-CHANGE state is ended, and the trigger condition for entering the next state is waited. As can be seen from the above description, the handshake process is added after the parameter configuration of the data transmission link is changed, the data transmission accuracy of the rate switching is preliminarily judged, and the robustness of the transmission link is improved.

[0152] The above SPEED-CHANGE state is applied in two scenarios. One state is that before the data transmission is performed, the parameter of the port of the transmission link is modified. Figure 5 and Figure 6 as shown in the low-speed data transmission state or the high-speed data transmission state is entered.

[0153] Exemplarily, before entering the SPEED-CHANGE state, the protocol layer or the first controller of the first chip detects the current parameters of the first sending port and judges whether the current parameters of the first sending port are consistent with the parameters matched by the first sending port when transmitting data at the target data transmission rate. Meanwhile, the protocol layer or the second controller of the second chip detects the current parameters of the second receiving port and judges whether the current parameters of the second receiving port are consistent with the parameters matched by the second receiving port when receiving data at the target data transmission rate, i.e. judges whether the current parameters of the ports at both ends of the transmission link are consistent with the parameters matched by the ports at both ends of the transmission link when transmitting and receiving data at the target data transmission rate.

[0154] When the current parameters of the first sending port and the first receiving port are inconsistent with the parameters matched by them at the target data transmission rate, the protocol layer or the first controller of the first chip controls the first sending port to enter the SPEED-CHANGE state. In the specific control, the protocol layer or the first controller of the first chip controls the first sending port to enter a low-power state and then controls the first sending port to enter the SPEED-CHANGE state after entering the low-power state. In the above switching process, the protocol layer or the first controller of the first chip controls the first sending port to send a relevant switching control code stream to the first receiving port of the second chip, and the protocol layer or the second controller of the second chip controls the first receiving port to enter a low-power state and then enter the SPEED-CHANGE state after entering the low-power state by receiving the relevant control code stream. Similarly, the second receiving port of the first chip and the second sending port of the second chip also perform the above operations.

[0155] In the SPEED-CHANGE state, the first sending port and the first receiving port are switched to the parameters matched by them at the target data transmission rate according to the above Figure 10 Exemplary flow, the protocol layer or the first controller of the first chip switches the current parameters of the first sending port to the parameters matched by the first sending port when transmitting data at the target data transmission rate. Meanwhile, the protocol layer or the second controller of the second chip switches the parameters of the first receiving port to the parameters matched by the first receiving port when receiving data at the target data transmission rate; and after completing the switching, the first sending port and the first receiving port both enter a low-power state. After completing the matching and entering the low-power state, they wait to enter a high-speed data transmission state or a low-speed data transmission state corresponding to the target data transmission. In addition, after completing the port matching of the transmission link, the sending code stream confirms the matching parameters of the transmission link corresponding to the target data to improve the robustness of the transmission link.

[0156] In addition, when the current parameters of the first sending port and the first receiving port are consistent with the parameters matched by the first sending port and the first receiving port when transmitting and receiving data at the target data transmission rate, respectively, the first controller or the protocol layer of the first chip controls the first sending port to switch from the low-power state to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate. The second controller or the protocol layer of the second chip controls the first receiving port to switch from the low-power state to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate. That is, the transmission link is controlled to switch from the low-power state to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate.

[0157] Another aspect relates to the SPEED-CHANGE state for the transmission link in data transmission, when the data transmission rate changes, the transmission rate needs to be switched. For example, when the data transmission rate changes during low-speed data transmission or high-speed data transmission, the transmission rate of the transmission link needs to be adjusted to the transmission rate corresponding to the changed data. Specifically, the protocol layer or the first controller of the first chip controls the first sending port to enter the SPEED-CHANGE state. In the specific control, the protocol layer or the first controller of the first chip controls the first sending port to enter the low-power state, and after entering the low-power state, controls the first sending port to enter the SPEED-CHANGE state. In the above switching process, the protocol layer or the first controller of the first chip controls the first sending port to send a related switching control code stream to the first receiving port of the second chip, and the protocol layer or the second controller of the second chip controls the first receiving port to enter the low-power state and then enter the SPEED-CHANGE state by receiving the related control code stream. Similarly, the first receiving port of the first chip and the second sending port of the second chip also perform the above operations.

[0158] In the SPEED-CHANGE state, the parameters of the ports of the transmission link are switched to the parameters matched by the target data transmission rate according to the above-mentioned flowchart, and then the low-power state is entered after the matching is completed, and the high-speed data transmission state or the low-speed data transmission state corresponding to the target data transmission is waited to enter. In addition, after the ports of the transmission link are matched, a code stream is sent to confirm the matching parameters of the transmission link corresponding to the target data, so as to improve the robustness of the transmission link. Figure 10 The flowchart of the example switches the parameters of the ports of the transmission link to the parameters matched by the target data transmission rate, and then enters the low-power state after the matching is completed, and waits to enter the high-speed data transmission state or the low-speed data transmission state corresponding to the target data transmission. In addition, after the ports of the transmission link are matched, a code stream is sent to confirm the matching parameters of the transmission link corresponding to the target data, so as to improve the robustness of the transmission link.

[0159] Figure 11The working flow of the port in the RECOVERY state under the communication system architecture is shown. After the first sending port and the first receiving port are in the low power consumption state and receive the data transmission control code stream, the first sending port and the first receiving port enter the data transmission state to perform data transmission. The data transmission control code stream is a high-speed data control code stream or a low-speed data control code stream. The high speed refers to a speed of Gbps order of magnitude, and the low speed refers to a speed of Mbps.

[0160] If an error occurs in the data transmission process, the transmission link can exit the TRANS1 state and directly enter the RECOVERY state through the control code stream on the protocol layer of the first chip, and the transmission link repair is performed in the RECOVERY state.

[0161] In the above process, when a high-speed data transmission error is detected, the first controller or the protocol layer of the first chip controls the first sending port to enter the repair state, and sends a repair control code stream (RECOVER control code stream) to the second chip, so that the protocol layer or the second controller of the second chip controls the first receiving port to enter the repair state according to the repair control code stream. Thus, the first sending port and the first receiving port enter the repair state.

[0162] After entering the RECOVERY state, the first receiving port sends a repair related code stream according to the type of the data transmission link error described in the RECOVERY control code stream. The repair related code stream can include but is not limited to a receiver bit synchronization code stream, a receiver equalization training code stream and judgment information of the success of the transmission link repair.

[0163] In the RECOVERY state, the first controller or protocol layer of the first chip performs data repair (reset and repair) on the first sending port, and the second controller or protocol layer of the second chip performs modification on the first receiving port, and repairs the parameters of the first receiving port to the parameters when the first receiving port is in the high-speed data transmission state. The first sending port and the first receiving port in this state can take corresponding repair measures according to different transmission error conditions, that is, only the corresponding matching parameters in the data transmission state are repaired, and the basic configuration when the transmission link handshake is established is not involved. Taking reset as an example, the controller or protocol layer of the first chip resets the parameters of the sending port to the parameters matched in the high-speed data transmission state. Similarly, the protocol layer or controller of the second chip resets the parameters of the receiving port to the parameters matched in the high-speed data transmission state according to the related code stream sent by the first chip.

[0164] After completing the transmission link repair, it is confirmed that the parameters of the ports at both ends of the repaired transmission link are the matching parameters in the high-speed data transmission state. The sending port can judge whether the port is repaired successfully according to the repair-related code stream sent and received. If it is judged that the sending port is not repaired successfully, the protocol layer is notified of the repair failure and returns to the LOW-POWER0 state; if it is judged that the port is repaired successfully, the RECOVERY state ends, and waits for the trigger condition of the next state. As can be seen from the above description, after the parameter configuration of the data transmission link is changed, a handshake process is added, a preliminary judgment on the accuracy of the repaired data transmission is performed, and the robustness of the transmission link is improved.

[0165] After completing the transmission link repair, the transmission link is controlled to enter the low-power state to wait for the next trigger condition.

[0166] The communication method provided by the embodiment of the application further includes a TRANS1 state, and specific details can be referred to the related description of the TRANS1 state in the method for controlling the transmission link. Figure 5 After completing the high-speed data transmission of the transmission link, the transmission link is controlled to enter the low-power state to wait for the trigger condition of the next state.

[0167] In addition, for the TRANS1 state, the transmission link can be triggered to enter the low-speed data transmission state by the low-speed data control code stream, and low-speed data transmission is performed; after completing the low-speed data transmission, the transmission link is controlled to enter the low-power state.

[0168] For the LOW-POWER1 state, when no data transmission is performed, the transmission link enters the ultra-low power state from the low-power state.

[0169] As can be seen from the above description, no matter what working state the transmission link is in, it jumps into the low power consumption state after completion, and the intercommunication between the states of the state machine is improved through the low power consumption state, the transmission link configuration process is reasonably arranged, and the conversion between any different states only needs to jump twice at most.

[0170] In the communication method in the embodiments of the present application, only Figure 10 The working process described above can also only include Figure 11 The working process described above, or can further include Figure 10 And Figure 11 The combination of the working processes described above.

[0171] The embodiments of the present application also provide a chip, which can be the first chip and the second chip described above. Specifically, reference can be made to the first chip or the second chip in the communication system described in Figure 8

[0172] When the chip is the first chip 100, and the first chip 100 mainly implements Figure 11 The working process described above, the first chip 100 includes a first sending port 101 and a first controller 105; the first controller 105 is configured to control the first sending port 101 to enter a repair state when a data transmission error is detected in a high-speed data transmission state; and send a repair control code stream to a peer chip (the second chip 200) to control a first receiving port 203 of the peer chip to enter the repair state; the first controller 105 is further configured to perform data repair on the first sending port 101 in the repair state, and repair parameters of the first sending port 101 to parameters of the first sending port 101 in the high-speed data transmission state; the first controller 105 is further configured to control the first sending port 101 to enter a low power consumption state or a high-speed data transmission state again after completing the data repair on the first sending port 101; wherein the transmission rate of the data in the high-speed data transmission state is greater than or equal to 1 Gbps. In a specific implementation, the first controller 105 is further configured to control the first sending port 101 to enter the low power consumption state after detecting the data transmission error and before controlling the first sending port 101 to enter the repair state. Facilitate state switching.

[0173] In addition, the first controller 105 is further configured to control the first sending port 101 to enter the low power consumption state before the first sending port 101 enters the high-speed data transmission state. After completing the data repair, and before controlling the first sending port 101 to enter the low power consumption state, it is confirmed that the parameters of the first sending port 101 after repair are the parameters of the first sending port 101 in the high-speed data transmission state. Improve the reliability of the transmission link.

[0174] ​When the transmission link is established, the first chip 100 further comprises a second receiving port 103; the second receiving port 103 is configured to receive port information of the first receiving port 203 sent by the second sending port 201 of the opposite chip; and the first controller 105 is further configured to control the first sending port 101 to establish the transmission link with the first receiving port 203 of the opposite chip, and to control the first sending port 101 to send the port information of the first sending port 101 to the first receiving port 203 of the opposite chip.

[0175] When the chip is the second chip 200, the second chip 200 comprises a first receiving port 203 and a second controller 205; the first receiving port 203 is configured to receive a repair control code stream sent by the first sending port 103 of the opposite chip (the first chip 100); the second controller 205 is configured to control the first receiving port 203 to enter a repair state according to the repair control code stream; wherein the repair control code stream is a repair control code stream for controlling the first receiving port 203 to switch to the repair state, which is generated by the first controller 105 of the opposite chip when the first controller 105 detects a data transmission error in the high-speed data transmission state; the second controller 205 is further configured to perform data repair on the first receiving port 203 in the repair state, and repair the parameters of the first receiving port 203 to the parameters of the first receiving port 203 in the high-speed data transmission state; the second controller 205 is further configured to control the first receiving port 203 to enter a low-power-consumption state or the high-speed data transmission state again after completing the data repair on the first receiving port 203; wherein in the high-speed data transmission state, the transmission rate of data is greater than or equal to 1 Gbps. For details, refer to the description in Figure 11 .

[0176] In addition, the second controller 205 is further configured to control the first receiving port 203 to enter the low-power-consumption state before the first receiving port 203 enters the high-speed data transmission state. In addition, the second controller 205 is further configured to control the first receiving port 203 to enter the low-power-consumption state after detecting the data transmission error and before controlling the first receiving port 203 to enter the repair state. The second controller 205 is further configured to confirm that the parameters of the first receiving port 203 after the repair are the parameters of the first receiving port 203 in the high-speed data transmission state after completing the data repair and before controlling the first receiving port 203 to enter the low-power-consumption state. The reliability of the transmission link is improved. For details, refer to the description in Figure 11 .

[0177] When the transmission link is established, the second chip 200 further comprises a second sending port 201; the second controller 205 is further configured to control the first receiving port 203 to establish a transmission link with the first sending port 103 of the opposite chip, and control the second sending port 201 to send the port information of the first receiving port 203 to the second receiving port 103 of the opposite chip; the first receiving port 203 is further configured to receive the port information of the first sending port 103 sent by the first sending port 103 of the opposite chip. For details, refer to the description in Figure 11 .

[0178] When the chip is used to implement the workflow shown in Figure 10 and Figure 11 , when the chip is the first chip, the first chip comprises a first sending port 101 and a first controller 105, the first controller 105 is configured to detect the current parameters of the first sending port 101 and determine whether the current parameters of the first sending port 101 are consistent with the parameters matched by the first sending port 101 when transmitting data at a target data transmission rate before the first sending port 101 enters a data transmission state; the first controller 105 is further configured to control the first sending port 101 to enter a rate switching state when the current parameters of the first sending port 101 are inconsistent with the parameters matched by the first sending port 101 at the target data transmission rate; the first controller 105 is further configured to switch the current parameters of the first sending port 101 to the parameters matched by the first sending port 101 when transmitting data at the target data transmission rate in the rate switching state; the first controller 105 is further configured to control the first sending port 101 to send a control code stream to the first receiving port 203 of the opposite chip to control the first receiving port 203 to enter the rate switching state; the first controller 105 is further configured to control the first sending port 101 to enter a low-power-consumption state after the switching is completed. For details, refer to the step flow shown in Figure 10 .

[0179] The first controller 105 is further configured to receive the data transmission control code stream and control the first sending port 101 to switch from the low-power state to a high-speed data transmission state or a low-speed data transmission state matching the target data transmission rate after the current parameters of the first sending port 101 are switched to the parameters matching the first sending port 101 when transmitting data at the target data transmission rate; the first controller 105 is further configured to control the first sending port 101 to send a control code stream to the first receiving port 203 of the opposite chip to control the first receiving port 203 to switch to the high-speed data transmission state or the low-speed data transmission state matching the target data transmission rate; wherein the high-speed data transmission rate is greater than the low-speed data transmission rate. In addition, the first controller 105 is further configured to control the first sending port 101 to enter the low-power state and enter the rate switching state from the low-power state when the data transmission rate changes during the data transmission process; the first controller 105 is further configured to control the current parameters of the first sending port 101 to switch to the parameters matching the first sending port 101 when transmitting data at the changed data transmission rate in the rate switching state; the first controller 105 is further configured to control the first sending port 101 to send a control code stream to the first receiving port 203 of the opposite chip to control the first receiving port 203 to enter the low-power state and the rate switching state; and the first controller 105 is further configured to control the first sending port 101 to enter the low-power state after the switching is completed. The first controller 105 is further configured to receive the data transmission control code stream and control the first sending port 101 to switch from the low-power state to a high-speed data transmission state or a low-speed data transmission state matching the target data transmission rate when the current parameters of the first sending port 101 are switched to the parameters matching the first sending port 101 when transmitting data at the changed data transmission rate; the first controller 105 is further configured to control the first sending port 101 to send a control code stream to the first receiving port 203 of the opposite chip to control the first receiving port 203 to switch to the high-speed data transmission state or the low-speed data transmission state matching the target data transmission rate. For details, please refer to the working process shown in Figure 10

[0180] ​The first controller 105 is further configured to control the first sending port 101 to enter a high-speed data transmission state for high-speed data transmission when the data transmission control code stream is a high-speed data transmission control code stream; the first controller 105 is further configured to control the first sending port 101 to enter a repair state when a data transmission error is detected in the high-speed data transmission state; and send a repair control code stream to the opposite chip to control the first receiving port 203 of the opposite chip to enter the repair state; the first controller 105 is further configured to perform data repair on the first sending port 101 in the repair state, and repair the parameters of the first sending port 101 to the parameters when the first sending port 101 is in the high-speed data transmission state; the first controller 105 is further configured to control the first sending port 101 to enter a low-power-consumption state or the high-speed data transmission state again after completing the data repair on the first sending port 101. The first controller 105 is further configured to control the first sending port 101 to enter the low-power-consumption state after detecting the data transmission error and before controlling the first sending port 101 to enter the repair state. For details, refer to the working process shown in Figure 11

[0181] When the chip is a second chip, the second chip includes a first receiving port 203 and a second controller 205. Before the first receiving port 203 enters a data transmission state, the first receiving port 203 is configured to receive a control code stream sent by the opposite chip to control the first receiving port 203 to enter a rate switching state; the second controller 205 is configured to control the first receiving port 203 to enter the rate switching state according to the control code stream for controlling the first receiving port 203 to enter the rate switching state; the second controller 205 is further configured to switch the current parameters of the first receiving port 203 to parameters matched by the first receiving port 203 when transmitting data at a target data transmission rate in the rate switching state; the second controller 205 is further configured to control the first receiving port 203 to enter a low-power-consumption state after completing the switching. The second controller 205 is further configured to control the first receiving port 203 to receive a control code stream for controlling the first receiving port 203 to switch to a high-speed data transmission state or a low-speed data transmission state matched by the target data transmission rate after the current parameters of the first receiving port 203 are switched to the parameters matched by the first receiving port 203 when transmitting data at the target data transmission rate, and control the first receiving port 203 to switch from the low-power-consumption state to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate according to the control code stream; wherein the high-speed data transmission rate is greater than the low-speed data transmission rate. For details, refer to the working process in Figure 10

[0182] ​​In the data transmission process, when the data transmission rate changes, the first receiving port 203 is configured to receive a control code stream sent by the opposite end chip to control the first receiving port 203 to enter a low-power state and a rate switching state; the second controller 205 is configured to control the first receiving port 203 to enter the low-power state according to the control code stream for controlling the first receiving port 203 to enter the low-power state and the rate switching state, and to enter the rate switching state after entering the low-power state; the second controller 205 is further configured to control the current parameters of the first receiving port 203 to switch to parameters matched by the first receiving port 203 when transmitting data at the changed data transmission rate in the rate switching state; the second controller 205 is further configured to control the first receiving port 203 to enter the low-power state after the switching is completed. The second controller 205 is further configured to control the first receiving port 203 to receive a control code stream for controlling the first receiving port 203 to switch to a high-speed data transmission state or a low-speed data transmission state matched by the target data transmission rate after the current parameters of the first receiving port 203 are switched to the parameters matched by the first receiving port 203 when transmitting data at the target data transmission rate, and to control the first receiving port 203 to switch from the low-power state to the high-speed data transmission state or the low-speed data transmission state matched by the target data transmission rate according to the control code stream. For details, please refer to the workflow in Figure 10 .

[0183] The second controller 205 is further configured to control the first receiving port 203 to enter the high-speed data transmission state for high-speed data transmission when the control code stream is a control code stream for controlling the first receiving port 203 to switch to the high-speed data transmission state; the second controller 205 is configured to control the first receiving port 203 to enter a repair state according to a repair control code stream; wherein the repair control code stream is a repair control code stream for controlling the first receiving port 203 to switch to the repair state generated by the first controller 105 of the opposite end chip when a data transmission error is detected in the high-speed data transmission state; the second controller 205 is further configured to perform data repair on the first receiving port 203 in the repair state to repair the parameters of the first receiving port 203 to the parameters when the first receiving port 203 is in the high-speed data transmission state; the second controller 205 is further configured to control the first receiving port 203 to enter the low-power state or the high-speed data transmission state again after completing the data repair on the first receiving port 203; the second controller 205 is further configured to control the first receiving port 203 to enter the low-power state after detecting the data transmission error and before controlling the first receiving port 203 to enter the repair state. For details, please refer to the workflow in Figure 11 .

[0184] It should be understood that the first chip and the second chip provided in the embodiments of the present application can also be applied to the modification of data transmission errors occurring in the low-speed data transmission state. The first controller and the second controller can perform the same repair process as when data transmission errors occur in the high-speed data state, which will not be described here again, and can be specifically referred to the description of data repair in Figure 5 and Figure 6 .

[0185] Figure 12 is another communication system to which the present application can be applied, comprising a first chip 300, a second chip 400 and an out-of-band control link. The first chip 300 only has the ability to receive data, and the second chip 400 only has the ability to send data. The out-of-band control link is a communication path outside the first chip 300 and the second chip 400, has certain bidirectional communication ability, and does not share a physical layer port with the first chip 300 and the second chip 400. Commonly used out-of-band control links are I2C, SPI, etc., and their main function is to transmit control information and configuration information from the protocol layer.

[0186] The first chip 300 to which the present application is applied comprises a protocol layer and a physical layer structure. The protocol layer is responsible for sending or receiving data information, sending and receiving control information of the out-of-band control link, and can control the physical layer according to the control information of the out-of-band control link. The physical layer comprises a first controller 303, a sending module or a receiving module. The first controller 303 and the second controller 403 are directly controlled by the protocol layer to realize the management of the corresponding sending module or receiving module of the first chip 300 and the second chip 400. The sending module includes a first data processing module 302 and a sending port 301. The first data processing module 302 performs operations such as encoding, scrambling, serial processing, etc. on the data information from the protocol layer to process the data information into a data packet, and then sends the data packet out through the sending port 301. The receiving module includes a second data processing module 402 and a receiving port 401. The receiving port 401 receives the data packet from the transmission link, and the second data processing module 402 performs operations such as decoding, descrambling, deserial processing, etc. on the data packet, and then transmits the data information to the protocol layer.

[0187] The present application manages the ports of the communication system through a port working mode state machine. The ports of the first chip 300 and the second chip 400 of the communication system perform power-on operation, high-speed data transmission operation, low-speed data transmission operation and ultra-low power consumption operation according to the port working mode management flow. In the communication system, the LINK-STARTUP state, the SPEED-CHANGE state and the RECOVERY state flow of the chip are as follows:

[0188] Figure 13The working flow of the port in the LINK-STARTUP state under the communication system architecture is shown. After the initialization of the port is completed, the receiving port controlled by the protocol layer of the first chip enters the LINK-STARTUP state. The protocol layer can exchange basic information with the sending port of the second chip through the out-of-band control link, and negotiate the rate of the in-band communication. The physical layer configures the port parameters according to the basic information of the two ports and the negotiated in-band communication rate, and communicates on the in-band transmission link at the negotiated rate. If the communication is successful, the condition for entering the next state is waited for; if the communication fails, the protocol layer is notified, and the PHY-INIT state is returned.

[0189] Figure 14 The working flow of the port in the SPEED-CHANGE state under the communication system architecture is shown. When the protocol layer needs to change the current in-band communication rate, the target communication rate of the in-band transmission link can be negotiated with the opposite port through the out-of-band control link. Then the protocol layer instructs the physical layer port to end the current state (LOW-POWER0 state or TRANS0 state or TRANS1 state) and enter the SPEED-CHANGE state. The physical layer configures the port parameters according to the negotiated target data transmission rate of the in-band transmission link, and communicates on the in-band transmission link at the negotiated rate. If the communication is successful, the condition for entering the next state is waited for; if the communication fails, the protocol layer is notified, and the LOW-POWER0 state is returned.

[0190] Figure 15 The working flow of the port in the RECOVERY state under the communication system architecture is shown. When an error occurs in the in-band data transmission link during communication, the protocol layer confirms the error type of the in-band transmission link with the opposite port through the out-of-band control link. Then the protocol layer instructs the physical layer port to end the current state (LOW-POWER0 state or TRANS1 state) and enter the RECOVERY state. The physical layer sends or receives the repair-related code stream on the in-band transmission link according to the error type, and takes repair measures on the in-band communication transmission link according to the repair-related code stream. The repair-related code stream can include but is not limited to receiver bit synchronization code stream and receiver equalization training code stream. If the repair is successful, the condition for entering the next state is waited for; if the repair fails, the protocol layer is notified, and the LOW-POWER0 state is returned.

[0191] It should be understood that the above first chip, second chip and out-of-band control link provided in the embodiments of the present application can also be applied to the modification of the low-speed transmission data state when a data transmission error occurs. The first chip, the second chip and the out-of-band control link can perform the same repair process as when a data transmission error occurs in the high-speed data state, which is not described here again, and can be referred to the description of the data repair in Figure 5 and Figure 6 .

[0192] As can be seen from the above description, the embodiment of the application provides a high-speed communication method, which increases the handshake process of a port after reconfiguring a transmission link parameter, and judges the data transmission accuracy of the transmission link; and the intercommunication between states of a state machine is improved through a low-power state, and the number of jumps between different states of the port is reduced.

[0193] The embodiment of the application also provides a mobile terminal, which comprises a chip and an opposite chip in communication connection with the chip; wherein the chip and the opposite chip are respectively the chip of any one of the above. In the above scheme, the transmission link is repaired when a fault occurs in high-speed data transmission through the setting of a repair state, and the reliability of high-speed data transmission is improved. In addition, only the matching parameters corresponding to the high-speed data transmission are repaired in the repair, and the matching of the basic information of the two chips in the handshake is not required again, and the repair effect is improved.

[0194] As shown in Figure 16 The embodiment of the application also provides a signal processing module 1000 for realizing the functions of the above method. The signal processing module 1000 can be a communication device or a device in the communication device. The signal processing module 1000 comprises at least one processor 1001 for realizing the functions of the device in the above method. For example, the processor 1001 can be used for controlling the state switching of the communication port 1003 (the sending port) according to the acquired transmission and reception requirement of the first chip, and the detailed description is referred to the method, which is not described here.

[0195] In some embodiments, the signal processing module 1000 can also comprise at least one memory 1002 for storing program instructions and / or data. The memory 1002 and the processor 1001 are coupled. The coupling in the embodiment of the application is the spaced coupling or communication connection between the devices, units or modules, which can be electrical, mechanical or other forms, and is used for the information interaction between the devices, units or modules. As another implementation, the memory 1002 can also be located outside the signal processing module 1000. The processor 1001 can operate in cooperation with the memory 1002. The processor 1001 can execute the program instructions stored in the memory 1002. At least one of the at least one memory can be included in the processor.

[0196] In some embodiments, the signal processing module 1000 includes a communication port 1003 for communicating with other devices through a transmission medium, so that the devices in the signal processing module 1000 can communicate with other devices. For example, the communication port 1003 can be a transceiver, a circuit, a bus, a module or other types of communication ports, and the other devices can be network devices or other terminal devices, etc. The processor 1001 transceives data using the communication port 1003, and is used to implement the methods in the above embodiments. For example, the communication port 1003 can be used to transmit signals.

[0197] The connection medium between the communication port 1003, the processor 1001 and the memory 1002 in the embodiments of the present application is not limited. For example, in the embodiments of the present application, the memory 1002, the processor 1001 and the communication port 1003 can be connected by a bus, and the bus can be divided into an address bus, a data bus, a control bus, etc. Figure 16

[0198] In the embodiments of the present application, the processor can be a general processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. The general processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as hardware processor execution or executed by a combination of hardware and software modules in the processor.

[0199] In the embodiments of the present application, the memory can be a non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., and can also be a volatile memory such as a random-access memory (RAM). The memory can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited to this. The memory in the embodiments of the present application can also be a circuit or other any device capable of realizing a storage function, used for storing program instructions and / or data.

[0200] ​The method provided by the embodiments of the present application can be implemented by software, hardware, firmware or any combination thereof, in whole or in part. When implemented by software, the method can be implemented in the form of a computer program product, in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the whole or part of the process or function according to the embodiments of the present application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, an SSD), etc.

[0201] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. A communication method, characterized in that: The following steps are involved: When a data transmission error is detected in a data transmission state, controlling both a transmitting port and a receiving port to enter a repair state, wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state, the transmitting port is located on a master chip side, and the receiving port is located on a slave chip side in a communication relationship with the master chip; In the repair state, performing data repair on the sending port and the receiving port, repairing the parameters of the sending port to the parameters when the sending port is in the data transmission state, and repairing the parameters of the receiving port to the parameters when the receiving port is in the data transmission state; After completing the data repair of the sending port and the receiving port, controlling the sending port and the receiving port to enter a low power consumption state or to enter the high-speed data transmission state again; When a data transmission error is detected, both the sending port and the receiving port are controlled to enter a repair state; specifically: When the data transmission error is detected, the sending port is controlled to enter the repair state, and a repair control code stream is sent to the slave chip, so that the protocol layer or controller of the slave chip controls the receiving port to enter the repair state according to the repair control code stream.

2. The communication method according to claim 1, wherein: After detecting the data transmission error and before controlling both the sending port and the receiving port to enter the repair state, the method further includes: Control the sending port and the receiving port to enter a low power consumption state.

3. The communication method according to claim 1, wherein: The controlling the sending port and the receiving port to enter a repair state specifically refers to: The transmitting port and the receiving port are controlled to enter the repairing state from the low power consumption state.

4. The communication method according to any one of claims 1 to 3, wherein: Also includes: After completing the data repair and before controlling both the sending port and the receiving port to enter the low power consumption state, the method further includes: confirming that the parameters of the sending port after repair are the parameters when the sending port is in the data transmission state and the parameters of the receiving port are the parameters when the receiving port is in the data transmission state.

5. The communication method according to claim 1, wherein: Before the data transmission state in which the data transmission error is detected, both the sending port and the receiving port are in the low power consumption state.

6. The communication method according to claim 1, wherein: Before both the transmitting port and the receiving port enter the low power consumption state for the first time, the method further includes: A transmission link is established between the master chip and the slave chip, and port information is exchanged, wherein the port information exchange refers to the master chip sending the port information of the sending port to the slave chip, and the slave chip sending the port information of the receiving port to the master chip; After completing the port information exchange, both the sending port and the receiving port enter the low power consumption state for the first time.

7. The communication method according to any one of claims 1 to 3 or 5 to 6, wherein: Also includes: After completing the data transmission, the sending port and the receiving port are controlled to enter the low power consumption state to wait for the next state triggering condition.

8. A communication method, characterized in that: The method includes: Before a sending port and a receiving port enter a data transmission state, detecting current parameters of the sending port and current parameters of the receiving port, and determining whether the current parameters of the sending port are consistent with parameters matched when the sending port sends data at a target data transmission rate, and determining whether the current parameters of the receiving port are consistent with parameters matched when the receiving port receives data at the target data transmission rate, the sending port being located on a master chip side, and the receiving port being located on a slave chip side having a communication relationship with the master chip; When the current parameters of the sending port and the receiving port are inconsistent with the parameters matched by them at the target data transmission rate, controlling the sending port and the receiving port to enter a rate switching state; In the rate switching state, current parameters of the sending port are switched to parameters that match when the sending port sends data at a target data transmission rate, and parameters of the receiving port are switched to parameters that match when the receiving port receives data at the target data transmission rate; After the switching is completed, both the sending port and the receiving port enter a low power consumption state.

9. The communication method according to claim 8, wherein: Also includes: After the current parameters of the sending port are switched to the parameters that match the sending port when sending data at the target data transmission rate, and the current parameters of the receiving port are switched to the parameters that match the receiving port when receiving data at the target data transmission rate, a data transmission control code stream is received and the control transmission link is switched from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data, and the high-speed data transmission rate is greater than the low-speed data transmission rate.

10. The communication method according to claim 8 or 9, wherein: Also includes: During data transmission, when the data transmission rate changes, controlling the transmitting port and the receiving port to enter the low power consumption state, and then to enter the rate switching state from the low power consumption state; In the rate switching state, current parameters of the sending port are switched to parameters that the sending port matches when transmitting data at the changed data transmission rate, and current parameters of the receiving port are switched to parameters that the receiving port matches when receiving data at the changed data transmission rate; After the switching is completed, the sending port and the receiving port are controlled to enter the low power consumption state.

11. The communication method according to claim 10, wherein: Also includes: When the current parameters of the sending port are switched to parameters that match the sending port when sending data at the changed data transmission rate, and the current parameters of the receiving port are switched to parameters that match the receiving port when receiving data at the changed data transmission rate, a data transmission control code stream is received and the transmission link is controlled to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data.

12. The communication method according to claim 9 or 11, wherein: Also includes: When a data transmission error is detected in the data transmission state, controlling both the sending port and the receiving port to enter a repair state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; In the repair state, performing data repair on the sending port and the receiving port, repairing the parameters of the sending port to the parameters when the sending port is in the data transmission state, and repairing the parameters of the receiving port to the parameters when the receiving port is in the data transmission state; After completing the data repair of the sending port and the receiving port, the sending port and the receiving port are controlled to enter a low power consumption state or to enter the high-speed data transmission state again.

13. The communication method according to claim 12, wherein: After detecting the data transmission error and before controlling both the sending port and the receiving port to enter the repair state, the method further includes: Control the sending port and the receiving port to enter a low power consumption state.

14. A chip, characterized in that: The device comprises a first transmitting port and a first controller; the first controller is configured to, upon detecting a data transmission error in a data transmission state, control the first transmitting port to enter a repair state; and transmit a repair control code stream to a peer chip for controlling a first receiving port of the peer chip to enter a repair state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; The first controller is further configured to perform data repair on the first sending port in the repair state, and repair the parameters of the first sending port to the parameters when the first sending port is in the data transmission state; The first controller is further configured to control the first sending port to enter a low power consumption state or to re-enter the high-speed data transmission state after completing data repair on the first sending port.

15. The chip according to claim 14, wherein: The first controller is further configured to control the first sending port to enter a low power consumption state after detecting the data transmission error and before controlling the first sending port to enter the repair state.

16. The chip according to claim 14 or 15, characterized in that: The first controller is further configured to, after completing the data repair and before controlling the first sending port to enter the low power consumption state, confirm that the parameters of the first sending port after repair are the parameters when the first sending port is in the data transmission state.

17. The chip according to claim 14 or 15, characterized in that: The first controller is further configured to control the first transmitting port to enter a low power consumption state before the first transmitting port enters the high-speed data transmission state.

18. The chip according to claim 14 or 15, characterized in that The chip further includes a second receiving port; the second receiving port is used to receive the port information of the first receiving port sent by the second sending port of the opposite chip; The first controller is further configured to control the first transmitting port to establish a transmission link with the first receiving port of the opposite chip, and control the first transmitting port to send port information of the first transmitting port to the first receiving port of the opposite chip.

19. A chip, characterized in that: It includes a first receiving port and a second controller; the first receiving port is used to receive the repair control code stream sent by the first sending port of the opposite chip; The second controller is configured to control the first receiving port to enter a repair state according to the repair control code stream; wherein the repair control code stream is a repair control code stream generated by the first controller of the opposite chip when a data transmission error is detected in the data transmission state and is used to control the first receiving port to switch to the repair state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; The second controller is further configured to perform data repair on the first receiving port in the repair state, and repair the parameters of the first receiving port to the parameters when the first receiving port is in the data transmission state; The second controller is further configured to control the first receiving port to enter a low power consumption state or to re-enter the high-speed data transmission state after completing data repair on the first receiving port.

20. The chip according to claim 19, wherein: The second controller is further configured to control the first receiving port to enter a low power consumption state after detecting the data transmission error and before controlling the first receiving port to enter the repairing state.

21. The chip according to claim 19 or 20, characterized in that The second controller is further configured to, after completing the data repair and before controlling the first receiving port to enter the low power consumption state, confirm that the parameters of the first receiving port after repair are the parameters when the first receiving port is in the data transmission state.

22. The chip according to claim 19 or 20, characterized in that The second controller is further configured to control the first receiving port to enter a low power consumption state before the first receiving port enters the high-speed data transmission state.

23. The chip according to claim 19 or 20, characterized in that Also includes a second transmitting port; the second controller is further used to control the first receiving port to establish a transmission link with the first transmitting port of the opposite chip, and control the second transmitting port to send the port information of the first receiving port to the second receiving port of the opposite chip; The first receiving port is further configured to receive port information of the first transmitting port sent by the first transmitting port of the opposite chip.

24. A chip, characterized in that: The device comprises a first sending port and a first controller, wherein the first controller is configured to detect current parameters of the first sending port and determine whether the current parameters of the first sending port are consistent with parameters matched when the first sending port sends data at a target data transmission rate before the first sending port enters a data transmission state; The first controller is further configured to control the first sending port to enter a rate switching state when a current parameter of the first sending port is inconsistent with a parameter matched by the first sending port at a target data transmission rate; The first controller is further configured to, in the rate switching state, switch current parameters of the first sending port to parameters that match when the first sending port sends data at a target data transmission rate; The first controller is further configured to control the first transmitting port to transmit a control code stream to the first receiving port of the opposite chip to control the first receiving port to enter a rate switching state; The first controller is further configured to control the first sending port to enter a low power consumption state after the switching is completed.

25. The chip according to claim 24, wherein: The first controller is further configured to receive a data transmission control code stream and control the first transmitting port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data after the current parameters of the first transmitting port are switched to parameters that match the first transmitting port when transmitting data at a target data transmission rate; The first controller is further configured to control the first transmitting port to transmit a control code stream to the first receiving port of the opposite chip, for controlling the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data; The high-speed data transmission rate is greater than the low-speed data transmission rate.

26. The chip according to claim 24 or 25, characterized in that The first controller is further configured to control the first transmitting port to enter the low power consumption state and enter the rate switching state from the low power consumption state when the data transmission rate changes during the data transmission process; The first controller is further configured to, in the rate switching state, control the current parameters of the first sending port to switch to parameters that match the first sending port when transmitting data at the changed data transmission rate; The first controller is further configured to control the first transmitting port to transmit a control code stream to the first receiving port of the opposite chip, controlling the first receiving port to enter a low power consumption state and a rate switching state; The first controller is further configured to control the first sending port to enter the low power consumption state after the switching is completed.

27. The chip according to claim 26, wherein: The first controller is further configured to receive a data transmission control code stream and control the first transmitting port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data when the current parameters of the first transmitting port are switched to parameters that match the first transmitting port when transmitting data at the changed data transmission rate; The first controller is also used to control the first sending port to send a control code stream to the first receiving port of the opposite chip to control the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data.

28. The chip according to claim 25 or 27, wherein: The first controller is further configured to, upon detecting a data transmission error in a data transmission state, control the first transmitting port to enter a repair state; and transmit a repair control code stream to the opposite chip to control the first receiving port of the opposite chip to enter a repair state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; The first controller is further configured to perform data repair on the first sending port in the repair state, and repair the parameters of the first sending port to the parameters when the first sending port is in the data transmission state; The first controller is further configured to control the first sending port to enter a low power consumption state or to re-enter the high-speed data transmission state after completing data repair on the first sending port.

29. The chip according to claim 28, wherein The first controller is further configured to control the first sending port to enter a low power consumption state after detecting the data transmission error and before controlling the first sending port to enter the repair state.

30. A chip, characterized in that: comprising a first receiving port and a second controller, Before the first transmitting port enters the data transmission state, the first receiving port is used to receive a control code stream sent by the opposite end chip to control the first receiving port to enter the rate switching state; The second controller is configured to control the first receiving port to enter a rate switching state according to a control code stream; and control the first receiving port to enter a rate switching state according to the control code stream; The second controller is further configured to, in the rate switching state, switch current parameters of the first receiving port to parameters that match when the first receiving port sends data at a target data transmission rate; The second controller is further configured to control the first receiving port to enter a low power consumption state after the switching is completed.

31. The chip according to claim 30, wherein The second controller is further configured to, after current parameters of the first receiving port are switched to parameters that match the first receiving port when sending data at a target data transmission rate, control the first receiving port to receive a control code stream that controls the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data, and control the first receiving port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data according to the control code stream; The high-speed data transmission rate is greater than the low-speed data transmission rate.

32. The chip according to claim 30 or 31, wherein: During data transmission, when the data transmission rate changes, the first receiving port is used to receive a control code stream sent by the opposite chip to control the first receiving port to enter a low power consumption state and a rate switching state; The second controller is configured to control the first receiving port to enter a low power state and a rate switching state according to a control code stream; and control the first receiving port to enter a low power state according to the control code stream, and to enter a rate switching state after entering the low power state; The second controller is further configured to control, in the rate switching state, current parameters of the first receiving port to be switched to parameters that match when the first receiving port transmits data at the changed data transmission rate; The second controller is further configured to control the first receiving port to enter the low power consumption state after the switching is completed.

33. The chip according to claim 32, wherein: The second controller is also used to control the first receiving port to receive a control code stream that controls the first receiving port to switch to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data after the current parameters of the first receiving port are switched to parameters that match the first receiving port when sending data at the target data transmission rate, and control the first receiving port to switch from the low power consumption state to a high-speed data transmission state or a low-speed data transmission state that matches the transmission rate of the target data according to the control code stream.

34. The chip according to claim 31 or 33, wherein: The second controller is further configured to control the first receiving port to enter a repair state according to a repair control code stream; wherein the repair control code stream is a repair control code stream generated by the first controller of the opposite chip when a data transmission error is detected in a high-speed data transmission state and is used to control the first receiving port to switch to the repair state; The second controller is further configured to perform data repair on the first receiving port in the repair state, and repair the parameters of the first receiving port to the parameters when the first receiving port is in the data transmission state; wherein the data transmission state includes a high-speed data transmission state and a low-speed data transmission state; The second controller is further configured to control the first receiving port to enter a low power consumption state or to re-enter the high-speed data transmission state after completing data repair on the first receiving port.

35. The chip according to claim 34, wherein The second controller is further configured to control the first receiving port to enter a low power consumption state after detecting the data transmission error and before controlling the first receiving port to enter the repairing state.

36. A communication system, characterized in that: comprising a first chip and a second chip; wherein the first chip is the chip according to any one of claims 14 to 18; the second chip is the chip according to any one of claims 19 to 23; or, The first chip is the chip according to any one of claims 24 to 29, and the second chip is the chip according to any one of claims 30 to 35.

37. A mobile terminal, characterized in that: comprising a first chip and a second chip; wherein the first chip is the chip according to any one of claims 14 to 18; the second chip is the chip according to any one of claims 19 to 23; or, The first chip is the chip according to any one of claims 24 to 29, and the second chip is the chip according to any one of claims 30 to 35.

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