Sequential slc read optimization

Abstract

Systems and methods for read operations and management are disclosed. More specifically, the disclosure relates to receiving a first read command directed to a first logical address, and receiving a second read command directed to a second logical address after the first read command. The method also includes receiving a third read command directed to a third logical address after the second read command, and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component, while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command in sequence.

Description

TECHNICAL FIELD

[0001] Embodiments of the disclosure generally relate to memory subsystems, and more specifically, to sequential SLC read optimization. BACKGROUND

[0002] A memory subsystem can be a storage system, such as a solid state drive (SSD), and can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the disclosure is described.

[0005] Figure 2A An example of a memory component according to some embodiments of the disclosure is described.

[0006] Figure 2B An example of a read order at a memory component according to some embodiments of the disclosure is described.

[0007] Figure 3 A flowchart of an example method of executing a read command at a memory component of a memory subsystem using read optimization according to some embodiments of the disclosure is described.

[0008] Figure 4 A flowchart of an example method of reading data at a memory component of a memory subsystem using read optimization according to some embodiments of the disclosure is described.

[0009] Figure 5 A block diagram of an example computer system in which embodiments of the disclosure can operate is described. DETAILED DESCRIPTION

[0010] Aspects of the disclosure relate to managing a memory subsystem and optimizing read operations performed in the memory subsystem. The memory subsystem can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Embodiments of the disclosure are described below in connection with Figure 1 Examples of a storage device and a memory module are described. Generally, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0011] A memory subsystem may include multiple memory components capable of storing data. Each memory component may contain a different type of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory and flash-based memory, such as single-level-cell (SLC) memory, three-level-cell (TLC) memory, and four-level-cell (QLC) memory. The characteristics of different types of media may differ between one media type and another. One example of a characteristic associated with a memory component is data density. Data density corresponds to the amount of data (e.g., data bits) that can be stored per memory cell of the memory component. Using an example of flash-based memory, a four-level-cell (QLC) memory can store four data bits, while a single-level-cell (SLC) memory can store one data bit. Therefore, a memory component containing QLC memory cells will have a higher data density than a memory component containing SLC memory cells. Another example of a memory component characteristic is access speed. Access speed corresponds to the amount of time it takes for the memory component to access data stored at the memory component. The methods and systems disclosed herein can be implemented in SLC, TLC, and QLC memories.

[0012] Memory cells are the basic building blocks of computer memory. A memory cell is an electronic circuit that stores one bit of binary information, and is configured to store logic 1 (high voltage level) and reset to store logic 0 (low voltage level). The value of the memory cell can be maintained / stored until the value is changed through a set / reset process. The value can be accessed by reading the value from the memory cell. Memory cells can be etched onto a silicon wafer in an array of columns (bit lines) and rows (word lines). The intersections of the bit lines and word lines constitute the address of the memory cell.

[0013] Memory cells may have a supporting infrastructure of dedicated circuitry. This circuitry performs functions such as: identifying each row and column (row address selection and column address selection); maintaining the refresh order (counter); reading and recovering signals from the cell (sensor amplifier); and informing the cell whether it should be charged (write enable). Other functions of the memory controller include a series of tasks such as identifying the type, speed, and amount of memory, and checking for errors.

[0014] A conventional memory subsystem contains memory components holding the data to be read. Data can be read for various reasons, including software implementation, host system functionality, data compression, and garbage collection. Typically, the controller executes read commands sequentially in the order they are received. That is, if the controller receives a first read command, then a second read command, and finally a third read command, it will execute the first read command first, then the second read command, and then the third read command, respectively.

[0015] However, sequentially executing read commands can consume excessive power, time, and resources. To read a data value from a physical address, a controller typically performs a non-selected word line set, a selected word line set, and reads data at the physical address. The controller typically performs this process to read data at each physical address. Often, the controller must read data values from physical addresses that share a word line but are not sequential in a read command queue. Traditionally, the controller executes read commands in the order that the controller receives the read commands. For example, if the controller receives a read command 1 for a first memory address, then receives a read command 2 for a second memory address, and then receives a read command 3 for a third memory address, the controller will execute read command 1, then execute read command 2, and finally execute read command 3. In other words, the controller executes read commands in a first-come, first-served order. The controller does not take into account the physical addresses of the memory cells being read. To execute a read command, the controller performs a selected word line set and a non-selected word line set. Thus, the controller performs a first selected word line set and a non-selected word line set to read the first memory address, a second selected word line set and a non-selected word line set to read the second memory address, and a third selected word line set and a non-selected word line set to read the third memory address. However, in some cases, the first memory address and the third memory address can be read using the same selected word line set and non-selected word line set because the first memory address and the third memory address are associated with the same physical word line. But because the controller does not take into account the physical addresses of the memory cells when executing read commands, the controller cannot take advantage of reading data from two memory addresses by using the same selected word line set and non-selected word line set.

[0016] The present disclosure is directed to reordering the order of read commands so as to take advantage of memory addresses that can be read together due to a shared physical characteristic (e.g., a word line). In the above example, embodiments of the present disclosure can reorder the order of read commands so that the controller performs a first non-selected word line set and a selected word line set to read the first memory address and the third memory address, and performs a second non-selected word line set and a selected word line set to read the second memory address. Thus, the controller can reorder the execution of read commands so that read commands directed to physical addresses that share a physical characteristic (e.g., a shared word line or bit line) are executed sequentially even though the controller does not receive the read commands from the host system sequentially. Thus, the number of non-selected word line sets and selected word line sets required to execute a batch / series of read commands is reduced. The reduction in non-selected word line sets and selected word line sets reduces cost by reducing the amount of time and resources required to execute non-selected word line sets and selected word line sets.

[0017] Figure 1An example computing environment 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is described. The memory sub-system 110 can include media, such as memory components 112A to 112N. The memory components 112A to 112N can be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory sub-system is a storage system. An example of a storage system is an SSD. In some embodiments, the memory sub-system 110 is a hybrid memory / storage sub-system. Generally, the computing environment 100 can include a host system 120 that uses the memory sub-system 110. For example, the host system 120 can write data to the memory sub-system 110 and read data from the memory sub-system 110.

[0018] The host system 120 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device. The host system 120 can include or be coupled to the memory sub-system 110, such that the host system 120 can read data from or write data to the memory sub-system 110. The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120.

[0019] The memory components 112A-112N can include any combination of different types of non-volatile and / or volatile memory components. Examples of non-volatile memory components include negative-and (NAND)-type flash memory. Each of the memory components 112A-112N can include one or more arrays of memory cells, such as single-level cell (SLC) or multi-level cell (MLC) (e.g., triple-level cell (TLC) or quad-level cell (QLC)). In some embodiments, a particular memory component can include both SLC and MLC portions of memory cells. Each of the memory cells can store one or more bits of data (e.g., a block of data) used by the host system 120. While non-volatile memory components such as NAND-type flash memory are described, the memory components 112A-112N can be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A-112N can be, but are not limited to, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or negative-or (NOR) flash memory, electrically erasable programmable read only memory (EEPROM), and cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can base bit storage on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. Furthermore, the memory cells of the memory components 112A-112N can be grouped into memory pages or blocks, which can refer to units of the memory components used to store data.

[0020] The memory system controller 115 (hereinafter referred to as the “controller”) can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N, and other such operations. The controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 has been illustrated as including the controller 115, in another embodiment of the present disclosure the memory sub-system 110 can not include the controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system). Figure 1

[0021] In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address associated with the memory components 112A to 112N. The controller 115 can also include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory components 112A to 112N, as well as convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0022] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive and decode an address from the controller 115 to access the memory components 112A to 112N.​

[0023] Memory sub-system 110 includes a read optimization component 113 that can be used to optimize reads of data in memory components 112A, 112N. In some embodiments, controller 115 includes at least a portion of read optimization component 113. For example, controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, read optimization component 113 is part of host system 120, an application, or an operating system.

[0024] Read optimization component 113 can reorder read commands to allow more efficient use of resources. In one example, a program running in host system 120 can specify or determine a first logical memory address, a second logical memory address, and a third logical memory address. The first, second, and third logical memory addresses can be determined by a central processing unit (CPU) of host system 120. A logical address is a virtual address because it does not physically exist. This logical address is used as a reference to access a physical address in memory components 112A-112N by the CPU. A hardware device called a memory management unit (MMU) can map the logical address to its corresponding physical address. A physical address identifies a physical location of data in memory components 112A-112N. Host system 120 can access the physical address by using its corresponding logical address. A relocation register can be used to map the logical address to the physical address in various ways. In some examples, when the CPU generates a logical address (e.g., 345), the MMU can generate a relocation register (e.g., 300) that is added to the logical address to identify the location of the physical address (e.g., 345 + 300 = 645).

[0025] To obtain data stored in the first, second, and third logical memory addresses, host system 120 can send a series of read commands to controller 115: a read command 1 for the first logical memory address, followed by a read command 2 for the second logical memory address, and finally a read command 3 for the third logical memory address, where read command 1 is received by controller 115 at a first time, read command 2 is received by controller 115 at a second time, and read command 3 is received by controller 115 at a third time. Read optimization component 113 can then use the MMU to identify a first physical memory address associated with the first logical memory address, a second physical memory address associated with the second logical memory address, and a third physical memory address associated with the third logical memory address.

[0026] The precise locations of the first physical address, the second physical address, and the third physical address can be determined by the design of the memory components 112A-112N. In the memory components 112A-112N, there can be a series of bit lines that extend in a first direction underneath the memory components 112A-112N. Each bit line can define a sub-block of memory of the memory components 112A-112N. The memory components 112A-112N can also have a series of word lines that extend in a second direction across the sub-blocks. The intersection of each word line with each bit line can be identified as a memory address. Thus, the controller 115 can identify the location of a physical memory address by identifying the word line and bit line intersection of the physical memory address. To read data at a physical memory address, the controller 115 can perform a non-selected word line set on all word lines that are not associated with the physical memory address, and perform a selected word line set on the word line that intersects the sub-block of the physical memory address. The non-selected word line set can include applying a first voltage across the non-selected word lines, and the selected word line set can include applying another given voltage across the selected word line. After performing the non-selected word line set and the selected word line set, the controller 115 can read a data value from the sub-block and send the data value to the host system 120.

[0027] The controller 115 can perform the following sequence in order to read data at the first physical address, the second physical address, and the third physical address. To read data located in the first physical address associated with the first logical memory address, the controller 115 can perform a non-selected word line set on the non-selected word lines, and perform a selected word line set on the word line associated with the first physical address. Then, to read data located in the second physical address associated with the second logical memory address, the controller 115 can perform a non-selected word line set on the non-selected word lines, and perform a selected word line set on the word line associated with the second physical address. Finally, to read data located in the third physical address associated with the third logical memory address, the controller 115 can perform a non-selected word line set on the non-selected word lines, and perform a selected word line set on the word line associated with the third physical address.

[0028] As shown above, the progression of the non-selected word line set and the selected word line set can be referred to as an order. The above progression of the non-selected word line set and the selected word line set can be referred to as a sequential set order, because the controller 115 performs the order according to first-come-first-served based on the time of receiving the read commands. If the controller is to read data in the first physical address, the second physical address, and the third physical address according to the above sequential set order, the controller 115 will perform a total of three non-selected word line sets and three selected word line sets.

[0029] Traditionally, the controller 115 would read the first physical address, the second physical address, and the third physical address without regard to any physical association between the addresses. However, the read optimization component 113 can recognize that the first physical address associated with the first memory address and the third physical address associated with the third memory address are associated with the same physical location (e.g., word line, bit line, etc.). In this example, the first physical address associated with the first logical memory address and the third physical address associated with the third logical memory address share a word line.

[0030] To reduce the amount of non-selected word line setup and selected word line setup, the read optimization component 113 can reorder the order in which the controller 115 reads the first physical address, the second physical address, and the third physical address such that the controller 115 reads both the data at the first physical address and the third physical address when the controller 115 performs the non-selected word line setup and the selected word line setup for the first physical address. The controller 115 can then perform the non-selected word line setup and the selected word line setup to read the data at the second physical address. Alternatively, the controller 115 can read the data at the second physical address, the first physical address, and the third physical address. Other read orders are also possible (e.g., third physical address, first physical address, second physical address; and second physical address, third physical address, first physical address). Thus, to read the data at the three physical addresses, the read optimization component 113 can instruct the controller 115 to perform a total of two non-selected word line setups and two selected word line setups. In this example, the read optimization component 113 can cause the controller 115 to avoid performing two word line setups. The cumulative reduction in non-selected word line setups and selected word line setups reduces costs by reducing the amount of time and resources required to perform the read command.

[0031] Figure 2AAn example of a memory component according to some embodiments of the disclosure is illustrated. Data block 200 contains sub-block 0 202, sub-block 1 204, sub-block 2 206, and sub-block 3 208 that share the same word line. Thus, when controller 115 wants to read data at any memory location in sub-block 0 202, sub-block 1 204, sub-block 2 206, and sub-block 3 208, controller 115 can use the same non-selected word line (WL) and selected word line (WL) set sequence. As disclosed above, this is valid if the sub-blocks sharing the same word line are read in sequential order. Reading sub-block 0 202, sub-block 1 204, sub-block 2 206, and sub-block 3 208 in sequential order can mean that controller 115 reads the sub-blocks sequentially without any intervening reads of another sub-block that does not share the same word line (e.g., read sub-blocks 0, 1, 2, 3; 1, 2, 3, 0; 3, 1, 0, 2, etc.). In another example, sub-block 0 202, sub-block 1 204, sub-block 2 206, and sub-block 3 208 can share the same non-selected bit line (BL) and selected bit line (BL) set sequence.

[0032] Figure 2B An example of a read sequence at a memory component according to some embodiments of the disclosure is illustrated. Read operation 210 shows how sub-block 0 202 and sub-block 1 204 can be read in sequence. Controller 115 can perform one non-selected word line set 220 and one selected word line set 222 in order to get data 216 from sub-block 0 202 and data 218 from sub-block 1 204. Non-selected word line set 220 takes a given amount of time 212 (e.g., X μβ), and selected word line set 222 takes a given amount of time 214 (e.g., Y μβ). Without read optimization component 113, if controller 115 receives another read command for a sub-block associated with a different word line between receiving a read command for sub-block 0 202 and a read command for sub-block 1 204, controller 115 will initiate a separate non-selected word line set and selected word line set to read sub-block 1 204. The present disclosure presents methods and systems for reordering the execution of read commands in order to limit the amount of non-selected word line sets and selected word line sets required to read data at physical memory addresses in a read command queue.

[0033] Figure 3 A flowchart of an example method for executing read commands at a memory component of a memory subsystem using read optimization according to some embodiments of the disclosure. Method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by Figure 1The read optimization component 113 performs. Although shown in a particular order or sequence, the order of the processes can be modified unless otherwise specified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated processes can be performed in different orders, and that some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0034] At block 302, a processing device can receive a first read command directed to a first logical address. The processing device (e.g., controller 115) can receive a first read command directed to a logical address from the host system 120. The host system 120 can send a read command to the controller 115 in order to obtain data at a first physical address associated with the first logical address. The read command can be sent based on a request of a program running in the host system 120.

[0035] At block 304, the processing device can receive a second read command directed to a second logical address after the first read command. The host system 120 can send a second read command to the controller 115 in order to obtain data at a second physical address associated with the second logical address.

[0036] At block 306, the processing device can receive a third read command directed to a third logical address after the second read command. The host system 120 can send a third read command to the controller 115 in order to obtain data at a third physical address associated with the third logical address.

[0037] At block 308, the processing device can determine that the first logical address corresponds to a first physical address, the third logical address corresponds to a third physical address, the first physical address and the third physical address are associated with a first word line of the memory component, and the second logical address corresponds to a second physical address associated with a second word line of the memory component. The read optimization component 113 can identify that the first physical address associated with the first logical address and the third physical address associated with the third logical address are associated with the same physical location (e.g., word line, bit line, etc.). In this example, the first physical address associated with the first logical address and the third physical address associated with the third logical address share a word line. The read optimization component 113 can perform an analysis to determine whether to reorder execution of the read commands. For example, if the controller 115 receives the third read command within a given closed time from receiving the first read command, or if the third read command is close to the first read command in the execution queue, the read optimization component 113 can reorder the commands. However, if the controller 115 receives the third read command within a given distance time from receiving the first read command, or if the third read command is far from the first read command in the execution queue, the read optimization component 113 can choose to execute the commands on a first come, first served basis and not reorder the commands.

[0038] At block 310, the processing device can execute the first read command and the third read command in sequence (e.g., one after the other). To reduce the amount of non-selected word line set and selected word line set, the read optimization component 113 can perform a non-selected word line set and a selected word line set for both the first read command and the third read command and read data at the first physical address and the third physical address. The controller 115 can then perform another non-selected word line set and selected word line set to read data at the second physical address. Alternatively, the controller 115 can read the second physical address, the first physical address, and then the third physical address. Other read orders are also possible (e.g., third physical address, first physical address, second physical address; second physical address, third physical address, first physical address). The processing device can execute the first read command and the third read command before executing the second read command. The processing device can execute the first read command and the third read command after executing the second read command. Thus, to read data at the three physical addresses, the read optimization component 113 can instruct the controller 115 to perform a total of two non-selected word line sets and two selected word line sets. In this example, the read optimization component 113 can cause the controller 115 to avoid performing a total of two word line sets. The reduction in non-selected word line sets and selected word line sets reduces cost by reducing the amount of time and resources needed to execute the read commands. After reading data at any given physical address, the controller 115 can send the data value to the host system 120.

[0039] The non-selected word line setting of the controller 115 can include applying a non-selected word line voltage to a non-selected word line. The performing the non-selected word line setting operation can include applying the non-selected word line voltage to one or more word lines not associated with the first physical address and the third physical address. The performing the selected word line setting operation can include applying the selected word line voltage to the first word line of the memory component. The selected word line setting of the controller 115 can include applying the selected word line voltage to the shared word line. Additionally, the first physical address can be a first data sub-block, the second physical address can be a second data sub-block, and the third physical address can be a third data sub-block.

[0040] Figure 4 A flow diagram of an example method 400 for reading data at a memory component of a memory sub-system using read optimization in accordance with some embodiments of the present disclosure. The method 400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by the read optimization component 113 of the memory sub-system 100. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the Figure 1 The method 400 is performed by the read optimization component 113 of the memory sub-system 100. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated processes can occur in different orders, and some processes can occur in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0041] At block 402, the processing device can receive a first read command directed to a first logical address. The processing device (e.g., the controller 115) can receive the first read command directed to the logical address from the host system 120. The host system 120 can send the read command to the controller 115 in order to obtain data at a first physical address associated with the first logical address.

[0042] At block 404, the processing device can receive a second read command directed to a second logical address after the first read command. The host system 120 can send the second read command to the controller 115 in order to obtain data at a second physical address associated with the second logical address.

[0043] At block 406, the processing device can receive a third read command directed to a third logical address after the second read command. The host system 120 can send the third read command to the controller 115 in order to obtain data at a third physical address associated with the third logical address.

[0044] At block 408, the processing device can determine that the first logical address corresponds to a first physical address, the third logical address corresponds to a third physical address, the first physical address and the third physical address are associated with a first word line of the memory component, and the second logical address corresponds to a second physical address associated with a second word line of the memory component. The read optimization component 113 can identify that the first physical address associated with the first logical address and the third physical address associated with the third logical address are associated with the same physical location (e.g., word line, bit line, etc.). In this example, the first physical address associated with the first logical address and the third physical address associated with the third logical address share a word line. The read optimization component 113 can perform an analysis to determine whether to reorder execution of the read commands. For example, if the controller 115 receives the third read command within a given closed time from receiving the first read command, or if the third read command is close to the first read command in the execution queue, the read optimization component 113 can reorder the commands. However, if the controller 115 receives the third read command within a given distance time from receiving the first read command, or if the third read command is far from the first read command in the execution queue, the read optimization component 113 can choose to execute the commands on a first-come, first-served basis and not reorder the commands.

[0045] At block 410, the processing device can reorder execution of the first read command, the second read command, and the third read command such that the first read command, the second read command, and the third read command are not executed in order (e.g., not in the order in which the controller 115 received the read commands). To reduce the amount of non-selected word line set and selected word line set operations, the read optimization component 113 can perform a non-selected word line set operation and a selected word line set operation for the first physical address and read data at the first physical address and the third physical address. The controller 115 can then perform another non-selected word line set and selected word line set to read data at the second physical address. Alternatively, the controller 115 can read data at the second physical address, the first physical address, and then the third physical. Other read orders are also possible (e.g., third physical address, first physical address, second physical address; second physical address, third physical address, first physical address). Thus, to read data at the three physical addresses, the read optimization component 113 can instruct the controller 115 to perform a total of two non-selected word line sets and two selected word line sets. In this example, the read optimization component 113 can cause the controller 115 to avoid performing a total of two word line sets. The reduction in non-selected word line sets and selected word line sets reduces cost by reducing the amount of time and resources needed to execute the read commands. After reading data at any given physical address, the controller 115 can send the data value to the host system 120.

[0046] The non-selected word line setting of controller 115 may include applying a non-selected word line voltage to the non-selected word line. The selected word line setting of controller 115 may include applying a selected word line voltage to the shared word line. Additionally, the first physical address may be a first data sub-block, the second physical address may be a second data sub-block, and the third physical address may be a third data sub-block.

[0047] Figure 5 An example machine is described as representing computer system 500, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 The host system (e.g., memory subsystem 110) of the memory subsystem 110 Figure 1 The host system 120, or a system that can be used to perform controller operations (e.g., execute an operating system to perform operations related to...). Figure 1 (The operation corresponding to the read optimization component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0048] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web application, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0049] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0050] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0051] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. The instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, the main memory 504 and processing device 502 also constituting machine-readable storage medium. Machine-readable storage medium 524, data storage system 518 and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0052] In one embodiment, instruction 526 includes instructions for implementing a read optimization component (e.g., Figure 1 The machine-readable storage medium 524 contains functional instructions for the read optimization component 113. Although in the exemplary embodiment, the machine-readable storage medium 524 is shown as a single medium, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0053] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this context, and for purposes of

[0054] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0055] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0056] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0057] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0058] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method for read optimization, comprising: Receive the first read command pointing to the first logical address; A second read command pointing to a second logical address is received after the first read command; A third read command pointing to a third logical address is received after the second read command; The first logical address corresponds to a first physical address, the third logical address corresponds to a third physical address, the first physical address and the third physical address are associated with a first word line of the memory component, and the second logical address corresponds to a second physical address associated with a second word line of the memory component; and The first read command and the third read command are executed sequentially.

2. The method of claim 1, wherein executing the first read command and the third read command sequentially includes executing the first read command and the third read command before executing the second read command.

3. The method of claim 1, wherein executing the first read command and the third read command sequentially includes executing the first read command and the third read command after executing the second read command.

4. The method of claim 1, further comprising: For both the first read command and the third read command, perform non-selected word line setting operation and selected word line setting operation.

5. The method of claim 4, wherein performing the non-selected word line setting operation comprises applying a non-selected word line voltage to one or more word lines not associated with the first physical address and the third physical address.

6. The method of claim 4, wherein performing the selected word line setting operation includes applying a selected word line voltage to the first word line of the memory component.

7. The method according to claim 1, wherein the first physical address is a first data sub-block, the second physical address is a second data sub-block, and the third physical address is a third data sub-block.

8. A system for read optimization, comprising: Memory components; as well as Processing device, coupled to the memory component, is configured to: Receive the first read command pointing to the first logical address; A second read command pointing to a second logical address is received after the first read command; A third read command pointing to a third logical address is received after the second read command; The first logical address corresponds to a first physical address, the third logical address corresponds to a third physical address, the first physical address and the third physical address are associated with a first word line of the memory component, and the second logical address corresponds to a second physical address associated with a second word line of the memory component; and The first read command and the third read command are executed sequentially.

9. The system of claim 8, wherein when the processing device executes the first read command and the third read command sequentially, the processing device executes the first read command and the third read command before executing the second read command.

10. The system of claim 8, wherein when the processing device executes the first read command and the third read command sequentially, the processing device executes the first read command and the third read command after executing the second read command.

11. The system of claim 8, wherein the processing device performs a non-selected word line setting operation and a selected word line setting operation for both the first read command and the third read command.

12. The system of claim 11, wherein performing the non-selected word line setting operation includes applying a non-selected word line voltage to one or more word lines not associated with the first physical address and the third physical address.

13. The system of claim 11, wherein performing the selected word line setting operation includes applying a selected word line voltage to the first word line of the memory component.

14. The system according to claim 8, wherein the first physical address is a first data sub-block, the second physical address is a second data sub-block, and the third physical address is a third data sub-block.

15. A non-transitory computer-readable storage medium comprising instructions, said instructions being... When executed by the processing device, the processing device performs the following operations: Receive the first read command pointing to the first logical address; A second read command pointing to a second logical address is received after the first read command; A third read command pointing to a third logical address is received after the second read command; The first logical address is determined to correspond to a first physical address, the third logical address corresponds to a third physical address, the first physical address and the third physical address are associated with a first word line of the memory component, and the second logical address corresponds to a second physical address associated with a second word line of the memory component; as well as The execution of the first read command, the second read command, and the third read command is reordered so that they are executed out of order.

16. The non-transitory computer-readable storage medium of claim 15, wherein when the processing means executes the first read command, the second read command, and the third read command out of sequence, the processing means executes the first read command and the third read command before executing the second read command.

17. The non-transitory computer-readable storage medium of claim 15, wherein when the processing means executes the first read command, the second read command, and the third read command not sequentially, the processing means executes the first read command and the third read command after executing the second read command.

18. The non-transitory computer-readable storage medium of claim 15, wherein the processing means performs a non-selected word line setting operation and a selected word line setting operation for both the first read command and the third read command.

19. The non-transitory computer-readable storage medium of claim 18, wherein performing the non-selected word line setting operation includes applying a non-selected word line voltage to one or more word lines not associated with the first physical address and the third physical address.

20. The non-transitory computer-readable storage medium of claim 18, wherein performing the selected word line setting operation includes applying a selected word line voltage to the first word line of the memory component.

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