Method, apparatus, electronic device and storage medium for data error correction

Abstract

Embodiments of the present disclosure provide a method, an apparatus, an electronic device, and a storage medium for data error correction. The method for data error correction includes: reading first object data from a storage address; performing a first check on the first object data; in response to the check result of the first check indicating that the first object data includes a first type of data error, using historical error correction information for a second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data; and obtaining error-free data corresponding to the storage address from the intermediate data, wherein, for the check algorithm adopted for the first check, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error. The method for data error correction can be used to improve the error correction ability of a memory, for example, correct uncorrectable errors in the related art, improve the reliability of the memory, and greatly reduce the risks of data loss and system downtime.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of data error correction technology, and more particularly, to methods, devices, electronic devices, and storage media for data error correction. Background Art

[0002] Data is prone to being interfered by factors such as the environment during transmission, communication, and storage, resulting in data errors. For example, Double Data Rate (DDR) memories (e.g., DDR SDRAM) are inevitably interfered by environmental factors such as electromagnetic interference during operation, leading to memory errors. For users with high stability requirements, memory errors may cause fatal problems. For example, for a server, which has relatively high requirements for the reliability of DDR data, DDR memory error correction technology can improve the stability and error correction ability of the server's memory. For example, a memory module supporting Error Correcting Code (ECC) can improve the stability and error correction ability of the server's memory.

[0003] For a certain memory module supporting ECC, the redundant bits used for ECC are fixed, and there are often limitations on the number of bits / bit width and positions for error correction. Therefore, the error correction ability of the memory module supporting ECC is limited. When the errors of the memory particles exceed the error correction ability of the memory module supporting ECC, the system will report an uncorrectable error. In the case of an uncorrectable error in the adopted ECC algorithm, data is generally lost and cannot be recovered. The loss of data will affect the processor or other computing units to perform corresponding operations, resulting in the inability of related functions or applications to run properly, and even causing the system to crash.

[0004] There is a need to improve the error correction ability of memories, such as correcting uncorrectable errors in related technologies. Summary of the Invention

[0005] At least one embodiment of the present disclosure discloses methods, devices, electronic devices, and storage media for data error correction, which are used to improve the error correction ability of memories, such as correcting uncorrectable errors in related technologies, improving the reliability of memories, and greatly reducing the risk of data loss and system crashes.

[0006] The first aspect of the present disclosure provides a method for data error correction, including: reading first object data from a storage address; performing a first check on the first object data; in response to the check result of the first check indicating that the first object data includes a first type of data error, using historical error correction information for a second type of data error of the storage address to at least partially correct the first type of data error to obtain intermediate data; and obtaining error-free data corresponding to the storage address from the intermediate data, wherein, for the check algorithm adopted for the first check, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error. In other words, for the check algorithm adopted for the first check, the redundant bits required to correct the second type of data error are less than the redundant bits required to correct the first type of data error.

[0007] For example, in the method provided by at least one embodiment of the present disclosure, using historical error correction information for a second type of data error of the storage address to at least partially correct the first type of data error to obtain intermediate data includes: in response to the historical error correction information indicating that there is a fixed error at the same position in the storage address, correcting the data bits corresponding to the same position in the first object data to obtain intermediate data.

[0008] For example, the method provided by at least one embodiment of the present disclosure further includes: judging whether there is a fixed error at the same position in the storage address according to the historical error correction information.

[0009] For example, in the method provided by at least one embodiment of the present disclosure, judging whether there is a fixed error at the same position in the storage address according to the historical error correction information includes: in response to the historical error correction information including N consecutive error correction messages related to the second type of data error and the N error correction messages being for the same position, determining that there is a fixed error at the same position in the storage address, where N is an integer greater than or equal to 2.

[0010] For example, the method provided by at least one embodiment of the present disclosure further includes: in response to the historical error correction information indicating that there is no fixed error at the same position in the storage address, reading second object data from the storage address again, performing the first check on the second object data again; and in response to the check result of the first check performed again indicating that the second object data includes a first type of data error, performing an error reporting operation.

[0011] For example, in the method provided by at least one embodiment of the present disclosure, obtaining error-free data corresponding to the storage address from the intermediate data includes: performing a second check on the intermediate data to correct the remaining data errors in the intermediate data, thereby obtaining error-free data corresponding to the storage address.

[0012] For example, in the method provided by at least one embodiment of the present disclosure, the first check and the second check adopt the same check algorithm.

[0013] For example, in the method provided by at least one embodiment of the present disclosure, the verification algorithm is the RS algorithm.

[0014] For example, in the method provided by at least one embodiment of the present disclosure, the storage address involves the same memory die or multiple memory dies in the memory.

[0015] Another aspect of the present disclosure provides a method for data error correction, including: respectively reading multiple object data from a storage address; respectively performing a first verification on the multiple object data; in response to the verification results of the first verification performed on the multiple object data indicating that the multiple object data respectively include correctable errors, storing multiple error correction information of the multiple object data, where each of the multiple error correction information includes the storage location targeted by the corresponding correctable error; and correcting the data error of the first object data subsequently read from the storage address according to the multiple error correction information.

[0016] For example, in the method provided by at least one embodiment of the present disclosure, correcting the data error of the first object data subsequently read from the storage address according to the multiple error correction information includes: in response to the verification result of the first verification on the first object data indicating that the first object data includes an uncorrectable error, using the multiple error correction information to at least partially correct the uncorrectable error to obtain intermediate data; and obtaining error-free data corresponding to the storage address from the intermediate data.

[0017] Another aspect of the present disclosure provides a device for data error correction, including: a reading unit configured to read first object data from a storage address; a first verification unit configured to perform a first verification on the first object data; a first correction unit configured to: in response to the verification result of the first verification indicating that the first object data includes a first type of data error, use historical error correction information for a second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data; and a second correction unit configured to obtain error-free data corresponding to the storage address from the intermediate data, where, for the verification algorithm adopted for the first verification, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error.

[0018] For example, in the device provided by at least one embodiment of the present disclosure, the first correction unit includes: a first correction subunit configured to: in response to the historical error correction information indicating that there is a fixed error at the same position in the storage address, correct the data bits corresponding to the same position in the first object data to obtain intermediate data.

[0019] For example, in the apparatus provided by at least one embodiment of the present disclosure, the first correction unit further includes: a fixed error determination unit configured to determine whether there is a fixed error at the same position for a storage address according to historical error correction information.

[0020] For example, in the apparatus provided by at least one embodiment of the present disclosure, the fixed error determination unit includes: a fixed error determination unit configured to, in response to the historical error correction information including N consecutive error correction information related to the second type of data error and the N error correction information being directed to the same position, determine that there is a fixed error at the same position for the storage address, where N is an integer greater than or equal to 2.

[0021] For example, in the apparatus provided by at least one embodiment of the present disclosure, the apparatus further includes an error reporting unit, wherein: the reading unit is further configured to: in response to the historical error correction information indicating that there is no fixed error at the same position for the storage address, read the second object data from the storage address again; the first verification unit is further configured to: perform the first verification on the second object data again; and the error reporting unit is configured to perform an error reporting operation in response to the verification result of the first verification performed again indicating that the second object data includes the first type of data error.

[0022] For example, in the apparatus provided by at least one embodiment of the present disclosure, the second correction unit includes: a second correction subunit configured to: perform a second verification on the intermediate data to correct the remaining data errors of the intermediate data, thereby obtaining error-free data corresponding to the storage address.

[0023] For example, in the apparatus provided by at least one embodiment of the present disclosure, the first verification and the second verification adopt the same verification algorithm.

[0024] For example, in the apparatus provided by at least one embodiment of the present disclosure, the verification algorithm is the RS algorithm.

[0025] For example, in the apparatus provided by at least one embodiment of the present disclosure, the storage address relates to the same memory die or multiple memory dies in the memory.

[0026] Another aspect of the present disclosure provides an apparatus for data error correction, including: a reading unit configured to read multiple object data from a storage address respectively; a first verification unit configured to perform a first verification on the multiple object data respectively; a storage unit configured to store multiple error correction information of the multiple object data in response to the verification result of the first verification performed on the multiple object data indicating that the multiple object data respectively include correctable errors, wherein each of the multiple error correction information includes the storage position targeted by the corresponding correctable error; and a correction unit configured to correct the data error of the first object data read from the storage address subsequently according to the multiple error correction information.

[0027] For example, in the apparatus provided by at least one embodiment of the present disclosure, the first verification unit is further configured to: perform a first verification on the first object data; and the correction unit includes a first correction unit and a second correction unit, wherein the first correction unit is configured to: in response to the verification result of the first verification of the first object data indicating that the first object data includes uncorrectable errors, use multiple error correction messages to at least partially correct the uncorrectable errors to obtain intermediate data; and the second correction unit is configured to: obtain error-free data corresponding to the storage address from the intermediate data.

[0028] Another aspect of the present disclosure provides an electronic device, including: a processor; a memory including one or more computer program modules; wherein, the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the method described in any one of the present disclosure when being executed by the processor.

[0029] Another aspect of the present disclosure provides a non-transitory computer-readable storage medium, on which executable instructions are stored, wherein, when the executable instructions are executed by a processor, the processor is caused to execute the method described in any one of the present disclosure.

[0030] As described above, at least one embodiment of the present disclosure lies in that, by using the historical error correction information of the second type of data error for the storage address to partially correct the first type of data error for the storage address, intermediate data containing partial remaining errors is obtained, and then the intermediate data can be corrected. In this way, step-by-step correction of data errors can be achieved, for example, gradually correcting the original uncorrectable errors, improving the reliability of the memory, and greatly reducing the risks of data loss and system downtime. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0032] Figure 1 The flowchart of a method for data error correction according to at least one embodiment of the present disclosure is shown.

[0033] Figure 2 The flowchart of another method for data error correction according to at least one embodiment of the present disclosure is shown.

[0034] Figure 3 The structural schematic diagram of an apparatus for data error correction according to at least one embodiment of the present disclosure is shown.

[0035] Figure 4Shows a schematic structural diagram of another apparatus for data error correction according to at least one embodiment of the present disclosure.

[0036] Figure 5 Shows a schematic diagram of an example scenario where there are uncorrectable errors.

[0037] Figure 6 Shows a schematic diagram of an example scenario where a method or apparatus for data error correction according to the present disclosure is utilized.

[0038] Figure 7 Shows a schematic diagram of an electronic device according to at least one embodiment of the present disclosure.

[0039] Figure 8 Shows a schematic diagram of another electronic device according to at least one embodiment of the present disclosure

[0040] Figure 9 Shows a schematic diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure. Detailed Description of the Embodiments

[0041] Now, specific embodiments of the present disclosure will be described in detail, and examples of the present disclosure are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover modifications, variations, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can all be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0042] The terms used in the present disclosure are those general terms that are currently widely used in the art in consideration of the functions of the present disclosure, but these terms can vary according to the intentions of those of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms can be selected by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be construed as mere names, but rather based on the meanings of the terms and the overall description of the present disclosure.

[0043] Flowcharts are used in the present disclosure to illustrate the operations performed by the systems according to the embodiments of the present disclosure. It should be understood that the operations before or below do not necessarily have to be executed precisely in order. On the contrary, various steps can be processed in reverse order or simultaneously as needed. At the same time, other operations can also be added to these processes, or one or several operations can be removed from these processes.

[0044] For ease of understanding, first, relevant terms related to at least one embodiment of the present disclosure are explained:

[0045] A correctable error (CE), also known as a CE error, refers to an error that the hardware (chip) can correct based on the ECC algorithm it uses. Due to different memory controller designs, the ability to correct errors may vary. For example, in a mainstream x86 server's memory controller (supporting memory modules with ECC), any error within a memory die with a 4-bit data width (X4 width / bit width) during a single read operation is correctable. If a memory rank is composed of memory dies with an 8-bit data width (X8 width / bit width), its correction ability still remains consistent with that of the X4-width memory dies and their positions. In an X8-width memory die, among the 8-bit data including DQ0-7, only DQ0-3 or DQ4-7 can be corrected.

[0046] An uncorrectable error (UCE), also known as a UCE error, refers to an error that the hardware (chip) cannot correct based on the ECC algorithm it uses. For example, during a single read operation, if the error data bits are distributed across different X4-width memory die ranges, that is, an error across memory dies occurs, it is an uncorrectable error in the current memory control design. Another example is that if a memory rank is composed of X8-width memory dies, its correction ability still remains consistent with that of the X4-width memory dies and their positions. In an X8-width memory die, if the error position is, for example, DQ2-5, although it is within the X4-width range but the position does not correspond to that of the X4-width, where the error position DQ2-3 corresponds to one X4-bit width and the error position DQ4-5 corresponds to another X4-bit width, that is, when the error position in a memory die spans different X4-bit widths, it cannot be corrected. Another example is that if a memory rank is composed of X8-width memory dies, its correction ability still remains consistent with that of the X4-width memory dies and their positions. In an X8 memory die, if it is, for example, DQ0-4, and the error bit width (in this case, X5 bit width) exceeds the correctable bit width (X4), it cannot be corrected.

[0047] For example, for DDR memories, there are various techniques to implement the correction of correctable errors. For example, the ECC error correction algorithm can use the RS algorithm, and the RS algorithm can only correct the data of one memory die on one channel in one operation. Another example is that the Parity+CRC structure can be used to correct memory dies, where one memory die is responsible for storing CRC check information for error checking, and another memory die is responsible for storing parity check information for error correction. However, whether it is single device data correction (SDDC) or double device data correction (DDDC), it can only correct the data of one memory die at a time. Such an error of one memory die belongs to a correctable error.

[0048] The redundant bits of the memory module supporting the above ECC technology are fixed, and there are often limitations in the number of error correction bits / bit widths and positions. Therefore, the error correction ability of the memory module supporting ECC is limited. When the error of the memory die exceeds the error correction ability of the memory module supporting ECC, the system will report an uncorrectable error. In the case of an uncorrectable error, data is generally lost and cannot be recovered. The loss of data will affect the processor or other computing units to perform corresponding operations, resulting in the abnormal operation of related functions or applications, and even causing the system to crash.

[0049] At least one embodiment of the present disclosure provides a method, apparatus, electronic device, and storage medium for data error correction, which are used to improve the error correction ability of the memory, for example, correct uncorrectable errors in related technologies, improve the reliability of the memory, and greatly reduce the risk of data loss and system crashes.

[0050] The following will refer to the accompanying drawings to introduce in detail the method, apparatus, electronic device, and storage medium for data error correction according to the embodiments of the present disclosure.

[0051] First, the method for data error correction according to the embodiments of the present disclosure will be introduced below. The method for data error correction can be applied to the apparatus for data error correction, electronic device, other suitable software or hardware, or the combination of hardware and software described further below.

[0052] Figure 1 A flowchart of a method for data error correction according to at least one embodiment of the present disclosure is shown. The method may include steps S102 to S108.

[0053] In step S102, the first object data is read from the storage address.

[0054] In some embodiments, the storage address corresponds to the address of the object data for a data read operation. For example, the storage address may refer to a storage row or a BANK. The first object data can be read from a data storage device or a data transmission device. For example, the first object data can be read from a memory (e.g., a DDR memory). In some embodiments, the first object data is the object data representing the current verification operation. For example, the first object data can be decoded and error-corrected (if necessary) during the verification operation to obtain data or instructions for performing calculations to achieve a predetermined function.

[0055] In step S104, perform a first verification on the first object data.

[0056] In some embodiments, the first object data read from the storage address may be incorrect due to interference from the environment such as electromagnetic interference. Therefore, a first verification can be performed on the first object data. In some embodiments, the first verification can be implemented using ECC technology. For example, the first verification can be implemented through Hamming codes, RS algorithms, Parity+CRC, or other suitable technologies. In some embodiments, during the execution of the first verification, it can be determined whether the first object data has an error and the location of the error.

[0057] In step S106, in response to the verification result of the first verification indicating that the first object data includes a first type of data error, use the historical error correction information of the second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data.

[0058] In some embodiments, for the verification algorithm adopted, the first type of data error may correspond to an uncorrectable error, and the second type of data error may correspond to a correctable error. However, the embodiments of the present disclosure are not limited thereto. In some embodiments of the present disclosure, for the verification algorithm adopted for the first verification, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error.

[0059] For example, when a second type of data error as described above occurs, the second type of data error can be corrected through ECC technology to obtain correct data. During the correction of the second type of data error through ECC technology, the historical error correction information of the second type of data error can be recorded or stored. When an uncorrectable error occurs, the historical error correction information can be used to at least partially correct the first type of data error. Compared with the first object data, the number of errors in the intermediate data thus obtained is reduced. For example, the error data included in the intermediate data can become a correctable error.

[0060] In step S108, error-free data corresponding to the storage address is obtained from the intermediate data.

[0061] In some embodiments, the intermediate data obtained above can be processed again by ECC technology to obtain error-free data corresponding to the storage address. For example, the RS algorithm can be used to correct the errors in the intermediate data, so as to obtain error-free data corresponding to the storage address.

[0062] As described above, the method for data error correction disclosed in at least one embodiment of the present disclosure is to partially correct the first type of data error for the storage address by using the historical error correction information of the second type of data error for the storage address, obtain intermediate data containing partial remaining errors, and then correct the intermediate data. In this way, without changing the redundant bits used for ECC, by gradually correcting data errors, for example, gradually correcting the original uncorrectable errors, the reliability of the memory is improved, and the risks of data loss and system downtime are greatly reduced.

[0063] The following will describe in detail other aspects of the method for data error correction in at least one embodiment of the present disclosure.

[0064] In the method for data error correction in some embodiments, it is possible to determine whether there is a fixed error at the same position for the storage address according to the historical error correction information. In this way, the fixed error can be determined, so as to subsequently use the historical error correction information corresponding to the fixed error to at least partially correct the first type of data error in the first object data.

[0065] In the method for data error correction in some embodiments, using the historical error correction information of the second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data may include: in response to the historical error correction information indicating that there is a fixed error at the same position for the storage address, correcting the data bits corresponding to the same position in the first object data to obtain intermediate data. In this way, using the historical error correction information corresponding to the fixed error to correct the data bits corresponding to the same position in the first object data realizes at least partial correction of the first type of data error.

[0066] In the method for data error correction in some embodiments, determining whether there is a fixed error at the same position for the storage address according to the historical error correction information may include: in response to the historical error correction information including N consecutive error correction information related to the second type of data error and the N error correction information being directed to the same position, determining that there is a fixed error at the same position for the storage address, where N is an integer greater than or equal to 2. For example, N can be 3 to 10, such as 5.

[0067] In some cases, it is impossible to determine whether the second type of data error is a fixed error only by reading an error correction message of the second type of data error. In some cases, the current first type of data error is related to the second type of data error in the previous several times or within a certain time range. When the time interval between the occurrence of the first type of data error and the occurrence of the second type of data error is relatively long, such as one day, one week, etc., using the error correction information of the second type of data error may reduce the effect of correcting at least part of the first type of data error. Therefore, in this embodiment, the value of N can be adaptively set according to the specific data storage environment, so as to select an appropriate number of error correction messages to determine whether there is a fixed error at the same position in the storage address, increasing the flexibility and reliability of the method.

[0068] In the method for data error correction in some embodiments, in response to the historical error correction information indicating that there is no fixed error at the same position in the storage address, the second object data can be read again from the storage address, and the first verification can be performed on the second object data again; and in response to the verification result of the first verification performed again indicating that the second object data includes the first type of data error, an error reporting operation can be performed.

[0069] In the method for data error correction in this embodiment, when it is determined that the historical error correction information indicates that there is no fixed error at the same position in the storage address, that is, it indicates that there is a random error in the second data error corresponding to the historical error correction information. Therefore, the first type of data error read may also include a random error. The second object data can be read again from the address where the first object data is read to eliminate the random data error in the first type of data error. Compared with directly discarding the data when the first type of data error occurs, in this way, the possibility of correcting the first type of data error can be increased. However, in some embodiments, if the data read again from the same storage address (i.e., the second object data) still shows the first type of data error after the first verification, then at this time, it can be selected not to repeat the attempt, but to perform an error reporting operation.

[0070] In addition, in the method for data error correction in this embodiment, the error reporting operation can include, for example, reporting data loss, reminding the staff to replace the memory module or other operations, etc., to prevent the risk of subsequent data loss and downtime.

[0071] In the method for data error correction in some embodiments, obtaining the error-free data corresponding to the storage address from the intermediate data may include: performing a second verification on the intermediate data to correct the remaining data errors of the intermediate data, so as to obtain the error-free data corresponding to the storage address. For example, the second verification can be performed through ECC technology. In this way, the remaining data errors can be corrected through the second verification to obtain the error-free data.

[0072] In the method for data error correction according to some embodiments, the first checksum and the second checksum adopt the same checksum algorithm. For example, both the first checksum and the second checksum can adopt the RS algorithm, and the embodiments of the present disclosure can also be applicable to scenarios adopting other algorithms. In this way, the types of algorithms that need to be used can be reduced, and the complexity of the checksum operation is lowered.

[0073] In the method for data error correction according to some embodiments, the storage address serving as the destination address of the data reading operation involves the same memory die or multiple (such as two or more) memory dies within the memory. In this way, at least one embodiment of the present disclosure can perform data error correction on the same memory die, or can perform data error correction on two memory dies.

[0074] Figure 2 The flowchart of another method for data error correction according to at least one embodiment of the present disclosure is shown, and this method may include steps S202 to S208.

[0075] In step S202, multiple pieces of object data are respectively read from the storage address.

[0076] In some embodiments, the object data can be read from a data storage device or a data transmission device. For example, the object data can be read from a memory (such as a DDR memory). In some embodiments, the object data includes data or instructions used to perform calculations to achieve a predetermined function.

[0077] In step S204, a first checksum is respectively performed on the multiple pieces of object data.

[0078] In some embodiments, the first checksum described with reference to Figure 2 can be the same as or similar to the first checksum described with reference to Figure 1 .

[0079] In step S206, in response to the checksum result of the first checksum performed on the multiple pieces of object data indicating that the multiple pieces of object data respectively include correctable errors, multiple pieces of error correction information of the multiple pieces of object data are stored, wherein each of the multiple pieces of error correction information includes the storage location targeted by the corresponding correctable error.

[0080] In some embodiments, during the process of performing the first checksum, it can be determined whether an error occurs in the object data and the location where the error occurs, and it can be determined whether the object data includes a correctable error based on the location where the error occurs. During the process of performing the first checksum, the correctable error can be corrected, and error correction information can be generated.

[0081] In step S208, according to the multiple pieces of error correction information, the data error of the first object data subsequently read from the storage address is corrected.

[0082] As described above, another method for data error correction disclosed by at least one embodiment of the present disclosure lies in that by storing error correction information for correctable errors of a storage address, the error correction information can be used to correct data errors in the data subsequently obtained from the storage address. In this way, the number of error bits of uncorrectable errors can be reduced, and the uncorrectable errors can be changed into correctable errors, thereby solving the problem of uncorrectable errors in the related art, improving the reliability of the memory, and greatly reducing the risks of data loss and system downtime.

[0083] In some embodiments, correcting data errors of the first object data subsequently read from a storage address according to multiple error correction information may include: in response to the check result of the first check of the first object data indicating that the first object data includes uncorrectable errors, using the multiple error correction information to at least partially correct the uncorrectable errors to obtain intermediate data; and obtaining error-free data corresponding to the storage address from the intermediate data. In this way, the uncorrectable errors can be at least partially corrected by using the error correction information, thereby realizing step-by-step error correction of uncorrectable errors.

[0084] The above respectively combines Figure 1 and Figure 2 to describe the method for data error correction according to the embodiments of the present disclosure. However, it can be understood that various aspects of the method for data error correction described in combination with Figure 1 and Figure 2 can be combined or cross-referenced with each other without exceeding the scope disclosed by the embodiments of the present disclosure.

[0085] To enable those skilled in the art to better understand and implement the embodiments of the present disclosure, the following describes the device for data error correction that can implement the method for data error correction described above with reference to Figure 1 and the additional aspects with reference to the accompanying drawings.

[0086] Corresponding to the method for data error correction provided by at least one embodiment of the present disclosure, the present disclosure also provides a device for data error correction. Figure 3 FIG. shows a schematic structural diagram of a device 300 for data error correction according to at least one embodiment of the present disclosure.

[0087] Referring to Figure 3 , the device 300 for data error correction according to the embodiments of the present disclosure may include a reading unit 310, a first check unit 320, a first correction unit 330, and a second correction unit 340.

[0088] The reading unit 310 is configured to read first object data from a storage address.

[0089] The first verification unit 320 is configured to perform a first verification on the first object data.

[0090] The first correction unit 330 is configured to, in response to the verification result of the first verification indicating that the first object data includes a first type of data error, use historical error correction information for a second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data.

[0091] The second correction unit 340 is configured to obtain error-free data corresponding to the storage address from the intermediate data, wherein, for the verification algorithm used in the first verification, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error.

[0092] As described above, the apparatus for data error correction disclosed in at least one embodiment of the present disclosure lies in that, by using the stored historical error correction information for the second type of data error for the storage address, the first type of data error for the storage address is partially corrected to obtain intermediate data containing some remaining errors, and then the intermediate data can be corrected. In this way, step-by-step correction of data errors can be achieved, for example, gradually correcting the original uncorrectable errors, improving the reliability of the memory, and greatly reducing the risks of data loss and system downtime.

[0093] The following will describe in detail other aspects of the apparatus for data error correction according to the embodiments of the present disclosure.

[0094] In the apparatus for data error correction according to some embodiments, the first correction unit 330 may include a first correction subunit, and the first correction subunit is configured to: in response to the historical error correction information indicating that there is a fixed error at the same position in the storage address, correct the data bits corresponding to the same position in the first object data to obtain intermediate data.

[0095] In the apparatus for data error correction according to some embodiments, the first correction unit 330 further includes a fixed error determination unit, and the fixed error determination unit is configured to determine whether there is a fixed error at the same position in the storage address according to the historical error correction information.

[0096] In the apparatus for data error correction according to some embodiments, the fixed error determination unit includes a fixed error determination subunit, and the fixed error determination subunit is configured to, in response to the historical error correction information including N consecutive error correction information related to the second type of data error and the N error correction information being directed to the same position, determine that there is a fixed error at the same position in the storage address, where N is an integer greater than or equal to 2.

[0097] In the apparatus for data error correction according to some embodiments, the apparatus 300 may further include an error reporting unit. In these embodiments, the reading unit 310 is further configured to, in response to the historical error correction information indicating that there is no fixed error at the same position for the storage address, read the second object data from the storage address again; the first verification unit 320 is further configured to perform the first verification on the second object data again; the error reporting unit is configured to, in response to the verification result of the first verification performed again indicating that the second object data includes a first type of data error, perform an error reporting operation.

[0098] In the apparatus for data error correction according to some embodiments, the second correction unit 340 may include a second correction subunit, and the second correction subunit is configured to perform a second verification on the intermediate data to correct the remaining data errors of the intermediate data, so as to obtain error-free data corresponding to the storage address.

[0099] In the apparatus for data error correction according to some embodiments, the first verification and the second verification adopt the same verification algorithm.

[0100] In the apparatus for data error correction according to some embodiments, the verification algorithm is the RS algorithm.

[0101] In the apparatus for data error correction according to some embodiments, the above storage address relates to the same memory die or multiple memory dies in the memory. For example, the above storage address is only located within the same memory die or is located in multiple (such as two or more) memory dies at the same time.

[0102] The above only combines Figure 3 describes a part of the apparatus 300 for data error correction according to at least one embodiment of the present disclosure, and the remaining part of the apparatus 300 for data error correction may correspond to various aspects of the method for data error correction combined with the present disclosure Figure 1 described, and the effects of various aspects of the method for data error correction combined with the present disclosure Figure 1 described can also be mapped to the apparatus 300 for data error correction of the present disclosure, which will not be elaborated here.

[0103] Corresponding to the method for data error correction provided by at least one embodiment of the present disclosure, the present disclosure also provides another apparatus for data error correction. Figure 4 FIG. shows a schematic structural diagram of another apparatus 400 for data error correction according to at least one embodiment of the present disclosure.

[0104] Referring to Figure 4 , the apparatus 400 for data error correction may include a reading unit 410, a first verification unit 420, a storage unit 430, and a correction unit 440.

[0105] The reading unit 410 is configured to read multiple pieces of object data from the storage address respectively.

[0106] The first verification unit 420 is configured to perform a first verification on multiple pieces of object data respectively.

[0107] The storage unit 430 is configured to store multiple pieces of error correction information of multiple pieces of object data in response to the verification result of the first verification performed on the multiple pieces of object data indicating that the multiple pieces of object data respectively include correctable errors, wherein each of the multiple pieces of error correction information includes the storage location targeted by the corresponding correctable error.

[0108] The correction unit 440 is configured to correct the data error of the first object data read subsequently from the storage address according to the multiple pieces of error correction information.

[0109] The reading unit 410 may be the same as or similar to the reading unit 310 described in conjunction with Figure 3 The first verification unit 420 may be the same as or similar to the first verification unit 320 described in conjunction with Figure 3 described.

[0110] As described above, another apparatus for data error correction disclosed in at least one embodiment of the present disclosure is that by storing error correction information for correctable errors of a storage address, the error correction information can be used to correct data errors in the data obtained subsequently from the storage address. In this way, it is possible to reduce the number of error bits of uncorrectable errors, change uncorrectable errors into correctable errors, thereby solving the problem of uncorrectable errors in the related art, improving the reliability of the memory, and greatly reducing the risks of data loss and system downtime.

[0111] In some embodiments, the first verification unit 320 is further configured to: perform a first verification on the first object data; and the correction unit 340 may include a first correction unit and a second correction unit, wherein the first correction unit is configured to: in response to the verification result of the first verification on the first object data indicating that the first object data includes uncorrectable errors, use multiple pieces of error correction information to at least partially correct the uncorrectable errors to obtain intermediate data; and the second correction unit is configured to: obtain error-free data corresponding to the storage address from the intermediate data.

[0112] The above only combines Figure 4 described a part of the apparatus 400 for data error correction according to at least one embodiment of the present disclosure, and the remaining part of the apparatus 400 for data error correction may correspond to various aspects of the method for data error correction described in conjunction with Figure 2 of the present disclosure, and according to the combination of the present disclosure Figure 2The effects of the various aspects of the described method for data error correction can similarly be mapped to the apparatus 400 for data error correction of the present disclosure, which will not be elaborated herein.

[0113] The above has separately combined Figure 3 and Figure 4 to describe the apparatus for data error correction according to an embodiment of the present disclosure. However, it can be understood that the various aspects of the apparatus for data error correction described in combination with Figure 3 and Figure 4 can be combined or cross-referenced to each other without exceeding the scope of the present disclosure.

[0114] Next, through Figure 5 and Figure 6 an example scenario that utilizes the method or apparatus for data error correction provided by at least one embodiment of the present disclosure will be described. It can be understood that Figure 5 and Figure 6 the scenarios shown are merely exemplary and do not exhaustively list all aspects of the above-mentioned method for data error correction and the apparatus for data error correction.

[0115] Figure 5 FIG. shows a schematic diagram of an example scenario where there are uncorrectable errors. For simplicity, Figure 5 only the example scenarios related to the method or apparatus for data error correction of at least one embodiment of the present disclosure are illustrated.

[0116] Referring to Figure 5 , data 504 can be read out from a target storage address in the DDR memory 502 according to a read request. For example, the data 504 has a corresponding length according to the read request, and the data 504 can be data + check value information (such as Data1+chk1, Data2+chk2... in the figure). Subsequently, the data 504 can be sent to the RS algorithm module 506. In the RS algorithm module 506, the data can be verified by the Reed-Solomon (RS) algorithm to determine whether the target data includes errors, or when errors are included, whether the errors are correctable errors or uncorrectable errors. For example, in the RS algorithm module 506, the RS algorithm can be used to indicate whether the data 504 has errors, whether the position where the errors occur involves a symbol error (i.e., a correctable error, i.e., a CE error), and whether the position where the errors occur involves two symbol errors (i.e., an uncorrectable error, i.e., a UCE error). Here, the symbol is the minimum unit of error correction, which can include a specific number of bit data, for example. If the data 504 has no errors or a CE error occurs, the correct data will be output. For example, when the data 504 has no errors, the correct data will be directly output (such as Data1, Data3, Data4 in the figure). When the data 504 has a CE error, for exampleFigure 5 An error occurs in Data2 in

[0117] However, in Figure 5 the scenario shown, once a UCE error occurs in the data, the data cannot be read back correctly and the data will be lost, as shown in module 510.

[0118] Figure 6 shows a schematic diagram of an example scenario using a method or apparatus for data error correction according to at least one embodiment of the present disclosure to exemplarily illustrate the implementation of solving the UCE error problem existing in the Figure 5 shown scenario. However, it can be understood that the method for data error correction and the apparatus for data error correction described according to at least one embodiment of the present disclosure can be applied to other scenarios.

[0119] Referring to Figure 6 , data 604 can be read out from the destination storage address in the DDR memory 602 according to a read request. For example, data 604 has a corresponding length according to the read request, and data 604 can be data + check value information. The data 604 here can be the object data mentioned above. However, the object data is not limited thereto and can be other forms of data.

[0120] Subsequently, data 604 can be sent to the RS algorithm module 606. In the RS algorithm module 606, a check operation can be performed on data 604 through the RS algorithm. The check operation here can be the first check mentioned above to determine whether data 604 has an error, and if there is an error, whether the error is a CE error or a UCE error. If the execution result of the RS algorithm module 606 indicates that data 604 has no error, the correct data 608 (such as Data1, Data3, Data4 in the figure) can be directly output. If the execution result of the RS algorithm module 606 indicates that data 604 has a CE error, the data can be corrected using the RS algorithm, that is, an error correction operation, to output the correct data 608 (such as Data2' in the figure).

[0121] When it is determined in the RS algorithm module 606 that data 604 includes a CE error and when correcting the CE error, the error correction information 612 of the CE error can be recorded. Exemplary error correction information 612 can include the position of the memory granule of the current CE error (such as E1 in the figure) and the associated syndrome information (such as Sym1 in the figure). The error correction information 612 is only exemplary, and the error correction information 612 can be changed depending on the algorithm adopted by different ECC technologies.

[0122] Figure 6The error correction information for three CE errors is shown. The error correction information for the most recent three CE errors will be recorded in the above figure. For the number of times of storing the error correction information of CE errors, it can be controlled by setting a threshold. For example, the threshold can be set according to the specific application situation. For example, when the threshold is set to 3, the error correction information for the most recent 3 consecutive CE errors is stored. If the threshold is set to 5, the error correction information for the most recent 5 consecutive CE errors is stored. Of course, other thresholds are also possible.

[0123] It can be understood that since the data errors are gradually accumulated. If a UCE error occurs before the number of CE errors reaches the threshold, then there is no way to correct it currently and there was no way to correct it before. Such a low-probability event is not within the scope of the embodiments of the present disclosure.

[0124] In some cases, the error correction information can be stored in a memory and can be read from the memory when the error correction information is needed (such as module 614 described below). In other cases, the error correction information can be stored in a register and can be read from the register when the error correction information is needed (such as module 614 described below). Compared with using a memory to store the error correction information, using a register to store the error correction information can improve the efficiency of storing and reading the error correction information.

[0125] Returning to module 610, when a UCE error occurs, the operation of module 614 will be triggered. In module 614, the stored error correction information 612 can be read, and it can be determined whether the error positions of the memory particles corresponding to the read error correction information are the same. As shown in the figure, module 614 can read the error correction information for three CE errors and determine whether the error positions of the memory particles corresponding to the error correction information for the three CE errors are the same.

[0126] If the positions are not the same (the "no" branch of module 614), it means that the three CE errors do not occur at the same position. Therefore, the UCE error that occurs in the read data 604 is also likely to be a random error. In some cases, the data can be read again from the storage address where the UCE error occurred previously to reduce the random error. The number of times of reading again can be controlled by setting a threshold. For example, the threshold can be set according to the specific application situation. For example, when the threshold is set to 2, it can be read two more times. Of course, other thresholds are also possible. In other cases, when a UCE error still occurs after the number of times of reading reaches the threshold, it will be regarded as an unsolvable UCE error, and an error reporting operation can be performed in module 616, such as reporting data loss, reminding the staff to replace the memory module or other operations.

[0127] If the positions are the same (the "Yes" branch of module 614), it indicates that the three CE errors occur at the same position, i.e., a fixed error. Therefore, the UCE error in the read data 604 is also very likely to be a fixed error, and the RS algorithm post-processing module 618 can be started. In the RS algorithm post-processing module 618, based on the error correction information of the CE error and the data with UCE error currently read (such as Datam+chkm in the figure), the correct data stored at the position corresponding to the CE error is calculated and deduced through the RS algorithm post-processing, and the intermediate data 620 (such as Datam'+chkm in the figure) is obtained. At this time, Datam' will only contain one error position. It can be understood that the RS algorithm post-processing here only shows an example way to calculate and deduce the correct data stored at the position corresponding to the CE error based on the error correction information of the CE error. The RS algorithm post-processing module 618 can also be alternatively implemented through other data processing methods or algorithms.

[0128] Subsequently, the intermediate data 620 (Datam'+chkm) can be input into the RS algorithm module 622 for operation. The RS algorithm module 622 shown here can be the same RS algorithm module as the RS algorithm module 606. In this case, the check result of the RS algorithm module 606 will report that the intermediate data 620 (Datam'+chkm) has a CE error, and the intermediate data with the CE error can be corrected back through the RS algorithm (corresponding to the second check described above), so as to obtain the completely correct data 624 (such as Datam” in the figure).

[0129] In the above scenario, the UCE error can be partially corrected through the error correction information to obtain intermediate data containing some remaining errors, and then this intermediate data can be corrected. In this way, without changing the redundant bits used for ECC, through the gradual correction of data errors, such as gradually correcting the original uncorrectable errors, the problem caused by the UCE error can be effectively solved, the reliability of the memory can be improved, and the risk of data loss and system downtime can be greatly reduced.

[0130] For example, in the above scenario, the UCE error can involve the first memory die and the second memory die, that is, the error across memory dies mentioned above. The error of the first memory die can be corrected through the error correction information of the CE error, and then the errors of different memory dies can be corrected, so as to achieve the correction of two error positions and effectively solve the problem caused by the UCE error.

[0131] For another example, in the above scenario, a UCE error may involve one memory die, that is, the error location of one memory die mentioned above spans different bit widths. The error located within the first bit width can be corrected by the error correction information of the CE error, and then the error located within the second bit width can be corrected, thereby enabling the correction of errors in memory dies with different bit widths and effectively solving the problems caused by UCE errors.

[0132] For another example, in the above scenario, when the bit width of a UCE error exceeds the bit width that can be corrected, a part of the UCE error can be corrected by the error correction information of the CE error to obtain intermediate data containing some remaining errors, and then the intermediate data can be further corrected, effectively solving the problems caused by UCE errors.

[0133] According to at least some embodiments of the present disclosure, by using the method of the embodiments of the present disclosure and recording the error correction information of previous CE errors in hardware, the purpose of correcting data errors one by one can be achieved, and the problem of UCE errors can be solved. This can improve the reliability of the memory and greatly reduce the risk of data loss and downtime.

[0134] It can be understood that the error correction information of the CE error described above with reference to Figure 6 can also be stored and used by software, and the corresponding modules (such as module 614 to module 624) can also be implemented by software. In this way, the compatibility of the DDR memory can be improved.

[0135] Figure 7 FIG. shows a schematic diagram of an electronic device 700 according to at least one embodiment of the present disclosure. As Figure 7 shown, the electronic device 700 includes a processor 710 and a memory 720.

[0136] The memory 720 includes one or more computer program modules 721. The one or more computer program modules 721 are stored in the memory 720 and are configured to be executed by the processor 710. The one or more computer program modules 721 include instructions for executing the method for data error correction provided by at least one embodiment of the present disclosure. When these instructions are executed by the processor 710, one or more steps of the method for data error correction provided by at least one embodiment of the present disclosure and its additional aspects can be executed. The memory 720 and the processor 710 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0137] For example, the processor 710 can be a central processing unit (CPU), a digital signal processor (DSP), or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA), etc.; for example, the central processing unit (CPU) can be of the X86 or ARM architecture, the RISC-V architecture, etc. The processor 710 can be a general-purpose processor or a dedicated processor, and can control other components in the electronic device 700 to perform desired functions.

[0138] For example, the memory 720 can include any combination of one or more computer program products, and the computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 721 can be stored on the computer-readable storage media, and the processor 710 can run one or more computer program modules 721 to implement various functions of the electronic device 700. Various application programs and various data, as well as various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media. The electronic device 700 can be, for example, a system-on-chip (SOC) or a computer, a television, a display, etc. including the SOC. The specific functions and technical effects of the electronic device 700 can refer to the description of the method for data error correction and its additional aspects in the foregoing text, and will not be elaborated here.

[0139] Figure 8 The schematic diagram of another electronic device 800 according to at least one embodiment of the present disclosure is shown. The electronic device 800 is, for example, suitable for implementing the method for data error correction and its additional aspects provided by at least one embodiment of the present disclosure. It should be noted that Figure 8 The shown electronic device 800 is only an example, and it will not bring any limitations to the functions and usage scope of at least one embodiment of the present disclosure.

[0140] As Figure 8As shown, the electronic device 800 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 810, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 into a random access memory (RAM) 830. In the RAM 830, various programs and data required for the operation of the electronic device 800 may also be stored. The processing device 810, the ROM 820, and the RAM 830 are connected to each other through a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0141] Generally, the following devices may be connected to the I / O interface 850: input devices 860 such as a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 870 such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 880 such as a magnetic tape, a hard disk, etc.; a communication device 890. The communication device 890 may allow the electronic device 800 to communicate with other electronic devices wirelessly or wiredly to exchange data. Although Figure 8 the electronic device 800 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices, and the electronic device 800 may alternatively implement or have more or fewer devices.

[0142] For example, the method for data error correction and its additional aspects provided by at least one embodiment of the present disclosure may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program codes for executing the above-mentioned method for data error correction and its additional aspects. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device 890, or installed from the storage device 880, or installed from the ROM 820. When the computer program is executed by the processing device 810, the method for data error correction and its additional aspects provided by at least one embodiment of the present disclosure may be executed.

[0143] At least one embodiment of the present disclosure also provides a non-transitory readable storage medium. Figure 9 A schematic diagram of a non-transitory readable storage medium 900 according to at least one embodiment of the present disclosure is shown. As Figure 9 shown, computer instructions 910 are stored on the non-transitory readable storage medium 900, and when the computer instructions 910 are executed by a processor, one or more steps of the method for data error correction and its additional aspects described above are executed.

[0144] For example, the non-transitory readable storage medium 900 may be any combination of one or more computer-readable storage media. For example, one computer-readable storage medium includes computer-readable program code for reading first object data from a storage address, another computer-readable storage medium includes computer-readable program code for performing a first check on the first object data, another computer-readable storage medium includes computer-readable program code for, in response to the check result of the first check indicating that the first object data includes a first type of data error, using historical error correction information for a second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data, and another computer-readable storage medium includes computer-readable program code for obtaining error-free data corresponding to the storage address from the intermediate data. As another example, one computer-readable storage medium includes computer-readable program code for separately reading multiple pieces of object data from a storage address, another computer-readable storage medium includes computer-readable program code for separately performing a first check on the multiple pieces of object data, another computer-readable storage medium includes computer-readable program code for, in response to the check results of the first check performed on the multiple pieces of object data indicating that the multiple pieces of object data respectively include correctable errors, storing multiple pieces of error correction information for the multiple pieces of object data, where each of the multiple pieces of error correction information includes computer-readable program code for the storage location targeted by the corresponding correctable error, and another computer-readable storage medium includes computer-readable program code for correcting data errors of first object data subsequently read from the storage address according to the multiple pieces of error correction information.

[0145] Of course, the above-mentioned respective program codes may also be stored in the same computer-readable medium, and the embodiments of the present disclosure do not limit this.

[0146] For example, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium and perform, for example, the method for data error correction and its additional aspects provided in any one of the embodiments of the present disclosure.

[0147] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, and may also be other applicable storage media.

[0148] It can be understood that the block diagrams in this article can represent a conceptual diagram of an illustrative circuit system or other functional units that embody the principles of the described embodiments. Similarly, it can be understood that any flowchart, etc., represents various processes that can be substantially represented in a computer-readable storage medium and executed by a computer or a processor, whether or not such a computer or processor is explicitly shown. The functions of various elements including functional blocks can be provided by using hardware (such as circuit hardware and / or hardware capable of executing software in the form of encoded instructions stored on the aforementioned computer-readable storage medium). Therefore, such functions and the shown functional blocks will be understood to be hardware-implemented and / or computer-implemented, and thus machine-implemented. In terms of hardware implementation, the functional blocks can include or cover but are not limited to digital signal processor (DSP) hardware, reduced instruction set processors, hardware (e.g., digital or analog) circuit systems, including but not limited to (multiple) application specific integrated circuit (ASIC) and / or (multiple) field programmable gate array (FPGA), and (where appropriate) state machines capable of executing these functions.

[0149] In terms of computer implementation, a computer is generally understood to include one or more processors or one or more controllers. When provided by a computer or a processor or a controller, the functions can be provided by a single dedicated computer or processor or controller, a single shared computer or processor or controller, or multiple separate computers or processors or controllers, some of which can be shared or distributed.

[0150] The various embodiments in this disclosure are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0151] In several embodiments provided by the present disclosure, it should be understood that each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and this module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the block / operation may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks / operations may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block / operation in the block diagram and / or flowchart, and the combination of blocks / operations in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

[0152] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements not only includes those elements, but also further includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the existence of additional identical elements in the process, method, article, or device comprising the elements.

[0153] The above are only the preferred embodiments of the present disclosure and are not used to limit the present disclosure. For those skilled in the art, the present disclosure may have various changes and variations.

Claims

1. A method for data error correction, comprising: Read first object data from a storage address; Perform a first check on the first object data; In response to the check result of the first check indicating that the first object data includes a first type of data error, use historical error correction information of a second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data; And Obtain error-free data corresponding to the storage address from the intermediate data, wherein, for the check algorithm used for the first check, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error, wherein using historical error correction information of a second type of data error for the storage address to at least partially correct the first type of data error to obtain the intermediate data includes: In response to the historical error correction information indicating that the storage address has a fixed error at the same position, correct the data bits in the first object data corresponding to the same position to obtain the intermediate data.

2. The method according to claim 1, further comprising: Judge whether the storage address has a fixed error at the same position according to the historical error correction information.

3. The method according to claim 2, wherein, Judge whether the storage address has a fixed error at the same position according to the historical error correction information, including: In response to the historical error correction information including N consecutive error correction information related to the second type of data error and the N error correction information being directed to the same position, determine that the storage address has a fixed error at the same position, where N is an integer greater than or equal to 2.

4. The method according to claim 1, further comprising: In response to the historical error correction information indicating that the storage address does not have a fixed error at the same position, read second object data from the storage address again and perform the first check on the second object data again; And In response to the check result of the first check performed again indicating that the second object data includes the first type of data error, perform an error reporting operation.

5. The method according to claim 1, wherein, Obtain error-free data corresponding to the storage address from the intermediate data, including: Perform a second check on the intermediate data to correct the remaining data errors in the intermediate data, thereby obtaining the error-free data corresponding to the storage address.

6. The method according to claim 5, wherein, The first check and the second check use the same check algorithm.

7. The method according to claim 1, wherein, The check algorithm is the RS algorithm.

8. The method according to claim 1, wherein, The storage address relates to the same memory die or multiple memory dies in a memory.

9. A method for data error correction, comprising: Read multiple object data from the storage address respectively; Perform a first check on the multiple object data respectively; In response to the check results of the first check performed on the multiple object data indicating that the multiple object data respectively include correctable errors, store multiple error correction information of the multiple object data, wherein each of the multiple error correction information includes the storage position targeted by the corresponding correctable error; Correct the data errors of the first object data read subsequently from the storage address according to the multiple error correction information, wherein correcting the data errors of the first object data read subsequently from the storage address according to the multiple error correction information includes: In response to the plurality of error correction messages indicating that there is a fixed error in the same storage location for the storage address, correct the data bits in the first object data corresponding to the same storage location.

10. The method according to claim 9, wherein, Correcting data errors of the first object data subsequently read from the storage address according to the plurality of error correction messages includes: In response to the verification result of the first verification of the first object data indicating that the first object data includes uncorrectable errors, using the plurality of error correction messages to at least partially correct the uncorrectable errors to obtain intermediate data; and Obtaining error-free data corresponding to the storage address from the intermediate data.

11. An apparatus for data error correction, comprising: A reading unit configured to read first object data from a storage address; A first verification unit configured to perform a first verification on the first object data; A first correction unit configured to: in response to the verification result of the first verification indicating that the first object data includes a first type of data error, use historical error correction information of a second type of data error for the storage address to at least partially correct the first type of data error to obtain intermediate data; And A second correction unit configured to obtain error-free data corresponding to the storage address from the intermediate data, wherein, for the verification algorithm adopted for the first verification, the number of correctable error bits in the second type of data error is less than the number of correctable error bits in the first type of data error, wherein the first correction unit is further configured to: In response to the historical error correction information indicating that there is a fixed error in the same location for the storage address, correct the data bits in the first object data corresponding to the same location to obtain the intermediate data.

12. An apparatus for data error correction, comprising: A reading unit reads a plurality of object data from a storage address respectively; A first verification unit performs a first verification on the plurality of object data respectively; A storage unit stores a plurality of error correction messages of the plurality of object data in response to the verification results of the first verification performed on the plurality of object data indicating that the plurality of object data respectively include correctable errors, wherein each of the plurality of error correction messages includes the storage location targeted by the corresponding correctable error; A correction unit corrects data errors of the first object data subsequently read from the storage address according to the plurality of error correction messages, wherein correcting data errors of the first object data subsequently read from the storage address according to the plurality of error correction messages includes: In response to the plurality of error correction messages indicating that there is a fixed error in the same storage location for the storage address, correct the data bits in the first object data corresponding to the same storage location.

13. An electronic device, comprising: A processor; A memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the method according to any one of claims 1-10 when executed by the processor.

14. A non-transitory computer-readable storage medium having executable instructions stored thereon, wherein, When the executable instructions are executed by a processor, the processor executes the method according to any one of claims 1-10.

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