AI SoC chip and startup method thereof

Abstract

The present invention proposes an AI SoC chip and a startup method thereof, which belong to the field of chips. The AI SoC chip includes: a state machine, and a target module connected to the state machine; wherein the state machine is used to receive a target signal, determine whether the target signal is a first target signal, generate a judgment result, and generate and send a first response signal to the target module when the judgment result is yes; the target module is used to receive the first response signal sent by the state machine, and perform corresponding operations based on the first response signal. The present invention uses a state machine to determine whether the received signal is a target signal. When the signal is a target signal, a corresponding signal is sent to the target module to start the target module, thereby realizing the use of a state machine to configure key IP or data processing in advance to achieve the effect of rapid system startup and improve startup efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to an AI SoC chip and a startup method thereof. Background Art

[0002] With the rapid development of deep learning, AI SoC chips have been widely used in personal computers, industrial computers, network video recorders, servers and other devices. The design complexity and circuit scale of AI SoC chips far exceed those of ordinary chips. The power-on startup process is particularly critical. Usually, chip power-on startup involves external power supply, reset, and clock; on-chip initialization of system control, power management, and high-security level mode.

[0003] The chip power-on startup process is an important part of chip design. The traditional chip power-on startup process flow is as follows:

[0004] 1. After the chip is powered on, the power management unit is used to determine whether the voltage is normal. If it is normal, the power-on reset signal is canceled;

[0005] 2. Chip reset is released synchronously, and the external reset signal is synchronized through the IO PAD input clock to reset the entire chip;

[0006] 3. Chip system initialization, through the IO PAD input to determine the CPU to select the external memory (Nandflash / eMMC / SPI flash / SD card) to obtain the instruction set, so that the chip enters the normal working state, where the instruction set content can be defined by the user.

[0007] Among them, in step 3, it takes a long time for the CPU to select the external memory to obtain the instruction set, which is not conducive to the rapid startup of the entire system solution. Summary of the Invention

[0008] The main purpose of the present invention is to provide an AI SoC chip and its startup method, aiming to solve the technical problem that the third step of the traditional power-on process is time-consuming and not conducive to the rapid startup of the entire chip.

[0009] To achieve the above objectives, the present invention provides an AI SoC chip, comprising:

[0010] A state machine, and a target module connected to the state machine; wherein,

[0011] The state machine is configured to receive a target signal, determine whether the target signal is a first target signal, generate a determination result, and generate and send a first response signal to the target module when the determination result is yes;

[0012] The target module is configured to receive the first response signal sent by the state machine and perform corresponding operations based on the first response signal.

[0013] Optionally, the AI SoC chip further includes:

[0014] A CPU module connected to the target module via a communication bus, and a memory module connected to the CPU module via a communication bus; wherein,

[0015] The CPU module is configured to receive a second target signal, read a corresponding operation instruction from the memory module based on the second target signal, and generate and send a third target signal to the target module based on the operation instruction;

[0016] The target module is further configured to receive the third target signal sent by the CPU module and perform corresponding operations based on the third target signal;

[0017] The memory module is used to store corresponding operation instructions.

[0018] Optionally, the state machine is further connected to the CPU module via a communication bus;

[0019] The state machine is further configured to determine whether the target signal is a fourth target signal, generate a determination result, and generate and send a second response signal to the CPU module when the determination result is yes;

[0020] The CPU module is further configured to read a corresponding operation instruction from the memory module upon receiving the second response signal, and generate and send the third target signal to the target module based on the operation instruction.

[0021] Optionally, the target module includes a PLL module; wherein,

[0022] The PLL module is configured to receive the first response signal sent by the state machine, be enabled based on the first response signal, and generate and output a fifth target signal and a target clock to the state machine.

[0023] Optionally, the target module further includes a PCIe module; wherein,

[0024] The state machine is further configured to determine whether the target signal is the fifth target signal, generate a determination result, and if the determination result is yes, generate a third response signal and send the third response signal and the target clock to the PCIe module;

[0025] The PCIe module is configured to adjust the working clock to the target clock upon receiving the third response signal.

[0026] Optionally, the state machine is further configured to determine whether the received signal is a reset signal, generate a determination result, and generate and send a reset signal to the CPU module and the target module respectively when the determination result is yes;

[0027] The CPU module is further configured to reset and stop working upon receiving the reset signal;

[0028] The target module is further configured to reset and stop working upon receiving the reset signal.

[0029] In addition, to achieve the above-mentioned purpose, the present invention also provides an AI SoC chip startup method for a state machine, the method comprising:

[0030] Receive target signal;

[0031] determining whether the target signal is a first target signal;

[0032] If it is a first target signal, an enable signal is generated and sent to the first target module to enable the first target module.

[0033] Optionally, after the step of generating and sending an enable signal to the first target module if the signal is the first target signal, the method further includes:

[0034] If a feedback signal sent by the first target module is received, a corresponding operation instruction is generated based on the feedback signal and sent to the corresponding second target module, so that the second target module performs a corresponding operation based on the corresponding operation instruction.

[0035] Optionally, after the step of generating and sending a corresponding operation instruction to the corresponding second target module based on the feedback signal if a feedback signal sent by the first target module is received, so that the second target module performs a corresponding operation based on the corresponding operation instruction, the method further includes:

[0036] Determine whether the received signal is a reset signal;

[0037] If it is a reset signal, a reset instruction is generated and sent to the corresponding target module, so that the corresponding target module is reset to stop working.

[0038] Optionally, it is characterized in that, after the step of determining whether the target signal is the first target signal, the method further includes:

[0039] If it is not the first target signal, determining whether the received signal is the second target signal;

[0040] If it is the second target signal, a response signal is generated and sent to the CPU module, so that the CPU module reads the corresponding instruction in the memory and enables the target module.

[0041] The present invention proposes an AI SoC chip and a startup method thereof, wherein the AI SoC chip includes: a state machine, and a target module connected to the state machine; wherein the state machine is used to receive a target signal, determine whether the target signal is a first target signal, generate a judgment result, and generate and send a first response signal to the target module when the judgment result is yes; the target module is used to receive the first response signal sent by the state machine and perform corresponding operations based on the first response signal. The present invention uses a state machine to determine whether the received signal is the first target signal. When the signal is the first target signal, the first response signal is sent to the target module to start the target module, thereby realizing the use of the state machine to configure key IP or data processing in advance to achieve the effect of rapid system startup and improve startup efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic diagram of the structure of the first embodiment of the AI SoC chip of the present invention;

[0043] Figure 2 This is a flowchart of the first embodiment of the AI SoC chip startup method of the present invention;

[0044] Figure 3 The figure is a flow chart of an implementation scenario of the present invention.

[0045] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0046] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0047] The main solution of an embodiment of the present invention is: the AI SoC chip includes: a state machine, and a target module connected to the state machine; wherein, the state machine is used to receive a target signal, determine whether the target signal is a first target signal, generate a judgment result, and generate and send a first response signal to the target module when the judgment result is yes; the target module is used to receive the first response signal sent by the state machine, and perform corresponding operations based on the first response signal.

[0048] Since the third step of the conventional power-on process in the existing technology takes a long time, it is not conducive to the rapid startup of the entire system solution.

[0049] The present invention provides a solution that uses a state machine to configure key IP or data processing in advance to achieve a rapid system startup effect and improve startup efficiency.

[0050] Reference Figure 1 , Figure 1 This is a structural diagram of the first embodiment of an AI SoC chip of the present invention. It should be noted that the SoC chip is called a system-on-chip (System on Chip), also known as a system on a chip, which means that it is a product, an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software.

[0051] The AI SoC chip includes:

[0052] A state machine, and a target module connected to the state machine; wherein,

[0053] The state machine can be composed of state registers and combinational logic circuits. It can transfer states according to pre-set states based on control signals. It is the control center that coordinates related signal actions and completes specific operations.

[0054] Among them, the target module may include a specific circuit structure, such as: efuse circuit, PLL circuit and / or PCIe, etc. Further, the circuit structure performs a power-on operation by receiving a corresponding electrical signal to achieve the purpose of enabling the target module.

[0055] The state machine is configured to receive a target signal, determine whether the target signal is a first target signal, generate a determination result, and generate and send a first response signal to the target module when the determination result is yes;

[0056] Among them, the target signal includes a high-level signal or a low-level signal. Further, after the state machine receives the target signal, it is determined whether the signal is a high-level signal. As an embodiment, if it is a high-level signal, a first response signal is generated and sent to the target module.

[0057] As another embodiment, the AI SoC chip further includes: a CPU module connected to the target module and the state machine via a communication bus, respectively; and a memory module connected to the CPU module via the communication bus, wherein the CPU module is configured to receive a second target signal, read a corresponding operation instruction from the memory module based on the second target signal, and generate and send a third target signal to the target module based on the operation instruction;

[0058] Among them, the memory module stores the startup instructions of the corresponding module. In this embodiment, the user can directly choose to use the CPU module to start the corresponding function of the chip, that is, the CPU selects the external memory (Nandflash / eMMC / SPIflash / SD card) to obtain the instruction set, so that the chip enters a normal working state. The content of the instruction set can be defined by the user. After obtaining the instruction set, the operation signal corresponding to the instruction set is generated and the operation signal is sent to the corresponding module.

[0059] Furthermore, the target module is further configured to receive the third target signal sent by the CPU module and perform corresponding operations based on the third target signal;

[0060] The memory module is used to store corresponding operation instructions.

[0061] As an optional embodiment, the state machine is further connected to the CPU module via a communication bus;

[0062] The state machine is further configured to determine whether the target signal is a fourth target signal, generate a determination result, and generate and send a second response signal to the CPU module when the determination result is yes;

[0063] The fourth target signal can be a low-level signal. After the state machine receives the low-level signal, it sends a corresponding signal to the CPU module, so that the CPU module selects the external memory (Nandflash / eMMC / SPI flash / SD card) to obtain the instruction set, so that the chip enters the normal working state. The content of the instruction set can be defined by the user. After obtaining the instruction set, the operation signal corresponding to the instruction set is generated and sent to the corresponding module.

[0064] The CPU module is further configured to read a corresponding operation instruction from the memory module upon receiving the second response signal, and generate and send the third target signal to the target module based on the operation instruction. If the third target signal is a low level signal, generate and send a second response signal to the CPU,

[0065] The target module is configured to receive the first response signal sent by the state machine and perform corresponding operations based on the first response signal.

[0066] An embodiment of the present invention proposes an AI SoC chip, wherein the AI SoC chip includes: a state machine, and a target module connected to the state machine; wherein the state machine is used to receive a target signal, determine whether the target signal is a first target signal, generate a judgment result, and generate and send a first response signal to the target module when the judgment result is yes; the target module is used to receive the first response signal sent by the state machine and perform corresponding operations based on the first response signal. The state machine determines whether the received signal is a target signal. When the signal is a target signal, a corresponding signal is sent to the target module to start the target module, thereby realizing the use of the state machine to configure key IP or data processing in advance to achieve the effect of rapid system startup and improve startup efficiency.

[0067] On the basis of the above embodiments, a second embodiment of the AI SoC chip of the present application is proposed. In this embodiment, the target module includes a PLL module; wherein, PLL (Phase Locked Loop) is a phase-locked loop or phase-locked loop, which is used to unify and integrate clock signals to enable high-frequency devices to work normally, such as memory access data. PLL is used as a feedback technology in oscillators. For many electronic devices to work properly, it is usually necessary to synchronize the external input signal with the internal oscillation signal. Due to process and cost reasons, ordinary crystal oscillators cannot achieve very high frequencies. When high-frequency applications are required, the corresponding device VCO is used to convert to high frequency, but it is not stable. Therefore, a phase-locked loop can be used to achieve a stable and high-frequency clock signal.

[0068] Furthermore, the PLL module is configured to receive the first response signal sent by the state machine, be enabled based on the first response signal, and generate and output the fifth target signal and the target clock to the state machine.

[0069] As an optional embodiment, after determining that the PLL can stably output the clock signal, a fifth target signal is generated and sent to the state machine.

[0070] Furthermore, the target module also includes a PCIe module; wherein, PCI-Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, its original name is "3GIO", which was proposed by Intel in 2001 and aims to replace the old PCI, PCI-X and AGP bus standards.

[0071] PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) functions.

[0072] The state machine is further configured to determine whether the target signal is a fifth target signal, generate a determination result, and if the determination result is yes, generate a third response signal and send the third response signal and the target clock to the PCIe module;

[0073] The PCIe module is configured to adjust the working clock to the target clock upon receiving the third response signal.

[0074] Furthermore, as a third embodiment of the AI SoC chip of the present application, the state machine is further configured to determine whether the received signal is a reset signal, generate a determination result, and generate and send a reset signal to the CPU module and the target module respectively when the determination result is yes;

[0075] The CPU module is further configured to reset and stop working upon receiving the reset signal;

[0076] The target module is further configured to reset and stop working upon receiving the reset signal.

[0077] Furthermore, after receiving the reset signal, the CPU and each target module are reset, stop working and wait for the next signal input.

[0078] Based on the above embodiments, a flowchart of a first embodiment of the AI SoC chip startup method of the present application is proposed, which is characterized in that it is used for a state machine and includes:

[0079] Step S10, receiving a target signal;

[0080] The target signal may include: high-level and low-level signals. As an embodiment, the first target signal is a high-level signal.

[0081] Step S20, determining whether the target signal is a first target signal;

[0082] Furthermore, after step S20, the method further includes:

[0083] Step S21, if it is not the first target signal, determine whether the received signal is the second target signal;

[0084] Step S22: If it is the second target signal, a response signal is generated and sent to the CPU module, so that the CPU module reads the corresponding instruction in the memory and enables the target module.

[0085] Step S30: If it is the first target signal, generate and send an enable signal to the first target module to enable the first target module.

[0086] Furthermore, as an optional embodiment, after step S30, the method further includes:

[0087] Step S31 : if a feedback signal sent by the first target module is received, then a corresponding operation instruction is generated based on the feedback signal and sent to the corresponding second target module, so that the second target module performs a corresponding operation based on the corresponding operation instruction.

[0088] Furthermore, as an optional embodiment, after step S31, the method further includes:

[0089] Step S32, determining whether the received signal is a reset signal;

[0090] Step S33: If it is a reset signal, generate and send a reset instruction to the corresponding target module to reset the corresponding target module to stop working.

[0091] As an optional embodiment, the state machine also sends a reset instruction to the CPU chip, so that the CPU chip is reset at the same time.

[0092] Based on the above embodiments, a practical application scenario of this application is proposed. Taking the AI SoC chip Slave mode startup scenario as an example, the AI SoC chip Slave mode requires PCIe to quickly establish a link with the host computer for communication. This process requires configuring multiple PLLs to output specific frequencies, releasing PCIe reset, and configuring PCIe. Figure 3 , Figure 3 Schematic diagram of the AI SoC chip application process:

[0093] When the state machine is in the ST_STM_IDLE state (startup mode state machine, idle state): ⑤ When IO PAD = 0, the state machine enters the ST_STM_NOM state; ① When IO PAD = 1, the state machine enters the ST_STM_SLV_PLL_EN state.

[0094] When the state machine is in the ST_STM_SLV_PLL_EN state (boot mode state machine, AI SoC chip slave mode PLL enabled state): After enabling and configuring the PLL, the state machine enters the ST_STM_SLV_PLL_LOCK state. Otherwise, the state machine remains in the ST_STM_SLV_PLL_EN state.

[0095] When the state machine is in the ST_STM_SLV_PLL_LOCK state (startup mode state machine, AI SoC chip slave mode waiting for PLL lock state): wait for pll_lock to equal 1 or timeout (stm_cnt[10:0]=2047), ③ the state machine enters the ST_STM_SLV_OPERATION state, otherwise the state machine stays in ST_STM_SLV_PLL_LOCK;

[0096] When the state machine is in the ST_STM_SLV_OPERATION state (startup mode state machine, normal working state of the AI SoC chip slave mode): switch the PCIe working clock from the reference clock to the PLL output clock, turn on the CLK_ICG related to PCIe and CPUCore 0; release the reset related to PCIe and CPU Core0; ④ After the corresponding module completes the above operations, the state machine enters ST_STM_DONE, otherwise it stays in ST_STM_SLV_OPERATION.

[0097] When the state machine is in the ST_STM_NOM state (boot mode state machine, AI SoC chip normal (host) mode state): release the CPU reset and clock ICG, the ⑥ state machine enters ST_STM_DONE, otherwise it stays in ST_STM_NOM.

[0098] When the state machine is in the ST_STM_DONE state (startup mode state machine, chip startup configuration state): In this state, the CPU starts to read the instruction set from the memory and performs the next initialization operation.

[0099] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An AI SoC chip, characterized in that: The AI SoC chip includes: A state machine, a target module connected to the state machine, a CPU module connected to the target module via a communication bus, and a memory module connected to the CPU module via a communication bus; wherein, The state machine is configured to receive a target signal during a startup phase of the AI SoC chip and determine a startup mode of the AI SoC chip based on a type of the target signal; wherein, when the target signal is a first target signal, the state machine generates and sends a first response signal to the target module; and when the target signal is a fourth target signal, the state machine generates and sends a second response signal to the CPU module; the CPU module is configured to, upon receiving the second response signal, read a corresponding operation instruction from the memory module based on the second response signal, generate a third target signal based on the operation instruction, and send the third target signal to the target module; The target module is used to perform corresponding operations according to the received content to complete the startup.

2. The AI SoC chip according to claim 1, wherein: The state machine is also connected to the CPU module via a communication bus; The state machine is further configured to determine whether the target signal is a fourth target signal, generate a determination result, and generate and send a second response signal to the CPU module when the determination result is yes; The CPU module is further configured to read a corresponding operation instruction from the memory module upon receiving the second response signal, and generate and send the third target signal to the target module based on the operation instruction.

3. The AI SoC chip according to claim 2, wherein: The target module includes a PLL module; wherein, The PLL module is configured to receive the first response signal sent by the state machine, be enabled based on the first response signal, and generate and output a fifth target signal and a target clock to the state machine.

4. The AI SoC chip according to claim 3, wherein: The target module also includes a PCIe module; wherein, The state machine is further configured to generate a third response signal and send the third response signal and the target clock to the PCIe module when a fifth target signal is received; The PCIe module is configured to adjust the working clock to the target clock upon receiving the third response signal.

5. The AI SoC chip according to claim 4, wherein: The state machine is further configured to generate and send reset signals to the CPU module and the target module respectively when a reset signal is received; The CPU module is further configured to reset and stop working upon receiving the reset signal; The target module is further configured to reset and stop working upon receiving the reset signal.

6. A method for starting an AI SoC chip, characterized in that: For a state machine, the method comprises: Receive target signals during the startup phase of the AI SoC chip; The startup mode of the AI SoC chip is determined according to the type of the target signal; wherein, when the target signal is a first target signal, an enable signal is generated and sent to the first target module to enable the first target module.

7. The AI SoC chip startup method according to claim 6, wherein: After the step of generating and sending an enable signal to the first target module to enable the first target module when the target signal is the first target signal, the method further includes: If a feedback signal sent by the first target module is received, a corresponding operation instruction is generated based on the feedback signal and sent to the corresponding second target module, so that the second target module performs a corresponding operation based on the corresponding operation instruction.

8. The AI SoC chip startup method according to claim 7, wherein: After the step of generating and sending a corresponding operation instruction to the corresponding second target module based on the feedback signal if a feedback signal sent by the first target module is received, so that the second target module performs a corresponding operation based on the corresponding operation instruction, the method further includes: Determine whether the received signal is a reset signal; If it is a reset signal, a reset instruction is generated and sent to the corresponding target module, so that the corresponding target module is reset to stop working.

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