Semiconductor storage devices

Abstract

A semiconductor memory device includes: a first counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal, and to generate a first count code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a second counting circuit adapted to count the second clock signal and to generate a second count code signal; and a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the first count code signal and the second count code signal.

Description

[0001] This patent application is a divisional application of Chinese invention patent application No. 201810156970.9, filed on February 24, 2018, entitled "Semiconductor Memory Device". Technical Field

[0002] An exemplary embodiment relates to a semiconductor design technique, and more specifically, to a semiconductor memory device that performs a refresh operation. Background Technology

[0003] Semiconductor memory devices consist of memory cells configured with transistors acting as switches and capacitors storing charge (data). Data is classified as logic high (logic 1) or logic low (logic 0) based on the presence or absence of charge in the capacitor of the memory cell (i.e., whether the voltage across the capacitor is high or low). In principle, data storage consumes no power because it is implemented by accumulating charge in the capacitor. However, data can be lost because the initial amount of charge stored in the capacitor may decrease due to leakage current caused by factors such as the PN junction of the MOS transistor. To prevent this, the data in the memory cell should be read before data loss, and the cell should be recharged to its normal charge level based on the read information. Data storage can only be maintained by periodically repeating this operation. This process of recharging the cell charge is called a refresh operation.

[0004] Meanwhile, as the integration density of semiconductor memory devices increases, the spacing between the multiple word lines included in the semiconductor memory device decreases. As the spacing between word lines decreases, the coupling effect between adjacent word lines increases.

[0005] Whenever data is input to or output from a memory cell, a word line switches between an active (activated) state and a deactivated (inactive) state. In this regard, due to the increased coupling effect between adjacent word lines as described above, the following phenomenon occurs: data in memory cells coupled to word lines adjacent to frequently active word lines becomes corrupted. This phenomenon is called row hammering. Due to row hammering, data in a memory cell may be corrupted before the cell is refreshed.

[0006] Figure 1 This is a diagram illustrating a portion of an array of memory cells included in a semiconductor memory device, used to illustrate row hammering.

[0007] refer to Figure 1Word line WLK corresponds to a frequently activated word line with a large number of activations, while word lines WLK-1 and WLK+1 correspond to adjacent word lines located adjacent to the frequently activated word line WLK. Furthermore, memory cell CELL_K is coupled to the frequently activated word line WLK, memory cell CELL_K-1 is coupled to the adjacent word line WLK-1, and memory cell CELL_K+1 is coupled to the adjacent word line WLK+1. The corresponding memory cells CELL_K, CELL_K-1, and CELL_K+1 include cell transistors TR_K, TR_K-1, and TR_K+1, and cell capacitors CAP_K, CAP_K-1, and CAP_K+1.

[0008] exist Figure 1 In this context, when a frequently activated word line WLK is activated or deactivated, the coupling phenomenon between the frequently activated word line WLK and its adjacent word lines WLK-1 and WLK+1 causes the voltage of the adjacent word lines WLK-1 and WLK+1 to increase or decrease, thus affecting the charge of the cell capacitors CAP_K-1 and CAP_K+1. Therefore, with frequent activation of the frequently activated word line WLK and its switching between active and deactivated states, the change in charge in the cell capacitors CAP_K-1 and CAP_K+1 included in the memory cells CELL_K-1 and CELL_K+1 can increase, and the data in the memory cells CELL_K-1 and CELL_K+1 may degrade.

[0009] Furthermore, data may be corrupted because electromagnetic waves generated when word lines switch between active and deactivated states can introduce electrons into or discharge electrons from the cell capacitors of memory cells coupled to adjacent word lines.

[0010] The primary method for addressing row hammering (where data degradation occurs in memory cells coupled to word lines WLK-1 and WLK+1 when word line WLK is repeatedly activated at least a predetermined number of times, according to row hammering) is to perform an additional refresh on adjacent word lines affected by row hammering (e.g., WLK+1 and WLK-1) in addition to the regular refresh operation. This additional refresh operation on adjacent word lines is called a target refresh operation. Summary of the Invention

[0011] Each embodiment of the present invention relates to a semiconductor memory device capable of effectively preventing row hammering in burst refresh mode.

[0012] In one embodiment, a semiconductor memory device may include: a first counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal, and to generate a first count code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a second counting circuit adapted to count the second clock signal and to generate a second count code signal; and a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the first count code signal and the second count code signal.

[0013] When the first count value corresponding to the first count code signal and the second count value corresponding to the second count code signal are the same, the control circuit can generate a latch control signal.

[0014] In response to a burst refresh command signal, the first counting circuit can be initialized in each burst refresh cycle and then count the first clock signal during each burst refresh cycle.

[0015] The periodic boot circuit can generate a second clock signal, which is activated based on a burst refresh command signal and deactivated based on a precharge signal.

[0016] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to the result of comparing a first count value corresponding to a first count code signal and a second count value corresponding to a second count code signal; a limiting unit adapted to generate a limiting signal activated during a limited period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal that switches during the limited period based on the limiting signal and a first clock signal.

[0017] The semiconductor memory device may also include a cycle switching circuit adapted to generate a non-periodic switching first clock signal based on a periodically switching third clock signal.

[0018] In one embodiment, a semiconductor memory device may include: a counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal, and to generate a count code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a randomization circuit adapted to generate a random code signal corresponding to a random value in each burst refresh cycle based on the second clock signal; and a control circuit adapted to generate a latch control signal for latching a target address in each burst refresh cycle based on the count code signal and the random code signal.

[0019] When the count value corresponding to the counter code signal and the random value corresponding to the random code signal are the same, the control circuit can generate a latch control signal.

[0020] In response to the burst refresh command signal, the counting circuit can be initialized in each burst refresh cycle and then count the first clock signal during each burst refresh cycle.

[0021] The periodic boot circuit can generate a second clock signal, which is activated based on a burst refresh command signal and deactivated based on a precharge signal.

[0022] The randomization circuit may include: a clock signal generation unit adapted to generate a third clock signal; a random value generation unit adapted to generate a code signal corresponding to a random value at least once in each burst refresh cycle based on the third clock signal; and a latching unit adapted to latch the code signal as a random code signal in each burst refresh cycle based on a second clock signal.

[0023] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to the result of comparing a count value corresponding to a counter code signal and a random value corresponding to a random code signal; a limiting unit adapted to generate a limiting signal activated during a limited period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal that switches during the limited period based on the limiting signal and a first clock signal.

[0024] The semiconductor memory device may also include a cycle switching circuit adapted to generate a non-periodic switching first clock signal based on a periodically switching fourth clock signal.

[0025] In one embodiment, a semiconductor memory device may include: a memory region adapted to perform normal operation based on a normal address signal and to perform a target refresh operation based on a target address signal; a refresh controller adapted to generate a latch control signal in each burst refresh cycle based on a burst refresh command signal, the latch control signal being activated within a restriction period different from a previous restriction period included in a previous burst refresh cycle; and an address latch adapted to latch a normal address signal input within a different restriction period as a target address signal in each burst refresh cycle based on the latch control signal.

[0026] The refresh controller may include: a first counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal, and generate a first count code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a second counting circuit adapted to count the second clock signal and generate a second count code signal; and a control circuit adapted to generate a latch control signal in each burst refresh cycle based on the first count code signal and the second count code signal.

[0027] When the first count value corresponding to the first count code signal and the second count value corresponding to the second count code signal are the same, the control circuit can generate a latch control signal.

[0028] In response to a burst refresh command signal, the first counting circuit can be initialized in each burst refresh cycle and then count the first clock signal during each burst refresh cycle.

[0029] The periodic boot circuit can generate a second clock signal, which is activated based on a burst refresh command signal and deactivated based on a precharge signal.

[0030] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to the result of comparing a first count value corresponding to a first count code signal and a second count value corresponding to a second count code signal; a limiting unit adapted to generate a limiting signal activated during a limited period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal that switches during the limited period based on the limiting signal and a first clock signal.

[0031] The refresh controller may also include a cycle switching circuit adapted to generate a non-periodic first clock signal based on a periodically switching third clock signal.

[0032] The refresh controller may include: a counting circuit adapted to count a first clock signal that switches continuously in each burst refresh cycle based on a burst refresh command signal, and generate a count code signal; a cycle guiding circuit adapted to generate a second clock signal that switches once in each burst refresh cycle based on the burst refresh command signal and a precharge signal; a randomization circuit adapted to generate a random code signal corresponding to a random value in each burst refresh cycle based on the second clock signal; and a control circuit adapted to generate a latching control signal in each burst refresh cycle when the count value corresponding to the count code signal and the random value corresponding to the random code signal are the same.

[0033] When the count value corresponding to the counter code signal and the random value corresponding to the random code signal are the same, the control circuit can generate a latch control signal.

[0034] In response to the burst refresh command signal, the counting circuit can be initialized in each burst refresh cycle and then count the first clock signal during each burst refresh cycle.

[0035] The periodic boot circuit can generate a second clock signal, which is activated based on a burst refresh command signal and deactivated based on a precharge signal.

[0036] The randomization circuit may include: a clock signal generation unit adapted to generate a third clock signal; a random value generation unit adapted to generate a code signal corresponding to a random value at least once in each burst refresh cycle based on the third clock signal; and a latching unit adapted to latch the code signal as a random code signal in each burst refresh cycle based on a second clock signal.

[0037] The control circuit may include: a comparison unit adapted to generate a comparison signal corresponding to the result of comparing a count value corresponding to a counter code signal and a random value corresponding to a random code signal; a limiting unit adapted to generate a limiting signal activated during a limited period based on the comparison signal and a burst refresh command signal; and an output unit adapted to output a latch control signal that switches during the limited period based on the limiting signal and a first clock signal.

[0038] The refresh controller may include a cycle switching circuit adapted to generate a non-periodic first clock signal based on a periodically switching fourth clock signal.

[0039] The memory area can perform a target refresh operation in each burst refresh cycle based on the burst refresh command signal and the previous target address signal that was latched as the target address signal during the previous restricted period.

[0040] In this embodiment, operational reliability under burst refresh mode can be improved by effectively preventing row hammering in burst refresh mode. Attached Figure Description

[0041] Figure 1 This is a diagram illustrating a portion of a memory cell array, used to illustrate row hammering.

[0042] Figure 2 This is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

[0043] Figure 3 The illustration shows an embodiment of the present invention. Figure 2The diagram shows a block diagram of the refresh controller.

[0044] Figure 4 The illustration shows another embodiment of the present invention. Figure 2 The diagram shows a block diagram of the refresh controller.

[0045] Figure 5 It is a diagram. Figure 3 and Figure 4 The block diagram of the control circuit shown is shown.

[0046] Figure 6 This means that the explanation includes Figure 3 The timing diagram shows the operation of the semiconductor memory device of the refresh controller.

[0047] Figure 7 This means that the explanation includes Figure 4 The timing diagram shows the operation of the semiconductor memory device of the refresh controller.

[0048] Figure 8 This is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

[0049] Figure 9 It is a diagram. Figure 8 The diagram shows a block diagram of the refresh controller.

[0050] Figure 10 It is a diagram. Figure 8 The diagram shows a block diagram of the refresh controller.

[0051] Figure 11 It is a diagram. Figure 9 and Figure 10 The block diagram of the randomization circuit shown is shown.

[0052] Figure 12 It is a diagram. Figure 9 and Figure 10 The block diagram of the control circuit shown is shown.

[0053] Figure 13 This means that the explanation includes Figure 10 The timing diagram shows the operation of the semiconductor memory device of the refresh controller. Detailed Implementation

[0054] Various embodiments will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in each of the drawings and embodiments of the invention.

[0055] Figure 2 This is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

[0056] refer to Figure 2 The semiconductor storage device may include a storage area 100, a refresh controller 200, and an address latch 300.

[0057] Memory area 100 can perform normal operations based on the normal command signal NOR_CMD and the normal address signal NADD, and perform target refresh operations based on the burst refresh command signal BUR_REF_CMD and the target address signal TADD. Although not shown in the figure, memory area 100 may include a memory array having multiple memory cells arranged in the row and column directions, and peripheral circuitry for performing normal and target refresh operations. For example, the peripheral circuitry may include word line drivers and row decoders for controlling the memory array row by row.

[0058] The burst refresh command signal BUR_REF_CMD can include multiple normal refresh command signals, which are input consecutively at the minimum time interval between them that allows the execution of the target refresh operation. For example, in an 8-burst refresh operation mode, the first through eighth normal refresh command signals can be input consecutively for each burst refresh cycle. In burst refresh operation mode, multiple target refresh operations are executed in a concentrated manner during a specific period of each burst refresh cycle, thus potentially ensuring that other operations (e.g., normal operations) can be performed during the remaining period of the burst refresh cycle without interference from the target refresh operations.

[0059] Normal operations may include write operations for writing data to the storage array and read operations for reading data from the storage array. Target refresh operations may include operations that refresh adjacent word lines in addition to normal refresh operations to cope with row hammering, in which the data in the storage cells coupled to adjacent word lines degrades because a particular word line is repeatedly accessed and activated at least a predetermined number of times.

[0060] The refresh controller 200 can generate a latch control signal SRLATEN for a restricted period in each burst refresh cycle based on the burst refresh command signal BUR_REF_CMD and the precharge signal PCG. This restricted period is different from the previous restricted period included in the previous burst refresh cycle.

[0061] Address latch 300 can latch the normal address signal NADD, which is input during different restricted periods in each burst refresh cycle, into the target address signal TADD based on the latch control signal SRLATEN.

[0062] Figure 3The illustration shows an embodiment of the present invention. Figure 2 The block diagram shown is of the refresh controller 200.

[0063] refer to Figure 3 The refresh controller 200 may include a first counting circuit 210, a periodic guidance circuit 220, a second counting circuit 230, and a control circuit 240.

[0064] The first counting circuit 210 can count the first clock signal OSC, which switches continuously during each burst refresh period, based on the burst refresh command signal BUR_REF_CMD, and generate a first count code signal OSC_CNT corresponding to its count value (hereinafter referred to as the "first count value"). In response to the burst refresh command signal BUR_REF_CMD, the first counting circuit 210 can be initialized in each burst refresh cycle and then count the first clock signal OSC during each burst refresh cycle.

[0065] The cycle bootstrapping circuit 220 can generate a second clock signal REFCLK that switches once in each burst refresh cycle based on the burst refresh command signal BUR_REF_CMD and the precharge signal PCG. The cycle bootstrapping circuit 220 can generate the second clock signal REFCLK, which is activated based on the burst refresh command signal BUR_REF_CMD and deactivated based on the precharge signal PCG. For example, the cycle bootstrapping circuit 220 may include an SR latch.

[0066] The second counting circuit 230 can count the second clock signal REFCLK and generate a second counting code signal REFCLK_CNT corresponding to its count value (hereinafter referred to as the "second count value").

[0067] The control circuit 240 can generate a latch control signal SRLATEN in each burst refresh cycle based on the first counter code signal OSC_CNT and the second counter code signal REFCLK_CNT. In each burst refresh cycle, when the first count value and the second count value are the same, the control circuit 240 can generate the latch control signal SRLATEN.

[0068] Figure 4 The illustration shows another embodiment of the present invention. Figure 2 The block diagram shown is of the refresh controller 200. Figure 3 and Figure 4 In this context, the same reference numerals are used to refer to the same elements.

[0069] refer to Figure 4The refresh controller 200 may include a first counting circuit 210, a period guiding circuit 220, a second counting circuit 230, a control circuit 240, and a period conversion circuit 250.

[0070] because Figure 4 The first counting circuit 210, the periodic guide circuit 220, the second counting circuit 230, and the control circuit 240 shown are... Figure 3 Those shown have essentially the same configuration, therefore their description will be omitted herein. However, the first counting circuit 210 can generate the first counting code signal PRBS_CNT based on the third clock signal PRBS, which will be described below, and the control circuit 240 can use the third clock signal PRBS and the first counting code signal PRBS_CNT instead of... Figure 3 The first clock signal OSC and the first counter code signal OSC_CNT shown are used to generate the latch control signal SRLATEN.

[0071] The control circuit 240 can generate a latch control signal SRLATEN based on the first counter code signal PRBS_CNT and the second counter code signal REFCLK_CNT when the first count value and the second count value are the same.

[0072] The cycle conversion circuit 250 can generate a non-periodic third clock signal PRBS based on a periodically switching first clock signal OSC. For example, the cycle conversion circuit 250 may include a pseudo-random binary sequence (PRBS) circuit.

[0073] Figure 5 It is a diagram. Figure 3 and Figure 4 The block diagram of the control circuit 240 shown is illustrated below. For ease of explanation, representative examples will be described in the following text. Figure 3 The control circuit 240 shown is shown.

[0074] refer to Figure 5 The control circuit 240 may include a comparison unit 241, a limiting unit 243, and an output unit 245.

[0075] The comparison unit 241 can generate a comparison signal CMP corresponding to the result of comparing the first count value and the second count value based on the first count code signal OSC_CNT and the second count code signal REFCLK_CNT.

[0076] The limiting unit 243 can generate a limiting signal GTED that is activated during the limiting period based on the comparison signal CMP and the burst refresh command signal BUR_REF_CMD. For example, the limiting unit 243 can generate a limiting signal GTED that is activated based on the burst refresh command signal BUR_REF_CMD and deactivated based on the comparison signal CMP.

[0077] Output unit 245 can generate a latch control signal SRLATEN that switches during a limited period based on a limit signal GTED and a first clock signal OSC. Output unit 245 can generate the latch control signal SRLATEN by strobing the first clock signal OSC according to the limit signal GTED. When the limit signal GTED is activated during the limited period, output unit 245 can output the first clock signal OSC as the latch control signal SRLATEN.

[0078] In the following text, reference will be made to Figure 6 and Figure 7 The operation of the semiconductor memory device having the above configuration according to the first embodiment will be described.

[0079] Figure 6 This means that the explanation includes Figure 3 The timing diagram shows the operation of the semiconductor memory device of the refresh controller 200.

[0080] refer to Figure 6 When the burst refresh command signal BUR_REF_CMD, which includes the first normal refresh command signal to the eighth normal refresh command signal, is input in 8-burst refresh operation mode, the burst refresh period tREFI*8 can include a time period corresponding to 8 times the normal refresh period tREFI assigned to each of the first normal refresh command signals to the eighth normal refresh command signals.

[0081] In each burst refresh cycle tREFI*8, the refresh controller 200 can generate a latch control signal SRLATEN within a restriction period that differs from the previous restriction period included in the previous burst refresh cycle. For example, in each burst refresh cycle tREFI*8, the refresh controller 200 can generate the latch control signal SRLATEN when the first count value corresponding to the first count code signal OSC_CNT and the second count value corresponding to the second count code signal REFCLK_CNT are the same. That is, in the first burst refresh cycle tREFI*8, when the restriction signal GTED is activated within the first restriction period from the time point when the burst refresh command signal BUR_REF_CMD is input to the time point when both the first count value and the second count value become "1", the refresh controller 200 can output the first clock signal OSC as the latch control signal SRLATEN. Furthermore, in the nth burst refresh cycle tREFI*8, when the limit signal GTED is activated during the nth limit period from the time point when the burst refresh command signal BUR_REF_CMD is input to the time point when both the first count value and the second count value become "n", the refresh controller 200 can output the first clock signal OSC as the latch control signal SRLATEN.

[0082] Address latch 300 can latch the normal address signal NADD, input during different restricted time periods in each burst refresh cycle tREFI*8, as the target address signal TADD based on the latch control signal SRLATEN. For example, in the first burst refresh cycle tREFI*8, address latch 300 can latch the normal address signal NADD, input during the second switch (i.e., the last switch) of the latch control signal SRLATEN during the first restricted time period, as the target address signal TADD. Furthermore, in the nth burst refresh cycle tREFI*8, address latch 300 can latch the normal address signal NADD, input during the (n+1)th switch (i.e., the last switch) of the latch control signal SRLATEN during the nth restricted time period, as the target address signal TADD.

[0083] For reference, if the latch control signal SRLATEN switches multiple times within each burst refresh cycle tREFI*8, the address latch 300 can latch the normal address signal NADD input each time the latch control signal SRLATEN switches. As a result, the address latch 300 can latch the normal address signal NADD input at the last switch of the latch control signal SRLATEN into the final target address signal TADD.

[0084] Simultaneously, within different defined time periods in each burst refresh cycle tREFI*8, the address latch 300 can latch the normal address signal NADD input during the last switching period of the latch control signal SRLATEN as the target address signal TADD. This is to sample any one of the multiple normal address signals NADD input sequentially in the burst refresh cycle tREFI*8. In other words, this is to sample any one of the normal address signals NADD input during different time periods in each burst refresh cycle tREFI*8. Here, sampling can mean randomly selecting the normal address signal NADD that has been input the most from among multiple normal address signals NADD. This is advantageous in terms of power and area compared to the method of counting multiple normal address signals NADD by each normal address signal, and also has the advantage of being able to sample and latch the normal address signal NADD input at different sampling time points in each burst refresh cycle tREFI*8 as the target address signal TADD.

[0085] Storage area 100 can perform a target refresh operation based on the burst refresh command signal BUR_REF_CMD and the target address signal TADD. For example, in each burst refresh cycle, when the burst refresh command signal BUR_REF_CMD is input, storage area 100 can perform a target refresh operation based on the previous target address signal TADD latched in the previous restricted period.

[0086] Figure 7 This means that the explanation includes Figure 4 The timing diagram shows the operation of the semiconductor memory device of the refresh controller 200.

[0087] because Figure 7 and Figure 6 They are essentially the same, therefore a description of them will be omitted in this article. However, in Figure 7 In comparison Figure 6 A non-periodic switching third clock signal PRBS can be used instead of a periodically switching first clock signal OSC. For example, the third clock signal PRBS can be switched non-periodicly in each predetermined period PRBS 15.

[0088] Figure 8 This is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

[0089] refer to Figure 8 The semiconductor storage device may include a storage area 1100, a refresh controller 1200, and an address latch 1300.

[0090] Since memory area 1100 and address latch 1300 can have substantially the same configuration as memory area 100 and address latch 300 shown in the first embodiment, a description of memory area 1100 and address latch 1300 will be omitted herein. The refresh controller 1200 will be described in detail below.

[0091] Figure 9 It is a diagram. Figure 8 The block diagram of the refresh controller 1200 shown is shown.

[0092] refer to Figure 9 The refresh controller 1200 may include a counting circuit 1210, a periodic guidance circuit 1220, a randomization circuit 1230, and a control circuit 1240.

[0093] Since the counting circuit 1210, the periodic guiding circuit 1220 and the control circuit 1240 can be used with the first embodiment (see...) Figure 3 The counting circuit 210, the periodic guide circuit 220 and the control circuit 240 included in the present invention have essentially the same configuration, so their description will be omitted here.

[0094] The randomization circuit 1230 can generate a random code signal RDNUM_CNT corresponding to a random value in each burst refresh cycle based on the second clock signal REFCLK.

[0095] Figure 10 It is a diagram. Figure 8 The block diagram of the refresh controller 1200 shown is shown.

[0096] refer to Figure 10 Compared to Figure 9 The refresh controller 1200 may also include a cycle conversion circuit 1250. Since the cycle conversion circuit 1250 can be used with the first embodiment (see...) Figure 4 The cycle conversion circuit 250 included in the present invention has a substantially the same configuration, therefore its description will be omitted here.

[0097] Figure 11 It is a diagram. Figure 9 and Figure 10 The block diagram of the randomization circuit 1230 shown is shown.

[0098] refer to Figure 11 The randomization circuit 1230 may include a clock signal generation unit 1231, a random value generation unit 1233, and a latch unit 1235.

[0099] The clock signal generation unit 1231 can generate a fourth clock signal OSC′.

[0100] The random value generation unit 1233 can generate a code signal RDNUM corresponding to the random value at least once in each burst refresh cycle based on the fourth clock signal OSC′.

[0101] The latch unit 1235 can latch the code signal RDNUM into a random code signal RDNUM_CNT in each burst refresh cycle based on the second clock signal REFCLK.

[0102] Figure 12 It is a diagram. Figure 9 and Figure 10 The block diagram of the control circuit 1240 shown is shown.

[0103] refer to Figure 12 The control circuit 1240 may include a comparison unit 1241, a limiting unit 1243, and an output unit 1245.

[0104] Since the comparison unit 1241, the limiting unit 1243, and the output unit 1245 can have substantially the same configuration as those in the first embodiment, a detailed description thereof will be omitted herein. However, the comparison unit 1241 can compare the random code signal RDNUM_CNT with the counting code signal OSC_CNT or PRBS_CNT.

[0105] In the following text, reference will be made to Figure 13 The operation of the semiconductor memory device having the above configuration according to the second embodiment will be described.

[0106] Figure 13 This means that the explanation includes Figure 10 The timing diagram shows the operation of the semiconductor memory device of the refresh controller 1200 shown.

[0107] refer to Figure 13 When the burst refresh command signal BUR_REF_CMD, which includes the first normal refresh command signal to the eighth normal refresh command signal, is input in 8-burst refresh operation mode, the burst refresh period tREFI*8 can include a time period corresponding to 8 times the refresh period tREFI assigned to each of the first normal refresh command signals to the eighth normal refresh command signals.

[0108] In each burst refresh cycle tREFI*8, the refresh controller 1200 can generate a latch control signal SRLATEN within a restriction period that is different from the previous restriction period included in the previous burst refresh cycle. For example, in each burst refresh cycle tREFI*8, when the count value corresponding to the counter code signal PRBS_CNT and the random value corresponding to the random code signal RDNUM_CNT are the same, the refresh controller 1200 can generate the latch control signal SRLATEN. If the random code signal RDNUM_CNT corresponding to the random value "5" is generated in the first burst refresh cycle tREFI*8, then when the restriction signal GTED is activated during the first restriction period from the time point when the burst refresh command signal BUR_REF_CMD is input to the time point when the count value corresponding to the counter code signal PRBS_CNT becomes the random value "5", the control circuit 1240 can output the third clock signal PRBS as the latch control signal SRLATEN. If a random code signal RDNUM_CNT corresponding to the random value "10" is generated in the second burst refresh cycle tREFI*8, then when the limit signal GTED is activated during the second limit period that includes the entire second burst refresh cycle tREFI*8, the control circuit 1240 can output the third clock signal PRBS as the latch control signal SRLATEN.

[0109] Address latch 1300 can latch the normal address signal NADD, input during different restricted periods in each burst refresh cycle tREFI*8, into a target address signal TADD based on the latch control signal SRLATEN. For example, in the first burst refresh cycle tREFI*8, address latch 1300 can latch the normal address signal NADD, input when the latch control signal SRLATEN last switches during the first restricted period, into the target address signal TADD.

[0110] Storage area 1100 can perform a target refresh operation based on the burst refresh command signal BUR_REF_CMD and the target address signal TADD. For example, in each burst refresh cycle, when the burst refresh command signal BUR_REF_CMD is input, storage area 1100 can perform a target refresh operation based on the previous target address signal TADD latched in the previous restricted period.

[0111] It is apparent from the embodiments of this disclosure that the target address signal can be latched (i.e. sampled) at different time points (i.e., different sampling time points) in each burst refresh cycle.

[0112] While various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor memory device comprising: a memory area adapted to perform a normal operation based on a normal address signal and to perform a target refresh operation based on a target address signal; a refresh controller adapted to generate a latch control signal in each burst refresh period based on a burst refresh command signal, the latch control signal being activated for a restriction period different from a previous restriction period included in a previous burst refresh period; and an address latch adapted to latch the normal address signal inputted for the restriction period different from the previous restriction period as the target address signal in each burst refresh period based on the latch control signal, wherein the refresh controller includes: a first count circuit adapted to count a first clock signal switched continuously in each burst refresh period based on the burst refresh command signal and to generate a first count code signal; a period guide circuit adapted to generate a second clock signal switched once in each burst refresh period based on the burst refresh command signal and a precharge signal; a second count circuit adapted to count the second clock signal and to generate a second count code signal; and a control circuit adapted to generate the latch control signal in each burst refresh period based on the first count code signal and the second count code signal.

2. The semiconductor memory device of claim 1, wherein the control circuit generates the latch control signal when a first count value corresponding to the first count code signal and a second count value corresponding to the second count code signal are the same. The first count circuit counts the first clock signal during each burst refresh period after being initialized in response to the burst refresh command signal.

3. The semiconductor memory device according to claim 1, wherein, The period guide circuit generates the second clock signal activated based on the burst refresh command signal and deactivated based on the precharge signal.

4. The semiconductor memory device according to claim 1, wherein, The control circuit includes:

5. The semiconductor memory device according to claim 1, wherein, a comparison unit adapted to generate a comparison signal corresponding to a result of comparing the first count value corresponding to the first count code signal and the second count value corresponding to the second count code signal; a restriction unit adapted to generate a restriction signal activated for the restriction period based on the comparison signal and the burst refresh command signal; and an output unit adapted to output the latch control signal switched for the restriction period based on the restriction signal and the first clock signal. The refresh controller further includes:

6. The semiconductor memory device according to claim 1, wherein, a period conversion circuit adapted to generate the first clock signal non-periodically switched based on a third clock signal periodically switched. The memory area performs the target refresh operation in each burst refresh period based on the burst refresh command signal and a previous target address signal latched as the target address signal for the previous restriction period.

7. The semiconductor memory device according to claim 1, wherein, 8. A semiconductor memory device comprising: a memory area adapted to perform a normal operation based on a normal address signal and to perform a target refresh operation based on a target address signal; ​ a refresh controller adapted to generate a latch control signal in each burst refresh period based on a burst refresh command signal, the latch control signal being activated for a restriction period different from a previous restriction period included in a previous burst refresh period; and an address latch adapted to latch a normal address signal inputted for a restriction period different from the previous restriction period as a target address signal in each burst refresh period based on the latch control signal, wherein the refresh controller includes: a count circuit adapted to count a first clock signal switched continuously in each burst refresh period based on the burst refresh command signal, and generate a count code signal; a period guide circuit adapted to generate a second clock signal switched once in each burst refresh period based on the burst refresh command signal and a precharge signal; a randomization circuit adapted to generate a random code signal corresponding to a random value in each burst refresh period based on the second clock signal; and a control circuit adapted to generate the latch control signal in each burst refresh period when a count value corresponding to the count code signal and the random value corresponding to the random code signal are the same based on the count code signal and the random code signal.

9. The semiconductor memory device according to claim 8, wherein, The count circuit counts the first clock signal during each burst refresh period after being initialized in response to the burst refresh command signal.

10. The semiconductor memory device according to claim 8, wherein, The period guide circuit generates the second clock signal activated based on the burst refresh command signal and deactivated based on the precharge signal.

11. The semiconductor memory device according to claim 8, wherein, The randomization circuit includes: a clock signal generation unit adapted to generate a third clock signal; a random value generation unit adapted to generate a code signal corresponding to a random value at least once in each burst refresh period based on the third clock signal; and a latch unit adapted to latch the code signal as the random code signal in each burst refresh period based on the second clock signal.

12. The semiconductor memory device according to claim 8, wherein, The control circuit includes: a comparison unit adapted to generate a comparison signal corresponding to a result of comparing a count value corresponding to the count code signal and a random value corresponding to the random code signal; a restriction unit adapted to generate a restriction signal activated for a restriction period based on the comparison signal and the burst refresh command signal; and an output unit adapted to output the latch control signal switched for the restriction period based on the restriction signal and the first clock signal.

13. The semiconductor memory device according to claim 8, wherein, The refresh controller includes: a period conversion circuit adapted to generate the first clock signal non-periodically switched based on a fourth clock signal periodically switched.

14. The semiconductor memory device according to claim 8, wherein, The storage area performs a target refresh operation in each burst refresh period based on the burst refresh command signal and a previous target address signal latched as the target address signal for a previous restriction period.

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