Semiconductor Memory Device and Method of Operating the Same

Abstract

This application relates to a semiconductor memory device and an operation method thereof. A semiconductor memory device includes: a memory block including a plurality of memory cells programmed to a plurality of programming states during a programming operation; a voltage generator configured to generate and apply a programming voltage and a select line voltage to the memory block during the programming operation; and a read / write circuit configured to temporarily store programming data during the programming operation and control the potential of a bit line of the memory block based on the temporarily stored programming data. The voltage generator generates the select line voltage as a first select line voltage during a first programming operation for some of the plurality of programming states, and generates the select line voltage as a second select line voltage during a second programming operation for the remaining programming states of the plurality of programming states, the potential of the second select line voltage being lower than the potential of the first select line voltage.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly, to a semiconductor memory device and a method of operating a semiconductor memory device. Background Art

[0002] Current computing paradigms are trending towards ubiquitous computing where a computer system can be accessed almost anywhere, anytime. For example, the use of portable electronic devices such as mobile phones, tablet computers, and laptop computers is increasing rapidly. Such portable electronic devices typically use a memory system including a semiconductor memory device, i.e., a data storage device. The data storage device serves as a main storage device or an auxiliary storage device of the portable electronic device.

[0003] The advantage of a data storage device using a semiconductor memory device is that, since there is no mechanical drive, stability and durability are excellent, the information access speed is very fast, and power consumption is low. As an example of a memory system having these advantages, the data storage device may include a universal serial bus (USB) memory device, a memory card having various interfaces, a solid state drive (SSD), etc.

[0004] Semiconductor memory devices are generally classified as volatile memory devices or non-volatile memory devices.

[0005] The read and write speeds of non-volatile memory devices are relatively slow, but even in the case of a power supply interruption, the non-volatile memory device still retains the stored data. Therefore, non-volatile memory devices are used to store data that needs to be retained even without power. Non-volatile memory devices may include read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR type and NAND type. Summary of the Invention

[0006] Embodiments of the present disclosure relate to a semiconductor memory device and a method of operating a semiconductor memory device capable of improving a programming interference phenomenon by controlling a drain select line voltage during a programming operation.

[0007] A semiconductor memory device according to an embodiment of the present disclosure includes: a memory block including a plurality of memory cells programmable to a plurality of programming states during a programming operation; a voltage generator configured to generate a programming voltage and a select line voltage applied to the memory block during the programming operation; and a read / write circuit configured to temporarily store programming data during the programming operation and control the potential of a bit line of the memory block based on the temporarily stored programming data. The voltage generator is configured to: generate the select line voltage as a first select line voltage during a first programming operation for some of the plurality of programming states, and generate the select line voltage as a second select line voltage during a second programming operation for the remaining programming states of the plurality of programming states, the potential of the second select line voltage being lower than the potential of the first select line voltage.

[0008] A semiconductor memory device according to an embodiment of the present disclosure includes: a memory block including a plurality of memory cells programmable to a first programming state to an n-th programming state; a voltage generator configured to generate a programming voltage and a select line voltage applied to the memory block during a plurality of programming operations corresponding to the respective first programming state to the n-th programming state; a read / write circuit configured to temporarily store programming data during the plurality of programming operations and control the potential of a bit line of the memory block based on the temporarily stored programming data; and a control logic configured to control the voltage generator and the read / write circuit to sequentially perform the plurality of programming operations. The control logic is configured to control the voltage generator to: generate the select line voltage as a first select line voltage during a programming operation corresponding to the first programming state to a specific programming state, and generate the select line voltage as a second select line voltage during a programming operation corresponding to at least one programming state after the specific programming state, the potential of the second select line voltage being lower than the potential of the first select line voltage.

[0009] A method of operating a semiconductor memory device according to an embodiment of the present disclosure includes: setting a drain select line voltage to a first drain select line voltage; sequentially performing a plurality of first programming cycles corresponding to a first programming state to a specific programming state among the first programming state to the n-th programming state; when a programming operation corresponding to the specific programming state is completed, setting the drain select line voltage to a second drain select line voltage having a potential lower than the potential of the first drain select line voltage; and sequentially performing a plurality of second programming cycles corresponding to programming states after the specific programming state.

[0010] According to the present technology, during a programming operation of a semiconductor memory device, by using a downward-set drain select line voltage during a programming operation for a next programming state when a programming operation for a specific programming state is completed, a programming interference phenomenon can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1It is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 2 It is an illustration Figure 1 of an embodiment of a memory cell array.

[0013] Figure 3 It is an illustration Figure 2 of a circuit diagram of any one of the memory blocks.

[0014] Figure 4 It is an illustration Figure 2 of a circuit diagram of another embodiment of any one of the memory blocks.

[0015] Figure 5 It is an illustration Figure 1 of a circuit diagram of any one of the memory blocks included in the memory cell array.

[0016] Figure 6 It is an illustration Figure 1 of an embodiment of the control logic shown.

[0017] Figure 7 It is an illustration Figure 6 of an embodiment of the voltage generation control circuit.

[0018] Figure 8 It is a diagram illustrating the programming states of a three-level cell.

[0019] Figure 9 It is a flowchart illustrating a programming operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Figure 10 It is a diagram illustrating multiple programming cycles during a programming operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Figure 11 It is an illustration during Figure 10 a programming voltage application operation of a programming cycle of the voltage waveform diagram applied to the memory block.

[0022] Figure 12 It is an illustration including Figure 1 a block diagram of an embodiment of a memory system of a semiconductor memory device.

[0023] Figure 13 It is an illustration Figure 12 of an application example of the memory system.

[0024] Figure 14 It is an illustration including reference Figure 13Block diagram of a computing system of the described memory system. Detailed Description

[0025] A specific structural or functional description is disclosed in this specification or this application to describe embodiments according to the concepts of the present disclosure. These embodiments can be implemented in various forms. Therefore, the presented description is not intended to limit possible embodiments, but to enable the present disclosure to be realized.

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings so as to be described in sufficient detail to enable a person of ordinary skill in the art to implement the technical concepts of the present disclosure.

[0027] Figure 1 Is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Referring to Figure 1 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, a voltage generator 150, and a current sensing circuit 160.

[0029] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells and can be configured with non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be configured as a memory cell array having a two-dimensional structure. According to another embodiment, the memory cell array 110 can be configured as a memory cell array having a three-dimensional structure. In addition, each of the plurality of memory cells included in the memory cell array can store at least one bit of data. In an embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a single-level cell (SLC) that stores one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a multi-level cell (MLC) that stores two bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a three-level cell (TLC) that stores three bits of data. In still another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a four-level cell (QLC) that stores four bits of data. According to an embodiment, the memory cell array 110 can include a plurality of memory cells each storing five or more bits of data.

[0030] The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to address decoder control signals AD_signals1 and AD_signals2 output from the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) inside the semiconductor memory device 100.

[0031] The address decoder 120 is configured to decode the block address among the received addresses. The address decoder 120 selects at least one memory block according to the decoded block address. Additionally, during the programming voltage application operation in the programming operation, the address decoder 120 applies the programming voltage Vpgm generated in the voltage generator 150 to the selected word lines of the selected memory block, and applies the pass voltage Vpass to the remaining unselected word lines. Additionally, during the programming verification operation, the address decoder 120 applies the verification voltage Vverify generated in the voltage generator 150 to the selected word lines of the selected memory block, and applies the pass voltage Vpass to the remaining unselected word lines. Additionally, during the read voltage application operation in the read operation, the read voltage Vread generated in the voltage generator 150 is applied to the selected word lines of the selected memory block, and the pass voltage Vpass is applied to the remaining unselected word lines. Additionally, during the programming operation of the selected memory block, the address decoder 120 may apply a drain select line voltage to the selected drain select line of the selected memory block, and apply a source select line voltage to the selected source select line of the selected memory block.

[0032] The address decoder 120 is configured to decode the column address CADD of the received address. The address decoder 120 sends the decoded column address CADD to the read / write circuit 130.

[0033] The programming operation and the read operation of the semiconductor memory device 100 are performed in units of pages. The addresses received when a read operation and a programming operation are requested include a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line according to the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read / write circuit 130. In this specification, the memory cells connected to one word line may be referred to as one "physical page".

[0034] The read / write circuit 130 includes a plurality of page buffers PB1 to PBm. The read / write circuit 130 may operate as a "read circuit" during the read operation of the memory cell array 110, and may operate as a "write circuit" during the write operation of the memory cell array 110.

[0035] During a programming operation, multiple page buffers PB1 to PBm temporarily store data DATA to be programmed received from outside the semiconductor memory device 100 and control the potential levels of corresponding bit lines BL1 to BLm according to the temporarily stored data DATA. For example, when the temporarily stored data DATA corresponds to a first data (“0”), each of the multiple page buffers PB1 to PBm may apply a programming permission voltage (e.g., ground voltage Vss) to the corresponding bit line, and when the temporarily stored data DATA corresponds to a second data (“1”), each of the multiple page buffers PB1 to PBm may apply a programming prohibition voltage (e.g., power supply voltage Vcc) to the corresponding bit line.

[0036] To sense the threshold voltage of a memory cell during a programming verification operation, the multiple page buffers PB1 to PBm sense a change in the amount of current flowing according to the programming state of the corresponding memory cell while continuously supplying a sense current to the bit line connected to the memory cell and latch the change as sense data. When it is determined that the threshold voltage of the corresponding memory cell is equal to or greater than a pre-verification voltage during a pre-verification operation in the programming verification operation, the multiple page buffers PB1 to PBm apply a set bit line voltage to the corresponding bit line. The set bit line voltage may be higher than the programming permission voltage and lower than the programming prohibition voltage. Additionally, when it is determined that the threshold voltage of the corresponding memory cell is equal to or greater than a main verification voltage during a main verification operation in the programming verification operation, the multiple page buffers PB1 to PBm apply a programming prohibition voltage to the corresponding bit line.

[0037] The multiple page buffers PB1 to PBm may generate a sense voltage VPB by using the temporarily stored data DATA to be programmed and the latched sense data.

[0038] The read / write circuit 130 operates in response to a page buffer control signal PBSIGNALS output from the control logic 140.

[0039] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, the voltage generator 150, and the current sense circuit 160. The control logic 140 receives a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. For example, the control logic 140 may generate and output an address decoder control signal AD_signals1 and AD_signals2, a page buffer control signal PBSIGNALS, and a control signal OP_CMD in response to the command CMD and the control signal CTRL.

[0040] In addition, the control logic 140 may determine whether a programming operation for multiple programming states has passed or failed in response to a PASS signal or a FAIL signal received from the current sensing circuit 160. The control logic 140 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0041] When it is determined that the programming operation for a specific programming state has passed during the programming operation, the control logic 140 according to an embodiment of the present disclosure may set down the drain select line voltage used during the programming operation for at least one or more programming states after the specific programming state. That is, the control logic 140 may control the voltage generator 150 to use a first drain select line voltage in a first programming operation that is the programming operation for the first programming state or the specific programming state among the programming operations for the first programming state to the nth programming state, and use a second drain select line voltage in a second programming operation that is the programming operation for the next programming state to the nth programming state after the specific programming state, where the potential of the second drain select line voltage is lower than the potential of the first drain select line voltage.

[0042] The voltage generator 150 generates a programming voltage Vpgm and a pass voltage Vpass during the programming voltage application operation in the programming operation, and generates a verification voltage Vverify and a pass voltage Vpass during the verification operation in the programming operation. In addition, the voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during the read operation.

[0043] In an embodiment of the present disclosure, after the programming operation for a specific programming state is completed, the voltage generator 150 may reduce and generate the drain select line voltage during the programming operation for at least one or more programming states after the specific programming state. For example, the voltage generator 150 may generate and output a first drain select line voltage in the programming operation for the first programming state to the specific programming state among the programming operations for the first programming state to the nth programming state, and generate and output a second drain select line voltage with a potential lower than the potential of the first drain select line voltage in the programming operation for the next programming state to the nth programming state after the specific programming state. For example, the specific programming state may be the programming state where the threshold voltage distribution is closest to the highest threshold voltage distribution of the programming states.

[0044] The current sensing circuit 160 may generate a reference current in response to an enable bit VRY_BTI<#> received from the control logic 140 during a current sensing operation, compare a reference voltage generated by the reference current with a sensed voltage VPB received from page buffers PB1 to PBm included in the read / write circuit 130, and output a pass signal PASS or a fail signal FAIL.

[0045] More specifically, during a current sensing operation, the current sensing circuit 160 may compare a voltage generated according to values of bit line sense latches in each of the page buffers PB1 to PBm with a reference voltage generated by a reference current, and determine whether a programming operation for a specific programming state is completed or not. For example, when it is determined that the programming operation for a specific programming state is completed, the current sensing circuit 160 may generate and output a pass signal PASS, and when it is determined that the programming operation for a specific programming state is not completed, the current sensing circuit 160 may generate and output a fail signal FAIL.

[0046] The address decoder 120, the read / write circuit 130, and the voltage generator 150 may be used as "peripheral circuits" for performing a programming operation, a programming verification operation, etc. on the memory cell array 110. The peripheral circuits perform a programming operation and a programming verification operation on the memory cell array 110 based on the control of the control logic 140.

[0047] Figure 2 is an illustration Figure 1 of an embodiment of the memory cell array.

[0048] Referring to Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged along the +X direction, the +Y direction, and the +Z direction. Referring to Figure 3 and Figure 4 The structure of each memory block will be described in more detail.

[0049] Figure 3 is an illustration Figure 2 of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0050] Referring to Figure 3 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in a row direction (i.e., the +X direction). In Figure 3In this case, two unit strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0051] Each of the multiple unit strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0052] Each of the selection transistors SST and DST and the memory cells MC1 to MCn can have a similar structure. In an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. In an embodiment, a pillar for providing a channel layer can be provided in each unit string. In an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film can be provided in each unit string.

[0053] The source selection transistor SST of each unit string is connected between a common source line CSL and the memory cells MC1 to MCp.

[0054] In an embodiment, the source selection transistors of the unit strings arranged in the same row are connected to a source selection line extending in the row direction, and the source selection transistors of the unit strings arranged in different rows are connected to different source selection lines. In Figure 3 this case, the source selection transistors of the unit strings CS11 to CS1m in the first row are connected to the first source selection line SSL1. The source selection transistors of the unit strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0055] In another embodiment, the source selection transistors of the unit strings CS11 to CS1m and CS21 to CS2m can be commonly connected to one source selection line.

[0056] The first memory cells MC1 to nth memory cells MCn of each unit string are connected between the source selection transistor SST and the drain selection transistor DST.

[0057] The first memory cell MC1 to the nth memory cell MCn can be divided into the first memory cell MC1 to the pth memory cell MCp and the (p + 1)th memory cell MCp+1 to the nth memory cell MCn. The first memory cell MC1 to the pth memory cell MCp are arranged in sequence in a direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the pipe transistor PT. The (p + 1)th memory cell MCp+1 to the nth memory cell MCn are arranged in sequence in the +Z direction and are connected in series between the pipe transistor PT and the drain selection transistor DST. The first memory cell MC1 to the pth memory cell MCp and the (p + 1)th memory cell MCp+1 to the nth memory cell MCn are connected to each other through the pipe transistor PT. The gates of the first memory cell MC1 to the nth memory cell MCn of each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0058] The gate of the pipe transistor PT of each cell string is connected to the pipe line PL.

[0059] The drain selection transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain selection line DSL2.

[0060] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. In Figure 5 the first column, the cell strings CS11 and CS21 are connected to the first bit line BL1. The cell strings CS1m and CS2m in the mth column are connected to the mth bit line BLm.

[0061] The memory cells connected to the same word line in the cell strings arranged in the row direction form a page. For example, among the cell strings CS11 to CS1m in the first row, the memory cells connected to the first word line WL1 form a page. Among the cell strings CS21 to CS2m in the second row, the memory cells connected to the first word line WL1 form another page. Any one of the drain selection lines DSL1 and DSL2 can be selected to select the cell strings arranged in one row direction. Any one of the word lines WL1 to WLn can be selected to select a page in the selected cell string.

[0062] In another embodiment, even bit lines and odd bit lines may be provided instead of the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to SC2m arranged in the row direction may be respectively connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be respectively connected to the odd bit lines.

[0063] In an embodiment, at least one of the first memory cells MC1 to the n-th memory cells MCn may be used as a dummy memory cell. For example, providing at least one dummy memory cell reduces the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, providing at least one dummy memory cell reduces the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKa is improved, but the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa can be reduced, but the operation reliability of the memory block BLKa decreases.

[0064] To efficiently control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation for the memory block BLKa, a programming operation may be performed on all or some of the dummy memory cells. When the erase operation is performed after the programming operation, the dummy memory cell may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0065] Figure 4 is an illustration Figure 2 of a circuit diagram of another embodiment of any one of the memory blocks BLK1 to BLKz, namely, memory block BLKb.

[0066] Referring to Figure 4 , the memory block BLKb includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, the first memory cells MC1 to the n-th memory cells MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0067] The source select transistors SST of each cell string are connected between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly connected to one source select line.

[0068] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0069] The drain select transistors DST of each cell string are connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select lines extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0070] As a result, except for excluding the tube transistor PT from each cell string, Figure 4 the memory block BLKb represents a circuit similar to the circuit of Figure 3 the memory block BLKa.

[0071] In another embodiment, even bit lines and odd bit lines can be provided instead of the first bit line BL1 to the mth bit line BLm. Additionally, the even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be respectively connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be respectively connected to the odd bit lines.

[0072] In an embodiment, at least one of the first memory cell MC1 to the nth memory cell MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operation reliability of the memory block BLKb is improved, but the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb can be reduced, but the operation reliability of the memory block BLKb decreases.

[0073] To efficiently control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation for the memory block BLKb, a programming operation may be performed on all or some of the dummy memory cells. When the erase operation is performed after the programming operation, the dummy memory cell may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0074] Figure 5 is an example showing the implementation Figure 1 of any one of the memory blocks BLK1 to BLKz included in the memory cell array 110.

[0075] Referring to Figure 5 , the memory block BKLc includes a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm may be respectively connected to a plurality of bit lines BL1 to BLm. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, the first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0076] Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. In an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film may be provided in each cell string.

[0077] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0078] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between a source selection transistor SST and a drain selection transistor DST.

[0079] The drain selection transistor DST of each cell string is connected between a corresponding bit line and the memory cells MC1 to MCn.

[0080] Memory cells connected to the same word line form a page. The cell strings CS1 to CSm can be selected by selecting a drain selection line DSL. A page among the selected cell strings can be selected by selecting any one of the word lines WL1 to WLn.

[0081] In another embodiment, even bit lines and odd bit lines can be provided instead of the first bit line BL1 to the mth bit line BLm. The even-numbered cell strings among the cell strings CS1 to CSm can be respectively connected to the even bit lines, and the odd-numbered cell strings can be respectively connected to the odd bit lines.

[0082] As described above, memory cells connected to one word line can form a physical page. In Figure 5 the example, among the memory cells belonging to the memory block BLKc, m memory cells connected to any one of the multiple word lines WL1 to WLn form a physical page.

[0083] As Figures 2 to 4 shown, the memory cell array 110 of the semiconductor memory device 100 can be constructed in a three-dimensional structure, but as Figure 5 shown, the memory cell array 110 can be constructed in a two-dimensional structure.

[0084] Figure 6 is a diagram illustrating an embodiment of the control logic 140 of Figure 1 .

[0085] Referring to Figure 6 , the control logic 140 can include a ROM 141, an address decoder control circuit 142, a page buffer control circuit 143, and a voltage generation control circuit 144.

[0086] The ROM 141 can store algorithms for performing various operations (programming operation, read operation, erase operation, etc.) of the semiconductor memory device. The ROM 141 outputs an internal control signal int_CS in response to a command CMD received from the Figure 1 current sensing circuit 160 and a pass / fail signal FAIL. For example, the pass / fail signal FAIL can be a signal indicating the completion or non-completion of a programming operation for a specific programming state.

[0087] The address decoder control circuit 142 generates and outputs address decoder control signals AD_signals1 and AD_signals2 for controlling the address decoder 120 in response to the internal control signal int_CS output from the ROM 141. Figure 1 of the address decoder 120.

[0088] The address decoder control circuit 142 may include a word line voltage control circuit 142WL and a select line voltage control circuit 142SL.

[0089] The word line voltage control circuit 142WL generates and outputs the address decoder control signal AD_signals1 in response to the internal control signal int_CS. In an embodiment, the address decoder control signal AD_signals1 is a signal for controlling Figure 1 the address decoder 120 to selectively apply the operation voltage (e.g., programming voltage, pass voltage, etc.) generated by the voltage generator 150 to the word line WL. Figure 1

[0090] The select line voltage control circuit 142SL generates and outputs the address decoder control signal AD_signals2 in response to the internal control signal int_CS. In an embodiment, the address decoder control signal AD_signals2 is a signal for controlling Figure 1 the address decoder 120 to selectively apply the drain select line voltage and the source select line voltage generated by the voltage generator 150 to the drain select line and the source select line. Figure 1

[0091] The page buffer control circuit 143 generates and outputs page buffer control signals PBSIGNALS for controlling the read / write circuit 130 in response to the internal control signal int_CS output from the ROM 141. Figure 1 of the read / write circuit 130.

[0092] The voltage generation control circuit 144 generates and outputs a control signal OP_CMD for controlling the voltage generator 150 in response to the internal control signal int_CS output from the ROM 141. In an embodiment, Figure 1 the voltage generator 150 may generate a programming voltage applied to the selected word line, a pass voltage applied to the remaining unselected word lines, a drain select line voltage applied to the drain select line of the selected memory block, and a source select line voltage applied to the source select line of the selected memory block during a programming operation in response to the control signal OP_CMD. Figure 1

[0093] Figure 7 is an illustration Figure 6 of an embodiment of the voltage generation control circuit 144.

[0094] Refer to Figure 7 , the voltage generation control circuit 144 may include a register 144A, a source selection line voltage controller 144B, and a drain selection line voltage controller 144C.

[0095] The register 144A may store information PDSL1 corresponding to the first drain selection line voltage and information PDSL2 corresponding to the second drain selection line voltage. The potential of the second drain selection line voltage may be lower than the potential of the first drain selection line voltage.

[0096] The register 144A may output information PDSL1 corresponding to the first drain selection line voltage or information PDSL2 corresponding to the second drain selection line voltage in response to an internal control signal int_CS. For example, during a programming operation for the first programming state to a specific programming state among programming operations for the first programming state to the nth programming state, the register 144A outputs information PDSL1 corresponding to the first drain selection line voltage in response to the internal control signal int_CS. During a programming operation for the next programming state to the nth programming state after the specific programming state among programming operations for the first programming state to the nth programming state, the register 144A outputs information PDSL2 corresponding to the second drain selection line voltage in response to the internal control signal int_CS. The internal control signal int_CS may include information about the programming state corresponding to the currently executing programming operation.

[0097] The source selection line voltage controller 144B generates and outputs a source selection line voltage control signal OP_CMD_SSL in response to the internal control signal int_CS. The source selection line voltage control signal OP_CMD_SSL may be a signal included in Figure 6 the control signal OP_CMD, and the source selection line voltage control signal OP_CMD_SSL may be a signal for controlling the potential level of the source selection line voltage generated in Figure 1 the voltage generator 150.

[0098] In response to information PDSL1 corresponding to the first drain selection line voltage or information PDSL2 corresponding to the second drain selection line voltage received from the register 144A, the drain selection line voltage controller 144C generates and outputs a drain selection line voltage control signal OP_CMD_DSL. The drain selection line voltage control signal OP_CMD_DSL may be a signal included in Figure 6 the control signal OP_CMD, and the drain selection line voltage control signal OP_CMD_DSL may be for controlling Figure 1A signal of the potential level of the drain select line voltage generated in the voltage generator 150. For example, when receiving the information PDSL1 corresponding to the first drain select line voltage from the register 144A, the drain select line voltage controller 144C generates a drain select line voltage control signal OP_CMD_DSL for controlling Figure 1 the voltage generator 150 to generate the first drain select line voltage. Additionally, when receiving the information PDSL2 corresponding to the second drain select line voltage from the register 144A, the drain select line voltage controller 144C can generate a drain select line voltage control signal OP_CMD_DSL for controlling Figure 1 the voltage generator 150 to generate the second drain select line voltage.

[0099] Figure 8 is a diagram illustrating the programming states of a three-level cell.

[0100] Referring to Figure 8 , a three-level cell (TLC) has threshold voltage states corresponding to one erase state E and each of seven programming states P1 to P7. The erase state E and the first programming state P1 to the seventh programming state P7 have corresponding bit codes. Various bit codes can be assigned to the erase state E and the first programming state P1 to the seventh programming state P7 as needed.

[0101] Each threshold voltage state can be distinguished based on the first read voltage R1 to the seventh read voltage R7. Additionally, the main verification voltages VR1 to VR7 can be used during the main verification operation for determining whether the programming of the memory cells corresponding to each programming state is completed.

[0102] The pre-verification voltages VR1 * to VR6 * can have voltages lower than the main verification voltages VR1 to VR6. The pre-verification voltages VR1 * to VR6 * can be used during the pre-verification operation, and it can be determined during the pre-verification operation whether the memory cells are programmed to have a threshold voltage higher than the pre-verification voltages VR1 * to VR6 * . The pre-verification voltages VR1 * to VR6 * are lower than the target threshold voltage of the memory cells. For example, the target threshold voltage can be the main verification voltages VR1 to VR6.

[0103] Although Figure 8The target programming state of the TLC is shown, but this is only for example, and the multiple memory cells included in the semiconductor memory device according to an embodiment of the present disclosure may be multi-level cells (MLCs). In another embodiment, the multiple memory cells included in the semiconductor memory device according to an embodiment of the present disclosure may be quad-level cells (QLCs).

[0104] Figure 9 is a flowchart illustrating a programming operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0105] Figure 10 is a diagram illustrating multiple programming cycles during a programming operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0106] Figure 11 is illustrated in Figure 10 a waveform diagram of the voltage applied to a memory block during a programming voltage application operation of the programming cycle LOOP14.

[0107] The following refers to Figures 1 to 11 describe the programming operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0108] In an embodiment, programming the memory cells by the TLC method is described as an example. In an embodiment, among the erase state E corresponding to the TLC and the first programming state P1 to the seventh programming state P7, each of the programming cycles corresponding to the first programming state to the sixth programming state includes a pre-verification operation and a main verification operation, and each of the programming cycles corresponding to the seventh programming state includes a main verification operation without a pre-verification operation. Additionally, in an embodiment, as an example, an example is described in which a specific programming state is set to the sixth programming state P6 among the erase state E corresponding to the TLC and the first programming state P1 to the seventh programming state P7. The specific programming state may be the programming state corresponding to the last executed programming cycle among the programming states corresponding to the programming cycles including a pre-verification operation and a main verification operation during the programming operation. For example, the programming cycles corresponding to the first programming state P1 to the sixth programming state P6 among the first programming state P1 to the seventh programming state P7 may include a pre-verification operation and a main verification operation, and the programming cycle corresponding to the seventh programming state P7 may only execute the main verification operation without a pre-verification operation. In this case, the sixth programming state P6 corresponding to the last executed programming cycle among the first programming state P1 to the sixth programming state P6 may be the specific programming state.

[0109] In step S910, a programming command CMD and programming data DATA corresponding to the programming operation are received from the outside of the semiconductor memory device 100.

[0110] The control logic 140 generates and outputs address decoder control signals AD_signals1 and AD_signals2, page buffer control signals PBSIGNALS, and a control signal OP_CMD for controlling the peripheral circuits to perform a programming operation of the semiconductor memory device 100 in response to a programming command CMD and a control signal CTRL.

[0111] Multiple page buffers PB1 to PBm of the read / write circuit 130 receive and temporarily store programming data DATA.

[0112] In step S920, the control logic 140 sets the drain select line voltage applied to the drain select line DSL of the selected memory block (e.g., BLKc) to a first drain select line voltage V during the programming operation. PDSL1 For example, the register 144A of the voltage generation control circuit 144 can output information PDSL1 corresponding to the first drain select line voltage in response to an internal control signal int_CS.

[0113] In step S930, the peripheral circuits perform a programming operation for the first programming state to the (n - 1) programming state among the first programming state to the n programming states under the control of the control logic 140. For example, the (n - 1) programming state can be a specific programming state, and in an embodiment, the (n - 1) programming state can be the sixth programming state P6. The programming operation for the first programming state to the (n - 1) programming state (i.e., the programming operation for the first programming state to the specific programming state) can be defined as the first programming operation.

[0114] The programming operations for the first programming state to the n programming states are described in more detail below.

[0115] Referring to Figure 10 , a plurality of programming loops LOOP1 to LOOP13 corresponding to the first programming state P1 to the sixth programming state P6 are sequentially executed. For example, programming loops LOOP1 to LOOP5 correspond to the first programming state P1, and programming loops LOOP6 to LOOP9 correspond to the second programming state P2. Additionally, programming loops LOOP10 to LOOP12 correspond to the third programming state P3, and programming loop LOOP13 corresponds to the sixth programming state P6. In Figure 10 , the programming loops corresponding to the fourth programming state P4 and the fifth programming state P5 are not shown, but for ease of description, some programming loops are not shown. Preferably, the programming loops corresponding to the fourth programming state P4 and the fifth programming state P5 are substantially set between programming loop LOOP12 and programming loop LOOP13 and are executed.

[0116] Each of a plurality of programming loops LOOP1 to LOOP13 corresponding to first to sixth programming states P1 to P6 includes a programming voltage application operation, at least one pre-verification operation, and a main verification operation. For example, programming loop LOOP1 may include a programming voltage application operation in which a programming voltage VP1 is applied to a selected word line WL1, a pre-verification operation in which a pre-verification voltage VR1 * is applied to the selected word line WL1, and a main verification operation in which a main verification voltage VR1 is applied to the selected word line WL1.

[0117] During the programming voltage application operation, the voltage generator 150 may generate a first drain select line voltage V in response to a drain select line voltage control signal OP_CMD_DSL output from the drain select line voltage controller 144C PDSL1 , and the address decoder 120 may apply the first drain select line voltage V to the drain select line DSL of the selected memory block BLKc PDSL1 . The plurality of page buffers PB1 to PBm apply a programming permission voltage or a programming prohibition voltage to the corresponding bit lines BL1 to BLm based on the temporarily stored programming data DATA. During the programming voltage application operation, the voltage generator 150 generates the programming voltage VP1, and the address decoder 120 applies the programming voltage VP1 generated in the voltage generator 150 to the selected word line WL1.

[0118] During the pre-verification operation, the plurality of page buffers PB1 to PBm sense the current amounts of the corresponding bit lines BL1 to BLm to latch the sensed data, and based on the temporarily stored programming data DATA and the sensed data, apply a set bit line voltage that is higher than the programming permission voltage and lower than the programming prohibition voltage to the bit lines connected to the memory cells whose threshold voltages are higher than the pre-verification voltage VR1 * among the memory cells to be programmed to the first to seventh programming states. The plurality of page buffers PB1 to PBm apply the programming permission voltage to the bit lines connected to the memory cells whose threshold voltages are lower than the pre-verification voltage VR1 * among the memory cells to be programmed to the first to seventh programming states.

[0119] During the main verification operation, the plurality of page buffers PB1 to PBm sense the current amounts of the corresponding bit lines BL1 to BLm to latch the sensed data, and based on the temporarily stored programming data DATA and the sensed data, apply a programming prohibition voltage to the bit lines connected to the memory cells whose threshold voltages are higher than the verification voltage VR1 among the memory cells to be programmed to the first programming state P1.

[0120] Thereafter, a set number of programming loops are executed in the same manner as the programming loop LOOP1, for example, programming loops LOOP2 and LOOP3. After executing the set number of programming loops LOOP1 to LOOP3, starting from the next programming loop (e.g., LOOP4), the programming voltage application operation, pre-verification operation, main verification operation for the first programming state P1, and the pre-verification operation for the next programming state can be executed together. For example, after sequentially executing the programming voltage application operation, pre-verification operation, and main verification operation for the first programming state P1 in programming loop LOOP4, the pre-verification operation for the second programming state P2 can be executed.

[0121] As described above, the pre-verification operation is executed in each programming loop, and a set bit line voltage higher than the programming permission voltage is applied to the bit line connected to the memory cell programmed with a threshold voltage higher than the pre-verification voltage as a result of the pre-verification operation. Therefore, the threshold voltage of the memory cell programmed with a threshold voltage higher than the pre-verification voltage can be increased more precisely in the next programming loop, and thus the threshold voltage distribution width of the memory cell can be formed to be narrower.

[0122] After executing each programming loop, the current sensing circuit 160 can perform a current sensing operation to determine whether the programming operation for each programming state is completed, and output a pass signal PASS or a fail signal FAIL. For example, as a result of the current sensing operation performed after the programming loop LOOP is completed, when the programming is completed such that the memory cell to be programmed to the first programming state P1 has a threshold voltage greater than the main verification voltage VR1, the current sensing circuit 160 generates and outputs a pass signal PASS.

[0123] In the method described above, the address decoder 120, read / write circuit 130, voltage generator 150, and current sensing circuit 160 sequentially execute the programming operations corresponding to the first programming state P1 to the sixth programming state P6 for the memory cell MC1 connected to the selected word line WL1 of the selected memory block BLKc. That is, the programming loops LOOP1 to LOOP13 corresponding to the first programming state P1 to the sixth programming state P6 are sequentially executed.

[0124] During the programming voltage application operation of each of the multiple programming loops LOOP1 to LOOP13 corresponding to the programming operations corresponding to the first programming state to the sixth programming state described above, the voltage generator 150 generates a first drain select line voltage V PDSL1 and the address decoder 120 applies the first drain select line voltage V to the drain select line DSL of the selected memory block BLKc PDSL1 .

[0125] As a result of the current sensing operation performed after the programming loop LOOP13 is completed, when programming is completed such that a memory cell to be programmed to the sixth programming state P6 has a threshold voltage greater than the main verification voltage VR6, the current sensing circuit 160 generates and outputs a pass signal PASS.

[0126] In step S940, the control logic 140 sets the drain select line voltage applied to the drain select line DSL of the selected memory block (e.g., BLKc) to a second drain select line voltage V PDSL2 . The second drain select line voltage V PDSL2 has a potential level lower than that of the first drain select line voltage V PDSL1 . For example, the register 144A of the voltage generation control circuit 144 may output information PDSL2 corresponding to the second drain select line voltage in response to an internal control signal int_CS.

[0127] The first drain select line voltage V PDSL1 and the second drain select line voltage V PDSL2 may be greater than the sum of the highest threshold voltage value in the threshold voltage distribution of the drain select transistor DST and the set bit line voltage value, and may be less than the sum of the lowest threshold voltage value in the threshold voltage distribution and the programming inhibit voltage value.

[0128] In step S950, the peripheral circuit performs a programming operation for the nth programming state among the first programming state to the nth programming state under the control of the control logic 140. In an embodiment, the nth programming state is the seventh programming state P7. The programming operation for at least one programming state after a specific programming state (e.g., P6) may be defined as a second programming operation.

[0129] The programming operation for the seventh programming state P7 will be described in more detail below.

[0130] Refer to Figure 10, a plurality of programming loops LOOP14 to LOOP16 corresponding to the seventh programming state P7 are sequentially executed. Each of the plurality of programming loops LOOP14 to LOOP16 corresponding to the seventh programming state P7 includes a programming voltage application operation and a main verification operation. Since the seventh programming state P7 has the largest threshold voltage distribution among the plurality of programming states and is the last programmed programming state among the plurality of programming states, the programming operation speed can be increased by performing the main verification operation without a pre-verification operation. For example, each of the plurality of programming loops LOOP14 to LOOP16 corresponding to the seventh programming state P7 may include a programming voltage application operation in which programming voltages VP14, VP15, and VP16 are applied to the selected word line WL1 and a main verification operation in which a main verification voltage VR7 is applied to the selected word line WL1.

[0131] The following refers to Figure 11 Describe the programming voltage application operation of the programming loop LOOP14.

[0132] Since the programming voltage application operations of each of the plurality of programming loops LOOP14 to LOOP16 corresponding to the seventh programming state P7 are similar to each other, the programming voltage application operation of the programming loop LOOP14 is representatively described.

[0133] Among the bit lines of the selected memory block, a programming permission voltage (e.g., Vss) is applied to the bit lines in the programming mode PGM Mode, and a programming inhibition voltage (e.g., Vcc) is applied to the bit lines in the programming inhibition mode Inhibit Mode.

[0134] Thereafter, a second drain selection line voltage V having a potential level lower than the potential level of the first drain selection line voltage V PDSL1 is applied to the drain selection line DSL of the selected memory block. Therefore, the potential level of the inhibit channel of the cell string corresponding to the bit line in the programming inhibition mode Inhibit Mode increases. PDSL2

[0135] Thereafter, a programming voltage VP14 is applied to the selected word line Sel WL(WL1) of the selected memory block, and the memory cells connected to the selected word line Sel WL(WL1) and the bit lines in the programming mode PGM Mode are programmed. At this time, the potential level of the channel Inhibit Channel of the cell string corresponding to the bit line in the programming inhibit mode Inhibit Mode is boosted by the programming voltage VP14 applied to the selected word line Sel WL(WL1), and thus the potential level can be further increased. In addition, a second drain select line voltage V PDSL1 whose potential level is lower than the first drain select line voltage V PDSL2 is applied to the drain select line DSL. Therefore, the leakage current flowing from the inhibit channel Inhibit Channel of the cell string to the bit line is suppressed. During the programming voltage application operation, a ground voltage Vss can be applied to the source select line SSL.

[0136] As described above, during the programming voltage application operation of each of the plurality of programming cycles LOOP14 to LOOP16 corresponding to the seventh programming state P7, the voltage generator 150 can generate the second drain select line voltage V PDSL2 in response to the drain select line voltage control signal OP_CMD_DSL output from the drain select line voltage controller 144C, and the address decoder 120 can apply the second drain select line voltage V PDSL2 to the drain select line DSL of the selected memory block BLKc. The second drain select line voltage V PDSL1 whose potential level is lower than the first drain select line voltage V PDSL2 is applied to the drain select line DSL. Therefore, the occurrence of the leakage current in which the channel level of the cell string corresponding to the bit line that has completed the programming operation and has been applied with the programming inhibit voltage leaks to the bit line through the drain select transistor DST among the plurality of cell strings CS1 to CSm can be suppressed. Therefore, during the programming voltage application operation, the cell string corresponding to the bit line in the programming inhibit mode to which the programming inhibit voltage is applied can maintain a high channel potential, thereby improving the programming interference phenomenon.

[0137] As a result of the current sensing operation performed after each of the plurality of programming cycles LOOP14 to LOOP16 is completed, when the programming is completed such that the memory cell to be programmed to the seventh programming state P7 has a threshold voltage greater than the main verification voltage VR7, the current sensing circuit 160 generates and outputs a pass signal PASS, and the control logic 140 determines that the programming operation of the memory cell MC1 connected to the selected word line WL is completed.

[0138] In the above-described embodiments, the case where a specific programming state is the sixth programming state P6 is described as an example, but the embodiments of the present disclosure are not limited thereto. Among the plurality of programming states, the programming state corresponding to the programming operation in which the pre-verification operation is not performed can be preferably set as the specific programming state. For example, among the first programming state P1 to the seventh programming state P7, when the pre-verification operation is performed in the programming cycles corresponding to the first programming state P1 to the fourth programming state P4, and only the main verification operation is included without the pre-verification operation in the programming cycles corresponding to the fifth programming state P5 to the seventh programming state P7, the specific programming state can be set as the fourth programming state P4. That is to say, in the embodiments of the present disclosure, the programming operations corresponding to the plurality of programming states can be sequentially performed according to the arrangement order of the threshold voltage distributions of the plurality of programming states. In the programming operation including the pre-verification operation, the first drain select line voltage V PDSL1 can be used. In the programming operation including only the main verification operation without the pre-verification operation, the second drain select line voltage V PDSL1 with a potential lower than that of the drain select line voltage V PDSL2 can be used. Therefore, the drain select transistor DST can suppress the occurrence of leakage current due to the second drain select line voltage, and thus the channel potential of the cell string in the programming prohibited mode can be maintained in a high state, thereby improving the programming interference phenomenon.

[0139] Figure 12 FIG. is an example showing a block diagram of a memory system 1000 including Figure 1 of the semiconductor memory device 100.

[0140] Referring to Figure 12 , the memory system 1000 includes a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 can be the semiconductor memory device described with reference to Figure 1 . Repeated descriptions are omitted hereinafter.

[0141] The controller 1100 is connected to the host Host and the semiconductor memory device 100. The controller 1100 is configured to access the semiconductor memory device 100 in response to a request from the host Host. For example, the controller 1100 is configured to control the read operation, write operation, erase operation, and background operation of the semiconductor memory device 100. The controller 1100 is configured to provide an interface between the semiconductor memory device 100 and the host Host. The controller 1100 is configured to drive the firmware for controlling the semiconductor memory device 100.

[0142] The controller 1100 includes a random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 serves as any one of an operation memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host Host. The processing unit 1120 controls the overall operation of the controller 1100. In addition, the controller 1100 can temporarily store programming data provided from the host Host during a programming operation.

[0143] The host interface 1130 includes a protocol for performing data exchange between the host Host and the controller 1100. In an embodiment, the controller 1100 is configured to communicate with the host Host through at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and / or a proprietary protocol.

[0144] The memory interface 1140 is interfaced with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

[0145] The error correction block 1150 is configured to detect and correct errors in data received from the semiconductor memory device 100 using an error correction code (ECC). The processing unit 1120 can control the semiconductor memory device 100 to adjust a read voltage based on the error detection result of the error correction block 1150, and perform a reread operation. In an embodiment, the error correction block can be provided as a component of the controller 1100.

[0146] The controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device. In an embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash card (CF), a SmartMedia card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or micro MMC), an SD card (SD, mini SD, micro SD or SDHC), and a Universal Flash Storage (UFS).

[0147] The controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operation speed of a host Host connected to the memory system 1000 is greatly improved.

[0148] As another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, or one of various components configuring a computing system.

[0149] In an embodiment, the semiconductor memory device 100 or the memory system 1000 can be mounted as various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 can be packaged and mounted by methods such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a wafer in waffle pack, a wafer form wafer, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat pack (TQFP), a small outline (SOIC), a shrink small outline package (SSOP), a thin small outline (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer level manufacturing package (WFP), or a wafer level processed package on package (WSP).

[0150] Figure 13 is an illustration Figure 12 of a block diagram of an application example of the memory system 1000.

[0151] Referring to Figure 13 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0152] In Figure 13 , multiple groups communicate with the controller 2200 through the first channel CH1 to the k-th channel CHk respectively. Each semiconductor memory chip is configured and operates similarly to the semiconductor memory device 100 described with reference to Figure 1 .

[0153] Each group is configured to communicate with the controller 2200 through a common channel. The controller 2200 is configured similarly to the controller 1100 described with reference to Figure 12 , and is configured to control multiple memory chips of the semiconductor memory device 2100 through multiple channels CH1 to CHk.

[0154] Figure 14 is a block diagram of a computing system 3000 including the memory system 2000 described with reference to Figure 13 .

[0155] The computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0156] The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0157] In Figure 14 , the semiconductor memory device 2100 is connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 can be configured to be directly connected to the system bus 3500. At this time, the functions of the controller 2200 are performed by the central processing unit 3100 and the RAM 3200.

[0158] In Figure 14 , the memory system 2000 described with reference to Figure 13 is indicated. However, the memory system 2000 can be replaced with the memory system 1000 described with reference to Figure 12 . In an embodiment, the computing system 3000 can be configured to include both the memory systems 1000 and 2000 described with reference to Figure 12 and Figure 13 .

[0159] The embodiments of the present disclosure disclosed in this specification and the drawings are only provided with specific examples to explain the technical content of the present disclosure and assist in understanding the present disclosure, and are not intended to limit the scope of the present disclosure. Those of ordinary skill in the art will recognize that other modified examples based on the technical concept of the present disclosure can be implemented in addition to the embodiments disclosed herein.

[0160] Cross-reference to related applications

[0161] This application claims priority to Korean Patent Application No. 10-2020-0131457, filed with the Korean Intellectual Property Office on October 12, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A memory block, the memory block including a plurality of drain select transistors and a plurality of memory cells programmed to a plurality of programming states during a programming operation; A voltage generator, the voltage generator generating a programming voltage and a select line voltage applied to the memory block during the programming operation; And A read / write circuit, the read / write circuit applying a programming enable voltage or a programming inhibit voltage to a bit line of the memory block based on programming data, Wherein, the voltage generator: During a first programming operation for some of the plurality of programming states, generates the select line voltage as a first select line voltage, and During a second programming operation for the remaining programming states among the plurality of programming states, generates the select line voltage as a second select line voltage, the potential of the second select line voltage being lower than the potential of the first select line voltage, and Wherein each of the first select line voltage and the second select line voltage is greater than the sum of the programming enable voltage and the highest threshold voltage of the plurality of drain select transistors, and less than the sum of the programming inhibit voltage and the lowest threshold voltage of the plurality of drain select transistors.

2. The semiconductor memory device according to claim 1, wherein, The select line voltage is a voltage applied to a drain select line connected to the plurality of drain select transistors.

3. The semiconductor memory device according to claim 1, wherein, The first programming operation includes a plurality of programming cycles, and Each of the plurality of programming cycles includes a programming voltage application operation, a pre-verification operation, and a main verification operation.

4. The semiconductor memory device according to claim 3, wherein, The voltage generator generates a pre-verification voltage during the pre-verification operation and provides the pre-verification voltage to the memory block, and The read / write circuit senses a current amount of the bit line and applies a set bit line voltage to the bit line based on the sensing result.

5. The semiconductor memory device according to claim 4, wherein, The set bit line voltage is higher than the programming enable voltage, and The set bit line voltage is lower than the programming inhibit voltage.

6. The semiconductor memory device according to claim 4, wherein, The voltage generator: During the main verification operation, generates a main verification voltage higher than the pre-verification voltage, and Provides the main verification voltage to the memory block.

7. The semiconductor memory device according to claim 1, wherein, The second programming operation includes a plurality of programming cycles, and Each of the plurality of programming cycles includes a programming voltage application operation and a main verification operation.

8. A semiconductor memory device, the semiconductor memory device comprising: A memory block, the memory block including a plurality of drain select transistors and a plurality of memory cells programmable to a first programming state to an nth programming state; A voltage generator, the voltage generator generating a programming voltage and a select line voltage applied to the memory block during a plurality of programming operations corresponding to the respective first programming state to the nth programming state; A read / write circuit, the read / write circuit applying a programming enable voltage or a programming inhibit voltage to a bit line of the memory block based on programming data; And Control logic that controls the voltage generator and the read / write circuit to sequentially perform the multiple programming operations. Wherein, the control logic controls the voltage generator to: During the programming operations corresponding to the first programming state to a specific programming state, generate the selection line voltage as a first selection line voltage, and During the programming operations corresponding to at least one programming state after the specific programming state, generate the selection line voltage as a second selection line voltage, the potential of the second selection line voltage being lower than the potential of the first selection line voltage, and Wherein, each of the first selection line voltage and the second selection line voltage is greater than the sum of the programming permission voltage and the highest threshold voltage of the multiple drain selection transistors, and less than the sum of the programming prohibition voltage and the lowest threshold voltage of the multiple drain selection transistors.

9. The semiconductor memory device according to claim 8, wherein, The selection line voltage is the voltage applied to the drain selection line connected to the multiple drain selection transistors.

10. The semiconductor memory device according to claim 8, wherein, The programming operations corresponding to the first programming state to the specific programming state include a programming voltage application operation, a pre-verification operation, and a main verification operation, and The programming operations corresponding to the at least one programming state after the specific programming state include the programming voltage application operation and the main verification operation.

11. The semiconductor memory device according to claim 10, wherein, The voltage generator provides a pre-verification voltage lower than the main verification voltage to the memory block during the pre-verification operation, and The read / write circuit senses the current amount of the bit line and applies a set bit line voltage to the bit line based on the sensing result.

12. The semiconductor memory device according to claim 8, wherein, The control logic includes: A ROM that generates an internal control signal in response to a command and a pass / fail signal; and A voltage generation control circuit that generates a control signal for controlling the voltage generator in response to the internal control signal, and Wherein, the pass / fail signal is a signal indicating the completion or non-completion of the programming operation for the specific programming state.

13. The semiconductor memory device according to claim 12, wherein, The control logic: When it is determined based on the pass / fail signal that the programming operation for the specific programming state is not completed, generates the control signal for controlling the voltage generator to generate the first selection line voltage; And When it is determined based on the pass / fail signal that the programming operation for the specific programming state is completed, generates the control signal for controlling the voltage generator to generate the second selection line voltage.

14. The semiconductor memory device according to claim 12, wherein, The voltage generation control circuit includes: A register that includes information about the first selection line voltage and information about the second selection line voltage, wherein the register outputs the information about the first selection line voltage or the information about the second selection line voltage in response to the internal control signal; and A selection line voltage controller generates a control signal for controlling the voltage generator to generate the first selected line voltage or the second selected line voltage based on the information about the first selected line voltage or the information about the second selected line voltage received from the register.

15. A method of operating a semiconductor memory device, the method comprising the steps of: Setting a drain selection line voltage applied to a drain selection line to a first drain selection line voltage, the drain selection line being coupled to a plurality of drain selection transistors included in the semiconductor memory device; While applying a program enable voltage or a program inhibit voltage to each of bit lines coupled to memory cells included in the semiconductor memory device based on program data, sequentially performing a plurality of first programming cycles corresponding to first programming states to a specific programming state among first programming states to an nth programming state; When a programming operation corresponding to the specific programming state is completed, setting the drain selection line voltage to a second drain selection line voltage having a potential lower than the potential of the first drain selection line voltage; And Sequentially performing a plurality of second programming cycles corresponding to programming states after the specific programming state, Wherein each of the first drain selection line voltage and the second drain selection line voltage is greater than the sum of the program enable voltage and the highest threshold voltage of the plurality of drain selection transistors, and less than the sum of the program inhibit voltage and the lowest threshold voltage of the plurality of drain selection transistors.

16. The method according to claim 15, wherein Each of the plurality of first programming cycles includes a programming voltage application operation, a pre-verification operation, and a main verification operation, and Each of the plurality of second programming cycles includes the programming voltage application operation and the main verification operation.

17. The method according to claim 16, wherein, The pre-verification operation includes: determining whether a threshold voltage of the memory cell is programmed to a pre-level lower than a target level.

18. The method according to claim 17, wherein The pre-verification operation includes: when, as a result of the pre-verification operation, the threshold voltage of the memory cell is programmed to the pre-level, setting a set bit line voltage to be higher than the program enable voltage.

19. The method according to claim 16, wherein, During the programming voltage application operation of each of the plurality of first programming cycles, applying the first drain selection line voltage to the drain selection line of the memory block.

20. The method according to claim 16, wherein, During the programming voltage application operation of each of the plurality of second programming cycles, applying the second drain selection line voltage to the drain selection line of the memory block.

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