Storage device, operation method and control circuit thereof

Abstract

The present invention provides a storage device, an operation method thereof and a control circuit. The storage device includes a page buffer circuit, the page buffer circuit includes a plurality of page buffer stages, and the plurality of page buffer stages each include a plurality of page buffers. The storage device also includes a control circuit, the control circuit is configured to generate a page buffer control signal for controlling the plurality of page buffers. The control circuit is also configured to detect each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups formed by the page buffer control signal.

Description

Technical Field

[0001] The present disclosure generally relates to an electronic device, and more particularly to a storage device and an operating method thereof. Background Art

[0002] A storage device is a device that stores data under the control of a host device (e.g., a computer or a smart phone). A storage device may include a storage device for storing data and a storage controller for controlling the storage device. A storage device may be classified as a volatile storage device or a non-volatile storage device.

[0003] A volatile memory device is a memory device that stores data only when power is supplied and the stored data is lost when power is interrupted. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] A nonvolatile memory device is a memory device that retains data even when power is interrupted. Nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the invention

[0005] Some embodiments relate to a memory device capable of checking a signal of a page buffer by using a reduced or minimum number of pads, and an operating method of the memory device.

[0006] According to one embodiment of the present disclosure, a memory device includes a page buffer circuit, the page buffer circuit includes a plurality of page buffer stages, the plurality of page buffer stages each include a plurality of page buffers, the memory device also includes a control circuit, the control circuit is configured to generate a page buffer control signal for controlling the plurality of page buffers, and is further configured to detect each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups formed by the page buffer control signal.

[0007] According to another embodiment of the present disclosure, a method for operating a memory device is provided, the memory device comprising a measurement pad and a plurality of detection pads. The method comprises: generating a page buffer control signal for controlling a plurality of page buffers; providing the page buffer control signal to the plurality of page buffers; and detecting each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups formed by the page buffer control signal.

[0008] According to another embodiment of the present disclosure, a control circuit is provided, which controls signals provided to multiple page buffer control stages each including multiple page buffers. The control circuit includes: multiple detection pads, each of which detects any one of multiple page buffer control signal groups composed of page buffer control signals for controlling the multiple page buffers; a measurement pad, which measures the page buffer control signal group detected by the multiple detection pads; and a control signal generator. The control signal generator is configured to generate: the page buffer control signal; a detection control signal, which is used to control the detection operation of the multiple detection pads; and a measurement control signal, which is used to control the measurement operation of the measurement pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings, however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to enable those skilled in the art to implement the present disclosure.

[0010] In the accompanying drawings, the dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always represent the same elements.

[0011] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A diagram showing the structure of a storage device.

[0013] Figure 3 It is shown Figure 2 A diagram of an embodiment of a memory cell array is shown.

[0014] Figure 4 It is shown Figure 3 A circuit diagram of one memory block among the multiple memory blocks shown.

[0015] Figure 5 It is shown Figure 3 A circuit diagram of another embodiment of one memory block among a plurality of memory blocks is shown.

[0016] Figure 6 It is shown Figure 3 A circuit diagram of yet another embodiment of a memory block among a plurality of memory blocks is shown.

[0017] Figure 7 Operations of a control circuit and a page buffer according to an embodiment of the present disclosure are illustrated.

[0018] Figure 8 Another operation of the control circuit and the page buffer according to an embodiment of the present disclosure is shown.

[0019] Fig. 9 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0020] Fig.10 is a diagram illustrating a detection operation of a storage device according to an embodiment of the present disclosure.

[0021] Fig.11 is a diagram illustrating a measurement operation of a storage device according to an embodiment of the present disclosure.

[0022] Fig.12 is a flowchart illustrating an operating method of a storage device according to an embodiment of the present disclosure.

[0023] Fig.13 is a flowchart illustrating an operating method of a storage device according to additional embodiments of the present disclosure.

[0024] Fig.14 It is shown Figure 1 A diagram of a storage controller is shown.

[0025] Fig.15 is a block diagram illustrating a memory card system to which a storage device is applied according to an embodiment of the present disclosure.

[0026] Fig.16 is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the present disclosure.

[0027] Fig.17 is a block diagram illustrating a user system to which a storage device is applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The specific structural description or functional description disclosed herein is shown only for the purpose of describing the embodiments according to the concept of the present disclosure. The embodiments of the present disclosure can be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0029] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0030] Reference Figure 1, the storage device 50 may include a storage device 100 and a storage controller 200 for controlling the operation of the storage device 100. The storage device 50 may be a device that stores data under the control of the host 300, such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet PC, or an in-vehicle infotainment system.

[0031] The storage device 50 may be manufactured as any of various types of storage devices according to a host interface as a communication scheme with the host 300. For example, the storage device 50 may be implemented using any of various types of storage devices, such as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro MMC (micro-MMC), a secure digital (SD) card, a mini SD card, a micro SD card, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media card (SMC), a memory stick, and the like.

[0032] The storage device 50 may be manufactured in any of a variety of packaging types. For example, the storage device 50 may be manufactured in any of a variety of packaging types, such as package on package (POP), system-in-package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0033] The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells for storing data.

[0034] Each of the memory cells may be operated as any one of a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, and a quad-level cell (QLC) storing four data bits.

[0035] The memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0036] In one embodiment, the memory device 100 may use a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphic double data rate (GDDR) SRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for the convenience of description, it is assumed and described that the memory device 100 uses a NAND flash memory.

[0037] The memory device 100 may receive a command CMD and an address ADDR from the memory controller 200, and access an area selected by the address ADDR in the memory cell array. The memory device 100 may perform an operation indicated by the command CMD on the area selected by the address ADDR. For example, the memory device 100 may perform a write operation (programming operation), a read operation, or an erase operation. In a programming operation, the memory device 100 may program data in an area selected by the address ADDR. In a read operation, the memory device 100 may read data from an area selected by the address ADDR. In an erase operation, the memory device 100 may erase data stored in an area selected by the address ADDR.

[0038] The storage controller 200 may control overall operations of the storage device 50 .

[0039] When power is supplied to the storage device 50, the storage controller 200 may execute firmware (FW). When the storage device 100 is a flash memory storage device, the FW may include a host interface layer (HIL) for controlling communication with the host 300, a flash translation layer (FTL) for controlling communication between the host and the storage device 100, and a flash interface layer (FIL) for controlling communication with the storage device 100.

[0040] In one embodiment, the storage controller 200 may receive data and a logical block address (LBA) from the host 300, and convert the LBA into a physical block address (PBA), which represents an address of a storage unit included in the storage device 100 where the data is to be stored. In this specification, LBA and "logical address" may have the same meaning. In this specification, PBA and "physical address" may have the same meaning.

[0041] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from the host 300. In a program operation, the memory controller 200 may provide a program command, a PBA, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0042] In one embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of any request from the host 300, and send the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing read operations and program operations accompanied by performing wear leveling, read recycling, garbage collection, etc.

[0043] In one embodiment, the storage controller 200 may control at least two storage devices 100. The storage controller 200 may control the storage devices according to an interleaving technique to improve operation performance. The interleaving technique may be a technique for controlling operations on at least two storage devices 100 to overlap with each other.

[0044] The host 300 may communicate with the storage device 50 using at least one of a variety of communication protocols, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Firewire, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0045] Figure 2 It is shown Figure 1 The schematic diagram of the structure of the storage device 100 is shown.

[0046] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0047] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to a page buffer group 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line may be defined as one page. Therefore, one memory block may include a plurality of pages.

[0048] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0049] Each memory cell included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0050] The peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm under the control of the control logic 130, or release the applied voltages.

[0051] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0052] The row decoder 121 is connected to the memory cell array 110 through a row line RL. The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In one embodiment, the word line may include a normal word line and a dummy word line. In one embodiment, the row line RL may also include a pipe selection line.

[0053] The row decoder 121 operates under the control of the control logic 130. The row decoder 121 receives a row address RADD from the control logic 130.

[0054] The row decoder 121 decodes the row address RADD. The row decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block to apply the voltage generated by the voltage generator 122 to the at least one word line WL according to the decoded address.

[0055] For example, in a programming operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage to unselected word lines. In a programming verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines.

[0056] In a read operation, the row decoder 121 may apply a read voltage to a selected word line, and apply a read pass voltage having a higher level than the read voltage to unselected word lines.

[0057] In one embodiment, the erase operation of the memory device 100 is performed in memory block units. In the erase operation, the row decoder 121 may select a memory block according to the decoded address. In the erase operation, the row decoder 121 may apply a ground voltage to a word line connected to the selected memory block.

[0058] The voltage generator 122 operates under the control of the control logic 130. The voltage generator 122 generates a plurality of voltages by using an external power supply voltage provided to the memory device 100. Specifically, the voltage generator may generate various operation voltages Vop used in a program operation, a read operation, and an erase operation in response to an operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130.

[0059] In one embodiment, the voltage generator 122 may generate the internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0060] In one embodiment, the voltage generator 122 may generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage.

[0061] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 130 .

[0062] The generated plurality of voltages may be provided to the memory cell array 110 by the row decoder 121 .

[0063] The page buffer group 123 includes a first page buffer PB1 to an m-th page buffer PBm. The first page buffer PB1 to the m-th page buffer PBm are connected to the memory cell array 110 through the first bit line BL1 to the m-th bit line BLm, respectively. The first bit line BL1 to the m-th bit line BLm operate under the control of the control logic 130. Specifically, the first bit line BL1 to the m-th bit line BLm may operate in response to the page buffer control signal PBSIGNALS. For example, the first page buffer PB1 to the m-th page buffer PBm may temporarily store data received through the first bit line BL1 to the m-th bit line BLm, or sense the voltage or current of the bit line BL1 to BLm in a read operation or a verification operation.

[0064] Specifically, in a programming operation, when a programming voltage is applied to a selected word line, the first page buffer PB1 to the mth page buffer PBm can transmit the data DATA received through the input / output circuit 125 to the selected memory cell through the first bit line BL1 to the mth bit line BLm. The memory cell of the selected page is programmed according to the transmitted data DATA. The memory cell connected to the bit line to which a programming enable voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cell connected to the bit line to which a programming inhibit voltage (e.g., a power supply voltage) is applied can be maintained. In a programming verification operation, the first page buffer PB1 to the mth page buffer PBm read page data from the selected memory cell through the first bit line BL1 to the mth bit line BLm.

[0065] In a read operation, the first to mth page buffers PB1 to PBm read data DATA from memory cells of a selected page through the first to mth bit lines BL1 to BLm and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0066] In an erase operation, the first to m-th page buffers PB1 to PBm may float the first to m-th bit lines BL1 to BLm.

[0067] The column decoder 124 may transmit data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may communicate data with the first to mth page buffers PB1 to PBm through the data lines DL or communicate data with the input / output circuit 125 through the column lines CL.

[0068] The input / output circuit 125 can convert the Figure 1 The memory controller 200 described here transfers the received command CMD and address ADDR to the control logic 130 , or exchanges data DATA with the column decoder 124 .

[0069] In a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to an enable bit VRYBIT signal and output a pass signal PASS or a fail signal FAIL by comparing a sensing voltage VPB received from the page buffer group 123 and a reference voltage generated by the reference current.

[0070] The control logic 130 may control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT signal in response to a command CMD and an address ADDR. In addition, the control logic 130 may determine whether the verification operation is passed or failed in response to a pass signal PASS or a fail signal FAIL. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit operating according to an algorithm and / or a processor executing a control logic code.

[0071] Figure 3 It is shown Figure 2 A diagram of an embodiment of a memory cell array is shown.

[0072] Reference Figure 3 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate (not shown). The plurality of memory cells may be arranged along +X, +Y, and +Z directions. Figure 4 and Figure 5 The structure of each memory block is described in more detail.

[0073] Figure 4 It is shown Figure 3 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz shown.

[0074] Reference Figure 4 , the memory block BLKa may include a plurality of memory cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m memory cell strings are arranged in a row direction (ie, +X direction). Figure 4 Two memory cell strings arranged in the column direction (ie, +Y direction) are shown. However, this is for convenience of description, and it should be understood that three memory cell strings may be arranged in the column direction.

[0075] Each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0076] The selection transistors SST and DST and the memory cells MC1 to MCn may have structures similar to each other. In one embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a column for providing a channel layer may be provided in each memory cell string. In one embodiment, a column for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each memory cell string.

[0077] The source selection transistor SST of each memory cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0078] In one embodiment, source selection transistors of memory cell strings arranged on the same row are connected to a source selection line extending in the row direction, and source selection transistors of memory cell strings arranged on different rows are connected to different source selection lines. Figure 4 , source selection transistors of memory cell strings CS11 to CS1m on a first row are connected to a first source selection line SSL1. Source selection transistors of memory cell strings CS21 to CS2m on a second row are connected to a second source selection line SSL2.

[0079] In another embodiment, source selection transistors of the memory cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0080] The first to nth memory cells MC1 to MCn of each memory cell string are connected between a source select transistor SST and a drain select transistor DST.

[0081] The first to nth memory cells MC1 to MCn may be divided into the first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the opposite direction of the +Z direction and are connected in series between the source selection transistor SST and the tube transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are sequentially arranged in the +Z direction and are connected in series between the tube transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected through the tube transistor PT. The gate electrodes of the first to nth memory cells MC1 to MCn of each memory cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0082] The gate of the pipe transistor PT of each memory cell string is connected to the pipe line PL.

[0083] The drain selection transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The memory cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the memory cell strings CS11 to CS1m on the first row are connected to the first drain selection line DSL1. The drain selection transistors of the memory cell strings CS21 to CS2m on the second row are connected to the second drain selection line DSL2.

[0084] The memory cell strings arranged in the column direction are connected to the bit lines extending in the column direction. Figure 4 , the memory cell strings CS11 and CS21 on the first column are connected to the first bit line BL1. The memory cell strings CS1m and CS2m on the mth column are connected to the mth bit line BLm.

[0085] The memory cells connected to the same word line in the memory cell strings arranged in the row direction constitute one page. For example, the memory cells connected to the first word line WL1 in the memory cell strings CS11 to CS1m on the first row constitute one page. The memory cells connected to the first word line WL1 in the memory cell strings CS21 to CS2m on the second row constitute another page. When any one of the drain selection lines DSL1 and DSL2 is selected, the memory cell strings arranged in one row direction can be selected. When any one of the word lines WL1 to WLn is selected, a page can be selected in the selected memory cell string.

[0086] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered memory cell strings among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered memory cell strings among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to odd bit lines, respectively.

[0087] In one embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a virtual memory cell. For example, the at least one virtual memory cell may be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, the at least one virtual memory cell may be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When the number of virtual memory cells increases, the reliability of the operation of the memory block BLKa improves. On the other hand, the size of the memory block BLKa increases. When the number of virtual memory cells decreases, the size of the memory block BLKa decreases. On the other hand, the reliability of the operation of the memory block BLKa may deteriorate.

[0088] In order to effectively control the at least one virtual memory cell, the virtual memory cell may have a desired threshold voltage. Before or after the erase operation of the memory block BLKa, a programming operation may be performed on all or part of the virtual memory cells. When an erase operation is performed after the programming operation is performed, the threshold voltage of the virtual memory cell controls the voltage applied to the virtual word line connected to each virtual memory cell, so that the virtual memory cell can have a desired threshold voltage.

[0089] Figure 5 It is shown Figure 3 FIG. 1 is a circuit diagram of another embodiment of one memory block BLKb among the memory blocks BLK1 to BLKz.

[0090] Reference Figure 5 , the memory block BLKb may include a plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0091] The source select transistor SST of each memory cell string is connected between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the memory cell strings arranged on the same row are connected to the same source select line. The source select transistors of the memory cell strings CS11' to CS1m' arranged on the first row are connected to the first source select line SSL1. The source select transistors of the memory cell strings CS21' to CS2m' arranged on the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of the memory cell strings CS11' to CS1m' and CS21' to CS2m' may be connected together to one source select line.

[0092] The first to nth memory cells MC1 to MCn of each memory cell string are connected in series between a source select transistor SST and a drain select transistor DST. Gate electrodes of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0093] The drain selection transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the memory cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the memory cell strings CS11' to CS1m' on the first row are connected to the first drain selection line DSL1. The drain selection transistors of the memory cell strings CS21' to CS2m' on the second row are connected to the second drain selection line DSL2.

[0094] therefore, Figure 5 The memory block BLKb has a structure similar to Figure 4 The circuit of the storage block BLKa is different in Figure 5 The tube transistor PT is excluded from each memory cell string.

[0095] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered memory cell strings in the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered memory cell strings in the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to odd bit lines, respectively.

[0096] In one embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, the at least one dummy memory cell may be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, the at least one dummy memory cell may be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the reliability of the operation of the memory block BLKb increases. On the other hand, the size of the memory block BLKb increases. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases. On the other hand, the reliability of the operation of the memory block BLKb may deteriorate.

[0097] In order to effectively control the at least one virtual memory cell, the virtual memory cell may have a desired threshold voltage. Before or after the erase operation of the memory block BLKb, a programming operation may be performed on all or part of the virtual memory cells. When an erase operation is performed after the programming operation is performed, the threshold voltage of the virtual memory cell controls the voltage applied to the virtual word line connected to each virtual memory cell, so that the virtual memory cell can have a desired threshold voltage.

[0098] Figure 6 It is shown Figure 3 FIG. 1 is a circuit diagram of another embodiment of a memory block BLKi among the memory blocks BLK1 to BLKz.

[0099] Reference Figure 6 , in the memory block BLKi, a plurality of word lines arranged in parallel to each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of memory cell strings ST connected between the bit lines BL1 to BLm and a common source line CSL. The bit lines BL1 to BLm may be connected to the memory cell strings ST, respectively, and the memory cell strings ST may be connected in common to the common source line CSL. The memory cell strings ST may be configured identically to each other, and thus the memory cell string ST connected to the first bit line BL1 will be described in detail as an example.

[0100] The memory cell string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series with each other between a common source line CSL and a first bit line BL1. At least one drain selection transistor DST may be included in one memory cell string ST, and a greater number of source selection transistors than the source selection transistor SST shown in the figure and a greater number of memory cells than the memory cells MC1 to MC16 shown in the figure may be included in the one memory cell string ST.

[0101] The source of the source selection transistor SST may be connected to a common source line SL, and the drain of the drain selection transistor DAT may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different memory cell strings ST may be connected to the source selection line SSL, and the gates of the drain selection transistors DST included in different memory cell strings ST may be connected to the source selection line SSL. The gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different memory cell strings ST may be referred to as a physical page PG. Therefore, a physical page PG corresponding to the number of word lines WL1 to WL16 may be included in a memory block BLKi.

[0102] One memory cell may store one bit of data. The one memory cell is generally referred to as a single-level cell (SLC). One physical page PG may store one logical page (LPG) of data. One LPG of data may include data bits corresponding to the number of memory cells included in the one physical page PG.

[0103] One memory cell can store two or more bits of data, and one physical page PG can store two or more LPG data.

[0104] Figure 7 is an example showing operations of a control circuit and a page buffer according to an embodiment of the present disclosure.

[0105] Reference Figure 7 , the memory device 100 may include a control circuit and a page buffer PB.

[0106] exist Figure 7 In the embodiment, the control circuit can be used to execute Figure 2 The circuit of the control logic 130 shown in FIG. 1 is shown in FIG. 1 . In addition, the page buffer PB may be Figure 2 Any one of the page buffers shown.

[0107] The control circuit Control Circuit can control the operation of the page buffer PB.

[0108] The control circuit Control Circuit may generate a page buffer control signal for controlling the page buffer PB. In one embodiment, the page buffer control signal may include a reset signal RST, a set signal SET, a transfer signal TRAN, a transfer signal TRAN_N, etc. For example, the control circuit Control Circuit may generate a reset signal RST in response to a control signal I_RST. In addition, the control circuit Control Circuit may generate a set signal SET in response to a control signal I_SET. In addition, the control circuit Control Circuit may generate a transfer signal TRAN in response to a control signal I_TRAN. In addition, the control circuit Control Circuit may generate a transfer signal TRAN_N in response to a control signal I_TRAN_N.

[0109] In addition, the control circuit Control Circuit may provide a page buffer control signal to the page buffer PB.

[0110] The page buffer PB can be operated according to the page buffer control signal. For example, the first transistor T1 can be connected between the node D and the node ND, and electrically connect the node D and the node ND in response to the reset signal RST. The second transistor T2 can be connected between the node D_N and the node ND, and electrically connect the node D_N and the node ND in response to the set signal SET. For example, in a state where the sensing node SO is precharged to a high level, when the reset signal RST is applied to the first transistor T1 at a logic high level, the node D and the node D_N are initialized to a logic low level and a logic high level, respectively. In addition, in a state where the sensing node SO is precharged to a high level, when the set signal SET is applied to the second transistor T2 at a logic high level, the node D and the node D_N are initialized to a logic high level and a logic low level, respectively. The third transistor T3 can be connected between the node D and the sensing node SO, and electrically connect the node D and the sensing node SO in response to the transmission signal TRAN. The fourth transistor T4 may be connected between the node D_N and the sensing node SO, and electrically connects the node D_N and the sensing node SO in response to the transmission signal TRAN_N.

[0111] Figure 8 is another example showing operations of a control circuit and a page buffer according to an embodiment of the present disclosure.

[0112] exist Figure 8In the embodiment, it is assumed that the memory device 100 includes a plurality of levels (level 1 to level N). The plurality of levels (level 1 to level N) can operate independently of each other. Each of the plurality of levels (level 1 to level N) can include a control circuit and four page buffers PB. However, the number of page buffers is not limited to four. In different embodiments, the number of page buffers may be different. In addition, it is assumed that one page buffer is controlled according to four signals. However, this is merely illustrative, and the number of signals for controlling the page buffers may vary.

[0113] The control circuit Control Circuit may control the page buffers included in the same level. Therefore, one control circuit Control Circuit included in each of a plurality of levels (level 1 to level N) may control four page buffers PB. Therefore, the one control circuit Control Circuit may control 16 signals, namely, RSTA, RSTB, RSTC, RSTD, SETA, SETB, SETC, SETD, TRANA, TRANB, TRANC, TRAND, TRANA_N, TRANB_N, TRANC_N, and TRAND_N, to control the page buffers PB.

[0114] In addition, the operation of the control circuit Control Circuit and the operation of each of the page buffers PB are the same as the above-described operations of the page buffer PB and the control circuit Control Circuit, and thus, a detailed description thereof will be omitted.

[0115] Meanwhile, in the case of a memory device (e.g., a peripheral lower unit (PUC)), the page buffer PB is located below the memory cell array. Therefore, an upper metal pad (uPAD) for measuring a signal will be used to check the signal of the page buffer PB. The upper metal pad is composed of a top metal. Figure 8 As shown, when 16 signals are generated from one stage, 16×N signals are generated in a plurality of stages (1st to Nth stages). However, since the area for setting the upper metal pad is limited, the signals of all page buffers PB cannot be checked in the memory device having the PUC structure. In addition, since there is no signal measurement path in the packaged memory device, the signals of the page buffers cannot be checked.

[0116] Therefore, according to an embodiment of the present disclosure, it is possible to check a signal of a page buffer by using a reduced or minimum number of pads.

[0117] Fig. 9 is a diagram showing a storage device 900 according to an embodiment of the present disclosure.

[0118] exist Fig. 9 In the example, the storage device 900 may be Figure 2 The storage device 100 is shown.

[0119] Reference Fig. 9 , the memory device 900 may include a page buffer circuit 910 and a control circuit 920 .

[0120] The page buffer circuit 910 may include a plurality of page buffer stages including a plurality of page buffers. The page buffer stages may be Figure 8 Level shown.

[0121] According to one embodiment, the control circuit 920 may detect the plurality of page buffer control signal groups through detection paths respectively corresponding to the plurality of page buffer control signal groups constituted by the page buffer control signal PBSIGNALS.

[0122] Specifically, the control circuit 920 may include a control signal generator 921 , a plurality of detection pads 922 , and a measurement pad 923 .

[0123] The control signal generator 921 may generate a page buffer control signal PBSIGNALS for controlling the plurality of page buffers. The control signal generator 921 may provide the page buffer control signal PBSIGNALS to the page buffer circuit 910. In one embodiment, the control signal generator 921 may provide the page buffer control signal PBSIGNALS to the plurality of page buffer stages included in the page buffer circuit 910 in parallel. That is, since the plurality of page buffer stages receive the page buffer control signal PBSIGNALS at constant intervals, the plurality of page buffer stages may operate in parallel according to the page buffer control signal PBSIGNALS.

[0124] In one implementation, the control signal generator 921 may generate a probe control signal PROBE for controlling transistors connected between the plurality of page buffers and the plurality of probe pads 922 .

[0125] In one implementation, the control signal generator 921 may generate a measurement control signal MEASURE for controlling transistors connected between the plurality of detection pads 922 and the measurement pads 923 .

[0126] Each of the plurality of detection pads 922 may detect any one of a plurality of page buffer control signal groups.

[0127] Each of the plurality of page buffer control signal groups may include page buffer control signals of the same kind in the page buffer control signal PBSIGNALS and provided in parallel to different page buffer levels. For example, it is assumed that the first page buffer level to the Nth page buffer level are included in the page buffer circuit 910, and the page buffer signal provided to each page buffer level includes a reset signal, a setting signal, a first transmission signal, and a second transmission signal. The first page buffer control signal group in the plurality of page buffer control signal groups may include reset signals for the plurality of page buffer levels. Specifically, the first page buffer control signal group may be a group including reset signals provided to the first page buffer level to the Nth page buffer level, respectively. In addition, the second page buffer control signal group in the plurality of page buffer control signal groups may include setting signals for the plurality of page buffer levels. Specifically, the second page buffer control signal group may be a group including setting signals provided to the first page buffer level to the Nth page buffer level, respectively. In addition, the third page buffer control signal group in the plurality of page buffer control signal groups may include first transmission signals for the plurality of page buffer levels. Specifically, the third page buffer control signal group may be a group including first transmission signals provided to the first page buffer level to the Nth page buffer level, respectively. Furthermore, a fourth page buffer control signal group among the plurality of page buffer control signal groups may include second transmission signals of the plurality of page buffer stages. Specifically, the fourth page buffer control signal group may be a group including second transmission signals respectively provided to the first to Nth page buffer stages.

[0128] In one embodiment, each of the plurality of detection pads 922 may detect a page buffer control signal group among the plurality of page buffer control signal groups corresponding to each of the plurality of detection pads 922. Specifically, each of the plurality of detection pads 922 may detect the page buffer control signal group through a detection path connected to each of the plurality of detection pads 922.

[0129] In one embodiment, when the transistors connected between the plurality of page buffers and the plurality of probing pads 922 are turned on according to the probing control signal PROPER, each of the plurality of probing pads 922 may detect the page buffer control signal group assigned to the probing pad 922. In addition, the plurality of probing pads 922 may provide the detected buffer control signal group to the measuring pad 923.

[0130] In one embodiment, the plurality of probing pads 922 may be configured as an upper metal pad (uPAD). For example, the plurality of probing pads 922 may be provided using a top metal located on an upper portion of the memory device 900 .

[0131] The measurement pad 923 may measure the page buffer control signal group detected by the plurality of detection pads 922 .

[0132] In one embodiment, when the transistors connected between the plurality of detection pads 922 and the measurement pad 923 are turned off according to the measurement control signal MEASURE, the measurement pad 923 can measure the detected page buffer control signal group. The measured page buffer control signal group can be used to analyze the page buffer.

[0133] In one implementation, the measurement pad 923 may be provided using a top metal located on the upper portion of the memory device 900 .

[0134] Fig.10 is a diagram illustrating a detection operation of a storage device according to an embodiment of the present disclosure.

[0135] Fig.10 Shown in Figure 8 The operation of detecting the A-th reset signal RSTA in the page buffer signal shown in FIG. Fig.10 The operation of detecting the Ath reset signal RSTA is described, but this is for the convenience of description, and in addition to the Ath reset signal RSTA, the detection operation can be similarly applied to other page buffer control signals RSTB, RSTC, RSTD, SETA, SETB, SETC, SETD, TRANA, TRANB, TRANC, TRAND, TRANA_N, TRANB_N, TRANC_N and TRAND_N.

[0136] Reference Fig.10 , a probing pad PROBING PAD_RSTA corresponding to the Ath reset signal among the plurality of probing pads may be a pad for probing the Ath reset signals RSTA_1 to RSTA_N provided to each of the plurality of page buffer stages (1st to Nth stages).

[0137] For example, when the transistor connected to the probing pad PROBING PAD_RSTA is turned on by the probing control signal PROBE, the probing pad PROBING PAD_RSTA can detect the Ath reset signals RSTA_1 to RSTA_N. The Ath reset signals RSTA_1 to RSTA_N can be detected through the probing path connected to the probing pad PROBING PAD_RSTA. In other words, the probing pad PROBING PAD_RSTA can detect only the Ath reset signals RSTA_1 to RSTA_N corresponding to the same kind among the page buffer control signals provided to the plurality of page buffer stages (1st to Nth stages).

[0138] On the other hand, when the transistor connected to the probing pad PROBING PAD_RSTA is turned off by the probing control signal PROBE, the probing pad PROBING PAD_RSTA does not perform the probing operation.

[0139] Therefore, according to an embodiment of the present disclosure, page buffer control signals having the same kind and provided to different page buffer stages are detected through the same detection pad, so that the page buffer control signals can be checked by using a reduced or minimum number of pads.

[0140] Fig.11 is a diagram illustrating a measurement operation of a storage device according to an embodiment of the present disclosure.

[0141] Fig.11 Shown in Figure 8 The measurement operation in the state where each of the page buffer control signals shown is detected by the corresponding detection pad. For example, it is assumed that each of the page buffer control signals provided to the plurality of page buffer stages is detected by any one of the detection pads PROBING PAD_RSTA, PROBING PAD_RSTB, ..., and PROBING PAD_TRAND_N based on the type of the page buffer control signal. Fig.11 In order to facilitate description, only the detection pad PROBING PAD_RSTA corresponding to the Ath reset signal, the detection pad PROBING PAD_RSTB corresponding to the Bth reset signal RSTB, and the detection pad PROBING PAD_TRAND_N corresponding to the transmission signal TRAND_N are shown. Fig.11 The described measurement operation may be similarly applied to probing pads corresponding to other page buffer control signals RSTC, RSTD, SETA, SETB, SETC, SETD, TRANA, TRANB, TRANC, TRAND, TRANA_N, TRANB_N, and TRANC_N.

[0142] Reference Fig.11 , the measurement pad MEASURE PAD can measure the page buffer control signal detected by the plurality of detection pads.

[0143] For example, when the transistor connected between the probing pad PROBING PAD_RSTA and the measuring pad MEASURE PAD is turned on by the measurement control signal MEASURE, the measuring pad MEASURE PAD can measure the Ath reset signal detected by the probing pad PROBINGPAD_RSTA. In addition, when the transistor connected between the probing pad PROBING PAD_RSTB and the measuring pad MEASURE PAD is turned on by the measurement control signal MEASURE, the measuring pad MEASURE PAD can measure the Bth reset signal detected by the probing pad PROBING PAD_RSTB. In addition, when the transistor connected between the probing pad PROBINGPAD_TRAND_N and the measuring pad MEASURE PAD is turned on by the measurement control signal MEASURE, the measuring pad MEASURE PAD can measure the transmission signal detected by the probing pad PROBING PAD_TRAND_N.

[0144] On the other hand, when the transistors connected to the probing pads PROBING PAD_RSTA, PROBING PAD_RSTB, . . . , and PROBING PAD_TRAND_N are turned off by the measurement control signal MEASURE, the measuring pad MEASURE PAD does not perform the measurement operation.

[0145] Therefore, according to an embodiment of the present disclosure, a page buffer control signal detected by a plurality of detection pads is measured through one measurement pad, thereby being able to measure the page buffer control signal even in a package type memory device.

[0146] Fig.12 is a flowchart illustrating an operating method of a storage device according to an embodiment of the present disclosure.

[0147] Fig.12 The operation method shown can be Fig. 9 The storage device 900 is shown to execute.

[0148] Reference Fig.12 In step S1201 , the memory device 900 may generate a page buffer control signal for controlling a plurality of page buffers.

[0149] In step S1203 , the memory device 900 may provide a page buffer control signal to a plurality of page buffers.

[0150] The memory device 900 may provide a plurality of page buffer control signals in parallel to a plurality of page buffer stages including a plurality of page buffers.

[0151] In step S1205 , the memory device 900 may detect each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups constituted of the page buffer control signals.

[0152] Each of the plurality of page buffer control signal groups may include page buffer control signals having the same kind among the page buffer control signals and being applied in parallel to different page buffer stages.

[0153] Fig.13 is a flowchart illustrating an operating method of a storage device according to additional embodiments of the present disclosure.

[0154] Fig.13 The operation method shown can be Fig. 9 The storage device 900 is shown to execute.

[0155] Reference Fig.13 In step S1301 , the memory device 900 may generate a page buffer control signal for controlling a plurality of page buffers.

[0156] In step S1303 , the memory device 900 may provide a page buffer control signal to a plurality of page buffers.

[0157] In step S1305 , the memory device 900 may generate a probing control signal for controlling a probing operation of the plurality of probing pads.

[0158] In step S1307 , the memory device 900 may detect each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups constituted of the page buffer control signals.

[0159] The memory device 900 may turn on transistors connected between the plurality of page buffers and the plurality of detection pads according to the detection control signal. In addition, the memory device 900 may detect a page buffer control signal group corresponding to each of the plurality of detection pads among the plurality of page buffer control signal groups by using each of the plurality of detection pads.

[0160] In step S1309 , the storage device 900 may generate a measurement control signal for controlling a measurement operation of the measurement pad.

[0161] In step S1311 , the memory device 900 may measure the page buffer control signal detected by the plurality of detection pads by using the measurement pad.

[0162] The memory device 900 may turn on transistors connected between the plurality of probing pads and the measuring pad according to the measuring control signal. In addition, the memory device 900 may measure the detected page buffer control signal.

[0163] Fig.14 It is shown Figure 1 A diagram of a storage controller 200 is shown.

[0164] Reference Figure 1 and Fig.14 , the storage controller 200 may include a processor 220 , a RAM 230 , an error correction circuit 240 , a ROM 250 , a host interface 270 , and a flash memory interface 280 .

[0165] The processor 220 may control the overall operation of the memory controller 200. The RAM 230 may be used as a buffer memory, cache memory, working memory, etc. of the memory controller 200.

[0166] The error correction circuit 240 may perform error correction. The error correction circuit 240 may perform error correction code (ECC) encoding on data to be written to the storage device through the flash memory interface 280. The ECC-encoded data may be transmitted to the storage device through the flash memory interface 280. The error correction circuit 240 may perform ECC decoding on data received from the storage device through the flash memory interface 280. For example, the error correction circuit 240 may be included in the flash memory interface 280 as a component of the flash memory interface 280.

[0167] The ROM 260 may store various information required in the operation of the memory controller 200 in the form of firmware.

[0168] The memory controller 200 may communicate with an external device (eg, the host 300 , an application processor, etc.) through the host interface 270 .

[0169] The memory controller 200 may communicate with the memory device 100 through the flash interface 280. The memory controller 200 may send commands CMD, addresses ADDR, control signals CTRL, etc. to the memory device 100 and receive data DATA through the flash interface 280. For example, the flash interface 280 may include a NAND interface.

[0170] Fig.15 is a block diagram illustrating a memory card system 2000 to which a storage device is applied according to an embodiment of the present disclosure.

[0171] Reference Fig.15 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0172] The storage controller 2100 is connected to the storage device 2200. The storage controller 2100 can access the storage device 2200. For example, the storage controller 2100 can control the read operation, write operation, erase operation and background operation of the storage device 2200. The storage controller 2100 provides an interface between the storage device 2200 and the host Host. The storage controller 2100 drives the firmware for controlling the storage device 2200. The storage controller 2100 can communicate with the reference Figure 1 The storage device 2200 may be implemented in the same manner as the storage controller 200 described in the prior art. Figure 2 The described storage device 100 is implemented identically.

[0173] The memory controller 2100 may include, for example, components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC circuit.

[0174] The storage controller 2100 can communicate with an external device through the connector 2300. The storage controller 2100 can communicate with an external device (e.g., a host) according to a specific communication protocol. The storage controller 2100 can communicate with an external device through at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an electronic integrated drive (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. The connector 2300 can be defined by at least one of the various communication protocols mentioned above.

[0175] For example, the storage device 2200 may be implemented using various types of non-volatile memory, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0176] The storage controller 2100 and the storage device 2200 may be integrated into a single semiconductor device to constitute a memory card. For example, the storage controller 2100 and the storage device 2200 may constitute a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash (CF) card, a Smart Media Card (SM and SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a Universal Flash Storage (UFS).

[0177] Fig.16 is a block diagram illustrating a solid state drive (SSD) system 3000 to which a storage device is applied according to an embodiment of the present disclosure.

[0178] Reference Fig.16 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 through a signal connector 3001, and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0179] In one embodiment, the SSD controller 3210 may act as a reference Figure 1 The storage controller 200 is described.

[0180] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. The signal SIG may be, for example, a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one interface, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0181] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 can receive the power PWR input from the host 3100 and charge the power PWR. When the power supply of the host 3100 is not stable, the auxiliary power supply 3230 can supply power to the SSD 3200. The auxiliary power supply 3230 can be located in the SSD 3200, or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the mainboard and provide auxiliary power to the SSD 3200.

[0182] The buffer memory 3240 is used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory (e.g., DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM), or a nonvolatile memory (e.g., FRAM, ReRAM, STT-MRAM, and PRAM).

[0183] Fig.17 is a block diagram showing a user system 4000 to which a storage device is applied according to an embodiment of the present disclosure.

[0184] Reference Fig.17 , the user system 4000 includes an application processor 4100 , a storage module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0185] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system-on-chip (SoC).

[0186] The memory module 4200 may operate as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory (e.g., DRAM, SDRAM, DDRSDRAM, DDR2 SDRM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2SDRAM, and LPDDR3 SDRAM), or a nonvolatile random access memory (e.g., PRAM, ReRAM, MRAM, and FRAM). For example, the application processor 4100 and the memory module 4200 may be packaged based on a package-on-package (PoP) and provided as one semiconductor package.

[0187] The network module 4300 can communicate with external devices. The network module 4300 can, for example, support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0188] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may send the data stored therein to the application processor 4100. The storage module 4400 may be implemented, for example, using a nonvolatile semiconductor memory having a three-dimensional structure, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory. The storage module 4400 may be provided, for example, as a removable drive, such as a memory card or an external drive of the user system 4000.

[0189] For example, the storage module 4400 may include a plurality of nonvolatile storage devices, and the plurality of nonvolatile storage devices may be associated with the reference Figure 1 The storage module 4400 may be the same as the storage device 100 described in the previous embodiment. Figure 1 The described storage device 50 operates identically.

[0190] The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include a user input interface (e.g., a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element). The user interface 4500 may include a user output interface (e.g., a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor).

[0191] According to the present disclosure, a memory device capable of checking a signal of a page buffer by using a reduced or minimum number of pads and an operating method of the memory device are provided.

[0192] Although the present disclosure has been shown and described with reference to certain embodiments, it will be understood by those skilled in the art that various changes in form and details may be made to the embodiments presented without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0193] In the above-mentioned embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely embodiments for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is to say, it is obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure.

[0194] Meanwhile, the embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used here, these terms are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many changes can be made within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0195] CROSS-REFERENCE TO RELATED APPLICATIONS

[0196] This application claims the priority of Korean Patent Application No. 10-2020-0131446 filed on October 12, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A storage device, comprising: a page buffer circuit comprising a plurality of page buffer stages, each of the plurality of page buffer stages comprising a plurality of page buffers; as well as A control circuit, the control circuit being configured to: generating a page buffer control signal for controlling the plurality of page buffers; as well as detecting each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups constituted by the page buffer control signal, Wherein, the control circuit comprises: a plurality of detection pads, each of which is connected to the plurality of page buffers according to a detection control signal for turning on transistors connected between the plurality of page buffers and the plurality of detection pads, and detects any one of the plurality of page buffer control signal groups; and A measurement pad is connected to the plurality of detection pads according to a measurement control signal for turning on transistors connected between the plurality of detection pads and the measurement pad, and measures a page buffer control signal group detected by the plurality of detection pads.

2. The storage device according to claim 1, wherein: The control circuit further comprises: A control signal generator generates the page buffer control signal and the detection control signal.

3. The storage device according to claim 2, wherein: The control signal generator generates the measurement control signal.

4. The storage device according to claim 1, wherein: The page buffer control signal includes at least one of a transfer signal, a set signal, and a reset signal.

5. The storage device according to claim 1, wherein: Each of the plurality of page buffer control signal groups includes page buffer control signals of the same kind among the page buffer control signals and provided in parallel to different page buffer stages.

6. A method for operating a storage device, the storage device comprising a measuring pad and a plurality of probing pads, the method comprising the following steps: generating a page buffer control signal for controlling a plurality of page buffers; providing the page buffer control signal to the plurality of page buffers; generating a detection control signal; Turning on transistors connected between the plurality of page buffers and the plurality of detection pads according to the detection control signal; detecting each of the plurality of page buffer control signal groups through a detection path corresponding to each of the plurality of page buffer control signal groups constituted by the page buffer control signal by using each of the plurality of detection pads; generating a measurement control signal; Turning on transistors connected between the plurality of detection pads and the measurement pad according to the measurement control signal; as well as The page buffer control signal group detected by the plurality of detecting pads is measured by using the measuring pad.

7. The method according to claim 6, wherein: Providing the page buffer control signal to the plurality of page buffers includes providing the page buffer control signal in parallel to a plurality of page buffer stages including the plurality of page buffers.

8. The method according to claim 7, wherein: Each of the plurality of page buffer control signal groups includes page buffer control signals of the same kind among the page buffer control signals and applied in parallel to different page buffer stages.

9. A control circuit for controlling signals provided to a plurality of page buffer control stages each including a plurality of page buffers, the control circuit comprising: a plurality of detection pads, each of which is connected to the plurality of page buffers according to a detection control signal and detects any one of a plurality of page buffer control signal groups consisting of page buffer control signals for controlling the plurality of page buffers; a measuring pad connected to the plurality of detection pads according to a measurement control signal and measuring a page buffer control signal group detected by the plurality of detection pads; as well as A control signal generator, wherein the control signal generator generates: the page buffer control signal; The detection control signal is used to turn on transistors connected between the plurality of page buffers and the plurality of detection pads; as well as The measurement control signal is used to turn on a transistor connected between the plurality of detection pads and the measurement pad.

10. The control circuit according to claim 9, wherein: Each of the plurality of page buffer control signal groups includes page buffer control signals of the same kind among the page buffer control signals and provided in parallel to different page buffer stages.

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