LDMOS device and method of manufacturing the same

Abstract

The application discloses an LDMOS device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing an FDSOI substrate, wherein the FDSOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer which are stacked in sequence from bottom to top; defining an active region and an isolation region on the FDSOI substrate, and forming an isolation structure in the isolation region; defining a drift region on the FDSOI substrate, and forming a mixed region in part of the drift region; forming a first well region in the FDSOI substrate containing the buried oxide layer, and forming a second well region in the drift region; forming a first buried layer and a second buried layer in the second well region, wherein the first buried layer is located between the buried oxide layer and the second buried layer. The application can improve the breakdown voltage of the LDMOS, reduce the on-resistance, improve the leakage current of the device, improve the switching characteristics and the breakdown resistance of the LDMOS, and thus improve the device performance of the LDMOS.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and in particular to an LDMOS device and its fabrication method. Background Technology

[0002] Laterally-diffused metal-oxide-semiconductor (LDMOS) devices are widely used in various high-voltage integrated circuits, such as power switches and AC / DC converters, due to their high voltage withstand capability and good compatibility with CMOS devices. In LDMOS devices, a drift region exists between the source and drain to increase the breakdown voltage. The drift region has a low doping concentration, equivalent to high resistance. When a high voltage is applied to the LDMOS device, the drift region can withstand a very high voltage, ensuring the device can operate normally without breakdown. For LDMOS devices, the length and doping concentration of the drift region are important design parameters. A long drift region and light doping concentration can increase the device's breakdown voltage, but also increase the on-resistance (Ron, sp). Low on-resistance requires a short drift region and heavy doping concentration. Therefore, LDMOS device design aims to achieve a lower on-resistance while meeting the source-drain breakdown voltage requirements.

[0003] With the development of integrated circuits, technology nodes have advanced from the micrometer to the nanometer scale. Traditional planar CMOS devices have been gradually replaced by FinFETs and fully-depleted silicon-on-insulator (FDSOI) devices. The FDSOI process is characterized by a wafer consisting of a silicon substrate, a buried oxide (BOX) layer, and a top silicon layer (SOI). The fully depleted SOI layer in FDSOI is very thin. The drift region formed by the SOI layer not only exhibits extremely high on-resistance in the on-state, but also, in the off-state, the ultra-thin drift region and the gradually thinning BOX layer reduce the device's breakdown voltage. This poses a challenge to the design of high-voltage, low-on-resistance LDMOS devices integrated on FDSOI technology. Summary of the Invention

[0004] In view of this, this application provides an LDMOS device and a method for fabricating the same, which can improve the device's breakdown voltage, reduce its on-resistance, improve its leakage current, enhance its switching characteristics and breakdown withstand capability, thereby improving the device's performance.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for fabricating an LDMOS device, the method comprising:

[0007] An FDSOI substrate is provided, the FDSOI substrate comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top;

[0008] An active region and an isolation region are defined on the FDSOI substrate, and an isolation structure is formed in the isolation region;

[0009] A drift region is defined on the FDSOI substrate, and a mixing region is formed in a portion of the drift region;

[0010] A first well region is formed in the FDSOI substrate containing the buried oxide layer, and a second well region is formed in the drift region;

[0011] A first buried layer and a second buried layer are formed in the second well region, wherein the first buried layer is located between the buried oxide layer and the second buried layer;

[0012] A gate stack is formed on the upper surface of the FDSOI substrate across the first well region and the second well region, and a first sidewall structure is formed on both sides of the gate stack;

[0013] A raised source / drain structure is formed on both sides of the gate stack and the drift region;

[0014] A second sidewall structure is formed on the surface of the first sidewall structure, and ion implantation is performed on the source / drain structure;

[0015] A metal silicide layer is formed on the source / drain structure and the gate stack to form a low-resistance contact between the source / drain and the gate.

[0016] Preferably, in the above manufacturing method, the first well region is an N-type well region and the second well region is a P-type well region;

[0017] Alternatively, the first well region may be a P-type well region, and the second well region may be an N-type well region.

[0018] Preferably, in the above manufacturing method, the first well region is an N-type well region and the second well region is a P-type well region;

[0019] The first buried layer is a P-type buried layer, and the second buried layer is an N-type buried layer.

[0020] Preferably, in the above manufacturing method, the first well region is a P-type well region and the second well region is an N-type well region;

[0021] The first buried layer is an N-type buried layer, and the second buried layer is a P-type buried layer.

[0022] Preferably, in the above manufacturing method, forming a first buried layer and a second buried layer in the second well region includes:

[0023] A first mask layer is formed on the entire surface of the device;

[0024] The first mask layer is photolithographically developed to form an ion implantation window;

[0025] Based on the ion implantation window, a first ion implantation is performed in the second well region to form the second buried layer;

[0026] Based on the ion implantation window, a second ion implantation is performed in the second well region to form the first buried layer;

[0027] Wherein, the first buried layer and the second buried layer satisfy the condition of being flush in a first direction, and in a second direction, the first buried layer is located between the buried oxide layer and the second buried layer; the first direction is parallel to the FDSOI substrate, and the second direction is the silicon substrate pointing towards the top silicon layer.

[0028] Preferably, in the above-described fabrication method, the ions used for the first ion implantation and the second ion implantation are different;

[0029] The ion used for the first ion implantation is boron ion, and the ion used for the second ion implantation is phosphorus ion;

[0030] Alternatively, the ion used for the first ion implantation is a phosphorus ion, and the ion used for the second ion implantation is a boron ion.

[0031] Preferably, in the above manufacturing method, the isolation structure is a local silicon oxide isolation structure or a shallow trench isolation structure.

[0032] Preferably, in the above manufacturing method, the isolation structure is a local silicon oxide isolation structure;

[0033] Forming the isolation structure in the isolation zone includes:

[0034] A second mask layer is formed on the entire surface of the device;

[0035] The second mask layer is photolithographically developed and etched away to remove the second mask layer located in the isolation region, exposing the top silicon surface of the isolation region, while retaining the second mask layer located in the active region;

[0036] The exposed top silicon of the isolation region is completely oxidized using a thermal oxidation process to form an isolation structure;

[0037] Remove the second mask layer from the active region.

[0038] Preferably, in the above manufacturing method, the isolation structure is a shallow trench isolation structure;

[0039] Forming the isolation structure in the isolation zone includes:

[0040] A second mask layer is formed on the entire surface of the device;

[0041] The second mask layer is photolithographically developed, and the second mask layer, top silicon, buried oxide layer and part of silicon substrate located in the isolation region are sequentially etched away to form an isolation region trench, while the second mask layer located in the active region is retained;

[0042] An oxide layer of a certain thickness is deposited in the formed isolation trench, and then ground down to the second mask layer using a chemical mechanical polishing method to form an isolation structure;

[0043] Remove the second mask layer located in the active region.

[0044] Preferably, in the above-described manufacturing method, forming a mixing zone in a portion of the drift zone includes:

[0045] A third mask layer is formed on the entire surface of the device;

[0046] The third mask layer is photolithographically developed to form an etched window;

[0047] Based on the etching window, the isolation structure, the top silicon layer, the buried oxide layer, and part of the silicon substrate are etched to form an etching trench.

[0048] Single-crystal silicon is grown in the etched trenches using selective epitaxial growth to form a mixed region;

[0049] The mixing region is flush with the top silicon in a second direction, where the silicon substrate points to the top silicon.

[0050] The present invention also provides an LDMOS device, comprising:

[0051] An FDSOI substrate, wherein the FDSOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top;

[0052] An active region and an isolation region are located on the FDSOI substrate, wherein the isolation region has an isolation structure;

[0053] The drift region located on the FDSOI substrate has a mixing region formed in a portion of the drift region;

[0054] A first well region and a second well region are located within the FDSOI substrate, wherein the first well region is located within the FDSOI substrate containing the buried oxide layer, and the second well region is located within the drift region;

[0055] The first buried layer and the second buried layer are located in the second well region, with the first buried layer located between the buried oxide layer and the second buried layer;

[0056] A gate stack located on the upper surface of the FDSOI substrate, spanning the first well region and the second well region, wherein the gate stack has a first sidewall structure on both sides;

[0057] Source and drain structures located on both sides of the gate stack and the drift region;

[0058] The second sidewall structure located on the surface of the first sidewall structure;

[0059] A metal silicide layer located on the source / drain structure and the gate stack.

[0060] As can be seen from the above description, in the FDSOI device and its fabrication method provided by the technical solution of the present invention, by introducing N-type buried layers and P-type buried layers under the buried oxide layer in the drift region by ion implantation, the breakdown voltage of LDMOS can be improved, the on-resistance can be reduced, the leakage current of the device can be improved, the switching characteristics and breakdown withstand of LDMOS can be improved, thereby improving the device performance of LDMOS. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0062] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0063] Figures 1-8 This is a process flow diagram of a fabrication method for an LDMOS device;

[0064] Figures 9-29 This is a process flow diagram of an LDMOS device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0065] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0066] As described in the background section, the fully depleted SOI layer in FDSOI is very thin. The drift region formed by the SOI layer not only exhibits extremely high on-resistance in the on-state, but also, in the off-state, the ultra-thin drift region and the gradually thinning buried oxide layer reduce the device's breakdown voltage. This poses challenges to the design of high-voltage, low-on-resistance LDMOS integrated on FDSOI technology.

[0067] In existing technologies, after defining the drift region, a portion of the drift region is opened and etched beneath the buried oxide layer to form a pure silicon region. Subsequently, P-wells / N-wells, STI (shallow trench isolation), gate morphology, source / drain regions, etc., are formed. This method solves the problem mentioned above where a large breakdown voltage cannot be obtained due to the thin SOI layer. However, extending the drift region inevitably leads to increased on-resistance and performance degradation of the device.

[0068] refer to Figures 1-8 , Figures 1-8 This is a process flow diagram of a method for fabricating an LDMOS device, the method comprising:

[0069] Step S1: As Figure 1 As shown, an FDSOI substrate 10 is provided, the FDSOI substrate 10 comprising a silicon substrate 11, a buried oxide layer 12 and a top silicon layer 13 stacked sequentially from bottom to top;

[0070] Step S2: As Figure 2 As shown, an LDMOS drift region is defined, and a portion of the drift region is etched down to 10-50 μm below the lower surface of the buried oxide layer 12 to form the etched region 25;

[0071] Step S3: As Figure 3 As shown, a pure silicon region is formed in the etched region 25 using epitaxial growth technology, and the interface remains consistent with the upper surface of the FDSOI substrate 10.

[0072] Step S4: As Figure 4 As shown, ion implantation is performed on the FDSOI substrate 10 with the buried oxide layer 12 to form a P-type well region 14; ion implantation is performed on the pure silicon region to form an N-type well region 15.

[0073] Step S5: As Figure 5 and Figure 6 As shown, a trench 16 is formed in the N-type well region 15 by photolithography and etching, and then silicon dioxide is filled in the trench 16 to form an STI region 17.

[0074] Step S6: As Figure 7 As shown, a gate stack is formed on the upper surface of the FDSOI substrate 10, spanning the N-type well region 15 and the P-type well region 14; the gate stack includes: a gate oxide layer 18 located on the upper surface of the FDSOI substrate 10; an HK thin film 19 located on the gate oxide layer 18; a TiN thin film 20 located on the HK thin film 19; and a gate thin film layer 21 located on the TiN thin film 20;

[0075] Step S7: As Figure 7 As shown, a first sidewall 23 is formed on the sidewall of the gate stack;

[0076] Step S8: As Figure 7 As shown, source and drain terminals 22 are formed on the FDSOI substrate 10 on both sides of the gate stack;

[0077] Step S9: As Figure 8 As shown, a second sidewall 24 is formed attached to the first sidewall 23;

[0078] Step S10: As Figure 8 As shown, ion implantation is performed at the source / drain terminals 22;

[0079] Step S11: Remove the gate thin film layer 21 in the gate stack to form a groove; then deposit metal in the groove.

[0080] Figures 1-8 The method shown solves the problem mentioned above where a large breakdown voltage cannot be obtained due to the thinness of the SOI. However, extending the drift region inevitably leads to an increase in the on-resistance of the device and a deterioration in performance.

[0081] To address the aforementioned problems, this invention proposes an LDMOS device that can be integrated into the FDSOI process and its fabrication method. For the FDSOI NLDMOS device, a heavily doped N-type buried layer is introduced beneath the buried oxide layer in the drift region via ion implantation. After voltage is applied to the device, the N-type buried layer provides an additional low-resistance conduction path for current flow. This achieves low on-resistance in the on-state. Subsequently, a P-type buried layer is introduced beneath the N-type buried layer to balance the excess donor impurities (electrons) introduced by the N-type buried layer, ensuring complete depletion of the drift region in the off-state, thereby achieving a high breakdown voltage. For the FDSOI PLDMOS device, a heavily doped P-type buried layer is introduced beneath the buried oxide layer in the drift region via ion implantation. After voltage is applied to the device, the P-type buried layer provides an additional low-resistance conduction path for current flow. This also achieves low on-resistance in the on-state. Then, an N-type buried layer is introduced under the P-type buried layer to balance the excess acceptor impurities (holes) brought by the P-type buried layer, ensuring that the drift region is completely depleted when the device is off, thereby achieving a high breakdown voltage and improving device performance.

[0082] The method for fabricating the LDMOS device includes:

[0083] An FDSOI substrate is provided, the FDSOI substrate comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top;

[0084] An active region and an isolation region are defined on the FDSOI substrate, and an isolation structure is formed in the isolation region;

[0085] A drift region is defined on the FDSOI substrate, and a mixing region is formed in a portion of the drift region;

[0086] A first well region is formed in the FDSOI substrate containing the buried oxide layer, and a second well region is formed in the drift region;

[0087] A first buried layer and a second buried layer are formed in the second well region, wherein the first buried layer is located between the buried oxide layer and the second buried layer;

[0088] A gate stack is formed on the upper surface of the FDSOI substrate across the first well region and the second well region, and a first sidewall structure is formed on both sides of the gate stack;

[0089] Source and drain structures are formed on both sides of the gate stack and the drift region;

[0090] A second sidewall structure is formed on the surface of the first sidewall structure, and ion implantation is performed on the source / drain structure;

[0091] A metal silicide layer is formed on the source / drain structure and the gate stack to form a low-resistance contact between the source / drain and the gate.

[0092] As can be seen from the above description, in the FDSOI device and its fabrication method provided by the technical solution of the present invention, by introducing N-type buried layers and P-type buried layers under the buried oxide layer in the drift region by ion implantation, the breakdown voltage of LDMOS can be improved, the on-resistance can be reduced, the leakage current of the device can be improved, the switching characteristics and breakdown withstand of LDMOS can be improved, thereby improving the device performance of LDMOS.

[0093] This invention achieves both high breakdown voltage in the off state and low on-resistance in the on state, thereby improving the performance of LDMOS devices. It effectively solves the aforementioned difficulties in integrating LDMOS devices on FDSOI and has promising application prospects.

[0094] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0095] refer to Figures 9-27 , Figures 9-27 This invention provides a process flow diagram of a method for fabricating an LDMOS device, the method comprising:

[0096] Step S101: As Figure 9 As shown, an FDSOI substrate 30 is provided, the FDSOI substrate 30 comprising a silicon substrate 31, a buried oxide layer 32 and a top silicon layer 33 stacked sequentially from bottom to top;

[0097] The thickness of the top silicon 33 is 10-40nm, such as 20nm or 30nm.

[0098] Step S102: As Figures 10-15 As shown, an active region and an isolation region are defined on the FDSOI substrate 30, and an isolation structure 35 is formed in the isolation region;

[0099] In this embodiment of the invention, the isolation structure 35 can be a Local Oxidation of Silicon (LOSOC) structure or a Shallow Trench Isolation (STI) structure.

[0100] The first method, such as Figures 10-12 As shown, when the isolation structure 35 is a local silicon oxide isolation structure, the method for forming the isolation structure 35 in the isolation region includes:

[0101] First, such as Figure 10 As shown, a second mask layer 34 is formed on the entire surface of the device. The second mask layer 34 can be formed by depositing a silicon nitride (SiN) thin film by chemical vapor deposition (CVD) or by a combination of pad oxide and SiN. After growth, the surface of the second mask layer 34 is oxidized to prevent nitrogen in SiN from diffusing into the photoresist, affecting the photoacid reaction at the bottom of the photoresist, and causing photoresist poisoning.

[0102] Then, as Figure 11 As shown, the second mask layer 34 is photolithographically developed, and the second mask layer 34 located in the isolation region is etched away to expose the surface of the top silicon 33 in the isolation region, while the second mask layer 34 located in the active region is retained.

[0103] Then, as Figure 12 As shown, the exposed top silicon 33 of the isolation region is completely oxidized using a thermal oxidation process to form an isolation structure 35;

[0104] Finally, the second mask layer 34 of the active region is removed.

[0105] The second method, such as Figures 13-15 As shown, when the isolation structure 35 is a shallow trench isolation structure, the method for forming the isolation structure 35 in the isolation area includes:

[0106] First, such as Figure 13 As shown, a second mask layer 34 is formed on the entire surface of the device;

[0107] Then, as Figure 14 As shown, the second mask layer 34 is photolithographically developed, and the second mask layer 34, the top silicon layer 33, the buried oxide layer 32 and part of the silicon substrate 31 located in the isolation region are sequentially etched away to form an isolation region trench, while the second mask layer 34 located in the active region is retained.

[0108] Then, as Figure 15 As shown, an oxide layer of a certain thickness is deposited in the formed isolation trench, and then ground down to the second mask layer 34 by chemical mechanical polishing to form an isolation structure 35;

[0109] Finally, the second mask layer 34 located in the active region is removed.

[0110] In this solution, both local silicon oxide isolation structure and shallow trench isolation structure can be used. Local silicon oxide isolation structure is mostly used for MOS devices larger than 0.35 micrometers, while shallow trench isolation structure is mostly used for MOS devices smaller than 0.25 micrometers.

[0111] It should be noted that this invention is only described using a local silicon oxide isolation structure as an example. Other methods can also be described using a shallow trench isolation structure, which will not be elaborated here.

[0112] Step S103: As Figures 16-19 As shown, a drift region is defined on the FDSOI substrate 30, and a mixing region 38 is formed in a portion of the drift region;

[0113] The method for forming a mixing region 38 in a portion of the drift region includes:

[0114] First, such as Figure 16 As shown, a third mask layer 36 is formed on the entire surface of the device;

[0115] Then, as Figure 17 As shown, the third mask layer 36 is photolithographically developed to form an etching window, and based on the etching window, the isolation structure 35, the top silicon layer 33, the buried oxide layer 32, and part of the silicon substrate 31 are etched to form an etching trench 37. The etching adopts anisotropic etching (dry etching). To ensure complete etching, it is necessary to over-etch 50-100nm to ensure that the buried oxide layer 32 is fully opened.

[0116] Then, as Figure 18 As shown, single-crystal silicon is grown in the etched trench 37 using selective epitaxial growth to form a mixed region 38; the material of the single-crystal silicon can be any one of SiCl4, SiH2Cl2, SiHCl3 or SiH4.

[0117] Finally, as Figure 19 As shown, the remaining third mask layer 36 is removed.

[0118] The mixing region 38 is flush with the top silicon 33 in a second direction, where the silicon substrate 31 points to the top silicon 33.

[0119] Step S104: As Figure 20 As shown, a first well region 39 is formed in the FDSOI substrate 30 containing the buried oxide layer 32, and a second well region 40 is formed in the drift region;

[0120] A first well region 39 can be formed in an FDSOI substrate 30 containing a buried oxide layer 32 by ion implantation, and a second well region 40 can be formed in a drift region.

[0121] Step S105: As Figure 21 and Figure 25As shown, a first buried layer 41 and a second buried layer 42 are formed in the second well region 40, wherein the first buried layer 41 is located between the buried oxide layer 32 and the second buried layer 42.

[0122] The method for forming a first buried layer 41 and a second buried layer 42 in the second well region 40 includes:

[0123] First, such as Figure 21 As shown, a first mask layer 50 is formed on the entire surface of the device;

[0124] Then, as Figure 22 As shown, the first mask layer 50 is photolithographically developed to form an ion implantation window 51;

[0125] Then, as Figure 23 As shown, based on the ion implantation window 51, the first ion implantation is performed in the second well region 40 to form the second buried layer 42;

[0126] Then, as Figure 24 As shown, based on the ion implantation window 51, a second ion implantation is performed in the second well region 40 to form the first buried layer 41;

[0127] Finally, as Figure 25 As shown, the remaining first mask layer 50 is removed.

[0128] Wherein, the first buried layer 41 and the second buried layer 42 are flush in a first direction, and in a second direction, the first buried layer 41 is located between the buried oxide layer 32 and the second buried layer 42; the first direction is parallel to the FDSOI substrate 30, and the second direction is the silicon substrate 31 pointing to the top silicon layer 33.

[0129] The ions used for the first ion implantation and the second ion implantation are different.

[0130] For FDSOI NLDMOS devices, the ions used for the first ion implantation can be boron ions, and the ions used for the second ion implantation can be phosphorus ions.

[0131] For FDSOI PLDMOS devices, the ions used for the first ion implantation can be phosphorus ions, and the ions used for the second ion implantation can be boron ions.

[0132] Step S106: As Figure 26 As shown, a gate stack is formed on the upper surface of the FDSOI substrate 30 by photolithography, development and etching, spanning the first well region 39 and the second well region 40, and a first sidewall structure 48 is formed on both sides of the gate stack.

[0133] In this embodiment, a gate oxide layer 43, a polysilicon layer 44 (a-Si), and a first sidewall structure 48 can be sequentially deposited on the surface of the FDSOI substrate 30. One or more dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxide can be used to form the first sidewall structure 48. In this embodiment, the first sidewall structure 48 includes a silicon oxide layer 45, a silicon nitride layer 46, and a silicon oxide layer 47.

[0134] Step S107: As Figure 27 As shown, a raised source drain structure 49 (RSD) is formed on both sides of the gate stack and the drift region;

[0135] To reduce series resistance and contact resistance, FDSOI devices typically employ selective epitaxial growth to thicken the source and drain regions of the transistor, forming the RSD (Residual Source Detector), making the source and drain regions thicker than the channel region. When forming the RSD of an FDSOI NLDMOS device, the PMOS region is completely covered under a hard mask layer, and single-crystal silicon is epitaxially grown on the source and drain regions of the NLDMOS device to form the RSD. Similarly, when forming the RSD of an FDSOI PLDMOS device, the NMOS region is completely covered under a hard mask layer, and a single-layer or multi-layer germanium-silicon layer and a silicon cap layer (Si Cap Layer) are epitaxially grown on the source and drain regions of the PLDMOS device. During selective epitaxial growth, the silicon source used is any one of SiCl4, SiH2Cl2, SiHCl3, or SiH4, and the germanium source is GeH4.

[0136] Step S108: As Figure 28 As shown, a second sidewall structure 52 is formed on the surface of the first sidewall structure 48, and ion implantation is performed on the source / drain structure 49;

[0137] The second sidewall structure 52 can be formed using dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxide. For example, phosphorus can be ion-implanted into the source / drain structure 49 of an NLDMOS device, and boron or carbon can be ion-implanted into the source / drain structure 49 of a PLDMOS device.

[0138] Step S109: As Figure 29 As shown, a metal silicide layer 53 is formed on the source / drain structure 49 and the gate stack to form a low-resistance contact between the source / drain gate.

[0139] In this process, a metal silicide layer 53 can be formed first on the source / drain structure 49. The gate metal silicide layer 53 needs to be formed on the polysilicon layer 44, requiring the removal of the sidewall structure previously formed on the polysilicon layer 44. A thick oxide layer can be deposited first using CVD, then chemical mechanical polishing (CMP) can be used to polish down to the polysilicon layer 44, and then the metal silicide layer 53 can be formed on the polysilicon layer 44. After the metal silicide layer 53 is formed, the remaining metal can be removed by wet etching.

[0140] Metal layers such as nickel (Ni), cobalt (Co), and titanium (Ti) can be deposited on patterned semiconductor devices. Thermal treatment then allows metal atoms in these layers to diffuse into exposed silicon at the source, drain, and gate electrodes, forming metal silicide layers. After the metal silicides are formed, any remaining metal is removed using wet etching.

[0141] In step S104, the first well region 39 can be an N-type well region, and the second well region 40 can be a P-type well region;

[0142] Alternatively, the first well region 39 can be a P-type well region, and the second well region 40 can be an N-type well region.

[0143] In one embodiment, the LDMOS device is an FDSOI PLDMOS device, the first well region 39 is an N-type well region, the second well region 40 is a P-type well region, the first buried layer 41 is a P-type buried layer, and the second buried layer 42 is an N-type buried layer.

[0144] The P-type and N-type buried layers were formed by implanting boron ions (B) and phosphorus ions (P) with different implantation energies from deep to shallow. The first ion implantation formed the N-type buried layer, and the second ion implantation formed the P-type buried layer.

[0145] For FDSOI PLDMOS devices, a heavily doped P-type buried layer is introduced beneath the buried oxide layer in the drift region via ion implantation. After voltage is applied to the device, the P-type buried layer provides an additional low-resistance conduction path for current flow, achieving low on-resistance in the on-state. Subsequently, an N-type buried layer is introduced beneath the P-type buried layer to balance the excess acceptor impurities (holes) introduced by the P-type buried layer, ensuring complete depletion of the drift region in the off-state, thereby achieving a high breakdown voltage and improving device performance.

[0146] In another embodiment, the LDMOS device is an FDSOI NLDMOS device, the first well region 39 is a P-type well region, the second well region 40 is an N-type well region; the first buried layer 41 is an N-type buried layer, and the second buried layer 42 is a P-type buried layer.

[0147] The N-type and P-type buried layers were formed by implanting boron ions (B) and phosphorus ions (P) with different implantation energies from deep to shallow. The first ion implantation formed the P-type buried layer, and the second ion implantation formed the N-type buried layer.

[0148] For FDSOI NLDMOS devices, a heavily doped N-type buried layer is introduced beneath the buried oxide layer in the drift region via ion implantation. After voltage is applied to the device, the N-type buried layer provides an additional low-resistance conduction path for current flow, achieving low on-resistance in the on-state. Subsequently, a P-type buried layer is introduced beneath the N-type buried layer to balance the excess donor impurities (electrons) introduced by the N-type buried layer, ensuring complete depletion of the drift region in the off-state, thereby achieving a high breakdown voltage and improving device performance.

[0149] The implantation energy of boron ions used to form P-type buried layers can be 50-200 keV, and the implantation energy of phosphorus ions used to form N-type buried layers can be 100-300 keV.

[0150] The injection concentration for N-type buried layers can be 0.6 × 10⁻⁶. 12 cm -2 ~1.0×10 12 cm -2 The injection concentration of the P-type buried layer can be 3.3 × 10⁻⁶. 12 cm -2 ~3.8×10 12 cm -2 The charge in the P-type buried layer must be balanced with the charge in the N-type buried layer and the n-well (drift region) to ensure that each layer is completely depleted.

[0151] As can be seen from the above description, in the fabrication method of the FDSOI device provided by the technical solution of the present invention, by introducing the first buried layer 41 and the second buried layer 42 under the buried oxide layer 32 in the drift region by ion implantation, the breakdown voltage of LDMOS can be improved, the on-resistance can be reduced, the leakage current of the device can be improved, the switching characteristics and breakdown resistance of LDMOS can be improved, thereby improving the device performance of LDMOS.

[0152] Based on the above embodiments, another embodiment of the present invention also provides an LDMOS device, such as... Figure 29 As shown, the LDMOS device includes:

[0153] FDSOI substrate 30, wherein the FDSOI substrate 30 comprises a silicon substrate 31, a buried oxide layer 32 and a top silicon layer 33 stacked sequentially from bottom to top;

[0154] An active region and an isolation region are located on the FDSOI substrate 30, wherein the isolation region has an isolation structure 35;

[0155] A mixing region 38 is formed in a portion of the drift region located on the FDSOI substrate 30;

[0156] A first well region 39 and a second well region 40 are located within the FDSOI substrate 30, wherein the first well region 39 is within the FDSOI substrate 30 containing the buried oxide layer 32, and the second well region 40 is located in the drift region.

[0157] The first buried layer 41 and the second buried layer 42 are located in the second well region 40, with the first buried layer 41 located between the buried oxide layer 32 and the second buried layer 42;

[0158] A gate stack located on the upper surface of the FDSOI substrate 30 spans the first well region 39 and the second well region 40, and the gate stack has a first sidewall structure 48 on both sides.

[0159] Source and drain structures 49 located on both sides of the gate stack and the drift region;

[0160] A second sidewall structure 50 is located on the surface of the first sidewall structure 48;

[0161] The metal silicide layer 53 is located on the source / drain structure 49 and the gate stack.

[0162] This invention proposes an LDMOS device that can be integrated into FDSOI technology and its fabrication method. For FDSOI NLDMOS devices, a heavily doped N-type buried layer is introduced beneath the buried oxide layer in the drift region via ion implantation. After voltage is applied to the device, the N-type buried layer provides an additional low-resistance conduction path for current flow, achieving low on-resistance in the on-state. Subsequently, a P-type buried layer is introduced beneath the N-type buried layer to balance the excess donor impurities (electrons) introduced by the N-type buried layer, ensuring complete depletion of the drift region in the off-state, thereby achieving a high breakdown voltage. For FDSOI PLDMOS devices, a heavily doped P-type buried layer and an N-type buried layer are introduced beneath the buried oxide layer in the drift region to improve device performance.

[0163] As can be seen from the above description, in the FDSOI device provided by the technical solution of the present invention, by introducing N-type buried layers and P-type buried layers under the buried oxide layer in the drift region through ion implantation, the breakdown voltage of LDMOS can be improved, the on-resistance can be reduced, the leakage current of the device can be improved, the switching characteristics and breakdown withstand of LDMOS can be improved, thereby improving the device performance of LDMOS.

[0164] This invention achieves high breakdown voltage in the off state while maintaining low on-resistance in the on state, thereby improving the performance of LDMOS devices. It effectively solves the difficulties mentioned in existing technologies regarding the integration of LDMOS devices on FDSOI, and has promising application prospects.

[0165] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the LDMOS devices disclosed in the embodiments, since they correspond to the fabrication methods of the LDMOS devices disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to the section on the fabrication methods of LDMOS devices.

[0166] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0167] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating an LDMOS device, characterized in that, The manufacturing method includes: An FDSOI substrate is provided, the FDSOI substrate comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top; An active region and an isolation region are defined on the FDSOI substrate, and an isolation structure is formed in the isolation region; A drift region is defined on the FDSOI substrate, and a mixing region is formed in a portion of the drift region; A first well region is formed in the FDSOI substrate containing the buried oxide layer, and a second well region is formed in the drift region; A first buried layer and a second buried layer are formed in the second well region, wherein the first buried layer is located between the buried oxide layer and the second buried layer, and the first buried layer and the second buried layer are located below the buried oxide layer; A gate stack is formed on the upper surface of the FDSOI substrate across the first well region and the second well region, and a first sidewall structure is formed on both sides of the gate stack; A raised source / drain structure is formed on both sides of the gate stack and the drift region; A second sidewall structure is formed on the surface of the first sidewall structure, and ion implantation is performed on the source / drain structure; A metal silicide layer is formed on the source / drain structure and the gate stack to form a low-resistance contact between the source / drain and the gate. Wherein, forming a mixing region in a portion of the drift region includes: A third mask layer is formed on the entire surface of the device; The third mask layer is photolithographically developed to form an etched window; Based on the etching window, the isolation structure, the top silicon layer, the buried oxide layer, and part of the silicon substrate are etched to form etching trenches; wherein, the etching trenches etch over the buried oxide layer by 50-100 nm to ensure that the buried oxide layer is fully exposed; Single-crystal silicon is grown in the etched trenches using selective epitaxial growth to form a mixed region; The mixing region is flush with the top silicon layer in a second direction, which is the direction from the silicon substrate to the top silicon layer.

2. The manufacturing method according to claim 1, characterized in that, The first well region is an N-type well region, and the second well region is a P-type well region; Alternatively, the first well region may be a P-type well region, and the second well region may be an N-type well region.

3. The manufacturing method according to claim 2, characterized in that, The first well region is an N-type well region, and the second well region is a P-type well region; The first buried layer is a P-type buried layer, and the second buried layer is an N-type buried layer.

4. The manufacturing method according to claim 2, characterized in that, The first well region is a P-type well region, and the second well region is an N-type well region; The first buried layer is an N-type buried layer, and the second buried layer is a P-type buried layer.

5. The manufacturing method according to claim 3 or 4, characterized in that, Forming a first buried layer and a second buried layer in the second well region includes: A first mask layer is formed on the entire surface of the device; The first mask layer is photolithographically developed to form an ion implantation window; Based on the ion implantation window, a first ion implantation is performed in the second well region to form the second buried layer; Based on the ion implantation window, a second ion implantation is performed in the second well region to form the first buried layer; Wherein, the first buried layer and the second buried layer satisfy the condition of being flush in a first direction, and in a second direction, the first buried layer is located between the buried oxide layer and the second buried layer; the first direction is parallel to the top surface of the FDSOI substrate, and the second direction is from the silicon substrate to the top silicon layer.

6. The manufacturing method according to claim 5, characterized in that, The ions used for the first ion implantation and the second ion implantation are different; The ion used for the first ion implantation is boron ion, and the ion used for the second ion implantation is phosphorus ion; Alternatively, the ion used for the first ion implantation is a phosphorus ion, and the ion used for the second ion implantation is a boron ion.

7. The manufacturing method according to claim 1, characterized in that, The isolation structure is a local silicon oxide isolation structure or a shallow trench isolation structure.

8. The manufacturing method according to claim 7, characterized in that, The isolation structure is a localized silicon oxide isolation structure; Forming the isolation structure in the isolation zone includes: A second mask layer is formed on the entire surface of the device; The second mask layer is photolithographically developed and etched away to remove the second mask layer located in the isolation region, exposing the top silicon surface of the isolation region, while retaining the second mask layer located in the active region; The exposed top silicon of the isolation region is completely oxidized using a thermal oxidation process to form an isolation structure; Remove the second mask layer located in the active region.

9. The manufacturing method according to claim 7, characterized in that, The isolation structure is a shallow trench isolation structure; Forming the isolation structure in the isolation zone includes: A second mask layer is formed on the entire surface of the device; The second mask layer is photolithographically developed, and the second mask layer, top silicon, buried oxide layer and part of silicon substrate located in the isolation region are sequentially etched away to form an isolation region trench, while the second mask layer located in the active region is retained; An oxide layer of a certain thickness is deposited in the formed isolation trench, and then ground down to the second mask layer using a chemical mechanical polishing method to form an isolation structure; Remove the second mask layer located in the active region.

10. An LDMOS device, characterized in that, include: An FDSOI substrate, wherein the FDSOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top; An active region and an isolation region are located on the FDSOI substrate, wherein the isolation region has an isolation structure; The drift region located on the FDSOI substrate has a mixing region formed in a portion of the drift region; A first well region and a second well region are located within the FDSOI substrate, wherein the first well region is located within the FDSOI substrate containing the buried oxide layer, and the second well region is located within the drift region; The first buried layer and the second buried layer are located in the second well region, the first buried layer is located between the buried oxide layer and the second buried layer, and the first buried layer and the second buried layer are located below the buried oxide layer; A gate stack located on the upper surface of the FDSOI substrate, spanning the first well region and the second well region, wherein the gate stack has a first sidewall structure on both sides; Source and drain structures located on both sides of the gate stack and the drift region; The second sidewall structure located on the surface of the first sidewall structure; Metal silicide layer located on the source / drain structure and the gate stack; The mixing region formed in a portion of the drift region includes: Located at the etching window, the mixed region extends through the isolation structure, the top silicon layer, the buried oxide layer, and part of the silicon substrate; wherein the lower surface of the mixed region is located 50-100 nm below the lower surface of the buried oxide layer to ensure that the buried oxide layer is fully open; The mixing region is flush with the top silicon layer in a second direction, which is the direction from the silicon substrate to the top silicon layer.

Images