Method for manufacturing semiconductor packages

Abstract

A method for manufacturing semiconductor packages is disclosed. A molding press with an upper sleeve and a lower sleeve is used. Molded underfill (MUF) material is dispensed onto the bottom surface of a mold cavity to form a first dispensing pattern with a serpentine shape. A substrate on which a wafer stack is mounted is loaded onto the upper sleeve. The mold cavity into which the wafer stack is inserted is closed, and MUF material flows between the wafer stacks to impregnate them.

Description

Technical Field

[0001] This disclosure relates generally to packaging technology, and more specifically to methods for manufacturing semiconductor packages. Background Technology

[0002] In the manufacturing process of semiconductor packages, there is a process for forming a molded underfill (MUF). The process for forming the MUF includes forming an underfill layer and a sealant layer in a single process, while the formation of the underfill layer and the sealant layer are performed independently previously. Semiconductor packages can be formed by flip-chip bonding a semiconductor die onto a substrate and forming the MUF.

[0003] A MUF may include an underfill portion that fills the space between a semiconductor wafer and a substrate, and a sealant portion that covers and protects the underfill portion and the semiconductor wafer. The underfill portion may be formed to fill the space between semiconductor wafers stacked perpendicularly to each other. The underfill portion may be used to insulate and protect connectors that electrically and physically connect the semiconductor wafers to the substrate. Summary of the Invention

[0004] One aspect of this disclosure provides a method for manufacturing a semiconductor package. This method can be performed using a mold press having an upper and lower mold, which provide a mold cavity. The method may include the steps of: dispensing a molded underfill (MUF) material onto the bottom surface of the mold cavity to form a first dispensing pattern having a serpentine shape; loading a substrate on which a wafer stack is mounted onto the upper mold; and closing the mold cavity and impregnating the wafer stack with the MUF material to mold the MUF material into a MUF. Attached Figure Description

[0005] Figure 1 This is a schematic cross-sectional view showing a substrate having a wafer stack disposed thereon, according to an embodiment of the present disclosure.

[0006] Figure 2 It is shown Figure 1 A schematic diagram of an enlarged view of a wafer stack.

[0007] Figure 3 It shows that it is arranged in Figure 1 A schematic plan view of the shape of the wafer stack.

[0008] Figure 4 This is a schematic cross-sectional view showing a molding machine according to an embodiment of the present disclosure.

[0009] Figure 5This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0010] Figure 6 It shows the method used to form Figure 5 A schematic diagram of the process of the first pattern allocation.

[0011] Figure 7 It is shown Figure 6 A schematic plan view of an example of the planar shape of the first assigned pattern.

[0012] Figure 8 It shows the method used to... Figure 5 A schematic diagram of the process of mounting the substrate onto the upper sleeve.

[0013] Figure 9 and Figure 10 It is shown Figure 5 A schematic diagram of the molding process.

[0014] Figure 11 This is a schematic diagram illustrating a semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 12 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0016] Figure 13 It shows the method used to form Figure 12 A schematic plan view of the process of the second distribution pattern.

[0017] Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0018] Figure 15 It shows the method used to form Figure 14 A schematic plan view of the process of the third distribution pattern.

[0019] Figure 16 This is a schematic cross-sectional view illustrating the effect of reducing voids in a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0020] The meanings of the terms used in the various embodiments are as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Unless otherwise defined, the terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the embodiments pertain.

[0021] In the description of examples in this disclosure, terms such as “first” and “second,” “top” and “bottom or lower” are intended to distinguish elements but are not used to limit elements or indicate a particular order. These terms indicate relative positional relationships but do not limit the specific situation where another element is further introduced at that element or is in direct contact with that element. The same interpretation can be applied to other expressions describing relationships between elements.

[0022] Semiconductor devices may include a semiconductor substrate or a structure in which multiple semiconductor substrates are stacked. A semiconductor device may refer to a semiconductor package structure in which the structure of stacked semiconductor substrates is encapsulated. A semiconductor substrate may refer to a semiconductor wafer, semiconductor chip, or semiconductor chip in which electronic components and devices are integrated. A semiconductor chip may refer to a memory chip in which memory integrated circuits such as dynamic random access memory (DRAM) circuitry, static random access memory (SRAM) circuitry, NAND flash memory circuitry, NOR flash memory circuitry, magnetic random access memory (MRAM) circuitry, resistive random access memory (ReRAM) circuitry, ferroelectric random access memory (FeRAM) circuitry, or phase-change random access memory (PCRAM) are integrated, or to a logic chip or ASIC chip in which logic circuitry is integrated in the semiconductor substrate, or to a processor such as an application processor (AP), graphics processing unit (GPU), central processing unit (CPU), or system-on-a-chip (SoC). Semiconductor devices can be implemented in information and communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems. Semiconductor packages are suitable for the Internet of Things (IoT).

[0023] Throughout this specification, the same reference numerals denote the same devices. Even if reference numerals are mentioned or described without reference to the accompanying drawings, they may be mentioned or described with reference to another drawing. Furthermore, even if reference numerals are not shown in the accompanying drawings, they may be shown in another drawing.

[0024] Figure 1 This is a schematic cross-sectional view showing a substrate 120 on which a wafer stack 110 is disposed, according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A schematic diagram of an enlarged view of the wafer stack 110. Figure 3 It shows that it is arranged in Figure 1 A schematic plan view of the shape of the wafer stack 110.

[0025] Reference Figure 1 and Figure 2The substrate 120, on which the wafer stack 110 is disposed, can be used in a method of manufacturing a semiconductor package. In a non-limiting embodiment, the substrate 120 may be a semiconductor wafer or a portion thereof having an integrated circuit 129. The integrated circuit 129 integrated on the semiconductor wafer may include active devices such as transistors or passive devices such as capacitors or inductors. In an embodiment, the substrate 120 may be a semiconductor wafer having a memory device as the integrated circuit 129. In an embodiment, the substrate 120 may be a wiring structure having a wiring circuit structure such as a printed circuit board (PCB).

[0026] A wafer stack 110 can be constructed by stacking semiconductor wafers 111 perpendicularly to each other on a substrate 120. The semiconductor wafers 111 may include memory devices.

[0027] Semiconductor wafers 111 stacked on top of each other to form a wafer stack 110 can be perpendicularly connected to each other via conductive connectors 113. Some of the connectors 113 can perpendicularly connect the vertically stacked semiconductor wafers 111 to each other. Other portions of the connectors 113 can perpendicularly connect the semiconductor wafers 111 to the substrate 120. The connectors 113 can be introduced as conductive members such as conductive bumps. In embodiments, each of the connectors 113 can be introduced in the form of a conductive post or a conductive head.

[0028] Connectors 113 can be disposed between semiconductor wafers 111 disposed perpendicularly to each other, such that the semiconductor wafers 111 are perpendicularly spaced apart. Therefore, a first gap 114 can be formed between the stacked semiconductor wafers 111. Furthermore, a second gap 115 can be formed between the lowermost semiconductor wafer 111 and the substrate 120. Wafer stacks 110 and adjacent wafer stacks can be disposed on the substrate 120 while being spaced apart by a third gap 116. Molded underfill (MUF) portions can be formed to fill the first gap 114, the second gap 115, and the third gap 116.

[0029] In one embodiment, the wafer stack 110 can be constructed by flip-chip mounting only one semiconductor wafer 111 on the substrate 120. The wafer stack 110 can also be constructed by providing at least one semiconductor wafer 111 on the substrate 120.

[0030] Reference Figure 1 , Figure 2 and Figure 3 Another wafer stack 110 may be disposed adjacent to one wafer stack 110 on the substrate 120. Multiple wafer stacks 110 may be arranged on the substrate 120 in both horizontal and vertical directions.

[0031] Refer again Figure 1 The substrate 120 can be attached to the carrier 130. With the substrate 120 attached to the carrier 130, a stacking process for disposing the wafer stack 110 on the substrate 120 can be performed.

[0032] Figure 4 This is a schematic cross-sectional view showing a molding machine 300 according to an embodiment of the present disclosure.

[0033] Reference Figure 4 The method for manufacturing a semiconductor package according to embodiments of the present disclosure can be performed using a molding die 300. The molding die 300 may include a lower sleeve 310 and an upper sleeve 350. The lower sleeve 310 may be configured to provide a lower mold with a cavity 320 that substantially provides the shape of a MUF (Metal-in-the-Flight) package. A wafer stack is disposed thereon. Figure 1 The substrate of 110 in the middle ( Figure 1 The wafer stack 110 can be mounted on the upper sleeve 350. The wafer stack 110 can be positioned to be substantially inserted into the mold cavity 320.

[0034] The lower sleeve 310 may include a lower pressure plate 311, a lower sleeve bottom 312, and a lower sleeve side 313. The lower sleeve bottom 312 and the lower sleeve side 313 may be assembled together to provide a cavity 320 in which the wafer stack 110 will be inserted. The MUF may be molded to fill the cavity 320 such that the cavity 320 may have a specific shape that provides a shape for the molded MUF.

[0035] Based on the rising and falling operation of the lower pressure plate 311, the bottom 312 of the lower sleeve can rise and fall along the inner surface of the lower sleeve side 313. The lower sleeve side 313 can be constructed as a tubular member. The lower sleeve side 313 can be connected to and supported by the lower pressure plate 311 via a lower elastic portion 314. The lower elastic portion 314 can include an elastic member such as a spring.

[0036] Release film 315 may also be included in lower sleeve 310. Release film 315 may be introduced as an element to assist in separation from lower sleeve 310 after MUF is molded. Release film 315 may be an element to assist in creating a vacuum in mold cavity 320 during the molding process used to form MUF. Bottom surface 321 of mold cavity 320 may be substantially the surface of release film 315.

[0037] The upper sleeve 350 may include an upper pressure plate 351, an upper sleeve body 352, and an upper sleeve wall 353. The upper sleeve body 352 can rise and fall along the inner surface of the upper sleeve wall 353 based on the lowering and rising operation of the upper pressure plate 351. The upper sleeve wall 353 may be constructed as a tubular member. The upper sleeve wall 353 may be connected to and supported by the upper pressure plate 351 via an upper elastic portion 354. The upper elastic portion 354 may include an elastic member such as a spring.

[0038] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 6 It shows the method used to form Figure 5 A schematic cross-sectional view of process S11 of the first distribution pattern 410. Figure 7 It is shown Figure 6 A schematic plan view of an example of the planar shape of the first allocation pattern 410.

[0039] Reference Figure 5 and Figure 6 The method for manufacturing a semiconductor package according to an embodiment may include a process S11 (S11) for forming a first distribution pattern 410 on the bottom surface 321 of the cavity 320 of the lower sleeve 310. The first distribution pattern 410 may have, for example, Figure 7 The shape of the serpentine folded line pattern shown.

[0040] Reference Figure 6 The dispensing nozzle 400 can be introduced above the bottom surface 321 of the mold cavity 320 of the lower sleeve 310, and MUF material can be dispensed through the dispensing nozzle 400. By dispensing MUF material while moving the dispensing nozzle 400 above the bottom surface 321, the first dispensing pattern 410 can be formed having, as shown in the figure Figure 7 The serpentine shape is shown. The MUF material can be applied using a single-brush drawing method so that the first application pattern 410 can be formed into a continuous pattern shape. The first application pattern 410 may not be formed to cover the entire area of ​​the bottom surface 321, but may extend such that some portions of the pattern are partially distributed within the area of ​​the bottom surface 321.

[0041] Refer again Figure 7 The first distribution pattern 410 may have a continuous pattern shape including a guide portion 411, a first linear portion 412 and a second linear portion 414, and a folded portion 413. The bottom surface 321 of the mold cavity 320 may include a central region 321R1, an intermediate region 321R2, and an edge region 321R3.

[0042] The central region 321R1 of the bottom surface 321 of the mold cavity 320 can be the region having the center 321C of the bottom surface 321. The central region 321R1 can be the region extending outward from the center 321C of the bottom surface 321 by a certain distance. The central region 321R1 can be the region having several wafer stack overlapping regions 331.

[0043] The overlapping region 331 of the wafer stack can be one of them. Figure 1 The area where the wafer stack 110 overlaps with the bottom surface 321 of the mold cavity 320. When the wafer stack 110 or the substrate ( Figure 1 When the wafer stack 110 is loaded onto the mold cavity 320, it can be positioned to overlap with the wafer stack overlap region 331 respectively.

[0044] The edge region 321R3 of the bottom surface 321 of the cavity 320 may be a region extending inward from the edge 321E of the bottom surface 321 by a certain distance. The edge region 321R3 may be a region extending to overlap with the outermost wafer stack overlap region 331, which is the farthest from the center 321C among the wafer stack overlap regions 331. A portion of the edge region 321R3 may overlap with the outermost wafer stack overlap region 331M, but most of the edge region 321R3 may not include the wafer stack overlap region 331.

[0045] The middle region 321R2 of the bottom surface 321 of the mold cavity 320 can be the region between the central region 321R1 and the edge region 321R3.

[0046] Refer again Figure 7 and Figure 6 The guide portion 411 of the first distribution pattern 410 can be the starting portion of the distribution nozzle 400 forming the first distribution pattern 410. The distribution nozzle 400 can operate such that the guide portion 411 of the first distribution pattern 410 begins to form in the intermediate region 321R2 and extends to the edge region 321R3 of the bottom surface 321 of the mold cavity 320. At the starting point of the MUF material discharge from the distribution nozzle 400, it is difficult to control the discharge amount, which may lead to unintentional discharge of too much material. If the MUF material is excessively discharged from the distribution nozzle 400 in the edge region 321R3 of the bottom surface 321 of the mold cavity 320, it may cause defects such as molding overflow during the molding process. In order to suppress and prevent such defects in advance, the MUF material can be distributed by the distribution nozzle 400 starting in the intermediate region 321R2 of the bottom surface 321 of the mold cavity 320.

[0047] The first linear portion 412 of the first allocation pattern 410 can be formed to pass through the first row of wafer stack overlap regions 331-1 in the wafer stack overlap regions 331. The first row of wafer stack overlap regions 331-1 can refer to... Figure 7 The first allocation pattern 410 has a horizontally arranged row-by-row wafer stack overlap region 331. A second linear portion 414 of the first allocation pattern 410 can be formed to pass through a second row of wafer stack overlap regions 331-2 within the wafer stack overlap region 331. The second row of wafer stack overlap regions 331-2 can refer to a wafer stack overlap region 331 adjacent to the first row of wafer stack overlap regions 331-1. A folded portion 413 of the first allocation pattern 410 can be formed to connect the first linear portion 412 and the second linear portion 414. Thus, the first allocation pattern 410 is formed such that the shapes having the first linear portion 412 and the second linear portion 414, and the shape having the folded portion 413, alternately repeat, thereby achieving a serpentine shape for the first allocation pattern 410.

[0048] Linear portions 412 and 414, which are part of the first distribution pattern 410, can be formed to pass through at least one wafer stack. Figure 1 The overlapping region 331 of the wafer stack (110) overlaps. Each of the linear portions 412 and 414 of the first assignment pattern 410 can be formed to have a width D1 that is narrower than the width D2 of the wafer stack overlapping region 331.

[0049] When the linear portions 412 and 414 of the first assignment pattern 410 pass through the wafer stack overlap region 331, the passage of the first assignment pattern 410 intersects with the wafer stack ( Figure 1 The third gap between 110) Figure 1 The portion of the overlapping area of ​​the first distribution pattern 410 through the third gap 116 between the wafer stacks 110 can be substantially reduced or substantially minimized. When the portion of the first distribution pattern 410 that overlaps with the third gap 116 between the wafer stacks 110 is minimized, the phenomenon of voids getting trapped in the molded MUF material can be substantially suppressed, substantially reduced or substantially minimized.

[0050] Figure 16 This is a schematic cross-sectional view illustrating the effect of reducing voids 19 by a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0051] Reference Figure 16 and Figure 7 By using a first distribution pattern 410 formed by distributing MUF material, the wafer stack 110 can be MUF molded with virtually no voids 19 generated.

[0052] A large portion of the first distribution pattern 410 can be disposed in the wafer stack overlap region 331 overlapping with the wafer stack 110, thereby increasing the flow rate of the MUF material between semiconductor wafers 111 and between the semiconductor wafer 111 and the substrate 120. The introduction of the MUF material into the first gap 114 and the second gap 115 can be achieved more quickly than completely filling the third gap 116 between the wafer stacks 110 with the MUF material. Therefore, the MUF material can substantially completely fill the first gap 114 or the second gap 115 before the third gap 116 between the wafer stacks 110 is completely filled and the void 19 is embedded in the first gap 114 or the second gap 115.

[0053] Because the portion of the first distribution pattern 410 that overlaps with the third gap 116 between the wafer stacks 110 through the bottom surface 321 of the mold cavity 320 is substantially minimized, the amount of MUF material that can flow into the third gap 116 between the wafer stacks 110 can be relatively reduced compared to the total amount of MUF material. Therefore, MUF material can completely fill the first gap 114 and the second gap 115 before the third gap 116 between the wafer stacks 110 is completely filled.

[0054] Therefore, it is possible to substantially prevent, substantially suppress, or effectively reduce the occurrence of voids 19 in the MUF layer 400L.

[0055] Figure 8 It shows the method used to... Figure 5 A schematic diagram of the process S12 in which the base plate 120 is loaded onto the upper sleeve 350.

[0056] Reference Figure 8 and Figure 5 The method for manufacturing a semiconductor package according to embodiments of the present disclosure may include a process S12 for mounting a substrate 120 onto an upper housing body 352 of an upper housing 350. The back side 130S of a carrier 130 on which the substrate 120 is disposed may be held on the surface 352S of the upper housing body 352. The back side 130S of the carrier 130 may be vacuum-adsorbed onto the surface 352S of the upper housing body 352 by a vacuum holding system (not shown).

[0057] After the substrate 120 is mounted onto the upper sleeve 350, the upper sleeve 350 is lowered or the lower sleeve 310 is raised, or the lower sleeve 310 and the upper sleeve 350 are operated simultaneously, and thus the upper sleeve wall 353 can be in close contact with the release film 315. Therefore, the internal space formed by the upper sleeve wall 353 and the lower sleeve 310 can be disconnected from the outside, and a vacuum can be induced in the internal space. By inducing a vacuum state in the internal space formed by the upper sleeve wall 353 and the lower sleeve 310, the occurrence of voids during the MUF molding process can be reduced more effectively.

[0058] Figure 9 and Figure 10 It is shown Figure 5 A schematic diagram of the molding process S23. Figure 11 This is a schematic diagram illustrating a semiconductor package according to an embodiment of the present disclosure.

[0059] Reference Figure 9 , Figure 10 and Figure 5 A method for manufacturing a semiconductor package may include process S13, which involves operating an upper sleeve 350 and a lower sleeve 310 to close a mold cavity 320 and molding a MUF layer 400L. For example... Figure 9 As shown, by operating the upper pressure plate 351 to lower the upper sleeve body 352, the wafer stack 110 can be inserted into the mold cavity 320. The lower pressure plate 311 can be operated to raise the lower sleeve bottom 312.

[0060] like Figure 10 As shown, by continuously operating the upper pressure plate 351 or the lower pressure plate 311, the mold cavity 320 can be closed by bringing the edge portion 120E of the base plate 120 into close contact with the release film 315. After the mold cavity 320 is closed, the dispensed first distribution pattern 410 can be pressurized or heated to flow.

[0061] Reference Figure 10 and Figure 16 First allocation pattern ( Figure 9 The MUF material (410) can flow between the wafer stacks 110 to impregnate the wafer stacks 110. The MUF material of the first distribution pattern 410 can flow into the first gap 114, the second gap 115, and the third gap 116 to substantially completely fill the first gap 114, the second gap 115, and the third gap 116. Thereafter, the MUF material can be cooled and shaped to have a cavity 320, thereby forming a molded MUF layer 400L.

[0062] The upper sleeve 350 and the lower sleeve 310 can be released from each other, so that the mold cavity 320 is exposed to the outside, and the substrate 120 on which the MUF layer 400L is formed can be separated from the molding machine 300. Figure 11As shown, the semiconductor package in which the MUF layer 400L is formed can have a structure in which the MUF layer 400L is formed on the substrate 120 to cover the wafer stack 110.

[0063] Figure 12 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 13 It shows the method used to form Figure 12 A schematic plan view of the process of the second distribution pattern 420.

[0064] Reference Figure 12 and Figure 13 The method for manufacturing a semiconductor package may include a process S21 for forming a first distribution pattern 410 having a serpentine shape on the bottom surface 321 of the cavity 320 of the lower sleeve 310, a process S22 for forming a second distribution pattern 420 having a circular shape in the edge region 321R3 of the bottom surface 321 of the cavity 320 of the lower sleeve 310, and a process S22 for forming a second distribution pattern 420 having a circular shape on the upper sleeve ( Figure 4 The upper body of the 350) Figure 4 The process S23 of loading the substrate 120 onto the substrate 352) and the process S24 of molding the MUF material into a MUF layer.

[0065] The first dispensing pattern 410 can be formed on the bottom surface 321 of the lower sleeve 310, and the second dispensing pattern 420 can be formed using a dispensing nozzle. Figure 6 The MUF material is distributed onto the edge region 321R3 of the bottom surface 321 by the first distribution pattern 420. The second distribution pattern 420 may include a continuous pattern extending along the edge region 321R of the bottom surface 321 of the lower sleeve 310. The second distribution pattern 420 may be formed in a circular shape. The second distribution pattern 420 may be formed to partially overlap with the first distribution pattern 410.

[0066] In most of the edge region 321R3 of the bottom surface 321 of the cavity 320, the wafer stack overlap region 331 may not be provided. Therefore, the space in the edge region 321R3 of the cavity 320 is mostly filled with MUF material. In the middle region 321R2, the wafer stack overlap region 331 can be set to be relatively dense. Therefore, the space in the middle region 321R2 of the cavity 320 can be filled with wafer stack 110 and MUF material.

[0067] To fill the space in the edge region 321R3 of the mold cavity 320 with MUF material, it may be necessary to distribute a relatively larger amount of MUF material compared to the central region 321R2. A second distribution pattern 420 can be formed so that a relatively larger amount of MUF material is distributed on the edge region 321R3. Therefore, the occurrence of filling defects, in which insufficient MUF material is distributed on the edge region 321R3 of the bottom surface 321 of the mold cavity 320, can be effectively prevented, substantially suppressed, or substantially reduced.

[0068] Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Figure 15 It shows the method used to form Figure 14 A schematic plan view of the process S33 of the third distribution pattern 430.

[0069] Reference Figure 14 and Figure 15 A method for manufacturing a semiconductor package may include: a process S31 for forming a serpentine first distribution pattern 410 on the bottom surface 321 of the cavity 320 of the lower sleeve 310; a process S32 for forming a circular second distribution pattern 420 in the edge region 321R3 of the bottom surface 321 of the cavity 320 of the lower sleeve 310; a process S33 for forming a spiral third distribution pattern 430 in the central region 321R1 of the bottom surface 321 of the cavity 320 of the lower sleeve 310; and a process S34 for forming a spiral third distribution pattern 430 on the upper sleeve (… Figure 4 The process S34 of loading the substrate 120 onto the upper body 352 of the 350) and the process S35 of molding the MUF material into a MUF layer.

[0070] The first dispensing pattern 410 and the second dispensing pattern 420 can be formed on the bottom surface 321 of the lower sleeve 310, and the MUF material can be dispensed using a dispensing nozzle. Figure 6 The first distribution pattern 410 is distributed in the central region 321R1 of the bottom surface 321 to form a third distribution pattern 430. The third distribution pattern 430 may be formed to partially overlap with the first distribution pattern 410. The third distribution pattern 430 may be formed to distribute a relatively larger amount of MUF material in the central region 321R1 of the bottom surface 321 of the mold cavity 320 compared to the intermediate region 321R2. The third distribution pattern 430 allows the MUF material to flow from the central region 321R1 of the bottom surface 321 of the mold cavity 320 to the intermediate region 321R2, etc., so as to effectively prevent or reduce voids in the central region 321R1 of the mold cavity 320.

[0071] The inventive concept of the present invention has been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the invention. Therefore, the embodiments disclosed in this specification should not be considered restrictive but rather illustrative. The scope of the inventive concept is not limited to the foregoing description but is defined by the appended claims, and all distinguishing features within the equivalent scope should be interpreted as included in the inventive concept.

[0072] Cross-references to related applications

[0073] This application claims priority to Korean Application No. 10-2020-0133039, filed on October 14, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor package using a molding machine having an upper sleeve and a lower sleeve providing a mold cavity, the method comprising the steps of: A molded bottom filler MUF material is distributed on the bottom surface of the mold cavity to form a first distribution pattern with a serpentine shape; A substrate is mounted on the upper sleeve, and a wafer stack is mounted on the substrate; and The mold cavity is closed and the MUF material is impregnated into the wafer stack to mold the MUF material into a MUF layer. The first allocation pattern includes: The first linear portion passes through the first row of wafer stack overlap regions among the plurality of wafer stack overlap regions that overlap with the wafer stack on the bottom surface of the mold cavity; The second linear portion passes through the second row of the wafer stack overlap region within the wafer stack overlap region; and A folded portion that connects the first linear portion and the second linear portion.

2. The method according to claim 1, wherein, The first assignment pattern includes a continuous portion of a wafer stack overlap region that extends through the bottom surface of the mold cavity and overlaps with at least one wafer stack.

3. The method according to claim 2, wherein, The continuous portion of the first distribution pattern has a width narrower than the width of the wafer stack overlap region on the bottom surface of the mold cavity.

4. The method according to claim 1, wherein, The bottom surface of the mold cavity includes: An edge region extending from the edge of the bottom surface to overlap with the outermost wafer stack overlap region within the wafer stack overlap region; The central region includes the center of the bottom surface; and The intermediate region, which is located between the central region and the edge region, and The first distribution pattern begins in the middle region and also includes a guide portion connected to the first linear portion.

5. The method according to claim 1, wherein, The bottom surface of the mold cavity includes an edge region that extends from the edge of the bottom surface to overlap with the outermost wafer stack overlap region of the wafer stack, the wafer stack overlap region overlapping the wafer stack.

6. The method according to claim 5, further comprising the following steps: The MUF material is further distributed in the edge region to form a second distribution pattern extending along the edge region.

7. The method according to claim 6, wherein, The second distribution pattern is formed to have a circular shape.

8. The method according to claim 6, wherein, The second allocation pattern is formed to partially overlap with the first allocation pattern.

9. The method according to claim 4, further comprising the following steps: The MUF material is further distributed in the central region at the center of the bottom surface of the mold cavity to form a third distribution pattern with a spiral shape.

10. The method according to claim 9, wherein, The third allocation pattern is formed to partially overlap with the first allocation pattern.

11. The method according to claim 1, wherein, The wafer stack is formed by vertically stacking one or more semiconductor wafers.

12. The method according to claim 1, wherein, The wafer stack includes a plurality of semiconductor wafers stacked perpendicularly to each other with a first gap between them, and the plurality of semiconductor wafers are stacked such that a second gap exists between the plurality of semiconductor wafers and the substrate. The wafer stacks are spaced apart by a third gap, and The MUF material fills the first gap, the second gap, and the third gap.

13. The method according to claim 1, wherein, The substrate includes a semiconductor wafer with integrated circuits.

14. The method according to claim 1, wherein, The substrate includes a printed circuit board (PCB).

15. The method according to claim 1, wherein, When the mold cavity is closed, the wafer stack is inserted into the closed mold cavity.

Images