An isolation trench and a method of manufacturing an isolation trench

Abstract

The present invention relates to an isolation trench and a method of manufacturing an isolation trench. The isolation trench includes an oxide layer on the trench, a nitride liner at the bottom within the oxide layer, a first oxide within the nitride liner and flush with the surface of the nitride liner, and a second oxide on the first oxide; the second oxide is flush with the surface of the oxide layer. By removing a portion of the deposited material in the isolation trench and re-depositing the second oxide, hot carrier electrons that become trapped can be prevented from generating a channel in the active region, thereby avoiding the adverse effects of hot electron punchthrough.

Description

Technical Field

[0001] This application relates to semiconductor devices, and more specifically to an isolation trench and a method for manufacturing the isolation trench. Background Technology

[0002] To isolate transistors within a semiconductor chip, shallow trench isolation (STI) is typically used, which involves forming trenches on a semiconductor substrate and filling them with an insulating film. For example... Figure 1A The image shows a top view of cell region A, NMOS region B, and PMOS region C on a semiconductor substrate. Figure 1B The figure shows a cross-sectional view of the cell region 301, the NMOS region 302, and the PMOS region 303 on the semiconductor substrate.

[0003] like Figure 1B As shown, during the transistor discrete process, a channel oxide 2 (such as silicon dioxide) and a nitride pad 3 (such as silicon nitride) are formed in the trenches of the cell region, NMOS region, and PMOS region, and an oxide 4 (such as silicon dioxide) is deposited on them. Using a nitride pad can reduce the stress on the device and prevent the active region from being oxidized during subsequent oxidation processes, thereby improving the characteristics of the transistor.

[0004] like Figure 2 The diagram shows a PMOS region where the first PMOS (7A) and the second PMOS (7B) are isolated by an isolation trench 130. However, on the nitride pad 3 of the isolation trench in the PMOS transistor, hot carrier electrons 201 form traps 202, creating leakage paths 203, leading to hot electron-induced punch-through (HEIP) effect, resulting in defects. HEIP defects occur because the hot carrier electrons 201, which become traps 202, create channels in the active region that should be isolated (insulated), allowing unwanted current 203 to flow between transistors, thus degrading the transistor's turn-off characteristics. Current methods involve thickening the channel oxide 2 deposited in all regions. While this prevents hot electron penetration and trap formation 202, thicker channel oxide 2 leads to reduced performance in the cell region. Summary of the Invention

[0005] To address the aforementioned problems, this application provides an isolation trench, comprising: an oxide layer on the trench, a nitride liner at the bottom of the oxide layer, a first oxide within the nitride liner and flush with the surface of the nitride liner, and a second oxide on the first oxide; the second oxide being flush with the surface of the oxide layer.

[0006] To address the aforementioned problems, this application also provides a method for manufacturing an isolation trench, comprising the following steps: forming a PMOS region isolation trench comprising a first oxide and a nitride pad on a semiconductor substrate; etching the PMOS region isolation trench using a photoresist exposure process and an etching process to remove part of the deposited material in the isolation trench; depositing a second oxide on the first oxide; planarizing the second oxide; and etching the second oxide and the nitride pad using an etching process.

[0007] The advantage of this application is that by removing part of the deposited material in the isolation trench and then depositing the second oxide, it is possible to prevent hot carrier electrons that have become traps from generating channels in the active region, thereby avoiding the adverse effects of hot electron penetration. Attached Figure Description

[0008] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0009] Figure 1A A top view of the existing cell region, NMOS region, and PMOS region is shown;

[0010] Figure 1B Cross-sectional views of the existing cell region, NMOS region, and PMOS region are shown;

[0011] Figure 2 A schematic diagram of hot electron penetration in the PMOS region is shown;

[0012] Figure 3A A schematic diagram of the structure of the isolation trench according to an embodiment of this application is shown;

[0013] Figure 3B A schematic diagram of the structure of an isolation trench according to another embodiment of this application is shown;

[0014] Figure 3C A schematic diagram illustrating the prevention of hot electron penetration into the PMOS region according to an embodiment of this application is shown;

[0015] Figure 4 A schematic diagram illustrating the semiconductor manufacturing steps according to an embodiment of this application is shown;

[0016] Figure 5A A schematic diagram of trenches being formed on a semiconductor substrate is shown;

[0017] Figure 5B A schematic diagram showing the deposition of an oxide layer and a nitride liner in a trench is shown;

[0018] Figure 5C A schematic diagram of planarization of the cell region, NMOS region, and PMOS region is shown.

[0019] Figure 6A A schematic diagram showing the application of photoresist in the cell region, NMOS region, and PMOS region is shown.

[0020] Figure 6B A schematic diagram is shown showing the removal of a portion of the first oxide in the isolation trench of the PMOS region using exposure and etching processes;

[0021] Figure 6C A schematic diagram of etching and removing a portion of a nitride pad in an exposed PMOS region isolation trench is shown;

[0022] Figure 7 A schematic diagram is shown of the deposition of a second oxide on the remaining nitride pads and the first oxide in the isolation trench of the PMOS region. Detailed Implementation

[0023] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0025] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0026] Figure 3AA schematic diagram of the isolation trench according to an embodiment of this application is shown. The isolation trench of the PMOS region 303 includes: an oxide layer 102 on the trench 140, a nitride pad 103 at the bottom of the oxide layer 102, a first oxide 104 within the nitride pad 103 and flush with the surface of the nitride pad 103, and a second oxide 105 on the first oxide 104; the second oxide 105 is flush with the surface of the oxide layer 102. Figure 3B A schematic diagram of another isolation trench according to an embodiment of this application is shown. When the first oxide 105 and the second oxide 105 are made of the same material, the first oxide 104 and the second oxide 105 form an oxide isolation layer 200. The oxide isolation layer 200 is on the nitride pad 103 and flush with the surface of the oxide layer 102. For example... Figure 3C As shown, the nitride pad 103 at the bottom of the oxide layer 102, being only a small layer and lower than the regions where the first PMOS (7A) and second PMOS (7B) are located, prevents the leakage path 203 generated by the hot carrier electrons 201 that become traps 202 in the active region from forming a channel in the active region of the first PMOS (7A) and second PMOS (7B). Therefore, no unwanted current flows between the transistors, maintaining the transistor's turn-off characteristics. Isolation trenches in other regions of the pad 100 are as follows... Figure 3A As shown. Pad 100 includes cell region 301, NMOS region 302 and PMOS region 303.

[0027] Figure 4 A method for fabricating an isolation trench is illustrated. An example method begins in operation 401, where a PMOS region isolation trench 130 comprising a first oxide 104 is formed on a semiconductor substrate 100. As... Figure 5A As shown, the semiconductor substrate 100 is etched using an etching process to form trenches 140 in the cell region 301, NMOS region 302, and PMOS region 303. Figure 5B As shown, an oxide layer 102 and a nitride liner 103 are sequentially deposited in trench 140. Figure 5C As shown, a first oxide 104 is filled onto the nitride pads 103 in the trenches of NMOS region 302 and PMOS region 303. The cell region 301, NMOS region 302 and PMOS region 303 after filling with oxide 104 are planarized to form cell region isolation trench 110, NMOS region isolation trench 120 and PMOS region isolation trench 130.

[0028] Continue with step 402, using photoresist exposure and etching processes to etch the PMOS region isolation trench 130, removing some of the deposited material in the isolation trench 130. For example... Figure 6AAs shown, photoresist 108 is coated on cell region 301, NMOS region 302, and PMOS region 303, exposing the isolation trench 130 of the PMOS region to be etched. Figure 6B As shown, a portion of the first oxide 104 in the exposed PMOS region isolation trench 130 is etched using exposure and etching processes. Figure 6C As shown, a portion of the nitride pad 103 in the exposed PMOS region isolation trench 130 is etched and removed, wherein the depth of etching the first oxide 104 is consistent with the depth of etching the nitride pad 103, so that the height of the nitride pad 103 is consistent with the height of the remaining first oxide 104.

[0029] Continue with operation 403 to deposit the second oxide on the first oxide. (Example:) Figure 7 As shown, after removing the photoresist 108, a second oxide 105 is deposited on the remaining nitride pad 103 and first oxide 104 in the PMOS region isolation trench 130 using a high-density plasma chemical vapor deposition (HDP) process. The use of HDP process does not affect the active region.

[0030] Continue with operation 404 to planarize the second oxide 105. Stop at nitride pad 103.

[0031] Continue with operation 405, using an etching process to etch the second oxide 105 and the nitride pad 103. (Example:) Figure 3A As shown, the second oxide 105 on the PMOS region isolation trench 130 is etched and removed using an etching process, with an etching thickness of less than or equal to 200 angstroms. The nitride pad 103 on the PMOS region isolation trench 130 is etched and removed using an etching process. This makes the surface of the second oxide 105 flush with the oxide layer 102.

[0032] Etching processes include dry etching and / or wet etching. Taking operation 402 as an example, when etching the PMOS region isolation trench 130, a portion of the oxide 104 and a portion of the nitride pad 103 in the PMOS region isolation trench 130 can be etched and removed using either wet or dry etching. From the start of etching the PMOS region isolation trench 130 until a portion of the deposited material in the PMOS region isolation trench 130 is removed, a method that does not cause photoresist etch (PRAttack) to the cell region 301 and the NMOS region 302 is used. Taking operation 405 as an example, wet etching is used to remove the second oxide 105 on the isolation trench 130 and the second oxide 105 outside the isolation trench 130, with an etching thickness of less than or equal to 200 angstroms. Then, wet etching is used to remove the nitride pads 103 on the isolation trench 130 and the nitride pads 103 on the active region, and dry etching is used to remove the nitride pads 103 outside the isolation trench 130.

[0033] In one embodiment, the material of the oxide layer 105 is further silicon dioxide.

[0034] In one embodiment, the materials of the first oxide 104 and the second oxide 105 are further silicon dioxide. If the first oxide 104 and the second oxide 105 are made of the same material, the structure of the isolation trench 130 of the formed PMOS region 303 is as follows: Figure 3B As shown. If the first oxide 104 and the second oxide 105 are made of different materials, the structure of the isolation trench 130 of the formed PMOS region 303 is as follows. Figure 3A As shown.

[0035] In one embodiment, the material of the nitride pad 103 is further silicon nitride.

[0036] The method in this application removes part of the deposited material in the PMOS isolation trench and then deposits a second oxide, which can prevent hot carrier electrons that have become traps from generating channels in the active region, thereby avoiding the adverse effects caused by hot electron penetration, preventing the degradation of transistor turn-off characteristics, and without reducing the performance of the cell region.

[0037] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0038] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. An isolation trench, characterized in that, include: An oxide layer on the trench, a nitride liner at the bottom of the oxide layer, a first oxide flush with the surface of the nitride liner, and a second oxide on the first oxide; the second oxide is flush with the surface of the oxide layer; the sidewall of the second oxide is in contact with the oxide layer; The isolation trench also includes regions where the first PMOS and the second PMOS are located on both sides; the isolation trench is used to isolate the first PMOS and the second PMOS; the height of the nitride pad is lower than the regions where the first PMOS and the second PMOS are located.

2. The isolation trench as described in claim 1, characterized in that, When the first oxide and the second oxide are made of the same material, the first oxide and the second oxide form an oxide isolation layer, which is on the nitride liner and flush with the surface of the oxide layer.

3. A method for manufacturing an isolation trench, characterized in that, The method for preparing an isolation trench as described in claim 1 or 2 includes the following steps: A PMOS region isolation trench comprising a first oxide and a nitride pad is formed on a semiconductor substrate; The PMOS region isolation trench is etched using photoresist exposure and etching processes to remove some of the deposited material in the isolation trench; A second oxide is deposited on the first oxide, wherein the sidewalls of the second oxide are in contact with the oxide layer; The second oxide is planarized; The second oxide and nitride pads are etched using an etching process; The step of forming a PMOS region isolation trench including a first oxide and a nitride pad on a semiconductor substrate further includes the following step: etching the semiconductor substrate using an etching process to form a trench in the PMOS region; An oxide layer and a nitride pad are sequentially deposited in the trench, and a first oxide layer is filled in. The PMOS region after filling with the first oxide layer is planarized to form a PMOS region isolation trench. The PMOS region isolation trench also includes regions where the first PMOS and the second PMOS are located on both sides. The PMOS region isolation trench is used to isolate the first PMOS and the second PMOS. The step of using photoresist exposure and etching processes to etch the PMOS region isolation trench and remove part of the deposited material in the isolation trench further includes the following step: coating the PMOS region with photoresist to expose the PMOS region isolation trench to be etched. Using exposure and etching processes, a portion of the first oxide in the exposed PMOS region isolation trench is etched and removed; Etching and removing a portion of the nitride pad in the exposed PMOS region isolation trench, wherein the depth of etching the first oxide is consistent with the depth of etching the nitride pad, so that the height of the nitride pad is consistent with the height of the remaining first oxide. The height of the nitride pad is lower than the regions where the first PMOS and the second PMOS are located.

4. The method for manufacturing the isolation trench as described in claim 3, characterized in that, The step of depositing the second oxide on the first oxide further includes the following steps: Remove the photoresist; A second oxide is deposited on the remaining nitride pads and the first oxide in the isolation trench of the PMOS region using a high-density plasma chemical vapor deposition process.

5. The method for manufacturing the isolation trench as described in claim 3, characterized in that, The step of planarizing the second oxide further includes the following steps: The second oxide is planarized, stopping at the nitride pad.

6. The method for manufacturing the isolation trench as described in claim 3, characterized in that, The step of etching the second oxide and nitride pads using an etching process further includes the following steps: The second oxide on the isolation trench is etched and removed using an etching process, with an etching thickness of less than or equal to 200 angstroms; The nitride liner on the isolation trench is etched and removed using an etching process.

7. The method for manufacturing the isolation trench as described in claim 6, characterized in that, The etching process includes dry etching and / or wet etching.

8. The method for manufacturing the isolation trench as described in claim 3, characterized in that, in, The material of the oxide layer is further silicon dioxide.

9. The method for manufacturing the isolation trench as described in claim 4, characterized in that, in, The first oxide and the second oxide are materials that are further silicon dioxide.

10. The method for manufacturing the isolation trench as described in claim 3, characterized in that, in, The material of the nitride liner is further silicon nitride.

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