A method of manufacturing a semiconductor device

Abstract

The present disclosure provides a semiconductor device manufacturing method. The semiconductor device manufacturing method comprises the following steps: providing a semiconductor substrate, then forming a capacitor structure above the semiconductor substrate, and forming an interlayer dielectric layer above the capacitor structure. The present disclosure processes the interlayer dielectric layer as follows: first processing the interlayer dielectric layer to form a plurality of columnar protrusions on the interlayer dielectric layer; second processing the interlayer dielectric layer to reduce the height of the columnar protrusions; and finally, chemically mechanically polishing the interlayer dielectric layer to make the upper surface of the interlayer dielectric layer flush, thereby achieving the effect that the upper surface of the interlayer dielectric layer is planarized. In the present disclosure, the first processing can be dry etching, and the second processing can be wet etching. Compared with the prior art, the technical solution provided by the present disclosure can effectively eliminate the step height difference between different positions on the device while protecting the interlayer dielectric layer that needs to be reserved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device fabrication technology, and more specifically, this disclosure provides a method for manufacturing a semiconductor device. Background Technology

[0002] As the size of semiconductor memory devices shrinks, it is necessary to ensure that capacitors maintain a certain capacitance while achieving device miniaturization. During device fabrication, the step height difference between the cell array region and the peripheral circuit region (core / peri) can be significant. This difference can potentially hinder subsequent processes, necessitating surface planarization to eliminate step height differences at different locations on the device. However, current methods for eliminating step height differences often require the planarization equipment to apply considerable pressure, which may damage the upper film that needs to be preserved, leading to a decrease in semiconductor device yield.

[0003] Therefore, how to eliminate the step height difference while minimizing damage to the upper film has become a technical problem that urgently needs to be solved and a key research focus for those skilled in the art. Summary of the Invention

[0004] To address the problem of easily damaging the upper film layer that needs to be retained in existing methods for eliminating step height differences, this disclosure provides a method for manufacturing a semiconductor device. This disclosure allows for multi-step pretreatment of the interlayer dielectric layer (including but not limited to dry etching, wet etching, or photolithography) before the chemical mechanical polishing step. This weakens the connection strength between the parts to be removed and the parts to be retained. Therefore, the technical solution provided by this disclosure can minimize damage to the upper film layer that needs to be retained while eliminating step height differences.

[0005] To achieve the aforementioned technical objectives, this disclosure provides a method for manufacturing a semiconductor device. This method includes, but is not limited to, the following steps: providing a semiconductor substrate, forming a capacitor structure on the semiconductor substrate, and forming an interlayer dielectric layer on the capacitor structure. This disclosure performs the following processing on the interlayer dielectric layer: a first processing to form multiple columnar protrusions on the interlayer dielectric layer; a second processing to reduce the height of the columnar protrusions; and finally, chemical mechanical polishing to make the upper surface of the interlayer dielectric layer flush, achieving a planarization effect. The first processing can be dry etching, and the second processing can be wet etching or a combination of photolithography and dry etching.

[0006] The beneficial effects of this disclosure are as follows: Compared with the prior art, the technical solution provided by this disclosure can effectively eliminate the step height difference between different locations on a semiconductor device while protecting the interlayer dielectric layer that needs to be retained. It is evident that this disclosure can perform multi-step etching or etching combined with photolithography on the interlayer dielectric layer, which serves as the upper film, before the chemical mechanical polishing (CMP) step. This effectively weakens the connection strength between the parts of the interlayer dielectric layer that need to be removed and the parts that need to be retained. Therefore, the technical solution provided by this disclosure can effectively avoid damage to the upper film that needs to be retained while eliminating the step height difference at different locations on the device. Attached Figure Description

[0007] Figure 1 This diagram shows a longitudinal cross-sectional structure of a semiconductor device after a capacitor structure, a protective layer, and an interlayer dielectric layer are sequentially formed on a semiconductor substrate.

[0008] Figure 2 It shows the Figure 1 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device formed after dry etching of the interlayer dielectric layer.

[0009] Figure 3 It shows the Figure 2 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device formed after wet etching of the protrusions.

[0010] Figure 4 It shows the Figure 2 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device formed after photolithography and dry etching of each protrusion.

[0011] Figure 5 It shows the Figure 3 or Figure 4 A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device formed after the interlayer dielectric layer is chemically and mechanically polished.

[0012] In the picture,

[0013] 100. Semiconductor substrate.

[0014] 200. Capacitor structure.

[0015] 300. Protective layer.

[0016] 400. Interlayer dielectric layer.

[0017] 401. Protrusion.

[0018] 402. Groove. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0021] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0022] One or more embodiments of this disclosure can provide a method for manufacturing a semiconductor device, thereby effectively solving the problem that the interlayer dielectric layer in the prior art is prone to damage in subsequent processes, while eliminating the step height differences at different locations on the semiconductor device.

[0023] like Figure 1 As shown, a semiconductor substrate 100 is provided. In this embodiment, the semiconductor substrate 100 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). In specific implementations of this disclosure, the appropriate selection can be made according to actual processing needs. This embodiment is capable of forming an active region (ACT) on the semiconductor substrate 100.

[0024] This disclosure describes forming a capacitor structure 200 on a semiconductor substrate 100. The capacitor structure 200 may include a metal material layer, such as tungsten. A protective layer 300 may then be formed on the capacitor structure 200. In this embodiment, the protective layer 300 includes, but is not limited to, silicon nitride, such as silicon nitride. In this embodiment, an interlayer dielectric layer 400 (i.e., the upper film of this disclosure embodiment) may be formed on the capacitor structure 200. The interlayer dielectric layer (ILD) 400 may include, but is not limited to, silicon oxide, such as silicon oxide. In some specific complex semiconductor device structures, the interlayer dielectric layer 400 in this embodiment may include, but is not limited to, ILD0, ILD1, ILD2, ILD3, ILD4, etc.

[0025] like Figure 2 As shown, this disclosure enables the interlayer dielectric layer 400 to undergo a first processing (initial preprocessing) to form multiple columnar protrusions 401 on the interlayer dielectric layer 400. However, it should be understood that "columnar" is a preferred structural form of the protrusions 401 in some embodiments of this disclosure. This disclosure can also adopt thin plate-like, small block-like, irregular shapes, etc., and those skilled in the art can make reasonable modifications or alterations based on the content of this disclosure.

[0026] In one or more embodiments of this disclosure, the process of performing a first treatment on the interlayer dielectric layer 400 includes: etching the interlayer dielectric layer 400 to form a plurality of columnar protrusions 401 by etching a plurality of grooves 402 on the interlayer dielectric layer 400. In this embodiment, the method of etching the interlayer dielectric layer 400 is dry etching. The plurality of different grooves 402 can be arranged in a crisscross pattern to "cut out" a plurality of columnar protrusions 401, and the etching depth can be determined according to the required thickness of the interlayer dielectric layer to be retained. To ultimately form a more reliable dielectric layer structure, in this embodiment, each groove 402 is positioned directly above the capacitor structure 200, i.e., directly above the cell array region.

[0027] like Figure 3As shown, this disclosure enables a second processing (secondary pretreatment) of the interlayer dielectric layer 400 to reduce the height of the columnar protrusions 401 or even almost eliminate them. In some embodiments of this disclosure, the second processing of the interlayer dielectric layer 400 may include: removing the columnar protrusions 401 by etching and reducing the thickness of the interlayer dielectric layer 400. In this embodiment, the etching method for the columnar protrusions 401 is wet etching. As a preferred embodiment of this disclosure, in some embodiments, a BOE-based solution is filled into the gaps (which can be understood as grooves 402) between adjacent columnar protrusions 401 to wet-etch the columnar protrusions 401 using the BOE-based solution. The intensity of the wet etching depends on the height and thickness of the columnar protrusions 401, which will not be elaborated in this embodiment. The BOE-based solution is a buffered oxide etching solution, which can be a mixture of hydrofluoric acid, water, and ammonium fluoride. By using BOE-type solutions, one or more embodiments of this disclosure can reduce the possibility of cross-sectional degradation of the interlayer dielectric layer 400 and avoid problems such as bending or deformation of the interlayer dielectric layer 400 in subsequent processes. Of course, other embodiments of this disclosure can also use other solutions similar to the BOE-type solutions described above that can be used to achieve wet etching. This disclosure focuses on the etching process that can complete the columnar protrusions 401.

[0028] like Figure 4 As shown, in some other embodiments of this disclosure, the process of performing a second processing on the interlayer dielectric layer 400 includes: performing photolithography and dry etching on the columnar protrusions 401 according to a set pattern; forming a mask by photolithography; and then using the mask to perform dry etching, thereby reducing the height of the "step" (i.e., the columnar protrusions 401 with reduced height) on the surface of the interlayer dielectric layer 400. The set pattern may correspond to the location of the columnar protrusions 401 on the interlayer dielectric layer 400, that is, removing part or all of the columnar protrusions 401 by photolithography. Figure 4 The photolithography and dry etching processes in the process are similar to Figure 3 The wet etching process described herein is one of two parallel embodiments of this disclosure, both of which can reduce the height of the columnar protrusions 401 or even almost eliminate them. When dealing with interlayer dielectric layers 400 of different materials, thicknesses, or processing environments, this disclosure can adopt either wet etching or photolithography and dry etching processes depending on the actual situation.

[0029] like Figure 5As shown, after the above multi-step etching or photolithography and etching combination process, the interlayer dielectric layer 400 also needs to be planarized, that is, it also needs to be chemical-mechanical polishing (CMP) to make the upper surface of the interlayer dielectric layer 400 flush; finally, the planarization effect is achieved, so that the step height at different positions on the upper surface of the device is the same or the difference is small, thereby eliminating the step height difference at different positions on the device while effectively avoiding damage to the upper film to be retained.

[0030] The intensity of chemical mechanical polishing (CMP) can be determined based on the current step height and the thickness of the interlayer dielectric layer 400 to be retained, which will not be elaborated further in this embodiment. Clearly, the solution provided in this disclosure allows the CMP equipment to achieve planarization of the upper surface of the interlayer dielectric layer 400 while operating at a lower intensity. Therefore, this disclosure can eliminate step height differences while minimizing damage to the upper film. Compared to CMP equipment that must operate at high intensity, this disclosure can certainly provide better protection for the interlayer dielectric layer to be retained while achieving planarization of the upper surface of the interlayer dielectric layer.

[0031] The improved technical solution provided in this disclosure can effectively avoid the problem of upper film rupture caused by reducing the step height difference at different positions of the device. It has the advantages of simple process, easy implementation and can greatly improve the yield of semiconductor devices.

[0032] This disclosure applies to fields such as memory semiconductors. It is evident that one or more embodiments of this disclosure can also provide a dynamic random access memory (DRAM), which may include a semiconductor device formed by any embodiment of this disclosure, which may have a buried channel array transistor (BCAT).

[0033] One or more embodiments of this disclosure can also provide an electronic device that includes a dynamic random access memory (DRAM) provided in any embodiment of this disclosure. The electronic device includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0034] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0035] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide semiconductor substrates; A capacitor structure is formed over the semiconductor substrate; An interlayer dielectric layer is formed above the capacitor structure; The interlayer dielectric layer is subjected to a first treatment to form multiple columnar protrusions on the interlayer dielectric layer; The interlayer dielectric layer is subjected to a second treatment to reduce the height of the columnar protrusions; The interlayer dielectric layer is subjected to chemical mechanical polishing to make the upper surface of the interlayer dielectric layer flush; The first and second processes are used to weaken the connection strength between the portion to be removed and the portion to be retained on the interlayer dielectric layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of performing the first treatment on the interlayer dielectric layer includes: The interlayer dielectric layer is etched to form the plurality of columnar protrusions by etching a plurality of grooves on the interlayer dielectric layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Each groove is located directly above the capacitor structure.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, characterized in that, The interlayer dielectric layer is etched using dry etching.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of performing a second treatment on the interlayer dielectric layer includes: The columnar protrusions are removed by etching, and the thickness of the interlayer dielectric layer is reduced.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The columnar protrusions are etched using a wet etching method.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The wet etching process includes: A BOE-based solution is filled between adjacent columnar protrusions to wet-etch the columnar protrusions using the BOE-based solution.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of performing a second treatment on the interlayer dielectric layer includes: The columnar protrusions are subjected to photolithography and dry etching according to the set pattern.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming the interlayer dielectric layer, the following is also included: A protective layer is formed on the capacitor structure.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The interlayer dielectric layer is silicon oxide.

Images