Memory structure and method for forming the same

Abstract

A memory structure and method for forming the same, wherein the memory structure comprises: a substrate; two separate floating gate structures located on the substrate, a first opening defined between the two floating gate structures, the floating gate structure comprising a first floating gate portion and a second floating gate portion located on the first floating gate portion, the first opening exposing the sidewalls of the first floating gate portion and the sidewalls of the second floating gate portion, with the sidewalls of the first floating gate portion being recessed relative to the sidewalls of the second floating gate portion; a control gate structure located on each of the floating gate structures, a second opening defined between the two control gate structures; and a word line structure located within the first and second openings. Because the second floating gate portion is staggered relative to the first floating gate portion, a subsequently formed word line structure, when wrapping around the sidewalls of the floating gate structure, forms three erase sites between the second floating gate portion and the floating gate portion, thereby improving the erase performance of the memory structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] NOR flash memory, developed based on Intel's ETOX structure, is a non-volatile memory that retains stored data even after the chip loses power. NOR flash memory is a voltage-controlled device that uses hot electron injection to write data and tunneling to erase data. Its notable feature is its high random read speed. As a non-volatile memory, NOR flash memory offers advantages such as non-volatility, high device density, low power consumption, and electrical rewritability. It is widely used in portable electronic products such as mobile phones, digital cameras, and smart cards.

[0003] The structure of a Flash memory cell is similar to that of a MOS device, with a floating gate and dielectric layer used to store charge. The access of electrons to and from the floating gate causes the device threshold voltage to change, thereby indicating the state of the Flash memory cell. The NorFlash array is connected together by horizontal gates, called word lines. The drains are connected to vertical metal strips, called bit lines, through contact holes. The sources of two adjacent devices are connected together to form a horizontal source line.

[0004] However, existing Nor Flash devices still have many problems during their formation. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a forming method thereof, so as to improve the erasing performance of the memory structure.

[0006] To solve the above problems, the present invention provides a memory structure, comprising: a substrate, the substrate including a memory cell region; two separate floating gate structures located on the memory cell region, a first opening being provided between the two floating gate structures, the floating gate structure including a first floating gate portion, and a second floating gate portion located on the first floating gate portion, the first opening exposing the sidewalls of the first floating gate portion and the sidewalls of the second floating gate portion, and the sidewalls of the first floating gate portion being recessed relative to the sidewalls of the second floating gate portion; a control gate structure located on each of the floating gate structures, a second opening being provided between the two control gate structures, the second opening exposing the first opening; and a word line structure located within the first opening and the second opening.

[0007] Optionally, an overlapping area of ​​the second floating gate portion and the first floating gate portion accounts for 80% to 100% of the second floating gate portion.

[0008] Optionally, the control gate structure covers a top surface of the second floating gate portion and an exposed top surface of the first floating gate portion.

[0009] Optionally, the floating gate structure includes: a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on a sidewall of the floating gate layer.

[0010] Optionally, the control gate structure includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on a sidewall of the control gate layer.

[0011] Optionally, the first gate dielectric layer and the second gate dielectric layer are a single-layer structure or a multi-layer structure.

[0012] Optionally, when the first gate dielectric layer and the second gate dielectric layer are a multi-layer structure, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0013] Optionally, the material of the word line structure is a semiconductor material, and the semiconductor material includes: polysilicon.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a memory structure, comprising: providing a substrate, the substrate including a memory cell area; forming two separate floating gate structures on the memory cell area, with a first opening between the two floating gate structures, the floating gate structure including a first floating gate portion, and a second floating gate portion located on the first floating gate portion, the first opening exposing the sidewalls of the first floating gate portion and the sidewalls of the second floating gate portion, and the sidewalls of the first floating gate portion are recessed relative to the sidewalls of the second floating gate portion; forming a control gate structure on each of the floating gate structures, with a second opening between the two control gate structures, the second opening exposing the first opening; and forming a word line structure in the first opening and the second opening.

[0015] Optionally, an overlapping area of ​​the second floating gate portion and the first floating gate portion accounts for 80% to 100% of the second floating gate portion.

[0016] Optionally, the control gate structure covers a top surface of the second floating gate portion and an exposed top surface of the first floating gate portion.

[0017] Optionally, the floating gate structure includes: a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on a sidewall of the floating gate layer.

[0018] Optionally, the control gate structure includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on a sidewall of the control gate layer.

[0019] Optionally, the method for forming the two floating gate structures and the control gate structure located on each of the floating gate structures includes: forming a sacrificial layer on the substrate; forming a floating gate material layer on the substrate, the floating gate material layer covering the sidewalls and top surface of the sacrificial layer; forming a control gate material layer on the floating gate material layer; forming a patterned layer on the control gate material layer, the patterned layer exposing a portion of the top surface of the control gate material layer; using a first etching process to etch the control gate material layer using the patterned layer as a mask until the top surface of the floating gate material layer is exposed, thereby forming two initial control gate structures, with an initial second opening between the two initial control gate structures; and exposing the control gate material layer at the initial second opening. The second gate dielectric layer is formed on the sidewall of the initial control gate structure to form two control gate structures, and the initial second opening is formed into the second opening; after the control gate structure is formed, a second etching process is adopted to etch the floating gate material layer with the patterned layer as a mask until the top surface of the sacrificial layer is exposed, thereby forming two initial floating gate structures; after the initial storage gate structure is formed, the sacrificial layer is removed to form an initial first opening between the two initial floating gate structures; after the sacrificial layer is removed, the second tunneling oxide layer is formed on the sidewall of the initial floating gate structure exposed by the initial first opening to form two floating gate structures, and the initial first opening is formed into the first opening.

[0020] Optionally, the first gate dielectric layer and the second gate dielectric layer are a single-layer structure or a multi-layer structure.

[0021] Optionally, when the first gate dielectric layer and the second gate dielectric layer are a multi-layer structure, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0022] Optionally, the material of the sacrificial layer is different from the material of the floating gate structure; the material of the sacrificial layer includes: silicon nitride.

[0023] Optionally, the process of removing the sacrificial layer includes: a wet etching process.

[0024] Optionally, the material of the word line structure is a semiconductor material, and the semiconductor material includes: polysilicon.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] The memory structure of the technical solution of the present invention includes: two separate floating gate structures located above the memory cell region, with a first opening defined between the two floating gate structures. The floating gate structure includes a first floating gate portion and a second floating gate portion located above the first floating gate portion. The first opening exposes the sidewalls of the first floating gate portion and the second floating gate portion, and the sidewalls of the first floating gate portion are recessed relative to the sidewalls of the second floating gate portion. Because the second floating gate portion is staggered relative to the first floating gate portion, a subsequently formed word line structure, when wrapping around the sidewalls of the floating gate structure, forms three erase sites between the second floating gate portion and the word line structure, thereby improving the erase performance of the memory structure.

[0027] In the method for forming a memory structure according to the technical solution of the present invention, two separate floating gate structures are formed on the memory cell region, with a first opening defined between the two floating gate structures. The floating gate structure includes a first floating gate portion and a second floating gate portion located above the first floating gate portion. The first opening exposes the sidewalls of the first and second floating gate portions, and the sidewalls of the first floating gate portion are recessed relative to the sidewalls of the second floating gate portion. Because the second floating gate portion is staggered relative to the first floating gate portion, a subsequently formed word line structure, when wrapping around the sidewalls of the floating gate structure, forms three erase sites between the second floating gate portion and the word line structure, thereby improving the erase performance of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of each step of a method for forming a memory structure;

[0029] Figures 2 to 10 It is a schematic structural diagram of each step of the memory structure and its formation method in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, existing Nor Flash devices still have many problems during their formation, which will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 The present invention is a schematic structural diagram of each step of a method for forming a memory structure.

[0032] Please refer to Figure 1, providing a substrate 100, the substrate 100 including a memory cell region; forming two separate floating gate structures 101 on the memory cell region, with a first opening (not marked) between the two floating gate structures 101; forming a control gate structure 102 on each of the floating gate structures 101, with a second opening (not marked) between the two control gate structures 102, the second opening exposing the first opening; and forming a word line structure 103 in the first opening and the second opening.

[0033] The thermal erasing mechanism of the flash memory is achieved by applying high voltage to the word line structure 103 in a tunneling (Fowler Nordheim, FN) manner. When the tip of the floating gate structure 101 is sharper, the electric field is larger, the barrier width is smaller, the electrons are more likely to tunnel, and the erasing performance of the flash memory is better.

[0034] In this embodiment, the floating gate structure 101 is a single-layer flat structure, and there is only one erase site (i.e., a tip, such as Figure 1 During the manufacturing process of the memory gate structure, multiple oxidation and heat treatments are performed, which can easily cause the erase site to be oxidized into an arc shape, resulting in a blunt discharge angle of the floating gate structure. This can easily lead to unstable erase performance of the memory structure due to fluctuations in other processes.

[0035] On this basis, the present invention provides a memory structure and a method for forming the same, wherein the floating gate structure includes a first floating gate portion and a second floating gate portion, and the second floating gate portion is staggered and stacked relative to the first floating gate portion, so that when the subsequently formed word line structure covers the side wall of the floating gate structure, three erasure sites will be formed between the second floating gate portion to improve the erasure performance of the memory structure.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 10 It is a schematic structural diagram of each step of the memory structure and its formation method in an embodiment of the present invention.

[0038] Please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 includes a memory cell area.

[0039] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0040] In this embodiment, after providing the substrate 200, it also includes: forming two separate floating gate structures on the memory cell area, with a first opening between the two floating gate structures, the floating gate structure including a first floating gate portion, and a second floating gate portion located on the first floating gate portion, the first opening exposing the sidewalls of the first floating gate portion and the sidewalls of the second floating gate portion, and the sidewalls of the first floating gate portion are recessed relative to the sidewalls of the second floating gate portion; forming a control gate structure on each of the floating gate structures, with a second opening between the two control gate structures, and the second opening exposing the first opening.

[0041] In this embodiment, the floating gate structure includes: a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on the sidewalls of the floating gate layer; the control gate structure includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on the sidewalls of the control gate layer. For the specific formation process of the floating gate structure and the control gate structure, please refer to Figures 3 to 9 .

[0042] Please refer to Figure 3 , a sacrificial layer 201 is formed on the substrate 200 .

[0043] In this embodiment, the method for forming the sacrificial layer 201 includes: forming a sacrificial material layer (not shown) on the substrate 200 ; and patterning the sacrificial material layer to form a plurality of sacrificial layers 201 .

[0044] In this embodiment, the material of the sacrificial layer 201 is different from the material of the floating gate structure. Specifically, the material of the sacrificial layer 201 is silicon nitride.

[0045] In this embodiment, before forming the sacrificial layer 201 , a coupling oxide layer 202 is formed on the substrate 200 .

[0046] Please refer to Figure 4 , a floating gate material layer 203 is formed on the substrate 200 , and the floating gate material layer 203 covers the sidewalls and top surface of the sacrificial layer 201 .

[0047] In this embodiment, the floating gate material layer 203 is formed by an atomic layer deposition process.

[0048] Please continue to refer to Figure 4 , forming a control gate material layer 204 on the floating gate material layer 203 .

[0049] In this embodiment, the control gate material layer 204 is formed by an atomic layer deposition process.

[0050] In this embodiment, the floating gate material layer 203 and the control gate material layer 204 are used to form the floating gate structure and the control gate structure through subsequent patterning.

[0051] Please refer to Figure 5 , forming a patterned layer 205 on the control gate material layer 204 , wherein the patterned layer 205 exposes a portion of the top surface of the control gate material layer 204 .

[0052] In this embodiment, the patterned layer 205 includes: a first mask layer (not labeled), a second mask layer (not labeled) located on the first mask layer, the first mask layer and the second mask layer have patterned openings (not labeled), the patterned openings expose a portion of the top surface of the control gate material layer 204, and a sidewall layer (not labeled) located on the sidewalls of the patterned openings.

[0053] In this embodiment, the material of the first mask layer is silicon nitride, the material of the second mask layer is silicon oxide, and the material of the sidewall spacer is silicon oxide.

[0054] Please refer to Figure 6 , using a first etching process, the control gate material layer 204 is etched with the patterned layer 205 as a mask until the top surface of the floating gate material layer 203 is exposed, forming two initial control gate structures (not marked), with an initial second opening (not marked) between the two initial control gate structures; forming the second gate dielectric layer (not marked) on the sidewalls of the initial control gate structure exposed by the initial second opening to form the two control gate structures 206, and forming a second opening 207 based on the initial second opening.

[0055] In this embodiment, the first gate dielectric layer and the second gate dielectric layer are multi-layer structures. Specifically, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer (not labeled), a silicon nitride layer (not labeled) located on the first silicon oxide layer, and a second silicon oxide layer (not labeled) located on the silicon nitride layer.

[0056] The first silicon oxide layer and the second silicon oxide layer can be well bonded to the substrate, and the silicon nitride layer is located in the middle, which can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0057] In other embodiments, the first gate dielectric layer and the second gate dielectric layer may also be a single-layer structure.

[0058] In this embodiment, the first etching process adopts a wet etching process; in other embodiments, the first etching process may also adopt a dry etching process.

[0059] Please refer to Figure 7 After forming the control gate structure 206 , a second etching process is performed to etch the floating gate material layer 203 using the patterned layer 205 as a mask until the top surface of the sacrificial layer 201 is exposed, thereby forming two initial floating gate structures 208 .

[0060] In this embodiment, the second etching process adopts a wet etching process; in other embodiments, the second etching process may also adopt a dry etching process.

[0061] Please refer to Figure 8 After forming the initial storage gate structure 208 , the sacrificial layer 201 is removed, and an initial first opening 209 is formed between the two initial floating gate structures 208 .

[0062] In this embodiment, the process of removing the sacrificial layer 201 adopts a wet etching process.

[0063] Please refer to Figure 9 After removing the sacrificial layer 201 , a second tunneling oxide layer (not shown) is formed on the sidewalls of the initial floating gate structure 208 exposed by the initial first opening 209 to form two floating gate structures 210 , and a first opening 211 is formed based on the initial first opening 209 .

[0064] In this embodiment, the floating gate structure 210 includes a first floating gate portion 210a (eg, Figure 10 ), and a second floating gate portion 210b located on the first floating gate portion 210a (as shown Figure 10 As shown, the first opening 211 exposes the sidewalls of the first floating gate portion 210a and the sidewalls of the second floating gate portion 210b, and the sidewalls of the first floating gate portion 210a are recessed relative to the sidewalls of the second floating gate portion 210b. Because the second floating gate portion 210b is staggered relative to the first floating gate portion 210a, the subsequently formed word line structure, when wrapping around the sidewalls of the floating gate structure 210, forms three erase sites between the second floating gate portion 210b and the word line structure, thereby improving the erase performance of the memory structure.

[0065] In this embodiment, the overlapping area of ​​the second floating gate portion 210 b and the first floating gate portion 210 a accounts for 80% to 100% of the second floating gate portion 210 b .

[0066] In this embodiment, the control gate structure 206 covers the top surface of the second floating gate portion 210 b and the exposed top surface of the first floating gate portion 210 a .

[0067] In this embodiment, the second tunneling oxide layer is also formed in the initial first opening 209 (eg Figure 8 shown) bottom surface.

[0068] In other embodiments, the first tunneling oxide layer and the coupling oxide layer exposed by the initial first opening may be removed before forming the second tunneling oxide layer. This is because the first tunneling oxide layer and the coupling oxide layer exposed by the initial first opening may be damaged to a certain extent during the removal of the sacrificial layer. To improve the reliability of the ultimately formed device structure, the first tunneling oxide layer and the coupling oxide layer exposed by the initial first opening may be removed before forming the second tunneling oxide layer.

[0069] Please refer to Figure 10 , a word line structure 212 is formed in the first opening 211 and the second opening 207 .

[0070] In this embodiment, the method for forming the word line structure 212 includes: forming a word line material layer (not shown) in the first opening 211 and the second opening 207, and on the patterned layer 205; and planarizing the word line material layer until the top surface of the patterned layer 205 is exposed to form the word line structure 212.

[0071] In this embodiment, the word line structure 212 is made of semiconductor material, specifically, polysilicon.

[0072] In this embodiment, the planarization process adopts a chemical mechanical mask process.

[0073] Correspondingly, an embodiment of the present invention further provides a memory structure, please continue to refer to Figure 10, comprising: a substrate 200, the substrate 200 including a memory cell region; two separate floating gate structures 210 located on the memory cell region, a first opening 211 being provided between the two floating gate structures 210, the floating gate structure 210 including a first floating gate portion 210a and a second floating gate portion 210b located on the first floating gate portion 210a, the first opening 211 exposing sidewalls of the first floating gate portion 210a and sidewalls of the second floating gate portion 210b, and the sidewalls of the first floating gate portion 210a are recessed relative to the sidewalls of the second floating gate portion 210b; a control gate structure 206 located on each of the floating gate structures 210, a second opening 207 being provided between the two control gate structures 206, the second opening 207 exposing the first opening 211; and a word line structure located within the first opening 211 and the second opening 207.

[0074] In this embodiment, the floating gate structure 210 includes a first floating gate portion 210a and a second floating gate portion 210b located above the first floating gate portion 210a. The first opening 211 exposes the sidewalls of the first floating gate portion 210a and the sidewalls of the second floating gate portion 210b. The sidewalls of the first floating gate portion 210a are recessed relative to the sidewalls of the second floating gate portion 210b. Because the second floating gate portion 210b is staggered relative to the first floating gate portion 210a, the word line structure 212 formed when wrapping around the sidewalls of the floating gate structure 210 forms three erase sites between the second floating gate portion 210b and the word line structure 212, thereby improving the erase performance of the memory structure.

[0075] In this embodiment, the overlapping area of ​​the second floating gate portion 210 b and the first floating gate portion 210 a accounts for 80% to 100% of the second floating gate portion 210 b .

[0076] In this embodiment, the floating gate structure 210 includes a first tunneling oxide layer (not labeled), a floating gate layer (not labeled) located on the first tunneling oxide layer, and a second tunneling oxide layer (not labeled) located on the sidewall of the floating gate layer.

[0077] In this embodiment, the control gate structure 206 includes a first gate dielectric layer (not labeled), a control gate layer (not labeled) located on the first gate dielectric layer, and a second gate dielectric layer (not labeled) located on the sidewall of the control gate layer.

[0078] In this embodiment, the first gate dielectric layer and the second gate dielectric layer are multi-layer structures. Specifically, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer (not labeled), a silicon nitride layer (not labeled) located on the first silicon oxide layer, and a second silicon oxide layer (not labeled) located on the silicon nitride layer.

[0079] In other embodiments, the first gate dielectric layer and the second gate dielectric layer may also be a single-layer structure.

[0080] In this embodiment, the material of the word line structure 212 is a semiconductor material. Specifically, the semiconductor material is polysilicon.

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: a substrate comprising a memory cell region; Two separate floating gate structures located on the memory cell region, with a first opening defined between the two floating gate structures, the floating gate structure comprising a first floating gate portion and a second floating gate portion located on the first floating gate portion, the first opening exposing sidewalls of the first floating gate portion and sidewalls of the second floating gate portion, and the sidewalls of the first floating gate portion being recessed relative to the sidewalls of the second floating gate portion; a control gate structure located on each of the floating gate structures, wherein a second opening is defined between the two control gate structures, and the second opening exposes the first opening; A word line structure is located within the first opening and the second opening.

2. The memory structure according to claim 1, wherein: An overlapping area of ​​the second floating gate portion and the first floating gate portion accounts for 80% to 100% of the second floating gate portion.

3. The memory structure according to claim 1, wherein: The control gate structure covers a top surface of the second floating gate portion and an exposed top surface of the first floating gate portion.

4. The memory structure according to claim 1, wherein: The floating gate structure includes a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on a sidewall of the floating gate layer.

5. The memory structure according to claim 1, wherein: The control gate structure includes a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on a sidewall of the control gate layer.

6. The memory structure according to claim 5, wherein: The first gate dielectric layer and the second gate dielectric layer are single-layer structures or multi-layer structures.

7. The memory structure according to claim 6, wherein: When the first gate dielectric layer and the second gate dielectric layer are multi-layer structures, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

8. The memory structure according to claim 1, wherein: The word line structure is made of a semiconductor material, and the semiconductor material includes polysilicon.

9. A method for forming a memory structure, characterized in that: include: providing a substrate, the substrate comprising a memory cell region; forming two separate floating gate structures on the memory cell region, with a first opening defined between the two floating gate structures, the floating gate structure comprising a first floating gate portion and a second floating gate portion located on the first floating gate portion, the first opening exposing sidewalls of the first floating gate portion and sidewalls of the second floating gate portion, and the sidewalls of the first floating gate portion being recessed relative to the sidewalls of the second floating gate portion; forming a control gate structure on each of the floating gate structures, with a second opening between the two control gate structures, wherein the second opening exposes the first opening; A word line structure is formed in the first opening and the second opening.

10. The method for forming a memory structure according to claim 9, wherein: An overlapping area of ​​the second floating gate portion and the first floating gate portion accounts for 80% to 100% of the second floating gate portion.

11. The method for forming a memory structure according to claim 9, wherein: The control gate structure covers a top surface of the second floating gate portion and an exposed top surface of the first floating gate portion.

12. The method for forming a memory structure according to claim 9, wherein: The floating gate structure includes a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on a sidewall of the floating gate layer.

13. The method for forming a memory structure according to claim 12, wherein: The control gate structure includes a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on a sidewall of the control gate layer.

14. The method for forming a memory structure according to claim 13, wherein: The method for forming the two floating gate structures and the control gate structure located on each of the floating gate structures comprises: forming a sacrificial layer on the substrate; forming a floating gate material layer on the substrate, wherein the floating gate material layer covers the sidewalls and top surface of the sacrificial layer; forming a control gate material layer on the floating gate material layer; forming a patterned layer on the control gate material layer, wherein the patterned layer exposes a portion of the top surface of the control gate material layer; using a first etching process to etch the control gate material layer using the patterned layer as a mask until the top surface of the floating gate material layer is exposed, thereby forming two initial control gate structures, wherein an initial second opening is provided between the two initial control gate structures; and the initial second opening is exposed. The second gate dielectric layer is formed on the sidewall of the initial control gate structure to form two control gate structures, and the initial second opening is formed into the second opening; after the control gate structure is formed, a second etching process is adopted to etch the floating gate material layer with the patterned layer as a mask until the top surface of the sacrificial layer is exposed to form two initial floating gate structures; after the initial floating gate structure is formed, the sacrificial layer is removed to form an initial first opening between the two initial floating gate structures; after the sacrificial layer is removed, the second tunneling oxide layer is formed on the sidewall of the initial floating gate structure exposed by the initial first opening to form two floating gate structures, and the initial first opening is formed into the first opening.

15. The method for forming a memory structure according to claim 13, wherein: The first gate dielectric layer and the second gate dielectric layer are single-layer structures or multi-layer structures.

16. The method for forming a memory structure according to claim 15, wherein: When the first gate dielectric layer and the second gate dielectric layer are multi-layer structures, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

17. The method for forming a memory structure according to claim 14, wherein: The material of the sacrificial layer is different from the material of the floating gate structure; the material of the sacrificial layer includes silicon nitride.

18. The method for forming a memory structure according to claim 14, wherein: The process of removing the sacrificial layer includes: a wet etching process.

19. The method for forming a memory structure according to claim 9, wherein: The word line structure is made of a semiconductor material, and the semiconductor material includes polysilicon.

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