Tft structure of multiplexing circuit, display panel and display device

Abstract

The application relates to a TFT structure of a multiplexing circuit, a display panel and a display device. The TFT structure of the multiplexing circuit comprises a first active layer and a first metal layer, the first metal layer is sequentially arranged with the first active layer along the direction of backlight light; a first backlight channel is arranged on the first metal layer, and the backlight light passes through the first backlight channel to irradiate on the first active layer. In the application, the first backlight channel is arranged on the first metal layer, so that the backlight light can irradiate on the first active layer through the first backlight channel, the increase of carriers on the first active layer caused by the irradiation of the backlight light on the first active layer leads to the Vth negative bias of the TFT structure of the multiplexing circuit; the Vth negative bias of the TFT structure of the multiplexing circuit partially offsets the Vth positive bias of the TFT structure of the multiplexing circuit caused by short-time multiple opening, so that the driving performance of the multiplexing circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display devices, in particular to a TFT structure of a multiplexing circuit, a display panel and a display device. BACKGROUND

[0002] In the manufacturing process of a display panel, IC chips account for a large proportion in the cost. In order to reduce the number of IC chips and thus reduce the production cost, the signal of the IC chip to Gate or Data on the display panel is often designed by using a Demux (multiplexing) circuit. As shown in the prior art Demux circuit, Figure 4 the output signal D1 of the IC chip (Data signal in the middle) passes through signal output wires and then passes through switches T1, T2 and T3, and is input to the S1 column, S5 column and S3 column of pixels. Figure 5

[0003] Taking a 1920*1080 display panel as an example, the display panel has 1920*3 columns of pixels, and one output signal of the IC chip can be input to three columns of pixels, so 1920*3 / 3=1920 IC chip output signals are needed on the display panel; and the number of times of turning on the multiplexing circuit per frame is 1920. For the TFT structure at the position of the multiplexing circuit on the display panel, the TFT structure is turned on for a short time and multiple times, and is subjected to positive bias current stress stimulation (PCBTS), the TFT structure at the position of the multiplexing circuit is seriously biased, the Ion (on-state current) under the same voltage is reduced, the driving function of the multiplexing circuit is affected, the IC chip output signal cannot be transmitted to each column of pixels, and display abnormalities occur. SUMMARY

[0004] Therefore, it is necessary to provide a TFT structure of a multiplexing circuit, a display panel and a display device in view of the problem that the TFT structure at the position of the multiplexing circuit on the existing display panel is turned on for a short time and multiple times, the TFT structure at the position of the multiplexing circuit is seriously biased, and the driving function of the multiplexing circuit is affected.

[0005] In order to achieve the above-mentioned purpose, in one aspect, the embodiments of the present application provide a TFT structure of a multiplexing circuit, which comprises:

[0006] a first active layer;

[0007] a first metal layer, the first metal layer and the first active layer are sequentially arranged along the direction of backlight light; the first metal layer is provided with a first backlight passage, and the backlight light passes through the first backlight passage and irradiates on the first active layer.

[0008] Optionally, the first metal layer comprises a first metal piece and a second metal piece, the first metal piece and the second metal piece are parallel to each other, and the first backlight passage is arranged between the first metal piece and the second metal piece.​

[0009] Optionally, the first metal layer further comprises a first connecting member, the first connecting member being connected with the first metal member and the second metal member respectively.

[0010] Optionally, the first metal layer further comprises a second back light channel, the back light passing through the second back light channel to irradiate on the first active layer.

[0011] Optionally, the first metal layer further comprises a third metal member, the third metal member and the second metal member being parallel to each other, and the second back light channel being arranged between the second metal member and the third metal member.

[0012] Optionally, the TFT structure of the multiplexing circuit further comprises a second metal layer, the first metal layer, the first active layer and the second metal layer being arranged in sequence along the direction of the back light.

[0013] Optionally, the multiplexing circuit is connected with the second metal layer.

[0014] Optionally, the multiplexing circuit comprises:

[0015] a first switch, which controls the opening and closing of the circuit between the first pixel and the first output signal of the IC chip;

[0016] a second switch, which controls the opening and closing of the circuit between the first pixel and the first output signal;

[0017] a first control unit, which controls the opening and closing of the first switch;

[0018] a second control unit, which controls the opening and closing of the second switch;

[0019] When the control signal output by the first control unit is a high potential signal, the control signal output by the second control unit is a low potential signal; and when the control signal output by the first control unit is a low potential signal, the control signal output by the second control unit is a high potential signal.

[0020] On the other hand, the embodiments of the present application further provide a display panel comprising the TFT structure of the multiplexing circuit of any of the above.

[0021] On the other hand, the embodiments of the present application further provide a display device comprising the display panel of any of the above.

[0022] One of the above technical solutions has the following advantages and beneficial effects:

[0023] This application provides a TFT structure for a multiplexed circuit, a display panel, and a display device. A first backlight channel is provided on the first metal layer, so backlight light can shine through the first backlight channel onto the first active layer. The backlight light shining onto the first active layer increases the number of charge carriers on the first active layer, thereby causing the Vth of the TFT structure of the multiplexed circuit to be negatively biased. The negative bias of the Vth of the TFT structure of the multiplexed circuit partially cancels the positive bias of the Vth caused by the multiple short-term multiple turn-on of the TFT structure of the multiplexed circuit, thereby improving the driving performance of the multiplexed circuit. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of an existing display panel.

[0025] Figure 2 for Figure 1 A schematic diagram of the TFT structure of the Demux circuit on the central display panel.

[0026] Figure 3 for Figure 2 A schematic diagram of the structure of metal layer A in the TFT structure of the Demux circuit.

[0027] Figure 4 for Figure 2 A schematic diagram of the Demux circuit in the TFT structure of the Demux circuit.

[0028] Figure 5 This is a schematic diagram of the waveform of the input signal in an existing Demux circuit.

[0029] Figure 6 This is a schematic diagram of the TFT structure of the multiplexing circuit provided in the embodiments of this application.

[0030] Figure 7 for Figure 6 A schematic diagram of the first metal layer in the TFT structure of the multiplexed circuit.

[0031] Figure 8 for Figure 6 A schematic diagram of the multiplexing circuit in the TFT structure of the multiplexing circuit.

[0032] Figure 9 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0034] It is to be noted that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can be present. As used herein the terms "on", "side" and "opposite side" are used for illustrative purposes only. In addition, the ordinal numbers such as "first" and "second" used in the present application are not intended to denote any order, number or importance, but are used only to distinguish different parts.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] At present, the existing display panel structure as shown in Figure 1 The display panel includes TFT structures of GOA circuit, TFT structures of display area, TFT structures of Demux circuit and IC chip. The output signals of the IC chip include D1, D2, D3 and D4, which are input into each column of pixels of the display area through the Demux circuit, and the Gate signal output in the GOA circuit is input into each row of pixels of the display area. The existing TFT structure of Demux circuit as shown in Figure 2 The TFT structure of Demux circuit includes metal layer A 510 (M1), active layer A 520 and metal layer B 530 (M2) arranged in sequence in the backlight direction, Figure 2 The metal layer A 510 is the bottom layer, the metal layer B 530 is the top layer, and the active layer A 520 is located between the metal layer A 510 and the metal layer B 530. The metal layer A 510 inputs the Gate signal for each pixel, and the metal layer B 530 inputs the output signal of the IC chip for each pixel. The structure of the metal layer A 510 is as shown in Figure 3 The area of the metal layer A 510 is larger than that of the active layer A 520, and there is no hole in the metal layer A 510, so that the backlight cannot penetrate the metal layer A 510 to irradiate on the active layer A 520.

[0037] In the manufacturing process of the display panel, the IC chip accounts for a large proportion in the cost. In order to reduce the number of IC chips and reduce the production cost, the signal of the IC chip to Gate or Data on the display panel often adopts Demux (multiplexing) circuit design. The existing Demux circuit as shown in Figure 4 The output signal D1 of the IC chip is input into the Gate signal of the first pixel through the Demux circuit, the output signal D2 of the IC chip is input into the Gate signal of the second pixel through the Demux circuit, the output signal D3 of the IC chip is input into the Gate signal of the third pixel through the Demux circuit, and the output signal D4 of the IC chip is input into the Gate signal of the fourth pixel through the Demux circuit. Figure 5The data signal is routed through switches T1, T2, and T3 via signal output lines, and input to pixels in columns S1, S5, and S3 respectively; the control signal for switch T1 is... Figure 5 The control signal for switch T2 is the CKR signal. Figure 5 The control signal for switch T3 is the CKG signal. Figure 5 CKB signal.

[0038] Figure 4 The working principle of the existing Demux circuit in China is as follows:

[0039] Each signal is in Figure 5 At time a, the CKR signal is high, while the CKG and CKB signals are low. Switch T1 is open, and the D1 signal is high, inputting to the S1-th column pixel. If the Gate signal of the N-th row pixel is high at this time, then the pixel in the N-th row and S1-th column is charged; each signal is in... Figure 5 At time b, the CKR, CKG, and CKB signals are at low potentials, switch T1 is closed, and the pixel in column S1 maintains the high potential of the D1 signal. At this time, the Gate signal of the pixel in row N is at a high potential, so the pixel in row N and column S1 continues to charge.

[0040] Each signal is in Figure 5 At time c, the CKG signal is high, while the CKR and CKB signals are low. Switch T2 is open, and the D1 signal is high, inputting to the S5th column pixel. If the Gate signal of the Nth row pixel is high at this time, then the pixel in the Nth row and S5th column is charged; all signals are in... Figure 5 At time d, the CKR, CKG, and CKB signals are at low potentials, switch T2 is closed, and the pixel in column S5 maintains the high potential of the D1 signal. At this time, the Gate signal of the pixel in row N is at a high potential, so the pixel in column S5 of row N continues to charge.

[0041] Each signal is in Figure 5 At time e, the CKB signal is high, while the CKG and CKR signals are low. Switch T3 is open, and the D1 signal is high, inputting to the S3 column pixel. If the Gate signal of the Nth row pixel is high at this time, then the pixel in the Nth row and S3 column is charged; all signals are in... Figure 5 At time f, the CKR, CKG, and CKB signals are at low potentials, switch T3 is closed, and the pixel in column S3 maintains the high potential of the D1 signal. At this time, the Gate signal of the pixel in row N is at a high potential, so the pixel in column S3 of row N continues to charge.

[0042] As can be seen from the above, when any of the switches T1, T2, and T3 are turned on, the D1 signal is input to the column of pixels corresponding to the switches T1, T2, and T3.

[0043] Taking an existing display panel with a display panel of 1920*1080 as an example, the display panel has 1920*3 columns of pixels, and one output signal of the IC chip can be input into three columns of pixels, so 1920*3 / 3=1920 IC chip output signals are needed on the display panel; the number of times of turning on per frame of the multiplexing circuit is 1920. For the TFT structure at the multiplexing circuit of the display panel, the electrical stress received by the TFT structure due to short-time multiple turning on is positive bias current stress stimulation (PCBTS), the TFT structure at the multiplexing circuit is seriously positively biased, the Ion (on-state current) under the same voltage is reduced, the driving function of the multiplexing circuit is affected, the IC chip output signal cannot be transmitted to each column of pixels, and display abnormalities are caused.

[0044] To solve the above problems, the embodiments of the present application provide a TFT structure of a multiplexing circuit, a display panel and a display device, which will be described below with reference to the accompanying drawings. For example, please refer to Figure 6 , Figure 6 The structure diagram of the TFT structure of the multiplexing circuit provided by the embodiments of the present application is shown. The TFT structure 100 of the multiplexing circuit includes a first active layer 110 and a first metal layer 120, and the first metal layer 120 is arranged in sequence with the first active layer 110 along the direction of the backlight light. Please refer to Figure 7 , Figure 7 The structure diagram of the first metal layer 120 provided by the embodiments of the present application is shown, and the first metal layer 120 is provided with a first backlight passage 121, and the backlight light irradiates on the first active layer 110 through the first backlight passage 121.

[0045] The first metal layer 120 in the embodiments of the present application is provided with the first backlight passage 121, so that the backlight light can irradiate on the first active layer 110 through the first backlight passage 121, and the increase of the carriers on the first active layer 110 caused by the irradiation of the backlight light on the first active layer 110 causes the Vth negative bias of the TFT structure of the multiplexing circuit; the Vth negative bias of the TFT structure of the multiplexing circuit partially offsets the Vth positive bias of the TFT structure of the multiplexing circuit caused by short-time multiple turning on, thereby improving the driving performance of the multiplexing circuit.

[0046] For example, as shown in Figure 7 The first metal layer 120 in the embodiments of the present application includes a first metal piece 124 and a second metal piece 125, the first metal piece 124 and the second metal piece 125 are parallel to each other, and the first metal piece 124 and the second metal piece 125 are both rectangular. The first backlight passage 121 is arranged between the first metal piece 124 and the second metal piece 125.

[0047] For example, in the embodiments of this application, the first metal layer 120 further includes a first connector 128, which is connected to the first metal component 124 and the second metal component 125 respectively, thereby forming a first metal layer 120 with a stable connection between the first metal component 124 and the second metal component 125.

[0048] Examples such as Figure 7 As shown, in this embodiment, the first metal layer 120 is further provided with a second backlight channel 122, through which backlight illuminates the active layer. Since the first metal layer 120 has two backlight channels, the backlight light can illuminate the first active layer 110 through both channels, resulting in more backlight light illuminating the first active layer 110. This further enhances the negative bias of the TFT structure in the multiplexed circuit, thereby further improving the driving performance of the multiplexed circuit.

[0049] For example, in this embodiment of the application, the first metal layer 120 further includes a third metal element 126, which is parallel to the second metal element 125, and is also rectangular; wherein the first metal element 124, the second metal element 125, and the third metal element 126 are arranged sequentially along a first direction, as shown in the example. Figure 7 As indicated by the X-direction arrow. The aforementioned second backlight channel 122 is located between the second metal component 125 and the third metal component 126.

[0050] For example, in the embodiments of this application, the first metal layer 120 further includes a second connector 129, which is connected to the second metal piece 125 and the third metal piece 126 respectively, thereby forming a first metal layer 120 in which the second metal piece 125 and the third metal piece 126 are stably connected.

[0051] Examples such as Figure 7 As shown, in this embodiment, the first metal layer 120 is further provided with a third backlight channel 123, through which backlight shines onto the active layer. Since the first metal layer 120 has three backlight channels, the backlight light can shine onto the first active layer 110 through all three channels. This results in more backlight light shining onto the first active layer 110, further improving the negative bias of the TFT structure in the multiplexed circuit, and thus further enhancing the driving performance of the multiplexed circuit.

[0052] For example, in this embodiment of the application, the first metal layer 120 further includes a fourth metal element 127, which is parallel to the third metal element 126, and the fourth metal element 127 is also rectangular; wherein the first metal element 124, the second metal element 125, the third metal element 126, and the fourth metal element 127 are arranged sequentially along the first direction. The aforementioned fourth backlight channel is disposed between the third metal element 126 and the fourth metal element 127.

[0053] Exemplarily, the first metal layer 120 in the embodiment of the present application further comprises a third connecting piece 1210, the third connecting piece 1210 is connected with the third metal piece 126 and the fourth metal piece 127 respectively, so as to form the first metal layer 120 with the third metal piece 126 and the fourth metal piece 127 connected stably.

[0054] Exemplarily, as shown in Figure 6 , the TFT structure of the multiplexing circuit in the embodiment of the present application further comprises a second metal layer 130, the first metal layer 120 (M1), the first active layer 110 and the second metal layer 130 (M2) are arranged in sequence along the direction of the backlight light. Figure 6 The direction of the backlight light in the present application is the direction of the backlight light passing through the first metal layer 120, the first active layer 110 and the second metal layer 130 in sequence.

[0055] Exemplarily, in the TFT structure of the multiplexing circuit in the embodiment of the present application, the multiplexing circuit is connected with the second metal layer 130, so that the multiplexing circuit inputs the output signal of the IC chip into the second metal layer 130. Please refer to Figure 8 , Figure 8 The circuit schematic diagram of the multiplexing circuit in the TFT structure of the multiplexing circuit provided by the embodiment of the present application is shown in the figure, the multiplexing circuit comprises a first switch T11, a second switch T12, a third switch T13, a fourth switch T14, a fifth switch T15, a sixth switch T16, a first control unit M2 and a second control unit M1, in order to facilitate understanding, the connection mode of each circuit device is described as follows:

[0056] The output end of the first switch T11 is connected with the first output signal D1 of the IC chip, the output end of the first switch T11 is connected with the S1 column of pixels, wherein the S1 column of pixels comprises a first pixel, that is, the output end of the first switch T11 is connected with the first pixel; the control end of the first switch T11 is connected with the first output end of the first control unit M2. Then the first switch T11 can control the circuit opening and closing between the first pixel and the first output signal D1, and the first control unit M2 can control the first switch T11 to be turned on or off.

[0057] The output end of the second switch T12 is connected with the first output signal D1 of the IC chip, and the output end of the second switch T12 is connected with the S1 column of pixels, that is, the output end of the second switch T12 is also connected with the first pixel; the control end of the second switch T12 is connected with the first output end of the second control unit M1. Then the second switch T12 can control the circuit opening and closing between the first pixel and the first output signal D1, and the second control unit M1 can control the second switch T12 to open or close. Wherein, when the control signal outputted by the first output end of the first control unit M2 is a high potential signal, the control signal outputted by the first output end of the second control unit M1 is a low potential signal; when the control signal outputted by the first output end of the first control unit M2 is a low potential signal, the control signal outputted by the first output end of the second control unit M1 is a high potential signal.

[0058] The output end of the third switch T13 is connected with the first output signal D1 of the IC chip, and the output end of the third switch T13 is connected with the S5 column of pixels, wherein the S5 column of pixels includes the second pixel, that is, the output end of the third switch T13 is also connected with the second pixel; the control end of the third switch T13 is connected with the second output end of the first control unit M2. Then the third switch T13 can control the circuit opening and closing between the second pixel and the first output signal D1, and the first control unit M2 can control the third switch T13 to open or close.

[0059] The output end of the fourth switch T14 is connected with the first output signal D1 of the IC chip, and the output end of the fourth switch T14 is connected with the S5 column of pixels, that is, the output end of the fourth switch T14 is also connected with the second pixel; the control end of the fourth switch T14 is connected with the second output end of the second control unit M1. Then the fourth switch T14 can control the circuit opening and closing between the second pixel and the first output signal D1, and the second control unit M1 can control the fourth switch T14 to open or close. Wherein, when the control signal outputted by the second output end of the first control unit M2 is a high potential signal, the control signal outputted by the second output end of the second control unit M1 is a low potential signal; when the control signal outputted by the second output end of the first control unit M2 is a low potential signal, the control signal outputted by the second output end of the second control unit M1 is a high potential signal.

[0060] The output end of the fifth switch T15 is connected with the first output signal D1 of the IC chip, and the output end of the fifth switch T15 is connected with the S3 column of pixels, wherein the S3 column of pixels includes the third pixel, that is, the output end of the fifth switch T15 is also connected with the third pixel; the control end of the fifth switch T15 is connected with the third output end of the first control unit M2. Then the fifth switch T15 can control the circuit opening and closing between the third pixel and the first output signal D1, and the first control unit M2 can control the fifth switch T15 to open or close.

[0061] The output end of the sixth switch T16 is connected with the first output signal D1 of the IC chip, the output end of the sixth switch T16 is connected with the S3 column of pixels, that is, the output end of the sixth switch T16 is also connected with the third pixel; the control end of the sixth switch T16 is connected with the third output end of the second control unit M1. Then the sixth switch T16 can control the circuit opening and closing between the third pixel and the first output signal D1, and the second control unit M1 can control the sixth switch T16 to open or close. Wherein, when the control signal outputted by the third output end of the first control unit M2 is a high potential signal, the control signal outputted by the third output end of the second control unit M1 is a low potential signal; when the control signal outputted by the third output end of the first control unit M2 is a low potential signal, the control signal outputted by the third output end of the second control unit M1 is a high potential signal.

[0062] The foregoing Figure 4 In the prior multiplexing circuit shown, each column of pixels is controlled to open or close by one switch (each column of pixels is controlled to open or close by T1, T2 or T3), and the number of times of opening of the multiplexing circuit is 1920 times per frame. In the multiplexing circuit provided by the present application, each column of pixels is controlled to open or close by two switches, for example, the S1 column of pixels is controlled to open or close by the first switch T11 and the second switch T12. And the present application sets that when the control signal outputted by the first output end of the first control unit M2 is a high potential signal, the control signal outputted by the first output end of the second control unit M1 is a low potential signal; when the control signal outputted by the first output end of the first control unit M2 is a low potential signal, the control signal outputted by the first output end of the second control unit M1 is a high potential signal.

[0063] When the control signal outputted by the first output end of the first control unit M2 is a high potential signal, the first output end of the first control unit M2 controls the first switch T11 to open, at this time, the circuit between the first pixel and the first output signal D1 is in communication; at this time, the control signal outputted by the first output end of the second control unit M1 is a low potential signal, so the second switch T12 is closed. When the control signal outputted by the first output end of the second control unit M1 is a high potential signal, the first output end of the second control unit M1 controls the second switch T12 to open, at this time, the circuit between the first pixel and the first output signal D1 is in communication; at this time, the control signal outputted by the first output end of the first control unit M2 is a low potential signal, so the first switch T11 is closed (the working principles of the third switch T13, the fourth switch T14, the fifth switch T15 and the sixth switch T16 are the same as those of the first switch T11 and the second switch T12). Similarly, taking the existing 1920*1080 display panel as an example, the display panel has 1920*3 columns of pixels, and one output signal of the IC chip can be input into three columns of pixels, so 1920*3 / 3=1920 IC chip output signals are needed on the display panel. However, since the second switch T12 is opened when the first switch T11 is closed, and the first switch T11 is opened when the second switch T12 is closed, the number of times that the second metal layer 130 in the TFT structure of the multiplexing circuit is opened is 1920 / 2=960 times per frame, so the number of times that the multiplexing circuit in the embodiment of the application is opened per frame is lower, the Vth negative bias of the TFT structure at the multiplexing circuit is reduced, and the driving performance of the multiplexing circuit is further improved.

[0064] The embodiment of the application further provides a display panel, please refer to Figure 9 , Figure 9 The display panel provided by the embodiment of the application has the structure shown in the figure, and the display panel comprises the TFT structure 100 of the multiplexing circuit provided by the above embodiment. It should be noted that the display panel provided by the embodiment of the application can also comprise other circuits and devices for supporting the normal work of the display device, for example, the TFT structure 200 of the display area, the TFT structure 300 of the GOA circuit and the IC chip 400. The output signals of the IC chip are input into each column of pixels in the display area through the multiplexing circuit, and the Gate signals in the GOA circuit are input into each row of pixels in the display area.

[0065] The embodiment of the application further provides a display device, which comprises the display panel provided by the above embodiment. It should be noted that the display device provided by the embodiment of the application can also comprise other circuits and devices for supporting the normal work of the display device, and the display device can be one of a mobile phone, a tablet computer, electronic paper and an electronic photo frame.

[0066] In summary, the application provides a TFT structure of a multiplexing circuit, a display panel and a display device, wherein the first metal layer is provided with a first backlight channel, so that the backlight light can irradiate on the first active layer through the first backlight channel, the increase of carriers on the first active layer caused by the irradiation of the backlight light on the first active layer leads to the negative bias of Vth of the TFT structure of the multiplexing circuit; the positive bias of Vth of the TFT structure of the multiplexing circuit caused by the short-time multiple opening is partially offset by the negative bias of Vth of the TFT structure of the multiplexing circuit, so as to improve the driving performance of the multiplexing circuit.

[0067] The technical features of the above-described embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.

[0068] The above-described embodiments only express several implementation manners of the application, the description is more specific and detailed, however, it should not be understood as the limitation of the patent application scope. It should be pointed out that, for the ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the application, and these all belong to the protection scope of the application. Therefore, the patent protection scope of the application should be subject to the appended claims.

Claims

1. A TFT structure for a multiplexing circuit, characterized by comprising: The TFT structure of the multiplexing circuit comprises: a first active layer; a first metal layer, which is sequentially arranged with the first active layer along the direction of backlight light; the first metal layer is provided with a first backlight channel, and the backlight light passes through the first backlight channel to irradiate on the first active layer; The multiplexing circuit comprises: a first switch, which controls the opening and closing of the circuit between the first pixel and the first output signal of the IC chip; a second switch, which controls the opening and closing of the circuit between the first pixel and the first output signal; a first control unit, which controls the opening and closing of the first switch; a second control unit, which controls the opening and closing of the second switch; When the control signal output by the first control unit is a high potential signal, the control signal output by the second control unit is a low potential signal; when the control signal output by the first control unit is a low potential signal, the control signal output by the second control unit is a high potential signal.

2. The multiplexed circuit TFT structure of claim 1, wherein, The first metal layer comprises a first metal piece and a second metal piece, the first metal piece and the second metal piece are parallel to each other, and the first backlight channel is arranged between the first metal piece and the second metal piece.

3. The multiplexed circuit TFT structure of claim 2, wherein, The first metal layer further comprises a first connecting piece, and the first connecting piece is connected with the first metal piece and the second metal piece respectively.

4. The multiplexed circuit TFT structure of claim 2, wherein, The first metal layer is further provided with a second backlight channel, and the backlight light passes through the second backlight channel to irradiate on the first active layer.

5. The multiplexed circuit TFT structure of claim 4, wherein, The first metal layer further comprises a third metal piece, the third metal piece and the second metal piece are parallel to each other, and the second backlight channel is arranged between the second metal piece and the third metal piece.

6. The TFT structure of multiplexing circuit according to any one of claims 1 to 5, characterized in that, The TFT structure of the multiplexing circuit further comprises a second metal layer, and the first metal layer, the first active layer and the second metal layer are sequentially arranged along the direction of the backlight light.

7. The multiplexed circuit TFT structure of claim 6, wherein, The multiplexing circuit is connected with the second metal layer.

8. A display panel, characterized by, The TFT structure of the multiplexing circuit comprises any one of claims 1 to 7.

9. A display device, characterized by comprising: The display panel comprises the multiplexing circuit of claim 8.

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