Diode structure and preparation method thereof, semiconductor device structure and preparation method thereof

Abstract

The present invention relates to a diode structure and a method for preparing the same, as well as a semiconductor device structure and a method for preparing the same. The diode structure of the present invention comprises: a gate structure; an anode located on one side of the gate structure and spaced apart from the gate structure; a cathode located on a side of the gate structure away from the anode and spaced apart from the gate structure; and a capacitor, wherein a first plate of the capacitor is connected to the anode and a second plate of the capacitor is connected to the gate structure. During transient ESD, a high voltage change rate can induce a capacitive coupling current, which will carry a certain amount of positive transition charge to the gate structure. The positive transition charge will be stored in the gate structure and pull down the energy band in the gate structure, forcing electrons to gather under the gate structure. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the gate structure, effectively releasing the accumulated electrostatic charge caused by ESD, thereby avoiding damage to the gate structure caused by ESD and enhancing the ESD robustness of the structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a diode structure and a preparation method thereof, and a semiconductor device structure and a preparation method thereof. Background Art

[0002] In recent years, due to the advancement of technology and materials, gallium nitride-based heterojunction materials have been widely used, making it occupy an extremely important position in the field of semiconductor technology. Although GaN-based HEMTs (high electron mobility transistors) and MICs (monolithic integrated circuits) have excellent working performance, they are still faced with the threat of failure caused by ESD (electrostatic discharge) events, especially the gates of p-GaN (p-type gallium nitride) HEMTs and MOS (metal oxide semiconductor)-HEMTs are relatively fragile. In the existing technology, due to the lack of a discharge path for the gate electrode of the p-GaN HEMT, the ESD robustness of the device under gate-to-source conditions is poor. Therefore, there is still an urgent need for an ESD protection diode to reduce ESD static electricity and improve the ESD robustness of the semiconductor device structure. Summary of the Invention

[0003] To solve the above technical problems, the present invention designs a diode structure and a preparation method thereof, a semiconductor device structure and a preparation method thereof, so as to reduce ESD static electricity and improve the ESD robustness of the semiconductor device structure.

[0004] The present invention provides a diode structure, which includes:

[0005] Gate structure;

[0006] an anode, located on one side of the gate structure and spaced apart from the gate structure;

[0007] a cathode, located on a side of the gate structure away from the anode and spaced apart from the gate structure;

[0008] A capacitor, wherein a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the gate structure.

[0009] In one embodiment, the gate structure includes:

[0010] gate;

[0011] a gate contact layer, located on a surface of the gate;

[0012] The floating gate is located on a surface of the gate contact layer away from the gate and is connected to the second electrode plate.

[0013] In one embodiment, the diode structure further comprises:

[0014] substrate;

[0015] an epitaxial layer, located on the surface of the substrate;

[0016] a barrier layer located on a surface of the epitaxial layer away from the substrate; the gate structure, the anode, the cathode and the capacitor are all located on a surface of the barrier layer away from the epitaxial layer;

[0017] A first passivation layer is located on a surface of the barrier layer away from the epitaxial layer, between the anode and the cathode, and outside the gate structure;

[0018] The second passivation layer is located on a surface of the first passivation layer away from the barrier layer.

[0019] The present invention also provides a method for preparing a diode structure, the method comprising:

[0020] A gate structure, an anode, a cathode and a capacitor are formed, wherein the anode is located on one side of the gate structure and has a distance from the gate structure; the cathode is located on a side of the gate structure away from the anode and has a distance from the gate structure; the first plate of the capacitor is connected to the anode, and the second plate of the capacitor is connected to the gate structure.

[0021] In one embodiment, before forming the gate structure, the anode, the cathode and the capacitor, the method further includes:

[0022] providing a substrate;

[0023] forming an epitaxial layer on the surface of the substrate;

[0024] A barrier layer is formed on a surface of the epitaxial layer away from the substrate.

[0025] In one embodiment, the gate structure includes a gate, a gate contact layer, and a floating gate, and forming the gate structure, an anode, a cathode, and a capacitor includes:

[0026] forming the gate on a surface of the barrier layer away from the epitaxial layer;

[0027] forming a first passivation layer on a surface of the barrier layer away from the epitaxial layer, wherein the first passivation layer is located outside the gate;

[0028] forming the anode and the cathode on the barrier layer, wherein the anode and the cathode are located on opposite sides of the first passivation layer;

[0029] forming the gate contact layer on a surface of the gate away from the barrier layer, and forming the first electrode plate on a surface of the barrier layer away from the epitaxial layer, wherein the first electrode plate is connected to the anode;

[0030] forming a dielectric material layer, wherein the dielectric material layer covers the first passivation layer, the anode, the cathode, the gate contact layer, and the first electrode plate;

[0031] Etching the dielectric material layer to form a second passivation layer on a surface of the first passivation layer away from the barrier layer, and forming a capacitor dielectric layer on a surface of the first electrode away from the barrier layer;

[0032] The floating gate is formed on a surface of the gate contact layer away from the gate, and the second electrode plate is formed on a surface of the capacitor dielectric layer away from the first electrode plate. The second electrode plate is connected to the floating gate.

[0033] The present invention further provides a semiconductor device structure, which includes: a diode structure and a transistor; wherein,

[0034] The diode structure includes: a first gate structure; an anode located on one side of the first gate structure and spaced apart from the first gate structure; a cathode located on a side of the first gate structure away from the anode and spaced apart from the first gate structure; a capacitor, wherein a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the first gate structure;

[0035] The transistor includes: a second gate structure connected to the anode; a source located on one side of the second gate structure, spaced apart from the second gate structure, and connected to the cathode; and a drain located on a side of the second gate structure away from the source, spaced apart from the second gate structure.

[0036] In one embodiment, the first gate structure includes: a first gate; a first gate contact layer located on a surface of the first gate; a floating gate located on a surface of the first gate contact layer away from the first gate and connected to the second plate;

[0037] The second gate structure includes: a second gate; a second gate contact layer located on a surface of the second gate; and a metal gate layer located on a surface of the second gate contact layer away from the second gate and connected to the anode.

[0038] In one embodiment, the semiconductor device structure further includes:

[0039] substrate;

[0040] an epitaxial layer, located on the surface of the substrate;

[0041] A barrier layer is located on a surface of the epitaxial layer away from the substrate; the transistor and the diode are both located on a surface of the barrier layer away from the epitaxial layer;

[0042] a first passivation layer, located on a surface of the barrier layer away from the epitaxial layer, between the anode and the cathode, and located outside the first gate structure;

[0043] a second passivation layer, located on a surface of the first passivation layer away from the barrier layer;

[0044] a third passivation layer, located on a surface of the barrier layer away from the epitaxial layer, between the source electrode and the drain electrode, and located outside the second gate structure;

[0045] The fourth passivation layer is located on a surface of the third passivation layer away from the barrier layer.

[0046] The present invention also provides a method for preparing a semiconductor device structure, the method comprising: forming a diode structure and a transistor, wherein:

[0047] The diode structure includes: a first gate structure; an anode located on one side of the first gate structure and spaced apart from the first gate structure; a cathode located on a side of the first gate structure away from the anode and spaced apart from the first gate structure; a capacitor, wherein a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the first gate structure;

[0048] The transistor includes: a second gate structure connected to the anode; a source located on one side of the second gate structure, spaced apart from the second gate structure, and connected to the cathode; and a drain located on a side of the second gate structure away from the source, spaced apart from the second gate structure.

[0049] In one embodiment, the first gate structure includes: a first gate, a first gate contact layer, and a floating gate; the second gate structure includes: a second gate, a second gate contact layer, and a metal gate layer; before forming the diode structure and the transistor, the method further includes:

[0050] providing a substrate;

[0051] forming an epitaxial layer on the surface of the substrate;

[0052] A barrier layer is formed on a surface of the epitaxial layer away from the substrate.

[0053] In one embodiment, forming the diode structure and the transistor includes:

[0054] forming the first gate and the second gate on a surface of the barrier layer away from the epitaxial layer;

[0055] forming a first passivation layer and a third passivation layer on a surface of the barrier layer away from the epitaxial layer, wherein the first passivation layer is located around the first gate; and the third passivation layer is located around the second gate;

[0056] forming the anode, the cathode, the source, and the drain on a surface of the barrier layer away from the epitaxial layer, wherein the anode and the cathode are located on opposite sides of the first passivation layer, and the source and the drain are located on opposite sides of the third passivation layer;

[0057] forming the first gate contact layer on a surface of the first gate away from the barrier layer, forming the second gate contact layer on a surface of the second gate away from the barrier layer, and forming the first electrode plate on a surface of the barrier layer away from the epitaxial layer, wherein the first electrode plate is connected to the anode;

[0058] forming a dielectric material layer, wherein the dielectric material layer covers the first passivation layer, the third passivation layer, the source electrode, the drain electrode, the anode electrode, the cathode electrode, the first gate contact layer, the second gate contact layer, and the first electrode plate;

[0059] Etching the dielectric material layer to form a second passivation layer on a surface of the first passivation layer away from the barrier layer, forming a fourth passivation layer on a surface of the third passivation layer away from the barrier layer, and forming a capacitor dielectric layer on a surface of the first electrode away from the barrier layer;

[0060] The floating gate is formed on the surface of the first gate contact layer away from the first gate, the metal gate layer is formed on the surface of the second gate contact layer away from the second gate, and the second electrode plate is formed on the surface of the capacitor dielectric layer away from the first electrode plate, and the second electrode plate is connected to the floating gate.

[0061] The present invention has the following beneficial effects:

[0062] The diode structure of the present invention includes a gate structure; an anode located on one side of the gate structure and spaced apart from the gate structure; a cathode located on a side of the gate structure away from the anode and spaced apart from the gate structure; a capacitor, wherein a first plate of the capacitor is connected to the anode and a second plate of the capacitor is connected to the gate structure, the anode and the gate are connected via the capacitor, and the ESD threshold voltage is reduced by adjusting the capacitance of the capacitor; and during a positive transient ESD event, a high dv / dt (voltage change rate) can induce a capacitive coupling current from the anode electrode to the cathode electrode. The capacitive coupling current will carry a certain amount of Qtran (positive transition charge) to the gate structure, and the positive transition charge will be stored in the gate structure, which can pull down the energy band in the gate structure and force electrons to gather under the gate structure. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the gate structure, effectively releasing the accumulated electrostatic charge caused by the ESD event, thereby avoiding damage to the gate structure by the ESD event, thereby enhancing the ESD robustness of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 is a schematic structural diagram of a diode structure in one embodiment of the present invention;

[0064] Figure 2 is a schematic diagram of an equivalent circuit of a diode structure in one embodiment of the present invention;

[0065] Figure 3 1 is a schematic flow chart of a method for preparing a diode structure in one embodiment of the present invention;

[0066] Figure 4 1 is a schematic diagram of a process for forming a gate structure, an anode, a cathode, and a capacitor in a method for preparing a diode structure according to an embodiment of the present invention;

[0067] Figure 5 is a schematic structural diagram of a semiconductor device structure in one embodiment of the present invention;

[0068] Figure 6 is a schematic diagram of an equivalent circuit of a semiconductor device structure in one embodiment of the present invention;

[0069] Figure 7 is a schematic flow chart of a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0070] Figure 8 1 is a schematic diagram of a process for forming a diode structure and a transistor in a method for preparing a semiconductor device structure according to an embodiment of the present invention;

[0071] Figure 9is a schematic cross-sectional view of a structure obtained from steps S701 to S703 in a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0072] Figure 10 is a schematic cross-sectional view of a structure obtained in step S801 of a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0073] Figure 11 1 is a schematic cross-sectional view of a structure obtained after depositing a dielectric material layer on a barrier layer in a method for preparing a semiconductor device structure according to one embodiment of the present invention;

[0074] Figure 12 1 is a schematic cross-sectional view of a structure obtained after separating the structure to isolate the transistor and the diode in a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0075] Figure 13 is a schematic cross-sectional view of a structure obtained in step S802 of a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0076] Figure 14 is a schematic cross-sectional view of a structure obtained in step S803 of a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0077] Figure 15 is a schematic cross-sectional view of a structure obtained in step S804 of a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0078] Figure 16 is a schematic cross-sectional view of a structure obtained in step S805 of a method for preparing a semiconductor device structure in one embodiment of the present invention;

[0079] Figure 17 It is a schematic cross-sectional structural diagram of the structure obtained in step S806 of the method for preparing a semiconductor device structure in one embodiment of the present invention.

[0080] Description of reference numerals:

[0081] 1. Substrate; 2. Epitaxial layer; 3. Two-dimensional electron gas channel; 4. Barrier layer; 5. Capacitor; 51. First plate; 52. Capacitor dielectric layer; 53. Second plate; 6. Anode; 7. First passivation layer; 8. Second passivation layer; 9. First gate structure; 91. First gate; 92. First gate contact layer; 93. Floating gate; 10. Cathode; 11. Source; 12. Third passivation layer; 13. Fourth passivation layer; 14. Second gate structure; 141. Second gate; 142. Second gate contact layer; 143. Metal gate layer; 15. Drain; 16. Gate structure; 161. Gate; 162. Gate contact layer; 163. Floating gate; 17. Gate material layer; 181. Dielectric material layer; 182. Dielectric material layer. DETAILED DESCRIPTION

[0082] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0083] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0085] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0086] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0087] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementation methods.

[0088] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0089] In recent years, due to advances in technology and materials, gallium nitride-based heterojunction materials have been widely used, making it occupy an extremely important position in the field of semiconductor technology. Although GaN-based HEMTs (high electron mobility transistors) and monolithic integrated circuits (MICs) have excellent working performance, they are still faced with the threat of failure caused by ESD (electrostatic discharge) events, especially the gates of p-GaN (p-type gallium nitride) HEMTs and MOS (metal oxide semiconductor)-HEMTs are relatively fragile. In the existing technology, due to the lack of a discharge path for the gate electrode of the p-GaN HEMT, the ESD robustness of the device under gate-to-source conditions is poor. Therefore, there is still an urgent need for an ESD protection diode to reduce ESD static electricity and improve the ESD robustness of the semiconductor device structure.

[0090] ESD (electrostatic discharge) occurs when surfaces become charged due to friction, induction, conduction, and other factors. When two charged objects are within the discharge distance, a discharge occurs. Robustness, a transliteration of "robust," refers to the ability of a control system to maintain certain performance characteristics under certain parameter perturbations (structural and numerical).

[0091] To solve the above technical problems, the present invention designs a diode structure and a preparation method thereof, a semiconductor device structure and a preparation method thereof, so as to reduce ESD static electricity and improve the ESD robustness of the semiconductor device structure.

[0092] The present invention designs a diode structure, such as Figure 1 and Figure 2 As shown, the diode structure includes:

[0093] Gate structure 16;

[0094] an anode 6 , located on one side of the gate structure 16 and spaced apart from the gate structure 16 ;

[0095] The cathode 10 is located on a side of the gate structure 16 away from the anode 6 and is spaced apart from the gate structure 16;

[0096] Capacitor 5 , a first plate 51 of capacitor 5 is connected to anode 6 , and a second plate 53 of capacitor 5 is connected to gate structure 16 .

[0097] The diode structure of the present invention includes a gate structure 16; an anode 6 located on one side of the gate structure 16 and spaced apart from the gate structure 16; a cathode 10 located on a side of the gate structure 16 away from the anode 6 and spaced apart from the gate structure 16; a capacitor 5, wherein a first plate 51 of the capacitor 5 is connected to the anode 6, and a second plate 53 of the capacitor 5 is connected to the gate structure 16. The anode 6 and the gate are connected via the capacitor 5, and the capacitance value of the capacitor 5 is adjusted to reduce the ESD turn-on voltage to below 10V. And as Figure 2 As shown in the equivalent circuit diagram of the diode structure, during a forward transient ESD event, high dv / dt (rate of voltage change) can induce a capacitive coupling current from the anode 6 electrode to the cathode 10 electrode. The capacitive coupling current will carry a certain amount of Qtran (positive transition charge) to the gate structure 16, and the positive transition charge will be stored in the gate structure 16, which can pull down the energy band in the gate structure 16 and force electrons to gather under the gate structure 16. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the gate structure 16, so that the accumulated electrostatic charge caused by the ESD event is effectively released, which can avoid damage to the gate structure 16 caused by the ESD event, thereby enhancing the ESD robustness of the gate structure 16.

[0098] Specifically, the material of the anode 6 may include but is not limited to titanium aluminum nickel gold; the material of the cathode 10 may include but is not limited to titanium aluminum nickel gold; the materials of the first electrode plate 51 and the second electrode plate 53 may include but are not limited to nickel gold.

[0099] Specifically, see Figure 1 There is also a capacitor dielectric layer 52 between the first electrode plate 51 and the second electrode plate 53 for connecting the first electrode plate 51 and the second electrode plate 53. The capacitor dielectric layer 52 may include but is not limited to SiN x layer.

[0100] In one embodiment, still referring to Figure 1 The gate structure 16 includes a gate 161, a gate contact layer 162, and a floating gate 163. The gate contact layer 162 is located on the surface of the gate 161. The floating gate 163 is located on the surface of the gate contact layer 162 away from the gate 161 and is connected to the second electrode plate 53. The gate contact layer 162 and the floating gate 163 are short-circuited. Specifically, the material of the gate 161 may include p-GaN (p-type gallium nitride); the material of the gate contact layer 162 may include, but is not limited to, nickel and gold; and the material of the floating gate 163 may include, but is not limited to, nickel and gold.

[0101] In one embodiment, still referring to Figure 1The diode structure also includes a substrate 1, an epitaxial layer 2, a barrier layer 4, a first passivation layer 7 and a second passivation layer 8; the epitaxial layer 2 is located on the surface of the substrate 1; the barrier layer 4 is located on the surface of the epitaxial layer 2 away from the substrate 1; the gate structure 16, the anode 6, the cathode 10 and the capacitor 5 are all located on the surface of the barrier layer 4 away from the epitaxial layer 2; the first passivation layer 7 is located on the surface of the barrier layer 4 away from the epitaxial layer 2, between the anode 6 and the cathode 10, and outside the gate structure 16; the second passivation layer 8 is located on the surface of the first passivation layer 7 away from the barrier layer 4.

[0102] Specifically, the epitaxial layer 2 and the barrier layer 4 may both include a Group III nitride layer. For example, the epitaxial layer 2 may include but is not limited to: AlN (aluminum nitride), GaN (gallium nitride) or InN (indium nitride); the barrier layer 4 may include but is not limited to: AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride); in this embodiment, the epitaxial layer 2 is preferably a GaN layer; the barrier layer 4 is preferably an AlGaN layer.

[0103] Specifically, see Figure 1 , a two-dimensional electron gas channel 3 is generated at the interface between the epitaxial layer 2 and the barrier layer 4. 2DEG (Two-Dimensional Electron Gas): When two III-nitride semiconductor materials with different lattice constants form a heterojunction, large stress will appear due to lattice mismatch, which in turn leads to the generation of piezoelectric polarization effect. The strong polarization electric field will change the band structure of the III-nitride semiconductor heterojunction (such as AlGaN / GaN heterojunction) and cause a high concentration of electrons to be trapped in the quantum well on the GaN side of the heterojunction interface. These trapped electrons are called a two-dimensional electron gas.

[0104] Combine Figure 1 Also see Figure 2 During a forward transient ESD event, the high dv / dt (rate of voltage change) can induce a capacitively coupled current from the anode 6 electrode to the cathode 10 electrode. The capacitively coupled current will carry a certain amount of Q tran (positive transition charge) to the floating gate 163, the positive transition charge will be stored in the floating gate 163, which can pull down the energy band in the floating gate 163 region and force electrons to gather under the gate structure 16. When the gate potential generated by the positive transition charge exceeds the threshold voltage of the 2DEG channel, the 2DEG channel under the gate structure 16 will be turned on, and then a large current can pass through the 2DEG channel under the gate structure 16. Therefore, the diode of the present invention can effectively release the accumulated electrostatic charge caused by the ESD event, effectively avoiding the damage of the ESD event to the gate structure 16, thereby enhancing the ESD robustness of the gate structure 16.

[0105] Specifically, the first passivation layer 7, the second passivation layer 8 and the capacitor dielectric layer 52 may all include SiN x The thickness of the first passivation layer 7, the second passivation layer 8 and the capacitor dielectric layer 52 may include 50nm ~ 120nm; In this embodiment, the capacitor dielectric layer 52 is preferably SiN x The thickness of the layer is preferably 100 nm. In order to obtain a 10 pF capacitor 5, the effective area required for the first plate 51 and the second plate 53 of the capacitor 5 is 0.0144 mm. 2 (120 μm×120 μm), which is less than 0.1% of the total area of ​​a conventional high-current p-GaN HEMT, can effectively help integrate the required pF-level capacitor 5 into the diode structure, which is also one of the significant improvements of the present invention.

[0106] Based on the same inventive concept, the present invention also provides a method for preparing a diode structure, which includes the steps of forming a gate structure 16, an anode 6, a cathode 10 and a capacitor 5; the anode 6 is located on one side of the gate structure 16 and has a distance from the gate structure 16; the cathode 10 is located on a side of the gate structure 16 away from the anode 6 and has a distance from the gate structure 16; the first plate 51 of the capacitor 5 is connected to the anode 6, and the second plate 53 of the capacitor 5 is connected to the gate structure 16.

[0107] It should be noted that the diode structure can refer to Figures 1 to 2 And the content of the detailed description of the embodiment text.

[0108] Specifically, the material of the anode 6 may include but is not limited to titanium aluminum nickel gold; the material of the cathode 10 may include but is not limited to titanium aluminum nickel gold; the materials of the first electrode plate 51 and the second electrode plate 53 may include but are not limited to nickel gold.

[0109] In one embodiment, before forming the gate structure 16, the anode 6, the cathode 10 and the capacitor 5, the process further includes:

[0110] providing a substrate 1;

[0111] forming an epitaxial layer 2 on the surface of the substrate 1;

[0112] A barrier layer 4 is formed on a surface of the epitaxial layer 2 away from the substrate 1 .

[0113] That is Figure 3 As shown, the method for preparing the diode structure of the present invention may further include the following steps:

[0114] S301: providing a substrate 1;

[0115] S302: forming an epitaxial layer 2 on the surface of the substrate 1;

[0116] S303: forming a barrier layer 4 on a surface of the epitaxial layer 2 away from the substrate 1;

[0117] S304: Form a gate structure 16, an anode 6, a cathode 10 and a capacitor 5; the anode 6 is located on one side of the gate structure 16 and has a distance from the gate structure 16; the cathode 10 is located on a side of the gate structure 16 away from the anode 6 and has a distance from the gate structure 16; the first plate 51 of the capacitor 5 is connected to the anode 6, and the second plate 53 of the capacitor 5 is connected to the gate structure 16.

[0118] Specifically, the epitaxial layer 2 and the barrier layer 4 may both include a Group III nitride layer. For example, the epitaxial layer 2 may include but is not limited to: AlN (aluminum nitride), GaN (gallium nitride) or InN (indium nitride); the barrier layer 4 may include but is not limited to: AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride); in this embodiment, the epitaxial layer 2 is preferably a GaN layer; the barrier layer 4 is preferably an AlGaN layer.

[0119] In one embodiment, please continue to see Figure 1 The gate structure 16 includes a gate 161, a gate contact layer 162 and a floating gate 163. Figure 4 As shown, forming the gate structure 16, the anode 6, the cathode 10 and the capacitor 5 may include the following steps:

[0120] S401: forming a gate 161 on a surface of the barrier layer 4 away from the epitaxial layer 2;

[0121] S402: forming a first passivation layer 7 on a surface of the barrier layer 4 away from the epitaxial layer 2, wherein the first passivation layer 7 is located outside the gate 161;

[0122] S403: forming an anode 6 and a cathode 10 on the barrier layer 4, wherein the anode 6 and the cathode 10 are located on opposite sides of the first passivation layer 7;

[0123] S404: forming a gate contact layer 162 on a surface of the gate away from the barrier layer 4, and forming a first electrode plate 51 on a surface of the barrier layer 4 away from the epitaxial layer 2, wherein the first electrode plate 51 is connected to the anode 6;

[0124] S405: forming a dielectric material layer, the dielectric material layer covering the first passivation layer 7, the anode 6, the cathode 10, the gate contact layer 162 and the first electrode 51;

[0125] S406: etching the dielectric material layer to form a second passivation layer 8 on the surface of the first passivation layer 7 away from the barrier layer 4, and forming a capacitor dielectric layer 52 on the surface of the first electrode 51 away from the barrier layer 4;

[0126] S407 : forming a floating gate 163 on a surface of the gate contact layer 162 away from the gate 161 , and forming a second electrode 53 on a surface of the capacitor dielectric layer 52 away from the first electrode 51 , wherein the second electrode 53 is connected to the floating gate 163 .

[0127] Specifically, the gate contact layer 162 and the floating gate 163 are short-circuited, and the material of the gate 161 may include p-GaN (p-type gallium nitride); the material of the gate contact layer 162 may include but is not limited to nickel gold; the material of the floating gate 163 may include but is not limited to nickel gold.

[0128] In one embodiment, the dielectric material layer may include SiN x Layer, correspondingly, the first passivation layer 7, the second passivation layer 8 and the capacitor dielectric layer 52 can all include SiN x Specifically, the thickness of the first passivation layer 7, the second passivation layer 8 and the capacitor dielectric layer 52 may include 50nm ~ 120nm; In this embodiment, the capacitor dielectric layer 52 is preferably SiN x The thickness of the layer is preferably 100 nm. In order to obtain a 10 pF capacitor 5, the effective area required for the first plate 51 and the second plate 53 of the capacitor 5 is 0.0144 mm. 2 (120μm×120μm), which is less than 0.1% of the total area of ​​traditional high-current p-GaN HEMTs. During the preparation process, it can effectively help integrate the required pF-level capacitor 5 into the diode structure.

[0129] Based on the same inventive concept, the present invention also provides a semiconductor device structure, such as Figure 5 As shown, the semiconductor device structure includes: a diode structure and a transistor; wherein the diode structure includes: a first gate structure 9; an anode 6, located on one side of the first gate structure 9, having a spacing therebetween; a cathode 10, located on a side of the first gate structure 9 away from the anode 6, having a spacing therebetween; a capacitor 5, wherein a first plate 51 of the capacitor 5 is connected to the anode 6, and a second plate 53 of the capacitor 5 is connected to the first gate structure 9; the transistor includes: a second gate structure 14, connected to the anode 6; a source 11, located on one side of the second gate structure 14, having a spacing therebetween and connected to the cathode 10; a drain 15, located on a side of the second gate structure 14 away from the source 11, having a spacing therebetween.

[0130] The semiconductor device structure of the present invention includes a diode structure and a transistor; wherein the diode structure includes: a first gate structure 9; an anode 6, located on one side of the first gate structure 9, having a spacing with the first gate structure 9; a cathode 10, located on the side of the first gate structure 9 away from the anode 6, having a spacing with the first gate structure 9; a capacitor 5, wherein the first plate 51 of the capacitor 5 is connected to the anode 6, and the second plate 53 of the capacitor 5 is connected to the first gate structure 9; the transistor includes: a second gate structure 14, connected to the anode 6; a source 11, located on one side of the second gate structure 14, having a spacing with the second gate structure 14, and connected to the cathode 10; a drain 15, located on the side of the second gate structure 14 away from the source 11, having a spacing with the second gate structure 14, connecting the anode 6 and the first gate structure 9 through the capacitor 5, and by adjusting the capacitance 5 value of the capacitor 5, the ESD turn-on voltage is reduced to below 10V. And as Figure 6 As shown in the equivalent circuit diagram of the semiconductor device structure, during a forward transient ESD event, a high dv / dt (rate of voltage change) can induce a capacitive coupling current from the anode 6 electrode to the cathode 10 electrode. The capacitive coupling current will carry a certain amount of Qtran (positive transition charge) to the first gate structure 9 and the second gate structure 14. The positive transition charge will be stored in the first gate structure 9 and the second gate structure 14, which can pull down the energy band in the first gate structure 9 and the second gate structure 14 and force electrons to gather under the first gate structure 9 and the second gate structure 14. When the gate potential generated by the positive transition charge is reached, a large current can pass through the first gate structure 9 and the second gate structure 14, effectively releasing the accumulated electrostatic charge caused by the ESD event, thereby avoiding damage to the first gate structure 9 and the second gate structure 14 caused by the ESD event, thereby enhancing the ESD robustness of the semiconductor device structure.

[0131] Specifically, the transistor may include p-GaN HEMTs; the structure of the diode may be Figures 1 to 4 And the diode structure described in the embodiment, the diode structure can refer to Figures 1 to 4 and detailed textual description.

[0132] Specifically, the material of the anode 6 may include but is not limited to titanium aluminum nickel gold; the material of the cathode 10 may include but is not limited to titanium aluminum nickel gold; the material of the source 11 may include but is not limited to titanium aluminum nickel gold; the material of the drain 15 may include but is not limited to titanium aluminum nickel gold; the materials of the first electrode 51 and the second electrode 53 may include but are not limited to nickel gold.

[0133] In one embodiment, still referring to Figure 5The first gate structure 9 includes: a first gate 91; a first gate contact layer 92, located on the surface of the first gate 91; a floating gate 93, located on the surface of the first gate contact layer 92 away from the first gate 91, connected to the second electrode 53; a short circuit between the first gate contact layer 92 and the floating gate 93; the second gate structure 14 includes: a second gate 141; a second gate contact layer 142, located on the surface of the second gate 141; a metal gate layer 143, located on the surface of the second gate contact layer 142 away from the second gate 141, connected to the anode 6; a short circuit between the second gate contact layer 142 and the metal gate layer 143;.

[0134] Specifically, the materials of the first gate 91 and the second gate 141 may include p-GaN (p-type gallium nitride); the materials of the first gate contact layer 92 and the second gate contact layer 142 may include but are not limited to nickel gold; the materials of the floating gate 93 and the metal gate layer 143 may include but are not limited to nickel gold.

[0135] Combine Figure 5 Also see Figure 6 During a forward transient ESD event, the high dv / dt (rate of voltage change) can induce a capacitively coupled current from the anode 6 electrode to the cathode 10 electrode. The capacitively coupled current will carry a certain amount of Q tran (positive transition charge) to the floating gate 93 and the metal gate layer 143, the positive transition charge will be stored in the floating gate 93 and the metal gate layer 143, which can pull down the energy band in the floating gate 93 and the metal gate layer 143 region, and force electrons to gather under the floating gate 93 and the metal gate layer 143, when the gate potential generated by the positive transition charge exceeds the threshold voltage of the 2DEG channel, the 2DEG channel under the first gate structure 9 and the second gate structure 14 will be turned on, and then, a large current can pass through the 2DEG channel under the first gate structure 9 and the second gate structure 14, which can effectively release the accumulated electrostatic charge caused by the ESD event, and effectively avoid the damage of the ESD event to the first gate structure 9 and the second gate structure 14 in this semiconductor device structure, thereby enhancing the ESD robustness of the semiconductor device structure.

[0136] In one embodiment, still referring to Figure 5The semiconductor device structure also includes: a substrate 1; an epitaxial layer 2, located on the surface of the substrate 1; a barrier layer 4, located on the surface of the epitaxial layer 2 away from the substrate 1; the transistor and the diode are both located on the surface of the barrier layer 4 away from the epitaxial layer 2; a first passivation layer 7, located on the surface of the barrier layer 4 away from the epitaxial layer 2, located between the anode 6 and the cathode 10, and located on the periphery of the first gate structure 9; a second passivation layer 8, located on the surface of the first passivation layer 7 away from the barrier layer 4; a third passivation layer 12, located on the surface of the barrier layer 4 away from the epitaxial layer 2, located between the source 11 and the drain 15, and located on the periphery of the second gate structure 14; a fourth passivation layer 13, located on the surface of the third passivation layer 12 away from the barrier layer 4.

[0137] Specifically, the epitaxial layer 2 and the barrier layer 4 may both include a Group III nitride layer. For example, the epitaxial layer 2 may include but is not limited to: AlN (aluminum nitride), GaN (gallium nitride) or InN (indium nitride); the barrier layer 4 may include but is not limited to: AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride); in this embodiment, the epitaxial layer 2 is preferably a GaN layer; the barrier layer 4 is preferably an AlGaN layer.

[0138] In one embodiment, the dielectric material layer 182 may include SiN x Correspondingly, the first passivation layer 7, the second passivation layer 8, the third passivation layer 12, the fourth passivation layer 13 and the capacitor dielectric layer 52 may all include SiN x Specifically, the thickness of the first passivation layer 7, the second passivation layer 8, the third passivation layer 12, the fourth passivation layer 13 and the capacitor dielectric layer 52 may include 50nm to 120nm; in this embodiment, the capacitor dielectric layer 52 is preferably SiN x The thickness of the layer is preferably 100 nm. In order to obtain a 10 pF capacitor 5, the effective area required for the first plate 51 and the second plate 53 of the capacitor 5 is 0.0144 mm. 2 (120 μm×120 μm), which is less than 0.1% of the total area of ​​a conventional high-current p-GaN HEMT, and thus can effectively help combine the diode structure with the capacitor 5 and the transistor to form the semiconductor device structure of the present invention.

[0139] Based on the same inventive concept, the present invention also provides a method for preparing a semiconductor device structure, which includes: forming a diode structure and a transistor, wherein the diode structure includes: a first gate structure 9; an anode 6, located on one side of the first gate structure 9, having a spacing therebetween; a cathode 10, located on a side of the first gate structure 9 away from the anode 6, having a spacing therebetween; a capacitor 5, wherein a first electrode plate 51 of the capacitor 5 is connected to the anode 6, and a second electrode plate 53 of the capacitor 5 is connected to the first gate structure 9; the transistor includes: a second gate structure 14, connected to the anode 6; a source 11, located on one side of the second gate structure 14, having a spacing therebetween and being connected to the cathode 10; and a drain 15, located on a side of the second gate structure 14 away from the source 11, having a spacing therebetween.

[0140] It should be noted that the semiconductor device structure can refer to Figures 5 and 6 And the content of the detailed description of the embodiment text.

[0141] In particular, the transistors may include p-GaN HEMTs.

[0142] Specifically, the material of the anode 6 may include but is not limited to titanium aluminum nickel gold; the material of the cathode 10 may include but is not limited to titanium aluminum nickel gold; the material of the source 11 may include but is not limited to titanium aluminum nickel gold; the material of the drain 15 may include but is not limited to titanium aluminum nickel gold; the materials of the first electrode 51 and the second electrode 53 may include but are not limited to nickel gold.

[0143] In one embodiment, still referring to Figure 5 The first gate structure 9 includes: a first gate 91, a first gate contact layer 92 and a floating gate 93; the second gate structure 14 includes: a second gate 141, a second gate contact layer 142 and a metal gate layer 143; before forming the diode structure and the transistor, it also includes:

[0144] providing a substrate 1;

[0145] forming an epitaxial layer 2 on the surface of the substrate 1;

[0146] A barrier layer 4 is formed on a surface of the epitaxial layer 2 away from the substrate 1 .

[0147] That is Figure 7 and Figure 9 As shown, the method for preparing the diode structure of the present invention may further include the following steps:

[0148] S701: providing a substrate 1;

[0149] S702: forming an epitaxial layer 2 on the surface of the substrate 1;

[0150] S703: forming a barrier layer 4 on a surface of the epitaxial layer 2 away from the substrate 1;

[0151] S704: Forming a diode structure and a transistor, wherein the diode structure includes: a first gate structure 9; an anode 6, located on one side of the first gate structure 9, having a spacing therebetween; a cathode 10, located on a side of the first gate structure 9 away from the anode 6, having a spacing therebetween; a capacitor 5, wherein a first electrode plate 51 of the capacitor 5 is connected to the anode 6, and a second electrode plate 53 of the capacitor 5 is connected to the first gate structure 9; the transistor includes: a second gate structure 14, connected to the anode 6; a source 11, located on one side of the second gate structure 14, having a spacing therebetween and being connected to the cathode 10; a drain 15, located on a side of the second gate structure 14 away from the source 11, having a spacing therebetween.

[0152] Specifically, the epitaxial layer 2 and the barrier layer 4 may both include a Group III nitride layer. For example, the epitaxial layer 2 may include but is not limited to: AlN (aluminum nitride), GaN (gallium nitride) or InN (indium nitride); the barrier layer 4 may include but is not limited to: AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride); in this embodiment, the epitaxial layer 2 is preferably a GaN layer; the barrier layer 4 is preferably an AlGaN layer.

[0153] like Figure 8 As shown, in one embodiment, forming a diode structure and a transistor may include the following steps:

[0154] S801: forming a first gate 91 and a second gate 141 on the surface of the barrier layer 4 away from the epitaxial layer 2, such as Figure 9 and Figure 10 As shown;

[0155] S802: forming a first passivation layer 7 and a third passivation layer 12 on the surface of the barrier layer 4 away from the epitaxial layer 2, wherein the first passivation layer 7 is located outside the first gate 91; the third passivation layer 12 is located outside the second gate 141, as shown in FIG. Figure 13 As shown;

[0156] S803: An anode 6, a cathode 10, a source 11, and a drain 15 are formed on the surface of the barrier layer 4 away from the epitaxial layer 2. The anode 6 and the cathode 10 are located on opposite sides of the first passivation layer 7, and the source 11 and the drain 15 are located on opposite sides of the third passivation layer 12. Figure 14 As shown;

[0157] S804: forming a first gate contact layer 92 on the surface of the first gate 91 away from the barrier layer 4, forming a second gate contact layer 142 on the surface of the second gate 141 away from the barrier layer 4, and forming a first electrode 51 on the surface of the barrier layer 4 away from the epitaxial layer 2, the first electrode 51 being connected to the anode 6, as shown in FIG. Figure 15 As shown;

[0158] S805: forming a dielectric material layer 182, the dielectric material layer 182 covers the first passivation layer 7, the third passivation layer 12, the source 11, the drain 15, the anode 6, the cathode 10, the first gate contact layer 92, the second gate contact layer 142 and the first electrode 51, as shown in FIG. Figure 16 As shown;

[0159] S806: Etching the dielectric material layer 182 to form a second passivation layer 8 on the surface of the first passivation layer 7 away from the barrier layer 4, forming a fourth passivation layer 13 on the surface of the third passivation layer 12 away from the barrier layer 4, and forming a capacitor dielectric layer 52 on the surface of the first electrode 51 away from the barrier layer 4, as shown in FIG. Figure 17 As shown;

[0160] S807: A floating gate 93 is formed on the surface of the first gate contact layer 92 away from the first gate 91, a metal gate layer 143 is formed on the surface of the second gate contact layer 142 away from the second gate 141, and a second electrode 53 is formed on the surface of the capacitor dielectric layer 52 away from the first electrode 51, and the second electrode 53 is connected to the floating gate 93; finally, the semiconductor device structure of the present invention is formed. The semiconductor device structure is still referred to in Figure 5 .

[0161] Specifically, forming the first gate 91 and the second gate 141 on the surface of the barrier layer 4 away from the epitaxial layer 2 includes:

[0162] A gate material layer 17 is formed on the barrier layer 4. The gate material layer 17 includes a p-GaN layer. Figure 9 As shown;

[0163] The gate material layer 17 is etched to form a first gate 91 and a second gate 141. Figure 10 shown.

[0164] Specifically, S802 may include:

[0165] A dielectric material layer 181 is deposited on the barrier layer 4, such as Figure 11 As shown;

[0166] The structure is partitioned to isolate the transistors and diodes, e.g. Figure 12 As shown;

[0167] The dielectric material layer 181 is etched to form the first passivation layer 7 and the third passivation layer 12. Figure 13 shown.

[0168] In one embodiment, both dielectric material layer 181 and dielectric material layer 182 may include SiN x Correspondingly, the first passivation layer 7, the second passivation layer 8, the third passivation layer 12, the fourth passivation layer 13 and the capacitor dielectric layer 52 may all include SiN x Specifically, the thickness of the first passivation layer 7, the second passivation layer 8, the third passivation layer 12, the fourth passivation layer 13 and the capacitor dielectric layer 52 may include 50nm to 120nm; in this embodiment, the capacitor dielectric layer 52 is preferably SiN x The thickness of the layer is preferably 100 nm. In order to obtain a 10 pF capacitor 5, the effective area required for the first plate 51 and the second plate 53 of the capacitor 5 is 0.0144 mm. 2 (120 μm×120 μm), which is less than 0.1% of the total area of ​​a conventional high-current p-GaN HEMT. Therefore, during the preparation process, it can effectively help combine the diode structure with the capacitor 5 with the transistor to form the semiconductor device structure of the present invention.

[0169] Specifically, the first gate contact layer 92 and the floating gate 93 are short-circuited; the second gate contact layer 142 and the metal gate layer 143 are short-circuited; the materials of the first gate 91 and the second gate 141 can both include p-GaN (p-type gallium nitride); the materials of the first gate contact layer 92 and the second gate contact layer 142 can include but are not limited to nickel gold; the materials of the floating gate 93 and the metal gate layer 143 can include but are not limited to nickel gold.

[0170] The diode structure of the present invention includes a gate structure 16; an anode 6, located on one side of the gate structure 16 and having a distance from the gate structure 16; a cathode 10, located on a side of the gate structure 16 away from the anode 6 and having a distance from the gate structure 16; a capacitor 5, wherein the first plate 51 of the capacitor 5 is connected to the anode 6, and the second plate 53 of the capacitor 5 is connected to the gate structure 16, and the anode 6 and the gate are connected through the capacitor 5. By adjusting the capacitance value of the capacitor 5, the ESD turn-on voltage is reduced to below 10V; and during a forward transient ESD event, a high dv / dt (voltage change rate) can induce a capacitive coupling current from the anode 6 electrode to the cathode 10 electrode. The capacitive coupling current will carry a certain amount of Qtran (positive transition charge) to the gate structure 16, and the positive transition charge will be stored in the gate structure 16, which can pull down the energy band in the gate structure 16 and force electrons to gather under the gate structure 16. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the gate structure 16, so that the accumulated electrostatic charge caused by the ESD event is effectively released, which can avoid damage to the gate structure caused by the ESD event, thereby enhancing the ESD robustness of the gate structure 16. In addition, the semiconductor device structure of the present invention includes a diode structure and a transistor; wherein the diode structure includes: a first gate structure 9; an anode 6, located on one side of the first gate structure 9 and having a spacing with the first gate structure 9; a cathode 10, located on a side of the first gate structure 9 away from the anode 6 and having a spacing with the first gate structure 9; a capacitor 5, wherein the first plate 51 of the capacitor 5 is connected to the anode 6, and the second plate 53 of the capacitor 5 is connected to the first gate structure 9; the transistor includes: a second gate structure 14, connected to the anode 6; a source 11, located on one side of the second gate structure 14, having a spacing with the second gate structure 14, and connected to the cathode 10; a drain 15, located on a side of the second gate structure 14 away from the source 11 and having a spacing with the second gate structure 14; during a forward transient ESD event, a high dv / dt (voltage change rate) can induce a capacitive coupling current from the anode 6 electrode to the cathode 10 electrode. The capacitive coupling current will carry a certain amount of Qtran (positive transition charge) to the first gate structure 9 and the second gate structure 14, and the positive transition charge will be stored in the first gate structure 9 and the second gate structure 14, which can pull down the energy band in the first gate structure 9 and the second gate structure 14 and force electrons to gather under the first gate structure 9 and the second gate structure 14. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the first gate structure 9 and the second gate structure 14, so that the accumulated electrostatic charge caused by the ESD event is effectively released, which can avoid the damage of the ESD event to the first gate structure 9 and the second gate structure 14, thereby enhancing the ESD robustness of the semiconductor device structure.

[0171] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0172] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A diode structure, characterized in that: The diode structure comprises: Gate structure; an anode, located on one side of the gate structure and spaced apart from the gate structure; a cathode, located on a side of the gate structure away from the anode and spaced apart from the gate structure; a capacitor, wherein a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the gate structure; The diode structure further comprises: substrate; an epitaxial layer, located on the surface of the substrate; A barrier layer is located on a surface of the epitaxial layer away from the substrate; the gate structure, the anode, the cathode and the capacitor are all located on a surface of the barrier layer away from the epitaxial layer; A first passivation layer is located on a surface of the barrier layer away from the epitaxial layer, between the anode and the cathode, and outside the gate structure; The second passivation layer is located on a surface of the first passivation layer away from the barrier layer.

2. The diode structure according to claim 1, wherein: The gate structure includes: gate; a gate contact layer, located on a surface of the gate; The floating gate is located on a surface of the gate contact layer away from the gate and is connected to the second electrode plate.

3. A method for preparing a diode structure, characterized in that: The preparation method of the diode structure comprises: forming a gate structure, an anode, a cathode, and a capacitor, wherein the anode is located on one side of the gate structure and is spaced apart from the gate structure; the cathode is located on a side of the gate structure away from the anode and is spaced apart from the gate structure; a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the gate structure; Wherein, the diode structure further includes: substrate; an epitaxial layer, located on the surface of the substrate; a barrier layer located on a surface of the epitaxial layer away from the substrate; the gate structure, the anode, the cathode and the capacitor are all located on a surface of the barrier layer away from the epitaxial layer; The gate structure includes a gate, a gate contact layer and a floating gate, and forming the gate structure, an anode, a cathode and a capacitor includes: forming the gate on a surface of the barrier layer away from the epitaxial layer; forming a first passivation layer on a surface of the barrier layer away from the epitaxial layer, wherein the first passivation layer is located outside the gate; forming the anode and the cathode on the barrier layer, wherein the anode and the cathode are located on opposite sides of the first passivation layer; forming the gate contact layer on a surface of the gate away from the barrier layer, and forming the first electrode plate on a surface of the barrier layer away from the epitaxial layer, wherein the first electrode plate is connected to the anode; forming a dielectric material layer, wherein the dielectric material layer covers the first passivation layer, the anode, the cathode, the gate contact layer, and the first electrode plate; Etching the dielectric material layer to form a second passivation layer on a surface of the first passivation layer away from the barrier layer, and forming a capacitor dielectric layer on a surface of the first electrode away from the barrier layer; The floating gate is formed on a surface of the gate contact layer away from the gate, and the second electrode plate is formed on a surface of the capacitor dielectric layer away from the first electrode plate. The second electrode plate is connected to the floating gate.

4. The method for preparing a diode structure according to claim 3, wherein: Before forming the gate structure, the anode, the cathode and the capacitor, the method further includes: providing a substrate; forming an epitaxial layer on the surface of the substrate; A barrier layer is formed on a surface of the epitaxial layer away from the substrate.

5. A semiconductor device structure, characterized in that: The semiconductor device structure includes: a diode structure and a transistor; wherein, The diode structure includes: a first gate structure; an anode located on one side of the first gate structure and spaced apart from the first gate structure; a cathode located on a side of the first gate structure away from the anode and spaced apart from the first gate structure; a capacitor, wherein a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the first gate structure; The transistor includes: a second gate structure connected to the anode; a source located on one side of the second gate structure, spaced apart from the second gate structure, and connected to the cathode; and a drain located on a side of the second gate structure away from the source, spaced apart from the second gate structure. The semiconductor device structure further includes: substrate; an epitaxial layer, located on the surface of the substrate; A barrier layer is located on a surface of the epitaxial layer away from the substrate; the transistor and the diode are both located on a surface of the barrier layer away from the epitaxial layer; a first passivation layer, located on a surface of the barrier layer away from the epitaxial layer, between the anode and the cathode, and located outside the first gate structure; a second passivation layer, located on a surface of the first passivation layer away from the barrier layer; a third passivation layer, located on a surface of the barrier layer away from the epitaxial layer, between the source electrode and the drain electrode, and located outside the second gate structure; The fourth passivation layer is located on a surface of the third passivation layer away from the barrier layer.

6. The semiconductor device structure according to claim 5, wherein: The first gate structure includes: a first gate; a first gate contact layer located on a surface of the first gate; a floating gate located on a surface of the first gate contact layer away from the first gate and connected to the second electrode plate; The second gate structure includes: a second gate; a second gate contact layer located on a surface of the second gate; and a metal gate layer located on a surface of the second gate contact layer away from the second gate and connected to the anode.

7. A method for preparing a semiconductor device structure, characterized in that: The method for preparing the semiconductor device structure includes: forming a diode structure and a transistor, wherein: The diode structure includes: a first gate structure; an anode located on one side of the first gate structure and spaced apart from the first gate structure; a cathode located on a side of the first gate structure away from the anode and spaced apart from the first gate structure; a capacitor, wherein a first plate of the capacitor is connected to the anode, and a second plate of the capacitor is connected to the first gate structure; The transistor includes: a second gate structure connected to the anode; a source located on one side of the second gate structure, spaced apart from the second gate structure, and connected to the cathode; and a drain located on a side of the second gate structure away from the source, spaced apart from the second gate structure. The first gate structure includes: a first gate, a first gate contact layer and a floating gate; the second gate structure includes: a second gate, a second gate contact layer and a metal gate layer; before forming the diode structure and the transistor, the further comprising: providing a substrate; forming an epitaxial layer on the surface of the substrate; forming a barrier layer on a surface of the epitaxial layer away from the substrate; The forming of the diode structure and the transistor includes: forming the first gate and the second gate on a surface of the barrier layer away from the epitaxial layer; forming a first passivation layer and a third passivation layer on a surface of the barrier layer away from the epitaxial layer, wherein the first passivation layer is located around the first gate; and the third passivation layer is located around the second gate; forming the anode, the cathode, the source, and the drain on a surface of the barrier layer away from the epitaxial layer, wherein the anode and the cathode are located on opposite sides of the first passivation layer, and the source and the drain are located on opposite sides of the third passivation layer; forming the first gate contact layer on a surface of the first gate away from the barrier layer, forming the second gate contact layer on a surface of the second gate away from the barrier layer, and forming the first electrode plate on a surface of the barrier layer away from the epitaxial layer, wherein the first electrode plate is connected to the anode; forming a dielectric material layer, wherein the dielectric material layer covers the first passivation layer, the third passivation layer, the source electrode, the drain electrode, the anode electrode, the cathode electrode, the first gate contact layer, the second gate contact layer, and the first electrode plate; Etching the dielectric material layer to form a second passivation layer on a surface of the first passivation layer away from the barrier layer, forming a fourth passivation layer on a surface of the third passivation layer away from the barrier layer, and forming a capacitor dielectric layer on a surface of the first electrode away from the barrier layer; The floating gate is formed on the surface of the first gate contact layer away from the first gate, the metal gate layer is formed on the surface of the second gate contact layer away from the second gate, and the second electrode plate is formed on the surface of the capacitor dielectric layer away from the first electrode plate, and the second electrode plate is connected to the floating gate.

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