An up-sampling method and device for high times interpolation of discrete signals

Abstract

The application relates to the technical field of digital signal processing, and discloses a high-multiple interpolation upsampling method and device for discrete signals. Through the application, a scheme for realizing high-multiple interpolation upsampling in stages is provided, that is, according to an interpolation target multiple which is a composite number, the interpolation multiples of upsampling processing in at least two stages are determined, then the original discrete signal is subjected to the at least two-stage upsampling processing, and a signal upsampling result is obtained. Through the interpolation stage design, the high-multiple interpolation is task-split, the interpolation multiples of the split stages are less than or equal to the maximum interpolation value supported by an FIR filter, and then the maximum interpolation value limited problem of the single-stage FIR filter can be solved through the multi-stage cascade FIR filter mode, the high-multiple interpolation value is realized, and the passband tolerance and the stopband tolerance are met. In addition, when the FPGA is implemented, the programmable logic resources consumed can be minimized.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing technology, and specifically relates to a method and apparatus for upsampling discrete signals by high-multiplication interpolation. Background Technology

[0002] In digital signal processing engineering applications, especially in embedded systems, data acquisition and processing are required. When acquiring data, high-sampling-rate analog-to-digital converters (ADCs) are often used. In such cases, downsampling is necessary to reduce the sampling rate and decrease the MIPS (Million Instructions Per Second) of signal processing. Alternatively, when processing multiple signal sources, downsampling or upsampling is required to synchronize multiple signals to the same sampling rate.

[0003] In upsampling design, it is usually necessary to interpolate the original discrete signal (i.e., inserting I-1 zero points at equal intervals between adjacent sampling points in a known sampling sequence, where I represents the interpolation factor) and then perform low-pass filtering. Direct interpolation lengthens the period in the spectrum, introducing signals that are not originally in the same period, a phenomenon known as "mirroring." To prevent "mirroring," the interpolated signal needs to be low-pass filtered to remove signals outside the original sampling rate signal. The traditional implementation method uses a single-stage FIR (Finite Impulse Response) filter to design the low-pass filter. For example, in the Vivado design platform (an integrated design environment released by Xilinx in 2012), an FIR IP core is used for implementation.

[0004] However, since FIR IP cores do not support high-multiplication interpolation (i.e., interpolation multiples greater than 4000), they cannot be used in high-multiplication interpolation cases. For such high-multiplication interpolation, CIC filters can be used (in digital signal processing, CIC filters are the optimal type of FIR filter, consisting of one or more pairs of integrator-comb filters). This involves using a CIC IP core to implement high-multiplication interpolation and then implementing low-pass filtering within the filter itself. To implement such a filter, a suitable filter can only be designed when the bandwidth of the useful signal is very small relative to the sampling rate. This minimizes the impact on the useful signal even with significant passband attenuation. The small bandwidth of the useful signal relative to the sampling rate implies a high sampling rate. Therefore, CIC filters are suitable for use in the front-end of multi-stage signal processing as anti-aliasing filters, or as back-end anti-aliasing interpolation filters. However, to achieve the design requirements of high-multiplication interpolation upsampling, it is difficult to simultaneously meet the errors of the passband tolerance and the stopband tolerance. This is because to achieve a large stopband attenuation, the number of filter stages must be increased, which will lead to an increase in the passband tolerance.

[0005] Therefore, in specific high-multiplication upsampling interpolation designs, how to provide a clever design method to solve the problem of the maximum interpolation limit of a single-stage FIR filter, and thus achieve the goal of satisfying the passband tolerance and stopband tolerance while achieving high-multiplication interpolation (i.e., interpolation greater than 4000 times), is a topic that urgently needs to be studied by those skilled in the art. Summary of the Invention

[0006] To address the issues of existing upsampling designs not fully considering high interpolation factors, the limitations of FIR IP core interpolation factors, and the problems arising from using CIC filters for high-multiplication interpolation, this invention aims to provide a novel upsampling method and apparatus for high-multiplication interpolation of discrete signals. This method utilizes a hierarchical interpolation design to decompose the high-multiplication task, ensuring that the interpolation factor of each stage is less than or equal to the maximum interpolation value supported by the FIR filter. Furthermore, by using a multi-stage cascaded FIR filter approach, the limitation on the maximum interpolation value of a single-stage FIR filter is resolved. This achieves high-multiplication interpolation while simultaneously satisfying passband and stopband tolerances, facilitating practical application and widespread adoption.

[0007] In a first aspect, the present invention provides an upsampling method for high-magnification interpolation of discrete signals, comprising:

[0008] Based on the interpolation target multiple, which is a composite number, the interpolation multiple of each upsampling process in at least two sequential upsampling processes is determined. Each upsampling process employs a method of first interpolating the discrete signal to an integer multiple and then low-pass filtering. The interpolation multiple of each upsampling process and the interpolation target multiple satisfy the following relationship:

[0009]

[0010] In the formula, ∏ represents the operator for multiplying terms together, N represents the total number of stages of the at least two upsampling processes, and N = Roundup(log n M, 0), Roundup() represents the function for rounding up numbers, M represents the interpolation target multiple and M > n, n represents the preset threshold used to determine high-multiple interpolation, i represents a positive integer, m i This represents the interpolation factor of the i-th upsampling process in the at least two upsampling processes, and m i ≤n and m i ∈R, where R represents the set of positive integers;

[0011] The original discrete signal is subjected to at least two levels of upsampling to obtain the signal upsampling result.

[0012] Based on the above-mentioned invention, a scheme for hierarchical high-multiplication interpolation upsampling design is provided. First, based on the target interpolation multiple (which is a composite number), the interpolation multiple of each of the at least two sequential upsampling processes is determined. Then, the original discrete signal is subjected to the at least two upsampling processes to obtain the signal upsampling result. By using hierarchical interpolation design to decompose the high-multiplication interpolation task, the interpolation multiples of each decomposed stage can be less than or equal to the maximum interpolation value supported by the FIR filter. Furthermore, by using multi-stage cascaded FIR filters, the problem of the limited maximum interpolation value of a single-stage FIR filter can be solved, achieving high-multiplication interpolation while satisfying passband and stopband tolerances.

[0013] In one possible design, the interpolation factor for each upsampling stage in at least two successive upsampling stages is determined based on the target interpolation factor being a composite number, including:

[0014] The total series N is determined according to the interpolation target multiple that is a composite number, using the following formula:

[0015] N = Roundup(log n M,0)

[0016] In the formula, Roundup() represents the function of rounding up numbers, M represents the interpolation target multiple and M>n, and n represents the preset threshold used to determine high-multiple interpolation.

[0017] Based on all factors of the interpolation target multiple M, at least one factor combination is obtained, wherein each factor combination contains N different non-1 positive integers, and the N non-1 positive integers and the interpolation target multiple M satisfy the following relationship:

[0018]

[0019] In the formula, ∏ represents the operator for multiplying terms together, and i represents a positive integer. Represents the i-th value among the N non-1 positive integers and has

[0020] In the at least one factor combination, each value in the factor combination corresponding to the minimum variance value is used as the interpolation multiple of each upsampling process in the N-level upsampling process, wherein each upsampling process adopts a method of interpolating the discrete signal by integer multiples and then low-pass filtering.

[0021] Based on the above possible designs, by making the interpolation factors of the upsampling processes at each stage close, the programmable logic resources required for implementation in the FPGA can be minimized, further enhancing the characteristics of easy implementation and stable operation.

[0022] In one possible design, the interpolation factor for each upsampling stage in at least two successive upsampling stages is determined based on the target interpolation factor being a composite number, including:

[0023] The total series N is determined according to the interpolation target multiple that is a composite number, using the following formula:

[0024] N = Roundup(log n M,0)

[0025] In the formula, Roundup() represents the function of rounding up numbers, M represents the interpolation target multiple and M>n, and n represents the preset threshold used to determine high-multiple interpolation.

[0026] Based on all factors of the interpolation target multiple M, at least one factor combination is obtained, wherein each factor combination contains N different non-1 positive integers, and the N non-1 positive integers and the interpolation target multiple M satisfy the following relationship:

[0027]

[0028] In the formula, ∏ represents the operator for multiplying terms together, and i represents a positive integer. Represents the i-th value among the N non-1 positive integers and has

[0029] For each factor combination in the at least one factor combination, a simulation program that implements N-level upsampling processing is applied to simulate the discrete test signal to obtain the corresponding signal upsampling simulation results and processing time. In the N-level upsampling processing, each upsampling process adopts a method of interpolating the discrete signal by integer multiples and then low-pass filtering, and the interpolation multiple of each upsampling process is set to the corresponding value in the factor combination.

[0030] In the at least one factor combination, each value in the factor combination corresponding to the shortest processing time is used as the interpolation multiple for each level of upsampling processing.

[0031] Based on the above possible designs, the optimal interpolation factor for each level of upsampling processing can be obtained, ensuring that the required programmable logic resources are minimized when the upsampling method is applied to the internal implementation of the FPGA.

[0032] In one possible design, the original discrete signal is subjected to at least two levels of upsampling to obtain the signal upsampling result, including:

[0033] Inside a Field Programmable Gate Array (FPGA), the original discrete signal is subjected to at least two levels of upsampling to obtain the signal upsampling result.

[0034] In one possible design, the original discrete signal undergoes at least two stages of upsampling, including:

[0035] After acquiring the first discrete signal obtained by the previous upsampling process, the effective data bit width of the first discrete signal is truncated to obtain the second discrete signal. Then, the second discrete signal is subjected to the next upsampling process. The previous upsampling process and the next upsampling process constitute two adjacent upsampling processes in the at least two upsampling processes.

[0036] In one possible design, the preset threshold is 4000.

[0037] Secondly, the present invention provides an upsampling device for high-multiplication interpolation of discrete signals, comprising at least two cascaded upsampling processing modules, wherein each upsampling processing module in the at least two-stage upsampling processing modules adopts a processing method of first interpolating the discrete signal by an integer multiple and then low-pass filtering, and the interpolation multiple of each upsampling processing module satisfies the following relationship with the target interpolation multiple:

[0038]

[0039] In the formula, ∏ represents the operator for multiplying terms together, N represents the total number of stages of the at least two upsampling processing modules, and N = Roundup(log n M, 0), Roundup() represents the function for rounding up numbers, M represents the interpolation target multiple and M > n, n represents the preset threshold used to determine high-multiple interpolation, i represents a positive integer, m i This represents the interpolation multiple of the i-th upsampling processing module in the at least two upsampling processing modules, and m i ≤n and m i ∈R, where R represents the set of positive integers;

[0040] The at least two-stage upsampling processing module is used to perform at least two stages of upsampling processing on the original discrete signal to obtain the signal upsampling result.

[0041] In one possible design, the upsampling device is arranged inside a field-programmable gate array (FPGA) to perform at least two levels of upsampling on the original discrete signal to obtain the signal upsampling result.

[0042] In one possible design, the upsampling device further includes a bit width truncation processing module connected in series between two adjacent upsampling processing modules in the at least two upsampling processing modules;

[0043] The bit width truncation processing module is used to truncate the effective data bit width of the first discrete signal after acquiring the first discrete signal output by the previous upsampling processing module and which is the upsampling result of the previous signal, to obtain a second discrete signal, and then send the second discrete signal to the next upsampling processing module. The previous upsampling processing module and the next upsampling processing module constitute the two adjacent upsampling processing modules.

[0044] In one possible design, the low-pass filter units in each upsampling processing module are implemented using the IP core of a finite-length unit impulse response (FIR) filter. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating the upsampling method for high-multiplication interpolation of discrete signals provided by the present invention.

[0047] Figure 2 This is an example diagram of the frequency response of the first-stage shaping filter and the second-stage shaping filter in a two-stage upsampling process provided by the present invention. Figure 2 (a) shows the raised cosine frequency response of the first-stage shaping filter. Figure 2 (b) shows the raised cosine frequency response of the second-stage shaping filter;

[0048] Figure 3 This is an example diagram of the signal timing during the first stage of upsampling in a two-stage upsampling process, as provided by the present invention.

[0049] Figure 4 This is an example diagram of the signal timing during the second upsampling process in the two-stage upsampling process provided by the present invention.

[0050] Figure 5 This is a schematic diagram of the upsampling device for high-multiplication interpolation of discrete signals provided by the present invention. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be noted that while the description of these embodiments is intended to aid in understanding the invention, it does not constitute a limitation thereof. The specific structural and functional details disclosed herein are only for describing exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0052] It should be understood that although the terms "first" and "second", etc., may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object may be referred to as the second object, and similarly, the second object may be referred to as the first object, without departing from the scope of the exemplary embodiments of the invention.

[0053] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone or A and B exist simultaneously. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.

[0054] like Figures 1-4As shown, the upsampling method for high-multiplication interpolation of discrete signals provided in the first aspect of this embodiment can be applied, but is not limited to, when multiple signal sources need to be processed, and can include, but is not limited to, the following steps S1 to S2.

[0055] S1. Based on the interpolation target multiple, determine the interpolation multiple of each upsampling process in at least two sequential upsampling processes, wherein each upsampling process adopts a method of first interpolating the discrete signal by integer multiples and then low-pass filtering, and the interpolation multiple of each upsampling process and the interpolation target multiple satisfy the following relationship:

[0056]

[0057] In the formula, ∏ represents the operator for multiplying terms together, N represents the total number of stages of the at least two upsampling processes, and N = Roundup(log n M, 0), Roundup() represents the function for rounding up numbers, M represents the interpolation target multiple and M > n, n represents the preset threshold used to determine high-multiple interpolation, i represents a positive integer, m i This represents the interpolation factor of the i-th upsampling process in the at least two upsampling processes, and m i ≤n and m i ∈R, where R represents the set of positive integers.

[0058] In step S1, the interpolation target multiple M is the target value to be interpolated between two adjacent values ​​of the discrete signal, and it needs to be a composite number (meaning that among integers greater than 1, it is divisible by all numbers except 0, excluding 1 and itself) to perform the subsequent interpolation task splitting. When M > n, it indicates that there is a high-multiplier interpolation situation. If a single-stage FIR filter is used, there will be a problem of limited maximum interpolation value. The upsampling scheme provided in this embodiment is required to achieve high-multiplier interpolation while satisfying the passband tolerance and stopband tolerance. The preset threshold n can be preset according to the maximum interpolation value supported by the FIR filter. Generally, the preset threshold is 4000. For example, when the interpolation target factor M is 6000, the total number of stages N of the at least two upsampling processes will be equal to 2, that is, the at least two upsampling processes are two-stage upsampling processes: a first-stage upsampling process and a second-stage upsampling process. The first-stage upsampling process and the second-stage upsampling process respectively adopt the processing method of interpolating the discrete signal by integer multiples and then low-pass filtering. The interpolation factor m1 of the first-stage upsampling process can be 60, and the interpolation factor m2 of the second-stage upsampling process can be 100. At this time, m1*m2=60*100=6000=M, which satisfies the aforementioned relationship.

[0059] In step S1, considering that the subsequent step S2 is preferably implemented internally in a Field Programmable Gate Array (FPGA), in order to ensure that the required logic resources for each upsampling process in the at least two upsampling processes are close, and to ensure the best effect of multi-stage interpolation and shaping filters, it is necessary to satisfy the condition that the interpolation multiples of each upsampling process are close. Therefore, preferably, the interpolation multiples of each upsampling process in the at least two sequential upsampling processes are determined based on the composite interpolation target multiple, including but not limited to the following steps S111~

[0060] S113.

[0061] S111. Based on the interpolation target multiples that are composite numbers, determine the total series N according to the following formula:

[0062] N = Roundup(log n M,0)

[0063] In the formula, Roundup() represents a function for rounding up numbers, M represents the interpolation target multiple and M>n, and n represents a preset threshold used to determine high-multiple interpolation.

[0064] In step S111, for example, when the interpolation target factor M is 6000, the total number of stages N of the at least two upsampling processes will be equal to 2.

[0065] S112. Based on all factors of the interpolation target multiple M, at least one factor combination is obtained, wherein each factor combination in the at least one factor combination contains N different non-1 positive integers, and the N non-1 positive integers and the interpolation target multiple M satisfy the following relationship:

[0066]

[0067] In the formula, ∏ represents the operator for multiplying terms together, and i represents a positive integer. Represents the i-th value among the N non-1 positive integers and has

[0068] In step S112, for example, when the interpolation target multiple M is 6000, its factors include 1, 2, 3, 5, 6, 10, 12, 15, 20, 24, 25, 30, 40, 48, 50, 60, 100, 120, 125, 150, 200, 240, 250, 300, 400, 500, 600, 1000, 1200, 2000, 3000, and 6000, etc. Therefore, at least one combination of factors obtained includes [2,3000], [3,2000], [5,1200], [6,1000], [10,600], [12,500], [15,400], [20,300], [24,250], [25,240], [30,200], [40,150], [48,125], [50,120], and [60,100].

[0069] S113. In the at least one factor combination, each value in the factor combination corresponding to the minimum variance value is used as the interpolation multiple of each upsampling process in the N-level upsampling process, wherein each upsampling process adopts a processing method of interpolating the discrete signal by integer multiples and then low-pass filtering.

[0070] In step S113, since the factor combination [60, 100] has the minimum variance value, the interpolation factor m1 of the first upsampling process can be set to 60 and the interpolation factor m2 of the second upsampling process can be set to 100 in the two-stage upsampling process, or the interpolation factor m1 of the first upsampling process can be set to 100 and the interpolation factor m2 of the second upsampling process can be set to 60.

[0071] S2. Perform the at least two-stage upsampling process on the original discrete signal to obtain the signal upsampling result.

[0072] In step S2, the original discrete signal is the target signal to be upsampled. The specific process of performing at least two levels of upsampling can be exemplified by sequential two-level upsampling. Figures 2-4 As shown, in the first-stage upsampling process, the original discrete signal is first interpolated by an integer multiple of m1, then subjected to first-stage low-pass filtering to obtain the first-stage signal upsampling result. Then, in the second-stage upsampling process, the first-stage signal upsampling result (which is also a discrete signal) is first interpolated by an integer multiple of m2, then subjected to second-stage low-pass filtering to obtain the second-stage signal upsampling result, which is the final signal upsampling result. Figure 4As shown, discrete symbol data can be cascaded through m1 and m2 interpolation shaping filters, changing the original symbol data rate from s1 to s1*m1*m2, thus completing the upsampling operation. By using a hierarchical interpolation design to decompose the high-magnification interpolation task, the interpolation factor of each stage can be less than or equal to the maximum interpolation value supported by the FIR filter. Therefore, by using multi-stage cascaded FIR filters, the problem of the limited maximum interpolation value of a single-stage FIR filter can be solved, achieving high-magnification interpolation while satisfying passband and stopband tolerances.

[0073] In step S2, preferably, the original discrete signal can be subjected to at least two stages of upsampling processing within the Field Programmable Gate Array (FPGA) to obtain the signal upsampling result. Furthermore, to minimize the signal noise in the final obtained signal upsampling result, it is necessary to reduce the introduced signal noise before the next stage of upsampling processing. That is, preferably, the at least two stages of upsampling processing on the original discrete signal include, but are not limited to: after obtaining the first discrete signal obtained from the previous stage of upsampling processing, first truncating the effective data bit width of the first discrete signal to obtain the second discrete signal, and then performing the next stage of upsampling processing on the second discrete signal. The previous stage of upsampling processing and the next stage of upsampling processing constitute two adjacent stages of upsampling processing in the at least two stages of upsampling processing. The aforementioned specific method of truncating the effective data bit width is an existing method.

[0074] Therefore, based on the upsampling method for high-multiplication interpolation of discrete signals described in steps S1-S2 above, a hierarchical scheme for implementing high-multiplication interpolation upsampling design is provided. First, based on the target interpolation multiple (which is a composite number), the interpolation multiple of each of the at least two sequential upsampling processes is determined. Then, the original discrete signal undergoes the at least two upsampling processes to obtain the signal upsampling result. By using hierarchical interpolation design to decompose the high-multiplication interpolation task, the interpolation multiples of each decomposed stage can be less than or equal to the maximum interpolation value supported by the FIR filter. Furthermore, by using cascaded FIR filters, the maximum interpolation value limitation problem of a single-stage FIR filter can be solved, achieving high-multiplication interpolation while satisfying passband and stopband tolerances. In addition, by making the interpolation multiples of each upsampling process close, the programmable logic resources required for implementation in an FPGA are minimized, further enhancing its ease of implementation and ensuring stable operation, thus facilitating practical application and promotion.

[0075] Based on the technical solution of the first aspect mentioned above, this embodiment also provides a possible design for optimizing the determination of the interpolation multiple of each stage of upsampling processing, that is, determining the interpolation multiple of each stage of upsampling processing in at least two stages of sequential upsampling processing according to the interpolation target multiple that is a composite number, including but not limited to the following steps S121 to S124.

[0076] S121. Based on the interpolation target multiples that are composite numbers, determine the total series N according to the following formula:

[0077] N = Roundup(log n M,0)

[0078] In the formula, Roundup() represents a function for rounding up numbers, M represents the interpolation target multiple and M>n, and n represents a preset threshold used to determine high-multiple interpolation.

[0079] S122. Based on all factors of the interpolation target multiple M, at least one factor combination is obtained, wherein each factor combination in the at least one factor combination contains N different non-1 positive integers, and the N non-1 positive integers and the interpolation target multiple M satisfy the following relationship:

[0080]

[0081] In the formula, ∏ represents the operator for multiplying terms together, and i represents a positive integer. Represents the i-th value among the N non-1 positive integers and has

[0082] S123. For each factor combination in the at least one factor combination, apply a simulation program that implements N-level upsampling processing sequentially to simulate the discrete test signal, and obtain the corresponding signal upsampling simulation results and processing time. The upsampling processing of each level in the N-level upsampling processing adopts the processing method of interpolating the discrete signal by integer multiples and then low-pass filtering, and the interpolation multiple of each level of upsampling processing is set to the corresponding value in the factor combination.

[0083] S124. In the at least one factor combination, each value in the factor combination corresponding to the shortest processing time is used as the interpolation multiple of the upsampling process at each level.

[0084] In steps S121 and S122, the specific details can be referred to in steps S111 and S112 above, and will not be repeated here. In step S123, the simulation program can be conventionally written in MATLAB code, and the discrete test signal can be simulated and processed in MATLAB software to obtain the signal upsampling simulation results and processing time corresponding to each factor combination. In step S124, since the processing time reflects the size of the logic resources required for the entire N-level upsampling process: the shorter the processing time, the smaller the required logic resources, each value in the factor combination corresponding to the shortest processing time can be used as the optimal interpolation multiple for each level of upsampling process, ensuring that the programmable logic resources consumed are minimized when step S2 is applied to the internal implementation of the FPGA.

[0085] Therefore, based on the possible design described in steps S121 to S124 above, the optimal interpolation factor for each level of upsampling processing can be obtained, ensuring that the required programmable logic resources are minimized when the upsampling method is applied to the internal implementation of the FPGA.

[0086] The second aspect of this embodiment provides an upsampling device for high-multiplication interpolation of discrete signals, comprising at least two cascaded upsampling processing modules. Each upsampling processing module in the at least two-stage upsampling processing modules employs a processing method of first interpolating the discrete signal at an integer multiple and then low-pass filtering. The interpolation multiple of each upsampling processing module satisfies the following relationship with the target interpolation multiple:

[0087]

[0088] In the formula, Π represents the operator for multiplying terms together, N represents the total number of stages of the at least two upsampling processing modules, and N = Roundup(log n M, 0), Roundup() represents the function for rounding up numbers, M represents the interpolation target multiple and M > n, n represents the preset threshold used to determine high-multiple interpolation, i represents a positive integer, m i This represents the interpolation multiple of the i-th upsampling processing module in the at least two upsampling processing modules, and m i ≤n and m i ∈R, where R represents the set of positive integers; the at least two-stage upsampling processing module is used to perform at least two-stage upsampling processing on the original discrete signal to obtain the signal upsampling result.

[0089] like Figure 5As shown in the example, the upsampling device includes two-stage upsampling processing modules: a first-stage upsampling processing module and a second-stage upsampling processing module. The first-stage upsampling processing module includes a first integer multiple interpolation unit and a first low-pass filtering unit, while the second-stage upsampling processing module includes a second integer multiple interpolation unit and a second low-pass filtering unit. This allows them to perform integer multiple interpolation followed by low-pass filtering on discrete signals, respectively. In terms of hardware structure, the high-multiple interpolation task can be split through a hierarchical interpolation design, ensuring that the interpolation multiples of each stage are less than or equal to the maximum interpolation value supported by the FIR filter. Furthermore, by using a multi-stage cascaded FIR filter, the problem of the limited maximum interpolation value of a single-stage FIR filter can be solved, achieving the goal of satisfying both passband and stopband tolerances while achieving high-multiple interpolation values. Furthermore, the method for determining the interpolation factor of each upsampling processing module can refer to the first aspect or any possible design of the upsampling method described in the first aspect, so as to obtain the optimal interpolation factor of each upsampling processing, ensuring that the required programmable logic resources are minimized when the upsampling method is applied to the internal implementation of the FPGA, and further having the characteristics of easy implementation and stable operation, which facilitates practical application and promotion.

[0090] In one possible design, the upsampling device is arranged inside a field-programmable gate array (FPGA) to perform at least two levels of upsampling on the original discrete signal to obtain the signal upsampling result.

[0091] In one possible design, the upsampling device further includes a bit width truncation processing module connected in series between two adjacent upsampling processing modules in the at least two upsampling processing modules.

[0092] The bit width truncation processing module is used to truncate the effective data bit width of the first discrete signal after acquiring the first discrete signal output by the previous upsampling processing module and which is the upsampling result of the previous signal, to obtain a second discrete signal, and then send the second discrete signal to the next upsampling processing module. The previous upsampling processing module and the next upsampling processing module constitute the two adjacent upsampling processing modules.

[0093] In one possible design, the low-pass filter units in each upsampling processing module are implemented using the IP core of a finite-length unit impulse response (FIR) filter.

[0094] The working process, working details and technical effects of the aforementioned device provided in the second aspect of this embodiment can be found in the upsampling method described in the first aspect or any possible design in the first aspect, and will not be repeated here.

[0095] Finally, it should be noted that this invention is not limited to the optional embodiments described above, and anyone can derive other various forms of products under the guidance of this invention. The specific embodiments described above should not be construed as limiting the scope of protection of this invention, which should be determined by the claims, and the specification can be used to interpret the claims.

Claims

1. A method of up-sampling for high factor interpolation of a discrete signal, characterized by, The method comprises the following steps: According to the interpolation target multiple which is a composite number, determining interpolation multiples of each level of upsampling processing in at least two levels of upsampling processing in sequence, wherein each level of upsampling processing adopts a processing mode of first integer times interpolation and then low-pass filtering on a discrete signal, and the interpolation multiples of each level of upsampling processing and the interpolation target multiple satisfy the following relationship: wherein represents an operator of multiplication of each term, N represents a total number of stages of the at least two-stage up-sampling process and has N = Roundup(log n M, 0), Roundup() represents a function of rounding up a number, M represents the interpolation target multiple and has M > n, n represents a preset threshold for determining a high multiple interpolation, i represents a positive integer, m i represents an interpolation multiple of the i-stage up-sampling process in the at least two-stage up-sampling process and has m i ≤ n and m i ∈ R, R represents a set of positive integers; Performing the at least two levels of upsampling processing on the original discrete signal to obtain a signal upsampling result.

2. The up-sampling method of claim 1, wherein, According to the interpolation target multiple which is a composite number, determining interpolation multiples of each level of upsampling processing in at least two levels of upsampling processing in sequence, comprising: According to the interpolation target multiple which is a composite number, determining a total number of levels N according to the following formula: N = Roundup(log n M,0) In the formula, Roundup() represents a function of rounding up a number, M represents the interpolation target multiple and has M > n, and n represents a preset threshold value for determining high-multiple interpolation; According to all factors of the interpolation target multiple M, obtaining at least one factor combination, wherein each factor combination in the at least one factor combination contains different N non-1 positive integers, and the N non-1 positive integers and the interpolation target multiple M satisfy the following relationship: In the formula, ∑ represents the operation symbol of summing up each term, i represents a positive integer, represents the i-th value in the N non-1 positive integers and has In the at least one factor combination, each value in a factor combination corresponding to a minimum variance value is one-to-one corresponding as an interpolation multiple of each level of upsampling processing in N levels of upsampling processing in sequence, wherein each level of upsampling processing adopts a processing mode of first integer times interpolation and then low-pass filtering on a discrete signal.

3. The up-sampling method of claim 1, wherein, According to the interpolation target multiple which is a composite number, determining interpolation multiples of each level of upsampling processing in at least two levels of upsampling processing in sequence, comprising: According to the interpolation target multiple which is a composite number, determining a total number of levels N according to the following formula: N = Roundup(log n M,0) In the formula, Roundup() represents a function of rounding up a number, M represents the interpolation target multiple and has M > n, and n represents a preset threshold value for determining high-multiple interpolation; According to all factors of the interpolation target multiple M, obtaining at least one factor combination, wherein each factor combination in the at least one factor combination contains different N non-1 positive integers, and the N non-1 positive integers and the interpolation target multiple M satisfy the following relationship: In the formula, represents the operator of multiplying each term, i represents a positive integer, represents the i-th value in the N non-1 positive integers and has For each factor combination in the at least one factor combination, a simulation program for implementing N levels of upsampling processing in sequence is applied to perform simulation processing on a discrete test signal to obtain corresponding signal upsampling simulation results and processing time, wherein each level of upsampling processing in the N levels of upsampling processing adopts a processing mode of first integer times interpolation and then low-pass filtering on a discrete signal, and interpolation multiples of each level of upsampling processing are one-to-one corresponding set as each value in the corresponding factor combination; In the at least one factor combination, each value in a factor combination corresponding to a minimum processing time is one-to-one corresponding as the interpolation multiple of each level of upsampling processing.

4. The up-sampling method of claim 1, wherein, Performing the at least two levels of upsampling processing on the original discrete signal to obtain a signal upsampling result, comprising: Performing the at least two levels of upsampling processing on the original discrete signal to obtain a signal upsampling result, comprising: Performing the at least two levels of upsampling processing on the original discrete signal to obtain a signal upsampling result, comprising:

5. The up-sampling method of claim 4, wherein, The at least two-stage up-sampling processing on the original discrete signal comprises: After obtaining a first discrete signal processed by a previous-stage up-sampling processing, the effective data bit width of the first discrete signal is first truncated to obtain a second discrete signal, and then a next-stage up-sampling processing is performed on the second discrete signal, wherein the previous-stage up-sampling processing and the next-stage up-sampling processing constitute two adjacent stages of the at least two-stage up-sampling processing.

6. The up-sampling method of claim 1, wherein, The preset threshold is 4000.

7. An up-sampling device for high factor interpolation of a discrete signal, characterized by The at least two-stage up-sampling processing module comprises at least two-stage up-sampling processing modules connected in sequence, wherein each up-sampling processing module in the at least two-stage up-sampling processing modules adopts a processing mode of first integer interpolation and then low-pass filtering on a discrete signal, and the interpolation multiple of each up-sampling processing module and the interpolation target multiple satisfy the following relationship: wherein ∑ represents an operator of multiplication of each term, N represents a total number of stages of the at least two-stage up-sampling processing modules and has N = Roundup(log n M, 0), Roundup() represents a function of rounding up a number, M represents the interpolation target multiple and has M > n, n represents a preset threshold for determining high-multiple interpolation, i represents a positive integer, m i represents an interpolation multiple of an i-stage up-sampling processing module in the at least two-stage up-sampling processing modules and has m i ≤ n and m i ∈ R, R represents a set of positive integers. The at least two-stage up-sampling processing module is configured to perform at least two-stage up-sampling processing on an original discrete signal to obtain a signal up-sampling result.

8. The up-sampling device of claim 7, wherein, The up-sampling device is arranged in an internal field programmable logic gate array (FPGA) to perform at least two-stage up-sampling processing on an original discrete signal to obtain a signal up-sampling result.

9. The up-sampling device of claim 8, wherein, The up-sampling device further comprises a bit width truncation processing module connected in series between two adjacent up-sampling processing modules in the at least two-stage up-sampling processing modules. The bit width truncation processing module is configured to, after obtaining a first discrete signal output by a previous-stage up-sampling processing module and serving as a previous-stage signal up-sampling result, perform bit width truncation processing on the effective data bit width of the first discrete signal to obtain a second discrete signal, and send the second discrete signal to a next-stage up-sampling processing module, wherein the previous-stage up-sampling processing module and the next-stage up-sampling processing module constitute the two adjacent up-sampling processing modules.

10. The up-sampling device of claim 8, wherein, The low-pass filter units in each up-sampling processing module are implemented by an IP core of a finite impulse response (FIR) filter.

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