Processor, method for executing compression auxiliary instructions and computer program product

Abstract

In one embodiment, the processor supports one or more compression auxiliary instructions, which can be used in the compression software to improve the performance of the processor when performing compression / decompression. That is, when the compression auxiliary instructions are used, the compression / decompression tasks can be performed more quickly and consume less power than when they are not used. In some cases, the cost of a more effective, more complex compression algorithm can be reduced to the cost of a less effective, less complex compression algorithm.

Description

Background Art Technical Field

[0002] Embodiments described herein relate to processors, and more particularly, to compression assist instructions in processors to improve compression / decompression performance and power efficiency.

[0003] Related technical description

[0004] In computing devices, compression is used for a variety of reasons. For example, a software download may be compressed for transmission over a network and may be decompressed on a target computing device for installation. In some cases, such as portable computing devices (e.g., smart phones, portable digital assistants, tablet computers, etc.), software may be decompressed, installed, and then recompressed for storage on the device. Storing various software in compressed form can save storage space on devices such as laptops, desktops, servers, etc., where storage space may be more limited than in larger computing devices.

[0005] Compression / decompression is primarily implemented in software, and therefore the performance cost (and power consumption, on portable devices with limited power supplies such as batteries) can be significant. The effectiveness of a compression algorithm is generally measured as the ratio of the size of the uncompressed original to the size of the compressed result (the compression ratio for short). Unfortunately, the effectiveness of a given compression algorithm is usually related to its complexity, and therefore the cost of effectiveness is performance (e.g., latency) and power. Summary of the invention

[0006] In one embodiment, the processor supports one or more compression auxiliary instructions, which can be used in the compression software to improve the performance of the processor when performing compression / decompression. That is, when the compression auxiliary instructions are used, the compression / decompression tasks can be performed more quickly and consume less power than when they are not used. In some cases, the cost of a more effective, more complex compression algorithm can be reduced to the cost of a less effective, less complex compression algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0008] Figure 1 is a block diagram of one implementation of decompression based on a finite state entropy (FSE) compression algorithm.

[0009] Figure 2 is a block diagram of one implementation of optimized decompression based on the FSE algorithm, where multiple interleaved FSE symbol streams share the same decoder and bitstream.

[0010] Figure 3 is a block diagram of another embodiment of optimized decompression based on the FSE algorithm, in which multiple interleaved FSE symbol and value streams share the same decoder table.

[0011] Figure 4 is a block diagram illustrating one embodiment of a bit stack read operation.

[0012] Figure 5 is a block diagram illustrating one embodiment of a bit stack write operation.

[0013] Figure 6 is a block diagram illustrating register inputs and outputs for one embodiment of a top unpack assist instruction.

[0014] Figure 7 is a block diagram illustrating register inputs and outputs for one embodiment of a top unpack assist instruction.

[0015] Figure 8 is a block diagram illustrating register inputs and outputs for creating one embodiment of a compressed assist instruction.

[0016] Fig. 9 is a block diagram illustrating register inputs and outputs for connecting one embodiment of a compressed assist instruction.

[0017] Fig.10 is a block diagram of one embodiment of a system including a processor.

[0018] Fig.11 yes Fig.10 A block diagram of one embodiment of a vector execution unit is shown.

[0019] Fig.12 is a flow chart illustrating the operation of one embodiment of a processor to execute top instructions.

[0020] Fig.13 is a flow chart illustrating the operation of one embodiment of a processor to execute a pop instruction.

[0021] Fig.14 is a flow chart illustrating the operation of one embodiment of a processor to execute a create instruction.

[0022] Fig.15 is a flow chart illustrating the operation of one embodiment of a processor to execute a connect instruction.

[0023] Although the embodiments described in this disclosure may be affected by various modifications and alternative forms, their specific embodiments are shown in the drawings by way of example and will be described in detail herein. However, it should be understood that the drawings and their specific embodiments are not intended to limit the embodiments to the disclosed specific forms, but on the contrary, the present invention is intended to cover all modifications, equivalents and alternatives falling within the essence and scope of the appended claims. The titles used herein are only used for organizational purposes and are not intended to be used to limit the scope of the specification. As used throughout this application, the word "may" is used in an allowed sense (i.e., meaning to have a possibility) rather than a mandatory sense (i.e., meaning to have to). Similarly, the words "including", "comprising" mean "including but not limited to". As used herein, the terms "first", "second", etc. serve as labels for the nouns thereafter, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless clearly indicated.

[0024] Within the present disclosure, different entities (which may be variously referred to as "units", "circuits", other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression - [an entity] configured to [perform one or more tasks] - is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. "A clock circuit configured to generate an output clock signal" is intended to cover, for example, a circuit that performs that function during operation, even if the circuit in question is not currently being used (e.g., the circuit is not connected to a power source). Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing. Typically, the circuits that form the structure corresponding to "configured to" may include hardware circuits. Hardware circuits may include any combination of the following: combinatorial logic circuits, clock storage devices (such as flip-flops, registers, latches, etc.), finite state machines, memories (such as static random access memory or embedded dynamic random access memory), custom designed circuits, analog circuits, programmable logic arrays, etc. Similarly, for ease of description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to".

[0025] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function, although it might be "configurable to" perform that function. After being appropriately programmed, the FPGA can then be considered "configured to" perform that function.

[0026] In one embodiment, a hardware circuit according to the present disclosure may be implemented by encoding a description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized for a cell library designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that can be transmitted to the factory to generate masks and ultimately produce an integrated circuit. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design together with the synthesized circuit. The integrated circuit may include transistors and may also include other circuit elements (e.g., passive elements, such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in an FPGA.

[0027] As used herein, the term "based on" or "depending on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B affects the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0028] This specification includes references to various embodiments to indicate that the disclosure is not intended to refer to one particular implementation, but rather to a series of embodiments falling within the spirit of the disclosure, including the appended claims. The particular features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0029] This specification may use the words "a" or "an" to refer to an element, or the word "the" to refer to an element. These words are not intended to mean that there is only one instance of an element. In various embodiments, there may be more than one. Therefore, unless explicitly described as only one, "a", "an" and "the" should be interpreted to mean "one or more".

[0030] The specification may describe various components, units, circuits, etc. as being coupled. In some embodiments, components, units, circuits, etc. may be coupled if they are electrically coupled (e.g., directly connected or indirectly connected through one or more other circuits) and / or communicatively coupled. DETAILED DESCRIPTION

[0031] As described above, processors implementing various embodiments of compression auxiliary instructions are disclosed. Generally speaking, compression auxiliary instructions can be instructions designed to improve processor performance when performing compression and / or decompression. Therefore, in some cases, compression auxiliary instructions can be instructions that are expected to be used only in decompression. In other cases, compression auxiliary instructions can be expected to be used only for compression, or for both compression and decompression.

[0032] To illustrate the compression assist instructions and their applications, several specific implementations of the finite state entropy (FSE) compression algorithm are shown. Although FSE is used as an example, mechanisms that employ one or more bitstreams or bit stacks as part of compression can benefit from the compression assist instructions described below.

[0033] Figure 1 FIG. 1 is a block diagram of an implementation scheme for decompressing FSE compressed data. Figure 1 As shown, the data includes a table 10 and a bit stream 12. That is, when the data is compressed in units of the FSE compression algorithm, the table 10 and the bit stream 12 are generated. The initial state can be used to find the initial entry in the table. That is, the state (shown at reference numeral 16) can be an index to the table 10. Each entry can include data similar to that shown in reference numeral 14. In particular, the entry can include a base, a symbol, and a number of bits (n). The symbol is part of the output data and can be provided to be combined with the previously read symbol to generate an output data stream as the original data. That is, the symbol is part of the original data and can be connected to the end of the data stream (or in the case of the initial state, the data stream can be initialized). The number of bits (n) can specify the number of bits to be consumed from the bit stream 12 to provide an incremental value to be added to the base to generate the next state. The next state replaces the initial state and looks up the table entry, from which the next symbol and the next state can be generated. Continuously repeating the next state generation, search and symbol output can generate a symbol stream, that is, uncompressed original data. At some point, the entry in the table can indicate that the end of the data has been reached. Alternatively, the uncompressed data may be of a fixed size, and thus the next state generation, lookup, and symbol output may occur a fixed number of times (assuming fixed-size symbols).

[0034] Figure 1 The implementation of is a fairly sequential process and therefore may be relatively slow. Various implementations may perform more parallel operations. For example, in Figure 2 , four states may be looked up in parallel. The four states 24 may correspond to four interleaved FSE symbol streams that share the same decoder table 26. That is, the symbol streams may be independent of each other but interleaved in the bit stack 20. Other embodiments may implement more or fewer parallel states / symbol streams as desired. Each state 24 may read a table entry 22 from the table 26. Each table entry 22 may be similar to Figure 1 14. Each of the four table entries 22 read in parallel can provide a symbol that can be connected to a corresponding output symbol stream (or used to initialize a corresponding output symbol stream for initial state 24). Each entry consumes its specified number of bits (n) from the bit stack 20 (where Figure 2 The entry at the top in the bit stack 20 reads the bit at the top of the bit stack 20, the next entry down reads the next bit in the bit stack 20, etc.). Thus, as described above, the bit stack 20 may have interleaved bit fields of the symbol stream. The result increment is added to the base from the corresponding entry 22 to generate the next state 24.

[0035] Figure 3 Another implementation of a parallelized version of the FSE algorithm is shown. Figure 3 In an embodiment of the present invention, instead of storing symbols directly in table 30, symbols can be generated based on a base value (value base, or V base) read from table 30, and the increment read from another bit stack 32 (value bit stack, or V bit stack 32) can be used to generate the symbol. That is, each symbol can correspond to a range of values ​​starting from the V base, and the specific value at a given point in the decoding process is determined by reading the increment from the V bit stack 32 and adding it to the V base. Therefore, the table entry 34 can include the V base and the number of bits consumed from the V bit stack 32 (nv) to be used as an increment (V increment) to be added to the V base to generate an output symbol from the entry. In addition, each entry 34 can include a state base (S base) and a number of bits (ns) to be read from a state bit stack 36 (S bit stack 36) to form an increment (S increment) to be added to the S base from each entry to generate the next state 38. In one embodiment, the V bit stack 32 and the S bit stack 36 can be implemented as a single bit stack, where the V bits and the S bits are interleaved in the stack. In yet other embodiments, a combination of interleaving of V bits and S bits in a stack and implementing multiple stacks may be used. For example, a set of 16 symbol streams may be represented as 4 sets of 4 interleaved symbol streams (eg, 4 bit stacks).

[0036] Executed in processors that include vector instructions Figure 2 or Figure 3 One method of decompression shown is to use vector operations. For example, if the processor supports vectors with 4 vector elements, then Figure 2 and Figure 3The implementation scheme of may use one vector instruction for each operation involved in table lookup, next state generation and symbol value generation to perform table lookup, next state generation and symbol value generation. However, the bit stack read operation may be more difficult to vectorize using standard vector instructions.

[0037] Generally speaking, vector operations are performed in parallel on multiple vector elements in one or more vector operands and perform specified operations on each vector element independently. For example, a vector addition operation can add vector elements at corresponding positions within a vector operand, thereby generating a sum as a vector element of a vector result operand. A four-element vector will have vector elements VE0, VE1, VE2, and VE3, arranged in the order listed in adjacent vector element positions within the vector. Vector addition will add the VE0 element of the source operand to generate the VE0 element of the result operand; add the VE1 element of the source operand to generate the VE1 element of the result operand; and so on. Although a four-element vector is used as an example, other embodiments may use different numbers of vector elements per vector and / or may support multiple numbers of vector elements per vector. For example, a 128-bit vector register set may support 2 64-bit vector elements, 4 32-bit vector elements, 8 16-bit vector elements, and 16 8-bit vector elements. Various vector instructions may be defined to use vector registers as vector elements of different sizes.

[0038] Therefore, vector operations / instructions perform well on vector elements of the same size, and many operations can be performed in parallel to improve the performance of vectorizable algorithms. However, the bit stack read operation (and the corresponding bit stack write operation during compression) can be a variable size operation. Each bit stack read can be any number of bits, from 1 bit (and possibly even 0 bits) to the maximum number of bits supported by the algorithm. For example, in Figure 3 In one embodiment of the algorithm in, it is possible to support bit stack reading from 1 bit to 32 bits. Implementing the bit stack as fixed-size elements (e.g., 32 bits in the example) will significantly reduce the compression ratio achievable by the algorithm and will therefore be counterproductive.

[0039] To enhance the use of vector operations, Figures 1 to 3 The compression algorithm shown performs compression and decompression, and compression auxiliary instructions have been defined to perform bit stack read and write operations, transferring data from the bit stack to vector elements (bit stack read) and from vector elements to packed bit stack data (bit stack write).

[0040] Figures 4 to 5The bit stack read operation and the bit stack write operation to vector register of an embodiment are shown.Compression auxiliary instruction has been defined as to make the processor (when executing compression auxiliary instruction) interpret the data in one or more vector registers of storage instruction operand as bit stack data rather than vector element.Therefore, a part of bit stack can be loaded into the vector register and processed using the compression auxiliary instruction defined herein.Any vector register can be designated as this type of operand; It is the specific operand that vector register is encoded as compression auxiliary instruction, causing the processor to interpret register data as bit stack data rather than vector element.

[0041] Figure 4 A portion of the bit stack 40 including the top of the bit stack is shown. Figure 4 The top of the bit stack can be Figure 4 , and can include increments x3 (top of the stack), x2 (next to the top of the stack), x1, and x0, as well as additional values ​​below these. Figure 4 The widths of x3, x2, x1, and x0 vary to show that each value is one or more bits and can vary. The first vector register 42 has four vector elements that store the size of the first four increments on the stack (b3 corresponds to x3, b2 corresponds to x2, etc.). Register 42 can be changed from Figure 2 Field "n" in the given table is loaded, or read from Figure 3 The fields "nv" or "ns" in the given table are read. Figure 3 In an embodiment of , two vector registers may be used, one for "nv" and one for "ns". Generally, one or more vector load instructions may perform a table read, and there may be additional vector instructions to isolate the size value in register 42 to perform a bit stack read.

[0042] Based on the size in register 42, bit fields x3, x2, x1, and x0 may be extracted from the top of the bit stack into result vector register 44, and the bit stack may be updated to remove the extracted bit fields. Figure 4 The updated stack 46 in includes the remaining additional values ​​at the top of the stack. Stacks 40 and 46 can show values ​​in memory so that the top of the stack moves in memory. When the top of the stack is loaded into a register, as described below, a bit stack read can include moving the new top of the stack left into the register (e.g., so that the most significant bit or MSB of the register has a bit at the top of the stack).

[0043] The bit stack read operation may be part of the decompression process.Creating the bit stack may include a bit stack write operation as the compression algorithm determines symbols and generates table entries and the bit stack. Figure 5 A bit stack write operation is shown.

[0044] Figure 5 The initial bit stack 48 in includes an additional value at the top of the stack, similar to Figure 4 The updated bit stack in 46. Figure 4 Space is shown on the top left of the bit stack 48 in to illustrate pushing more bit fields into the bit stack as part of the bit stack write. Vector register 50 may be encoded with vector elements corresponding to the size of each bit field (b3 for x3, b2 for x2, etc.). Another vector register 52 may have bit fields as vector elements (x3, x2, etc.). Vector registers 50 and 52 may be computed using other vector instructions based on the compression algorithm. The bit stack write operation connects the bit fields x3, x2, x1, and x0 so that they are adjacent in the bit stack and writes the bit fields to the top of the bit stack, resulting in Figure 5 An updated bit stack 54 is shown.

[0045] To implement Figure 4 The bit stack read operation shown, the processor described herein may include a pair of compression auxiliary instructions. These instructions are referred to as "top" and "pop-up" in this article. The top instruction, when executed, can make the processor extract multiple bit fields from the top of the bit stack (which can be stored in a vector register, as described below) to the vector element of the result vector register. The pop-up instruction, when executed, can make the processor remove the bit field from the top of the stack, and move the top of the stack downward to the next group of bit fields that have not yet been extracted using the top instruction.

[0046] Figure 6 is a block diagram of source operands and result operands of the top instruction of one embodiment. Figure 6 At the top of the top instruction, the mnemonic for the top instruction is shown with a result vector register (RV), a source stack register (SSR), and a source size vector register (SSV). The source stack register contents are shown at 60, the source size vector register contents are shown at 62, and the result vector register contents after executing the top instruction are shown at 64.

[0047] As previously mentioned, stack register can be vector register, but processor can interpret content differently by register being designated as the stack operand of a compression auxiliary instruction in compression auxiliary instruction.When vector register stores bit stack data, this register can comprise bit stack field 66 and bit count field 68.Bit stack field can be multiple bits, wherein in this embodiment, the MSB of multiple bits is in the MSB of register.The MSB of multiple bits can be the highest bit of bit stack.Bit count field 68 can be the current number of bits in stack register (for example, the quantity of multiple bits in bit stack field 66).In one embodiment, vector register can be 128 bits and bit count field can be 8 bits.Therefore, in this embodiment, bit stack field 66 can be up to 120 bits.Other embodiments can implement vector register of different sizes and support larger or smaller bit stack field and bit count field.

[0048] In bit stack field 66, Figure 6 , bit fields x3, x2, x1, and x0 are identified in the source size vector register 62. The bit fields are defined by the sizes in the source size vector register 62. More specifically, the source size vector register 62 can be a vector with multiple sizes. That is, the size can be a count of the number of bits in the corresponding bit field. For example, the size can be an integer. In the illustrated embodiment, there are four vector elements in the source size vector 62: vector element 3 (VE3), VE2, VE1, and VE0. Each vector element specifies the size of the corresponding bit field. Therefore, bit field x3 can be the most significant b3 bits of the bit stack field 66. Bit field x2 can be adjacent to bit field x3 (for example, the MSB of bit field x2 can be adjacent to the least significant bit or LSB of bit field x3) and the size can be b2 bits. Bit field x1 can be adjacent to bit field x2 and the size can be b1 bits, and bit field x0 can be adjacent to bit field x1 and the size can be b0 bits. The remaining bits in the bit stack field 66 are Figure 6 The MSB of p may be the MSB of the next bit field in the bit stack, which may be defined by the next table read from Table 26 or Table 30. Although the size field in register 62 is shown as occupying Figure 6 The extracted bit fields in the result vector register 64 may be up to the full size of a vector element, but the fields may occupy up to the entire vector element. In addition, the extracted bit fields in the result vector register 64 may be up to the full size of a vector element, but the size of each individual field is controlled by the corresponding vector element from the size vector.

[0049] Based on the size field in source size vector register 62, the processor executing the top instruction may be configured to extract the bit fields into corresponding vector elements of result vector register 64. Thus, x3 is element VE3 of result vector register 64, extracted based on size b3 in VE3 of source size vector register 62; x2 is element VE2 of result vector register 64, extracted based on size b2 in VE2 of source size vector register 62 and also affected by b3 because x3 is extracted in parallel from the MSB of bit stack field 66; x1 is element VE1 of result vector register 64, extracted based on size b1 in VE1 of source size vector register 62 and also affected by b3 and b2; and x0 is element VE0 of result vector register 64, extracted based on size b0 in VE0 of source size vector register 62 and also affected by b3, b2, and b1.

[0050] Figure 7 is a block diagram of source operands and result operands of a pop instruction according to one embodiment. Figure 7 , a mnemonic for a pop instruction is shown at the top of the figure, which includes a result stack register (RSR), a source stack register (SSR) and a source size vector register (SSV). The source stack register content is shown at 60, the source size vector register content is shown at 62, and the result stack register content after executing the pop instruction is shown at 70. The pop instruction may be intended to be paired with the top instruction to adjust the content of the bit stack to reflect the extraction and consumption of bit fields x3, x2, x1 and x0. Therefore, identical source registers 60 and 62 are shown. However, the pop instruction may be encoded with any source register generally.

[0051] As previously described, the processor executing the pop instruction removes the bits corresponding to the bit field consumed by the top instruction. Therefore, the pop instruction can use the sum of the size vector elements b3, b2, b1 and b0 from the source size vector register 62 to identify the number of bits to be removed, starting from the MSB of the register. The remaining bits (p) can be shifted so that the MSB of p is the MSB of the result stack register 70. In addition, the bit count field (n') can be calculated by subtracting the sum of the size vector elements from the bit count field n in the source stack register 60, as shown in the figure numeral 72.

[0052] It should be noted that the result stack register 70 can be encoded as the register identical with the source stack register 60 in the pop-up instruction, thereby using the top instruction to update the source stack register 60, for the next stack read operation to extract the next group of bit fields. When the bit stack field in the stack register is exhausted, it can be refilled by the remaining bit stack from the memory by the load instruction. Vector load instructions can be used, because the vector load instruction can only load data into the register. It is using the register as the stack register operand that causes the processor to interpret the content as a bit stack rather than a vector element.

[0053] The top instruction and the pop instruction may be compression auxiliary instructions that may be used for decompression. In some embodiments, one or more compression auxiliary instructions may also be defined for compression. In particular, Figure 5 The bit stack write operation shown defines compression assist instructions. In one embodiment, two compression assist instructions are defined: "Create" and "Connect".

[0054] Figure 8 is a block diagram of source operands and result operands of a create instruction of one embodiment. Figure 8 At the top of the diagram, a mnemonic for a create instruction is shown, which contains a result stack register (RSR), a source vector register (SV), and a source size vector register (SSV). Various vector instructions may be executed to generate a vector having bit fields and corresponding sizes, which may be in source vector register 80 and source size vector register 82 when the bit stack write operation is ready to be performed. Registers 80 and 82 are in Figure 8 82 and includes a vector element storing a bit field (register 80) and a corresponding vector element storing a size (register 82). Thus, VE3 of register 80 is a bit field x3 (VE3 of register 82) of size b3, VE2 of register 80 is a bit field x2 (VE2 field of register 82) of size b2, and so on. When the processor executes the create instruction, the processor may pack the bit fields from source vector register 80 into the MSB of result stack register 84, forming a plurality of bits in the MSB of result stack register 84, including bit fields x3, x2, x1, and x0 in adjacent bit positions within the plurality of bits (e.g., the LSB of x3 is adjacent to the MSB of x2, the LSB of x2 is adjacent to the MSB of x1, and so on). The bit count field "n" may be calculated as the sum of the size vector elements from register 82, as shown by reference numeral 86.

[0055] The create instruction creates multiple bits from a vector of bit fields. The connect instruction can be used to insert the result of the create instruction into a previous version of the bit stack (e.g., multiple bits are pushed onto the bit stack). The connect instruction can also be used in a bit stack read operation to refill the exhausted bit stack register from memory. For example, the next part of the bit stack can be loaded into a vector register from memory and can be connected to the bit stack register for the bit stack read.

[0056] Fig. 9 is a block diagram of a source operand and a result operand of a concatenation instruction of one embodiment. Fig. 9 , a mnemonic for a concatenation instruction is shown, which includes a result stack register (RSR), a source stack register 1 (SSR1), and a source stack register 2 (SSR2). Source stack register 1 and source stack register 2 are shown with reference numerals 88 and 90, respectively. Each source stack register may include a plurality of bits (p1 in register 88, p2 in register 90), and a bit count field indicates the number of the plurality of bits (n1 in register 88, n2 in register 90). A processor executing the concatenation instruction may concatenate the p2 bit to the p1 bit, thereby creating a larger plurality of bits, as shown in result stack register 92. The bit count field in the result stack register may be calculated as the sum of the bit count field n1 and the bit count field n2, as shown in reference numeral 94.

[0057] Although Figures 6 to 9 The embodiment shown has vectors with 4 vector elements, but other embodiments may support vectors with more or fewer vector elements (e.g., 2, 8, 16, etc.). In addition, as previously described, some embodiments may support multiple versions of vector instructions, including compressed auxiliary instructions, to use vectors with different numbers of vector elements (or operands such as immediate fields may select how many vector elements are in the vector for the instruction).

[0058] Fig.101 is a block diagram of one embodiment of a computer system 100. Computer system 100 includes a processor 102, a level 2 (L2) cache 106, a memory 108, and a mass storage device 110. As shown, processor 102 includes a level 1 (L1) cache 104 and an execution core 120 coupled to L1 cache 104 and register file 112. As shown, execution core 120 may include one or more execution units, such as integer execution unit 114, floating point (FP) execution unit 116, and vector execution unit 118. In various embodiments, execution units 114, 116, and 118 may be coupled to register file 112, and / or there may be multiple register files 112 for different operand types. Note that although specific components are shown and described in computer system 100, in alternative embodiments, different components and different numbers of components may be present in computer system 100. For example, computer system 100 may not include some of the memory hierarchy (e.g., L2 cache 104, memory 108, and / or mass storage device 110). Multiple processors similar to processor 102 may be included. Multiple execution units of a given type (e.g., integer, floating point, vector, load / store, etc.) may be included, and the number of execution units of a given type may be different from the number of execution units of another type. In addition, although L2 cache 106 is shown as being external to processor 102, it is contemplated that in other embodiments, L2 cache 106 may be internal to processor 102. It is also noted that in such embodiments, a third level (L3) cache (not shown) may be used. In addition, computer system 100 may include a graphics processor, a video card, a video capture device, a user interface device, a network card, an optical drive, and / or other peripheral devices coupled to processor 102 using a bus, a network, or another suitable communication channel (all not shown for simplicity).

[0059] In various embodiments, processor 102 may represent a general purpose processor that performs computing operations. For example, processor 102 may be a central processing unit (CPU), such as a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Processor 102 may be a stand-alone component, or may be integrated onto an integrated circuit with other components (e.g., other processors or other components in a system on a chip (SOC), etc.). Processor 102 may be a component in a multi-chip module (MCM) with other components.

[0060] More specifically, if Figure 1As shown, the processor 102 may include an execution core 120. The execution core 120 may be configured to execute instructions defined in an instruction set architecture implemented by the processor 102. As required, the execution core 120 may have any microarchitecture features and specific implementation features. For example, the execution core 120 may include a superscalar or scalar specific implementation. The execution core 120 may include an in-order or out-of-order specific implementation, as well as a speculative or non-speculative specific implementation. The execution core 120 may include any combination of the above features. In some embodiments, the specific implementation may include microcode. The execution core 120 may include a variety of execution units, each of which is configured to perform various types of operations (e.g., integer execution unit 114, floating point execution unit 116, vector execution unit 118, load / store execution unit (not shown) etc.). The execution core 120 may include different numbers of pipeline stages and various other performance enhancement features, such as branch prediction. The execution core 120 may include one or more of an instruction decoding unit, a scheduler or reservation station, a reorder buffer, a memory management unit, an I / O interface, etc.

[0061] Register file 112 may include a set of registers that may be used to store operands for various instructions. Register file 112 may include registers of various data types, based on the type of operands execution core 120 is configured to store in registers (e.g., integer, floating point, vector, etc.). Register file 112 may include architectural registers (i.e., those registers specified in the instruction set architecture implemented by processor 102). Alternatively or in addition, register file 112 may include physical registers (e.g., if register renaming is implemented in execution core 120).

[0062] L1 cache 104 may illustrate any cache structure. For example, L1 cache 104 may be implemented as a Harvard architecture (a separate instruction cache for instruction fetch and a data cache for execution units to read / write data for memory reference operations), a shared instruction and data cache, etc. In some embodiments, a load / store execution unit may be provided to perform memory reference operations.

[0063] Instructions can be executable entities defined in an instruction set architecture implemented by the processor 102. There are multiple instruction set architectures (e.g., x86 architecture originally developed by Intel, ARM from ARM Holdings, Power and PowerPC from IBM / Motorola, etc.). Each instruction is defined in an instruction set architecture, including the encoding of instructions in memory, the operation of instructions, and the influence of instructions on registers, memory locations, and / or other processor states. A given specific implementation of an instruction set architecture can directly execute each instruction, but its form can be changed by decoding and other manipulations in the processor hardware. Another specific implementation can decode at least some instructions into multiple instruction operations for execution by the execution unit in the processor 102. In some embodiments, some instructions can be micro-coded. Therefore, the term "instruction operation" can be used herein to refer to the operation that the execution unit in the processor 102 / execution core 120 is configured to perform as a single entity. An instruction can have a one-to-one correspondence with an instruction operation, and in some cases, an instruction operation can be an instruction (possibly modified in the form of the processor 102 / execution core 120). An instruction can also have a one-to-many (one-to-many) correspondence with an instruction operation. Instruction operations may be referred to more simply as "operations" herein.

[0064] The mass storage device 110, memory 108, L2 cache 106, and L1 cache 104 are storage devices that together form a memory hierarchy for storing data and instructions for the processor 102. More specifically, the mass storage device 110 can be a large non-volatile memory, such as a disk drive or a large flash memory unit with a long access time, while the L1 cache 104, L2 cache 106, and memory 108 may be smaller and have a shorter access time. These faster semiconductor memories store copies of frequently used data. The memory 108 can represent a memory device in the dynamic random access memory (DRAM) family of memory devices. The size of the memory 108 is generally larger than the L1 cache 104 and L2 cache 106, while the L1 cache 104 and L2 cache 106 are generally implemented using smaller devices in the static random access memory (SRAM) family of devices. In some embodiments, the L2 cache 106, the memory 108, and the mass storage device 110 are shared between one or more processors in the computer system 100.

[0065] In some embodiments, devices in the memory hierarchy (i.e., L1 cache 104, etc.) can access (i.e., read and / or write) multiple cache lines per cycle. These embodiments can more efficiently handle memory accesses that occur based on pointer vectors or array indexes that point to non-contiguous memory addresses.

[0066] It should be noted that the data structures and program instructions (i.e., code) described below can be stored on a non-transitory computer-readable storage device, which can be any device or storage medium that can store code and / or data for use by a computer system (e.g., computer system 100). Generally speaking, non-transitory computer-readable storage devices include, but are not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tapes, compact disks (CDs), digital versatile disks, or digital video disks (DVDs), or other media capable of storing computer-readable media now known or later developed. Therefore, mass storage device 110, memory 108, L2 cache 10, and L1 cache 104 are all examples of non-transitory computer-readable storage media.

[0067] As described above, the execution core 120 can be configured to execute vector instructions (e.g., in the vector execution unit 118). Vector instructions can be defined as single instruction multiple data stream (SIMD) instructions in the classical sense, because they can define the same operation to be performed on multiple data elements in parallel. The data elements operated by the instance of the instruction can be referred to as vectors. The data elements forming the vector can be referred to as vector elements. The vector elements themselves can have any data type (e.g., integer, floating point, etc.), and more than one data type can be supported for the vector elements.

[0068] In one embodiment, register file 112 may include vector registers that may store operand vectors and result vectors. In some embodiments, there may be 32 vector registers in the vector register file. However, in alternative embodiments, there may be different numbers of vector registers and / or different numbers of bits in each register. In addition, embodiments implementing register renaming may include any number of physical registers that may be assigned to architecture vector registers. Architecture registers may be registers that may be designated as operands in vector instructions.

[0069] More specifically, the vector execution unit 118 may be configured to execute the packed auxiliary instructions (or operations decoded from packed auxiliary instructions) described herein, in addition to various vector operations, such as arithmetic operations, logical, operations, shifts.

[0070] Fig.11 is a block diagram of one embodiment of at least a portion of vector execution unit 118, including circuitry configured to execute various compression assist instructions. Fig.11The circuits shown in may include circuits shared with other types of vector operations and / or circuits dedicated to compressed auxiliary instructions, or any combination thereof. Vector execution unit 118 is coupled to the input of the operation to be performed, as well as source operands V1 and V2. The result operation may be specified as part of the operation and may be forwarded to register file 112 along with the result.

[0071] Control circuitry 130 may receive the operation and may control other circuitry in vector execution unit 118 accordingly. Thus, control circuitry 130 may be coupled to Fig.11 The other circuits shown in Fig.11 132. The connections are not explicitly shown in order to avoid complicating the drawings. An adder circuit 132 may be provided, which may be coupled to a second source operand V2. The adder circuit 132 may be configured to add the various elements of the vector V2. For example, when the source operand V2 is a size vector, the sum of the sizes may be used during the execution of the operation. When the result operand is a stack register, the sum of all vector elements may be used for updating the bit count field (n). In addition, the partial sum of the vector elements may also be used.

[0072] For example, the top instruction can be implemented by right shifting the MSB of the stack based on the partial sum and the size of the vector element. In the case of four vector elements, if the size of the vector element is 32 bits, shifting the 32MSB right by 32-b3 can align x3 with the VE3 element in the result vector (e.g., right shift vector element size (Vs)-b3). Similarly, shifting the 64MSB right by 64-(b3+b2) can align x2 with the VE2 element in the result vector (e.g., 2Vs-(b3+b2)); shifting the 96MSB right by 96-(b3+b2+b1) can align x2 with the VE1 element in the result vector (e.g., 3Vs-(b3+b2+b1)); and shifting the 128MSB right by 128-(b3+b2+b1+b0) can align x0 with the VE0 element in the result vector (e.g., 4Vs-(b3+b2+b1+b0)). Other element sizes and numbers of elements can be implemented similarly. Thus, shift circuits 134A through 134N may be coupled to the V1 operand and the corresponding sum from adder circuit 132 to execute the top instruction. Corresponding mask circuits 136A through 136N may be coupled to the outputs of shift circuits 134A through 134N to mask bits that are not part of the vector elements (e.g., since x3 and x2 are adjacent in the source stack register, some bits of x3 may be in the MSB of the VE2 element after the shift and may be masked). Although in Fig.11134A to 134N and mask circuits 136A to 136N are shown, but other embodiments may implement shared shift circuits with control inputs from control circuit 130 to control the shift of each vector element position based on the size of a given vector. That is, the shared shift circuit can be defined to perform 2 64-bit shifts, 4 32-bit shifts, 8 16-bit shifts, or 16 8-bit shifts based on the size of the vector element of a given operand. The control input can select the correct shift to be performed based on the size selected for a given operation. The shift circuits 134A to 134N and mask circuits 136A to 136N can therefore be a specific implementation of extracting a bit field from multiple bits in a source stack register to a vector element of a result vector register.

[0073] A shift circuit 140 may be provided for a pop instruction / operation. The shift circuit 140 may shift the stack register operand left by the sum of the sizes in the size vector register (provided by the adder circuit 132). Thus, the shift circuit 140 may be coupled to the adder 132 and the V1 source operand. Alternatively, the shifter circuits 134A to 134N may be configured to also perform shifts on the pop operation and the shift circuit 136 may not be required. A calculate n circuit 138 may be provided to calculate the updated n for the pop instruction / operation and the create and connect instruction / operation. The calculate n circuit 138 may be coupled to the adder circuit 132 and may receive the sum of the sizes of the vector elements (e.g., b3+b2+b1+b0) to calculate the pop n and create instruction / operation.

[0074] In one embodiment, shift circuits 134A to 134N can also be used to perform create instructions / operations to shift source vector elements to the MSB of the result. For example, the x3 element can be shifted left by the size of the vector element size (Vs) minus the size of the x3 element (b3) (e.g., Vs-b3). The x2 element can be shifted left by twice the size of the vector element size minus the size of the x3 and x2 elements (e.g., 2Vs-(b3+b2)). Similarly, the x1 element can be shifted left by 3Vs-(b3+b2+b1), and the x0 element can be shifted left by 4Vs-(b3+b2+b1+b0). The resulting shift value can be masked and logically ored together to produce multiple bits of output for the result stack register. Therefore, the sum generated by adder circuit 132 can be used by shift circuits 134A to 134N. Adder circuit 132 may be configured to generate a full shift amount that includes the vector element size, or shift circuits 134A through 134N may explicitly or implicitly take the vector element size into account.

[0075] A concatenation instruction / operation may be performed using shift circuit 136 (shift p2 right by n1) and compute n circuit 138 to add n1 and n2 to produce output n. For example, shifted p2 may be logically ORed with p1 to produce the output bits of the result stack register.

[0076] Fig.11 Output selection circuitry 142 is shown to be coupled to mask circuits 136A through 136N, compute-n circuitry 138, and shift circuitry 140, and may be configured to select among the outputs to provide to register file 112 based on the operation being performed. For example, the outputs of mask circuits 136A through 136N connected together may be selected for top instructions, and the outputs of shift circuitry 140 and compute-n circuitry 138 may be selected for pop, create, and connect instructions.

[0077] Please note that Fig.11 The circuit of is only one example of a specific implementation of a portion of the vector execution unit 118. Any other desired circuit may be used. For example, the shift circuit may be a rotation circuit. Any equivalent of the circuit system shown may be used, including Boolean equivalents.

[0078] Figures 12 to 15 1 is a flow chart illustrating the operation of one embodiment of the processor 102 / execution core 120 / vector execution unit 118 to perform various compression assist instructions described herein. However, the blocks are shown in a particular order for ease of understanding, and other orders may be used. The blocks may be executed in parallel in combinatorial logic circuits in the processor 102 / execution core 120 / vector execution unit 118. The blocks, combinations of blocks, and / or the flow chart as a whole may be pipelined over multiple clock cycles.

[0079] Fig.12 1 is a flowchart of an embodiment showing the operation of executing the top instruction. The processor 102 / execution core 120 / vector execution unit 118 can extract the bit field from the MSB of the source stack register based on the source size vector (box 150). For example, the MSB of b3 can be extracted as x3, the next continuous (adjacent) b2 MSB can be extracted as x2, etc. The processor 102 / execution core 120 / vector execution unit 118 can align the bit field with the vector element of the result vector register (box 152). As described above, extraction and alignment can be performed by shifting. Other embodiments can extract the bit field in other ways. The processor 102 / execution core 120 / vector execution unit 118 can write the resulting vector into the result vector register (the vector register identified by the result operand) (box 154).

[0080] Fig.13156. The process flow diagram of the operation of the pop instruction of one embodiment is shown. The processor 102 / execution core 120 / vector execution unit 118 can determine the remaining amount of the stack based on the source size vector (box 156). For example, the processor 102 / execution core 120 / vector execution unit 118 can add the vector elements of the source size vector, and determine that the remaining stack is the stack after multiple MSBs equal to the sum of the vector elements of the source size vector have been removed. The processor 102 / execution core 120 / vector execution unit 118 can shift the bit stack portion of the source stack operand to place the remaining stack in the MSB of the result stack register (box 158). For example, the processor 102 / execution core 120 / vector execution unit 118 can shift the source stack left by the sum of the vector elements of the source size vector. The processor 102 / execution core 120 / vector execution unit 118 can calculate n' as n (box 160) of the sum of the vector elements of the size vector subtracted from the source stack register, and the shifted stack and n' can be written to the result stack register (box 162).

[0081] Fig.14 1 is a flowchart of an embodiment showing the operation of executing a create instruction. The processor 102 / execution core 120 / vector execution unit 118 can extract a bit field from a source vector element based on a source size vector element (box 170). The processor 102 / execution core 120 / vector execution unit 118 can align the bit field with the MSB of the result register (box 172). As previously described, extraction and alignment can be performed by shifting. Other embodiments can perform extraction and alignment in other ways. Once the bit fields are aligned, these bit fields can be adjacent in the result register (for example, the LSB of x3 can be adjacent to the MSB of x2, the LSB of x2 can be adjacent to the MSB of x1, etc.). The processor 102 / execution core 120 / vector execution unit 118 can calculate n as the sum of the size vector elements (box 174) and can write the result stack (MSB) and n (LSB) into the result stack register (box 176).

[0082] Fig.15 1 is a flow chart showing the operation of executing a connect instruction of one embodiment. The processor 102 / execution core 120 / vector execution unit 118 may shift the stack portion of the stack source operand 2 left by n1 (counting the number of bits in the stack portion of the source operand 1) (block 178). The processor 102 / execution core 120 / vector execution unit 118 may merge the stack portion of the source stack 1 with the shifted source stack 2 field (block 180). The processor 102 / execution core 120 / vector execution unit 118 may calculate n equal to the sum of n1 and n2 from source stack register 1 and source stack register 2, respectively (block 182). The processor 102 / execution core 120 / vector execution unit 118 may write the merged stack and n into the result stack register (block 184).

[0083] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. A processor, comprising: a register file, the register file comprising a plurality of vector registers; as well as an execution core coupled to the register file, wherein the execution core is configured to execute a first instruction specifying a first vector operand, a second operand, and a result vector operand, wherein the first vector operand is in a first vector register of the plurality of vector registers, the second operand is in a second register, and the result vector operand is to be written to a third vector register of the plurality of vector registers, wherein the execution core is configured to extract a plurality of variable-sized bit fields from the second operand in response to a plurality of vector elements in the first vector operand, wherein respective vector elements of the plurality of vector elements specify sizes of respective bit fields of the plurality of variable-sized bit fields, and wherein the execution core is configured to write the extracted plurality of variable-sized bit fields as corresponding vector elements in the result vector operand in response to executing the first instruction; and wherein the execution core is configured to execute a second instruction specifying the first vector operand, the second operand, and a second result operand, wherein the second result operand is to be written to a fourth register, and wherein the execution core is configured to remove from the portion of the second operand a number of bits equal to a sum of the number of bits specified by the vector elements of the first vector operand, and in response to executing the second instruction, write a remainder of the portion of the second operand to the fourth register as the second result operand.

2. The processor of claim 1 , wherein the second register is one of the plurality of vector registers, and wherein the execution core is configured to, in response to executing the first instruction, interpret a portion of a value in the second register as a plurality of consecutive bits rather than the plurality of vector elements. 3 . The processor of claim 2 , wherein the second portion of the value is a bit count indicating a number of the plurality of consecutive bits.

4. The processor of claim 1 , wherein the removed bits are most significant bits of the second operand, and wherein the execution core is configured to write a remainder of the portion of the second operand to the most significant bits of the fourth register in response to executing the second instruction.

5. The processor of claim 4 , wherein the execution core is configured to subtract the sum of the number of bits specified by the vector elements of the first vector operand from the bit count to generate a second bit count, and is configured to write the second bit count to the third portion of the fourth register in response to executing the second instruction.

6. The processor of claim 1 , wherein a first bit field of the plurality of variable-sized bit fields comprises a plurality of most significant bits of the second operand, wherein a number of the plurality of most significant bits is specified by a first vector element of the plurality of vector elements in the first vector operand.

7. The processor of claim 6 , wherein a second bit field of the plurality of variable-sized bit fields is adjacent to the first bit field in the second operand, and wherein the number of bits in the second bit field is specified by a second vector element of the plurality of vector elements in the first vector operand, wherein the second vector element is adjacent to the first vector element in the first vector operand.

8. The processor of claim 1 , wherein the execution core is configured to execute a third instruction that specifies a second vector operand in a second vector register of the plurality of vector registers, a third vector operand in a fourth vector register of the plurality of vector registers, and a third result operand, and wherein the execution core is configured to extract a plurality of bit fields from corresponding vector elements of the second vector operand in response to values ​​in corresponding vector elements of the third vector operand, and is configured to write the plurality of bit fields to the third result operand in response to executing the third instruction.

9. The processor of claim 8, wherein the execution core is configured to write the plurality of bit fields to adjacent bits in the first portion of the third result operand in response to executing the third instruction.

10. The processor of claim 9, wherein the execution core is configured to sum the values ​​of the corresponding vector elements of the third vector operand and write the sum to the second portion of the third result operand in response to executing the third instruction.

11. The processor of claim 1 , wherein the execution core is configured to execute a fourth instruction, the fourth instruction having a fifth operand in a fifth register, a sixth operand in a sixth register, and a fourth result operand, and wherein the fifth operand includes a first portion having a first plurality of bits and a second portion having a second bit count indicating a number of the first plurality of bits, and wherein the sixth operand includes a first portion having a second plurality of bits and a second portion having a third bit count indicating a number of the second plurality of bits, and wherein the execution core is configured to concatenate the first plurality of bits and the second plurality of bits in the first portion of the fourth result operand in response to executing the fourth instruction.

12. The processor of claim 11, wherein the execution core is configured to sum the second bit count and the third bit count and write the sum to a second portion of the fourth result operand in response to executing the fourth instruction.

13. The processor of claim 11 , wherein the fifth register, the sixth register, and a fourth result register storing the fourth result operand are included in the plurality of vector registers, and the execution core is configured to interpret values ​​in the fifth register, the sixth register, and the fourth result register as the first part and the second part instead of vector elements in response to executing the fourth instruction.

14. The processor of claim 1 , further comprising: a plurality of shift circuits configured to shift a plurality of variable-sized bit fields from the second operand to vector element positions based on a plurality of vector elements in the first vector operand; as well as A plurality of masking circuits are coupled to corresponding ones of the plurality of shifting circuits and are configured to mask the plurality of variable-sized bit fields based on the plurality of vector elements to thereby produce a plurality of extracted variable-sized bit fields in the vector element positions.

15. The processor of claim 14, wherein the execution core further comprises an adder circuit coupled to the plurality of shift circuits, wherein the adder circuit is configured to sum a subset of the plurality of vector elements and generate a shift amount for the plurality of shift circuits based on the sum of the subset of the plurality of vector elements.

16. The processor of claim 15 , wherein the second register is one of the plurality of vector registers, and wherein the execution core is configured to, in response to executing the first instruction, interpret a portion of a value in the second register as a plurality of consecutive bits rather than the plurality of vector elements, and wherein the second portion of the value is a bit count indicating a number of the plurality of consecutive bits, and wherein the execution core is configured to execute a second instruction specifying the first vector operand, the second operand, and a second result operand, wherein the second result operand is to be written to a fourth register, and wherein the execution core comprises: a second shift circuit configured to shift a portion of the second operand to remove a number of bits equal to a sum of the vector elements of the first vector operand, wherein the second shift circuit is coupled to the adder circuit and the adder circuit is configured to add the vector elements and provide the sum to the second shift circuit as a shift amount; as well as Wherein the execution core is configured to write a remainder of the portion of the second operand to the fourth register as the second result operand in response to executing the second instruction.

17. The processor of claim 16, wherein the execution core is configured to execute a third instruction that specifies a second vector operand in a second vector register of the plurality of vector registers, a third vector operand in a fourth vector register of the plurality of vector registers, and a third result operand, wherein: the plurality of shift circuits configured to shift corresponding vector elements of the second vector operand based on values ​​in corresponding vector elements of the third vector operand; The plurality of mask circuits are configured to mask the shifted vector elements based on the corresponding vector elements of the third vector operand to generate variable-sized bit fields; the execution core is configured to logically OR the variable-sized bit fields to generate a bitstream including the plurality of bit fields in adjacent bits; and The execution core is configured to write the plurality of bit fields to the third result operand in response to executing the third instruction.

18. The processor of claim 16, wherein the execution core is configured to execute a fourth instruction, the fourth instruction having a fifth operand in a fifth register, a sixth operand in a sixth register, and a fourth result operand, and wherein the fifth operand includes a first portion having a first plurality of bits and a second portion having a second bit count indicating a number of the first plurality of bits, and wherein the sixth operand includes a first portion having a second plurality of bits and a second portion having a third bit count indicating a number of the second plurality of bits, wherein: The execution core includes a second shift circuit configured to right shift the second plurality of bits by the second bit count; as well as The execution core is configured to logically OR the shifted second plurality of bits with the first plurality of bits to connect the first plurality of bits and the second plurality of bits in a first portion of the fourth result operand.

19. A method for executing a compression auxiliary instruction, comprising: executing a first instruction in a processor having a register file including a plurality of vector registers, wherein the first instruction specifies a first vector operand, a second operand, and a result vector operand, and wherein the first vector operand is in a first vector register of the plurality of vector registers, the second operand is in a second register, and the result vector operand is to be written to a third vector register of the plurality of vector registers; during the execution, extracting a plurality of bit fields from the second operand in response to a plurality of vector elements in the first vector operand, wherein respective ones of the plurality of vector elements specify sizes of respective ones of the plurality of bit fields; During the execution, writing the extracted plurality of bit fields as corresponding vector elements into the result vector operand, during the executing, executing a second instruction specifying the first vector operand, the second operand, and a second result operand, wherein the second result operand is to be written to a fourth register; as well as During the execution, a number of bits equal to a sum of the number of bits specified by the vector elements of the first vector operand is removed from the portion of the second operand, and in response to executing the second instruction, a remainder of the portion of the second operand is written to the fourth register as the second result operand.

20. A computer program product comprising a computer program which, when executed by a processor, causes the processor to perform the method according to claim 19.

21. A processor, comprising: a register file, the register file comprising a plurality of vector registers; as well as an execution core coupled to the register file, wherein the execution core is configured to execute a first instruction that specifies a first vector operand, a second operand, and a result operand, wherein the first vector operand is in a first vector register of the plurality of vector registers, the second operand is in a second register, and the result operand is in a third register, wherein the execution core is configured to remove from a portion of the second operand a number of bits that is equal to a sum of the number of bits specified by vector elements of the first vector operand and, in response to executing the first instruction, write a remainder of the portion of the second operand to the third register as a corresponding portion of the result operand.

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