Reuse of adjacent SIMD units for fast wide result generation

Abstract

A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for executing processor instructions. The system also includes a second instruction execution unit having a second result bus for executing processor instructions. The first instruction execution unit is configured to, during execution of the processor instruction, selectively send a portion of a result calculated by the first instruction execution unit to the second instruction execution unit if the second instruction execution unit is not used to execute the processor instruction and if the received processor instruction produces a result having a data width greater than a width of the first result bus. The second instruction execution unit is configured to receive the portion of the result calculated by the first instruction execution unit and place the received result on the second result bus.

Description

Background Art

[0001] The present invention relates to the field of computer systems, and more particularly to the reuse of adjacent SIMD (Single Instruction Multiple Data) units to process instructions that produce results of wider width.

[0002] In order to improve computing performance in the face of diminishing benefits from one generation of silicon technology improvements, designs have moved to implement more complex computing primitives. In general-purpose microprocessors, such computing primitives are typically in the form of extended instruction sets implemented on accelerators that are tightly coupled to a processor core responsible for implementing the standard (traditional) instruction set. The accelerator implements a short vector SIMD computing model, whereby each instruction specifies an operation to be performed across a wide data word, which is interpreted as a vector of a small number (1-16) of sub-words, depending on the specific instruction. A single instruction can then specify multiple operations on multiple data segments. Summary of the invention

[0003] Embodiments of the present invention relate to a system for processing instructions with extended results. The system includes a first instruction execution unit having a first result bus for executing processor instructions. The system also includes a second instruction execution unit having a second result bus for executing processor instructions. The second instruction execution unit is communicatively coupled to the first instruction execution unit. The first instruction execution unit is configured to selectively send a portion of a result calculated by the first instruction execution unit to the second instruction execution unit during execution of the processor instruction if the second instruction execution unit is not used to execute the processor instruction. The second instruction execution unit is configured to receive the portion of the result calculated by the first instruction execution unit and place the received result on the second result bus.

[0004] Embodiments of the present invention relate to a method for processing instructions with extended results. The method includes determining whether a received processor instruction produces a result having a data width greater than a width of a first result bus of a first instruction execution unit and greater than a width of a second result bus of a second instruction execution unit. In response to determining that the received processor instruction produces a result having a data width greater than a width of the first result bus and greater than a width of the second result bus, determining whether the second instruction execution unit is not used to execute the received processor instruction. The second instruction execution unit is communicatively coupled to the first instruction execution unit. In response to determining that the second instruction execution unit is not used to execute the processor instruction, a portion of a result calculated by the first instruction execution unit during execution of the processor instruction is selectively sent to the second result bus of the second instruction execution unit.

[0005] Embodiments of the present invention relate to a computer program product for processing instructions with extended results. The computer program product includes a computer-readable storage medium having program instructions embodied thereon. The program instructions are executable by a processor to cause the processor to perform a method. A non-limiting example of the method includes determining whether a received processor instruction produces a result having a data width greater than a width of a first result bus of a first instruction execution unit and greater than a width of a second result bus of a second instruction execution unit. In response to determining that the received processor instruction produces a result having a data width greater than a width of the first result bus and greater than a width of the second result bus, determining whether the second instruction execution unit is not used to execute the received processor instruction. The second instruction execution unit is communicatively coupled to the first instruction execution unit. In response to determining that the second instruction execution unit is not used to execute the processor instruction, a portion of the result calculated by the first instruction execution unit is selectively sent to the second result bus of the second instruction execution unit during execution of the processor instruction.

[0006] Additional technical features and benefits are achieved through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered to be part of the claimed subject matter. For a better understanding, reference is made to the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The details of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A high-level block diagram of a data processing system having multiple single instruction multiple data (SIMD) execution units according to an embodiment of the present invention is shown;

[0009] Figure 2 is a high-level block diagram illustrating components within a SIMD execution unit and an interface between the SIMD execution unit and a data processing system according to an embodiment of the present invention;

[0010] Figure 3 is a diagram illustrating logic for reusing unused result outputs of adjacent SIMD execution units according to an embodiment of the present invention;

[0011] Figure 4 is a diagram illustrating an enhanced vector floating point load extended double precision (DP) instruction according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram illustrating a dynamic channel masking function according to an embodiment of the present invention; and

[0013] Figure 6is a flowchart of a method for reusing adjacent SIMD execution units for fast wide result generation according to an embodiment of the present invention.

[0014] The figures described here are illustrative. Without departing from the spirit of the present invention, many changes may be made to the figures or operations described therein. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. In addition, the term "coupled" and its variations describe having a communication path between two elements, and do not imply a direct connection between elements without an intermediate element / connection between the elements. All of these changes are considered part of the specification.

[0015] In the drawings and the following detailed description of the disclosed embodiments, various elements shown in the drawings have double or triple reference numerals. With minor exceptions, the leftmost digit of each reference numeral corresponds to the figure in which its element is first shown. DETAILED DESCRIPTION

[0016] Typically, processors with a single instruction multiple data (SIMD) architecture are designed to maximize the amount of parallel processing in an instruction pipeline. In a SIMD architecture, the same instruction is executed in parallel to process multiple data inputs. SIMD instructions specify the execution and branching behavior of a single control thread that controls the operation of a vector of multiple data inputs. A vector is an instruction operand that includes a set of data elements packed into a one-dimensional array. An element can be an integer or a floating point value. Most SIMD instructions operate on vector operands. Vectors are also referred to as SIMD operands or grouped operands. Operands and data path widths define how much data can be processed at once; wider data paths can perform more complex functions, but this is usually achieved at a higher implementation cost. In addition, some vector instructions produce results of wider widths compared to instruction input elements. Exemplary instructions that produce wider results include, but are not limited to, instructions that convert data into larger data formats, multiplication operations, etc. Binary floating point numbers can be represented in any of three data formats: short, long, or extended. As a non-limiting example, the short format includes 32 bits, the long format includes 64 bits, and the extended format includes 128 bits. Therefore, the conversion from short format to long format or from long format to extended format produces a wider width result. Due to the wiring limitations on the chip, the result bus used by the SIMD execution unit in the traditional data processing system provides a result with limited size. It should be noted that even if the adjacent SIMD execution unit is not currently used, the traditional data processing system performs the above operation to produce a wider result over multiple instruction cycles. This inefficiency actually reduces the throughput of the data processing system and increases latency.

[0017] Conventional data processing systems use different approaches to solve these problems. Some conventional systems use a split instruction transaction model with pipeline operation. This model requires at least two coprocessors, where the instruction is divided into a low part and a high part, and each coprocessor executes the corresponding part. Using this method, at least two coprocessor instructions are required to execute the operation in the coprocessor and obtain the operation result from the coprocessor. For example, the first coprocessor can perform the high part of the multiplication operation, and the second processor can perform the low part of the multiplication operation. In contrast, embodiments of the present invention use a single transaction model, where only a single coprocessor instruction is required to initiate the operation and provide the result of the operation.

[0018] In general, pipelining improves central processing unit (CPU) performance primarily by reducing cycles per instruction (CPI), although it can also reduce CPU clock cycles to a lesser extent. Pipelining is a technique that breaks instruction execution into a series of steps. Each step in the pipeline, called a pipeline stage, completes a specified portion of the complete execution of an instruction. Each pipeline stage increases execution in the same way that stations of an assembly line increase the complete manufacture of a product. An instruction causes the last pipeline stage of the pipeline to be fully executed, just as a product causes an assembly line to be fully assembled.

[0019] Ideally, a number of instructions equal to the number of pipeline stages comprising the pipeline can overlap when executed, with each instruction occupying a different pipeline stage. If the CPU has sufficient resources, and earlier pipeline stages do not depend on the completion results of later pipeline stages, each pipeline stage can independently perform its function (according to the instruction currently occupying it) in parallel with other pipeline stages. In addition, if the average time required for the CPU to fully execute an instruction is divided equally between the pipeline stages, the speedup of CPU throughput for pipeline execution over sequential execution will be equal to the number of pipeline stages. Therefore, for an ideal pipeline comprising five pipeline stages, five instructions will be executed sequentially in the average time required to execute one instruction; the speedup in throughput is five times. Note that pipelining does not reduce the average time to execute a single instruction, but rather reduces the total average execution time by completing more instructions per unit time.

[0020] In order to handle the wider results generated by the execution of floating-point operations, some pipeline data processing systems use multiple cycles (as many as are required to complete the operation) to write the results. This method requires blocking the pipeline until the register write-back (WB) operation is completed. It should be noted that both of the above methods adopted by conventional data processing systems reduce bandwidth and increase latency because they both require multiple instructions to produce operation results and / or they both require multiple cycles to write results. Another disadvantage of the above methods is that they require additional multiplexing capabilities to recombine data elements associated with the results of the operations performed. Another disadvantage is that the additional instructions required due to the necessity of rearranging data between processing levels reduce code density and require more storage in memory and cache. It should be noted that each additional cycle required during the data forwarding stage generally results in an increased workload on the processor.

[0021] A different conventional approach to handling instructions that produce wider outputs is to utilize a wider data bus. However, this approach is also not very efficient because of the additional complexity in the design and higher implementation costs. Also, because only a limited number of instructions require this capability, this particular approach often results in underutilization of the wider data bus.

[0022] In general, vector SIMD engines with specialized instructions that provide larger outputs and have lane masking capabilities can be used to solve many current problems. For example, at least some artificial intelligence (AI) engines process small precision inputs to accumulate and generate higher precision outputs. Embodiments of the present invention solve all of the above problems by utilizing unused adjacent SIMD engines to generate wider results.

[0023] Referring now to the drawings, and in particular to Figure 1 , wherein a high-level block diagram of a data processing system with a SIMD execution unit according to an embodiment of the present invention is shown. As shown, the data processing system 100 includes a SIMD engine 102, which is coupled to a memory 114 via an instruction bus 108 and an address bus 110. The SIMD engine 102 fetches instructions from the memory 114 and dispatches these instructions to the selected SIMD execution units 106a-106c via an instruction dispatch bus 112. The memory 114 can be implemented at different levels with different speeds and capacities. This level of memory can be constructed so that from the perspective of any particular level in the hierarchy, the next lower level from the processor is considered to be a cache. A cache memory is an auxiliary memory that provides a buffering capability, by which a relatively slow and increasingly large main memory can be connected to the SIMD engine 102 (or the next higher level memory) through an interface at a cycle time that is closer to the SIMD engine 102 cycle time.

[0024] exist Figure 1 In the example shown, the plurality of execution units 106a-106c are SIMD execution units. Thus, within the data processing system 100, the SIMD engine 102 is interfaced with the SIMD execution units 106a-106c as other "execution classes" in the class of execution units in the data processing system 100. In at least some embodiments, the SIMD execution units 106a-106c can be used to perform floating point arithmetic operations and other operations. The SIMD execution units 106a-106c are coupled to the memory 114 via the buses 118a-118c.

[0025] Another execution unit within data processing system 100 may include, for example, load / store execution unit 104. Load / store execution unit 104, coupled to memory 114 via bus 116, is used to calculate addresses and provide the addresses to memory 114 during execution of instructions requiring memory access. Load / store execution unit 104 may be used to provide addresses to memory 114 during execution of instructions in other execution units.

[0026] Reference now Figure 2 , which shows a high-level block diagram further illustrating components within a SIMD execution unit and an interface between the SIMD execution unit and a data processing system according to an embodiment of the present invention. As shown, the SIMD execution unit 106 includes a control unit 202 and a plurality of processing elements 204. The control unit 202 dispatches commands to selected processing elements 204 via a command bus 206. The control unit 202 transmits data to and receives data from the processing elements 204 via a data bus 208. Each processing element 204 is coupled to the control unit 202 by a separate data bus 208.

[0027] The control unit 202 receives vector processing instructions from the CPU 210 via an instruction bus 212. A second level cache (L2 cache) 214 may be used to store data and instructions for all execution units, including the SIMD execution unit 106. The L2 cache 214 is coupled to the CPU 210 via a data bus 216. The L2 cache 214 is also coupled to the control unit 202 within the SIMD execution unit 106 via a data bus 218. A cache controller 220 provides address signals to the L2 cache 214. The L2 cache 214 may be accessed by the load / store execution unit 104 (see Figure 1 ) calculates the address used to generate such address signal.

[0028] Figure 3 is a diagram illustrating logic for reusing unused result outputs of adjacent SIMD execution units according to an embodiment of the present invention. Figure 3The SIMD execution units 106a and 106b shown on the left side adopt a split instruction transaction model. SIMD execution units 106a and 106b receive corresponding inputs 302a and 302b and generate corresponding outputs 304a and 304b. If the operation to be performed is expected to produce a wider result, SIMD execution units 106a and 106b use multiple cycles to perform the operation. In contrast, according to an embodiment of the present invention, Figure 3 The SIMD execution units 106a-106d shown on the right adopt both the split instruction transaction model and the single transaction model, and are configured to selectively reuse unused result outputs of adjacent SIMD execution units to deliver wider results. Advantageously, the disclosed single transaction model significantly increases the throughput and reduces latency of the data processing system 100. In addition, the single transaction model eliminates the need to implement a larger result bus 304.

[0029] More specifically, Figure 3 The exemplary configuration shown on the right side includes a first SIMD execution unit 106a, a second SIMD execution unit 106b, a third SIMD execution unit 106c, and a fourth SIMD execution unit 106d. The first SIMD execution unit 106a is connected to the second SIMD execution unit 106b via a first local connection 308a, and the third SIMD execution unit 106c is connected to the fourth SIMD execution unit 106d via a second local connection 308b. Figure 3 As shown, the second SIMD execution unit 106b and the fourth SIMD execution unit 106d include multiplexers 310b and 310d, respectively. The first multiplexer 310b is configured to select and combine the result calculated by the second SIMD execution unit 106b and a portion of the result calculated by the adjacent first SIMD execution unit 106a, as described herein. The second multiplexer 310d is configured to select and combine the result calculated by the fourth SIMD execution unit 106d and a portion of the result calculated by the adjacent third SIMD execution unit 106c. It can be noted that the adjacent second SIMD execution unit 106b and the fourth SIMD execution unit 106d are selectively used by the data processing system 100 only when they are available during the operation being performed.

[0030] According to an embodiment of the present invention, a subset of instructions is implemented, in which the instructions perform calculations directly on two adjacent SIMD execution units to produce wider results in one cycle. In one embodiment, the implemented instructions can use binary floating point data. In particular, an embodiment of the present invention eliminates the need to use additional wiring and logic to put back the results of instruction execution, allowing them to be executed with a small amount of additional logic in one cycle; thereby improving performance and reducing power consumption. These instructions include, for example, load extension (also known as load extension) instructions. However, since the load extension instruction operates on binary floating point numbers, details related to binary floating point numbers are initially provided. Binary floating point numbers can have a variety of formats, including, for example, 32-bit, 64-bit, and 128-bit formats, and each format has a format that includes, for example, a sign 410, an exponent 412, and a valid number 416 ( Figure 4 ) as shown in .

[0031] Typically, a load-extend instruction uses double-precision floating-point inputs and produces extended double-precision floating-point outputs (ie, outputs that are larger than the inputs received by the instruction). Figure 4 is a diagram illustrating enhancements to a vector floating point load extended double precision (DP) instruction according to an embodiment of the present invention. Figure 4 As shown, the conventional vector floating point load extend instruction requires two cycles (a first cycle 402 and a second cycle 404) to complete its operation using 64 bits. During the first cycle 402, the conventional vector floating point load extend instruction operates on a portion 406 (e.g., a low portion) of the significand 416. The size of the significand 416 is too large to be operated during the second cycle 404. During the second cycle 404, the conventional vector floating point load extend instruction operates on other portions of the floating point number (e.g., the sign 410, the exponent 412, and the second portion 414 (high portion) of the significand 416).

[0032] also, Figure 4 An enhanced vector floating point load extend DP instruction 420 implementation is shown according to an embodiment of the present invention. The enhanced vector floating point load extend instruction operates on 128 bits 422, 424. Compared to conventional vector floating point load extend instructions, the enhanced vector floating point load extend DP instruction 420 operates on all components 406 and 414 of the floating point number in one cycle. As described herein, the enhanced vector floating point load extend instruction can utilize the result bus of adjacent SIMD execution units to complete operations that produce wider results in one cycle.

[0033] In SIMD computers, as well as other types of computers, a basic concept commonly referred to as masking is required in order to conditionally perform individual operations in processing elements. Masking enables different instructions in an instruction sequence applied to a processing element to be implemented only in those processing elements where the specific data applied to a separate processing element satisfies the conditions of the specific instruction in the sequence. Different techniques for masking a specific processing element from certain instructions in an instruction sequence applied to a processing element are known in the art. A detailed overview of modern SIMD machines using masking can be found in Horde, R. Michael, "Parallel Supercomputing in SIMD Architectures" by 1990 CRC Press Inc, Boca Raton, Fla. In addition, U.S. Patents 4,907,148 and 5,045,995 also provide discussions of masking in these types of systems.

[0034] Figure 5 is a diagram illustrating a dynamic channel masking function according to an embodiment of the present invention. Figure 5 An exemplary multiplication operation performed by a SIMD circuit 500 having 8 channels (SIMD execution units) 106a-106h with channel masking capability is schematically shown. In one embodiment, each of the plurality of SIMD execution units 106a-106h includes a mask register. In one embodiment, the mask register may also include a mask context register that holds a single mask context (MC) bit and a global response flag register that holds a single global response flag (GRF) bit. The mask context bit is bitwise ANDed with a bit selected for a specific machine operation in a masking instruction to enable or disable a specific SIMD processing unit during an instruction call, as will be described in more detail below.

[0035] The SIMD execution units 106a-106h within the circuit 500 receive the input data elements 302a-302h and perform the required multiplications thereon, thereby generating corresponding result data elements 304a-304h. Assuming that each input data element is 32 bits wide, each multiplication data element will be at least 64 bits wide. In addition, the SIMD engine 102 ( Figure 1 The SIMD engine 102 includes logic for controlling the selective execution of instructions by adjacent SIMD processing elements 106a-106h. The plurality of SIMD execution units 106a-106h are configured to utilize the result bus of the adjacent SIMD processing units to produce a wider result, as described herein. The SIMD engine 102 is configured to instruct the selected SIMD execution unit 106a-106h to execute the current instruction within one cycle. Figure 5In the example shown, the second SIMD execution unit 106b, the fourth SIMD execution unit 106d, the sixth SIMD execution unit 106f, the seventh SIMD execution unit 106g, and the eighth SIMD execution unit 106h are masked. According to one embodiment of the present invention, the first SIMD execution unit 106a, the third SIMD execution unit 106c, and the fifth SIMD execution unit 106e are configured to use the result bus of the corresponding adjacent masked SIMD execution unit, such as Figure 5 In one embodiment, adjacent masked SIMD execution units are configured to delay processing of any instruction until a corresponding portion of a computation result is received from a corresponding SIMD execution unit.

[0036] Figure 6 6 is a flow chart of a method for reusing adjacent SIMD execution units for fast wide result generation according to an embodiment of the present invention. In block 602, the SIMD engine 102 loads the next instruction to be processed into an issue buffer. The SIMD instruction is held in the issue buffer until all lane mask dependencies are resolved.

[0037] At block 604, the SIMD execution unit 106 determines whether the received instruction represents a SIMD operation that produces a wide result. For example, the SIMD execution unit 106 may be requested to perform a multiplication where each input data element is 32 bits wide and the result data element is at least 64 bits wide and wider than the result bus. Some other examples of SIMD operations that produce wider results may include, but are not limited to, conversion from short format to long format, conversion from long format to extended format, etc. In response to determining that the received instruction does not represent an operation that produces a wide result (decision block 604, "no" branch), at block 608, the SIMD execution unit 106 issues the instruction in a conventional independent mode.

[0038] According to an embodiment of the present invention, in response to determining that the received instruction represents an operation that produces a wide result (decision block 604, "yes" branch), at block 606, SIMD execution unit 106 determines whether an adjacent SIMD execution unit is available (masked or unused). For example, referring to Figure 5 , the first SIMD execution unit 106a may be configured to determine whether the second SIMD execution unit 106b is masked.

[0039] According to an embodiment of the present invention, in response to determining that the adjacent SIMD execution unit is not available (decision block 606, "no" branch), at block 610, SIMD execution unit 106 issues a signal such as: Figure 4If the SIMD execution unit 106 determines that the adjacent SIMD execution unit is available (decision block 606, "yes" branch), then at block 612, the SIMD execution unit 106 issues the following instructions: Figure 4 The instruction shown is a new one cycle wide operation 420. At block 614, the SIMD execution unit performs the operation associated with the issued instruction.

[0040] Aspects of the present invention are described herein with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to embodiments of the present invention. It will be understood that each frame of the flow chart and / or block diagram and the combination of frames in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0041] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0042] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CDROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0043] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0044] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming language or similar programming languages). The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider through the Internet). In certain embodiments, in order to perform various aspects of the present invention, the electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0045] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0046] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0047] Various embodiments of the present invention are described herein with reference to the relevant drawings. Without departing from the scope of the present invention, alternative embodiments of the present invention may be designed. In the following description and accompanying drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described. Unless otherwise indicated, these connections and / or positional relationships may be direct or indirect, and the present invention is not intended to be limited in this respect. Therefore, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect positional relationships. In addition, various tasks and process steps described herein may be incorporated into a more comprehensive program or process with additional steps or functionality not described in detail herein.

[0048] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "including," "having," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0049] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect "connections" and direct "connections."

[0050] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time this application was filed. For example, "about" may include a range of ±8% or 5% or 2% of a given value.

[0051] The description of various embodiments of the present invention will be presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand.

[0052] Flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in flow chart or block diagram can represent the module, segment or part of instruction, and it comprises one or more executable instructions for realizing the logical function of appointment.In some alternative embodiments, the function mentioned in the frame may not occur in the order mentioned in the figure.For example, two frames shown continuously can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved.It will also be noted that the combination of the frame in each frame of block diagram and / or flow chart illustration and block diagram and / or flow chart illustration can be realized by the dedicated hardware-based system of performing specified function or action or performing the combination of special hardware and computer instruction.

Claims

1. A system for processing an instruction with an extended result, the system comprising: a memory having computer readable instructions; as well as One or more processors for executing the computer-readable instructions, the one or more processors comprising a first instruction execution unit and a second instruction execution unit, the computer-readable instructions controlling the one or more processors to perform operations, the operations comprising: receiving a processor instruction at the first instruction execution unit, the processor instruction producing a result having a data width greater than a width of a first result bus of the first instruction execution unit, the first instruction execution unit being communicatively coupled to the second instruction execution unit, and the first instruction execution unit and the second instruction execution unit being configured to perform the same operation on different input data, determining whether the second instruction execution unit is masked; In response to determining that the second instruction execution unit is masked: issuing the processor instruction as a single cycle width operation instruction to the first instruction execution unit; and selectively sending a portion of the result calculated by the first instruction execution unit to the second instruction execution unit for output on a second result bus of the second instruction execution unit, wherein the result of the processor instruction is output by the first result bus and the second result bus in the same calculation cycle; and In response to determining that the second instruction execution unit is not masked: issuing the processor instruction as a two cycle narrow operation instruction to the first instruction execution unit; and The result calculated by the first instruction execution unit is output on the first result bus, and is output within multiple calculation cycles.

2. The system according to claim 1, wherein: The first instruction execution unit and the second instruction execution unit comprise single instruction multiple data (SIMD) processing units, and wherein the processor instructions comprise SIMD instructions.

3. The system according to claim 2, wherein: The first instruction execution unit and the second instruction execution unit include a mask register, and wherein the mask register is configured to store a predefined lane mask.

4. The system according to claim 1, wherein: The width of result data produced by the executed processor instruction is greater than the width of the second result bus.

5. The system according to claim 1, wherein: The first instruction execution unit is arranged adjacent to the second instruction execution unit.

6. The system according to claim 1, wherein: The processor instructions include vector floating point FP load extend instructions.

7. The system according to claim 1, wherein: The processor instructions are executed in one computation cycle.

8. The system according to claim 1, wherein: The first instruction execution unit and the second instruction execution unit are configured to adopt a single transaction model.

9. A method for processing an instruction with an extended result, the method comprising: receiving a processor instruction at a first instruction execution unit, the processor instruction producing a result having a data width greater than a width of a first result bus of the first instruction execution unit, the first instruction execution unit being communicatively coupled to a second instruction execution unit, and the first instruction execution unit and the second instruction execution unit being configured to perform the same operation on different input data; determining whether the second instruction execution unit is masked; In response to determining that the second instruction execution unit is masked: issuing the processor instruction as a single cycle width operation instruction to the first instruction execution unit; and selectively sending a portion of the result calculated by the first instruction execution unit to the second instruction execution unit for output on a second result bus of the second instruction execution unit, wherein the result of the processor instruction is outputted by the first result bus and the second result bus in the same calculation cycle; as well as In response to determining that the second instruction execution unit is not masked: issuing the processor instruction as a two cycle narrow operation instruction to the first instruction execution unit; and The result calculated by the first instruction execution unit is output on the first result bus, and is output within multiple calculation cycles.

10. The method according to claim 9, wherein: The first instruction execution unit and the second instruction execution unit comprise single instruction multiple data (SIMD) processing units, and wherein the processor instructions comprise SIMD instructions.

11. The method according to claim 10, wherein: The first instruction execution unit and the second instruction execution unit include a mask register, and wherein the mask register is configured to store a predefined lane mask.

12. The method according to claim 9, wherein: The first instruction execution unit is arranged adjacent to the second instruction execution unit.

13. The method according to claim 9, wherein: The processor instructions include vector floating point FP load extend instructions.

14. The method according to claim 9, wherein: The processor instructions are executed in one computation cycle.

15. The method according to claim 9, wherein: The first instruction execution unit and the second instruction execution unit are configured to adopt a single transaction model.

16. A computer program product for processing instructions with extended results, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform a method comprising: receiving a processor instruction at a first instruction execution unit, the processor instruction producing a result having a data width greater than a width of a first result bus of the first instruction execution unit, the first instruction execution unit being communicatively coupled to a second instruction execution unit, and the first instruction execution unit and the second instruction execution unit being configured to perform the same operation on different input data; determining whether the second instruction execution unit is masked; In response to determining that the second instruction execution unit is masked: issuing the processor instruction as a single cycle width operation instruction to the first instruction execution unit; and selectively sending a portion of the result calculated by the first instruction execution unit to the second instruction execution unit for output on a second result bus of the second instruction execution unit, wherein the result of the processor instruction is outputted by the first result bus and the second result bus in the same calculation cycle; as well as In response to determining that the second instruction execution unit is not masked: issuing the processor instruction as a two cycle narrow operation instruction to the first instruction execution unit; and The result calculated by the first instruction execution unit is output on the first result bus, and is output within multiple calculation cycles.

17. The computer program product of claim 16, wherein: The first instruction execution unit and the second instruction execution unit comprise single instruction multiple data (SIMD) processing units, and wherein the processor instructions comprise SIMD instructions.

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