Memory device with dual transistor vertical memory cell and common plate

Abstract

Some embodiments include a device and a method of forming said device. One of the devices includes a data line, a memory cell coupled to the data line, a ground connection, and a wire. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The wire is electrically separated from the first region and the second region and crosses a portion of the first region of the first transistor and a portion of the second region of the second transistor, and forms the gate of the first transistor and the second transistor.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 62 / 892,982, filed on August 28, 2019, which is incorporated herein by reference in its entirety. Background Technology

[0003] Memory devices are widely used in computers and many other electronic devices to store information. They are generally classified into two types: volatile memory devices and non-volatile memory devices. Memory devices typically have numerous memory cells for storing information. In volatile memory devices, if the power supply is disconnected from the memory device, the information stored in the memory cells is lost. In non-volatile memory devices, the information stored in the memory cells is retained even if the power supply is disconnected.

[0004] The description in this article relates to volatile memory devices. Most conventional volatile memory devices store information as electrical charge in a capacitor structure contained within the memory cell. As the demand for device storage density increases, many conventional techniques offer methods for reducing the size of memory cells to increase the device storage density for a given device area. However, if the memory cell size needs to be reduced to a certain size, physical limitations and manufacturing constraints can pose challenges to such conventional techniques. Unlike some conventional memory devices, the memory device described in this article incorporates features that overcome the challenges faced by conventional techniques. Attached Figure Description

[0005] Figure 1 A block diagram illustrating a device in the form of a memory device including volatile memory cells, according to some embodiments described herein.

[0006] Figure 2 A schematic diagram showing a portion of a memory device according to some embodiments described herein, the memory device comprising a memory array of dual-transistor (2T) memory cells.

[0007] Figure 3 Demonstrating some embodiments according to the description herein Figure 2 The memory device includes the instance voltage used during read operations of the memory device.

[0008] Figure 4 Demonstrating some embodiments according to the description herein Figure 2 The memory device includes the instance voltage used during write operations of the memory device.

[0009] Figure 5, Figure 6 , Figure 7 and Figure 8 Demonstrating some embodiments according to the description herein Figure 2 Different views of the structure of the memory device.

[0010] Figures 9 to 22 The process of forming a memory device according to some embodiments described herein is illustrated.

[0011] Figures 23 to 28 The process for forming a memory device according to some embodiments described herein includes a shielding structure between adjacent memory cells.

[0012] Figure 29A , Figure 29B and Figure 29C Different views illustrating the structure of a memory device according to some embodiments described herein, the memory device comprising multiple stacks of memory cells. Detailed Implementation

[0013] The memory device described herein includes volatile memory cells, each of which may include two transistors (2T). One of the two transistors has a charge storage structure that forms a memory element of the memory cell to store information. The memory device described herein may have a structure that allows the size of the memory device to be relatively smaller than that of a similar conventional memory device (e.g., a 4F2 cell occupying an area). The described memory device may include a single access line (e.g., a word line) to control the two transistors of the memory cell. This can result in reduced power dissipation and improved processing. Each of the memory cells of the described memory device may include a cross-point gain cell structure (and cross-point operation) such that the memory cell can be accessed using a single access line (e.g., a word line) and a single data line (e.g., a bit line) during operation of the memory device (e.g., a read or write operation). See below. Figures 1 to 29C Discuss other improvements and benefits of the described memory device and its variations.

[0014] Figure 1This diagram illustrates a device in the form of a memory device 100 comprising volatile memory cells, according to some embodiments described herein. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 may include volatile memory devices such that memory cells 102 may be volatile memory cells. Examples of the memory device 100 include dynamic random access memory (DRAM) devices. If power supply (e.g., supply voltage Vcc) is disconnected from the memory device 100, information stored in the memory cells 102 of the memory device 100 may be lost (e.g., invalidated). Hereinafter, the supply voltage Vcc is referred to as representing some voltage level; however, it is not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator that generates an internal voltage based on the supply voltage Vcc... Figure 1 If (not shown in the text), then this internal voltage can be used instead of the supply voltage Vcc.

[0015] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed (e.g., stacked on different layers) in different layers above a substrate (e.g., a semiconductor substrate) of the memory device 100. The memory device 100 may also include multiple layers (e.g., multiple stacks) of memory cells, wherein one layer (e.g., one stack) of memory cells may be formed above (e.g., another stack) of additional memory cells (e.g., stacked on another layer). The structure of the memory array 101 including the memory cells 102 may include, as described below. Figures 2 to 29C The structure of the memory array and memory cells described.

[0016] like Figure 1 As shown, memory device 100 may include access lines 104 (e.g., "word lines") and data lines (e.g., bit lines) 105. Memory device 100 may use signals on access lines 104 (e.g., word line signals) to access memory cells 102, and use signals on data lines 105 to provide information (e.g., data) to be stored (e.g., written) to or read from memory cells 102 (e.g., sensed).

[0017] Memory device 100 may include an address register 106 for receiving address information ADDR (e.g., column address signals and row address signals) on lines (e.g., address lines) 107. Memory device 100 may include a column access circuitry (e.g., an X decoder) 108 and a row access circuitry (e.g., a Y decoder) 109 operable to decode the address information ADDR from address register 106. Based on the decoded address information, memory device 100 may determine which memory cells 102 to access during memory operation. Memory device 100 may perform write operations to store information in memory cells 102 and read operations to read (e.g., sense) information in memory cells 102 (e.g., previously stored information). Memory device 100 may also perform operations to refresh the values ​​of information stored in memory cells 102 (e.g., keep the values ​​valid) (e.g., refresh operations). Each of the memory cells 102 can be configured to store information that may represent a single bit (e.g., a single bit with binary 0 ("0") or binary 1 ("1")) or more than one bit (e.g., multiple bits with a combination of at least two binary bits).

[0018] The memory device 100 may receive supply voltages, including supply voltages Vcc and Vss on lines 130 and 132, respectively. The supply voltage Vss may operate at ground potential (e.g., having a value of approximately zero volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an AC-to-DC converter circuitry.

[0019] like Figure 1 As shown, memory device 100 may include a memory control unit 118, which includes circuitry (e.g., hardware components) for controlling memory operations (e.g., read and write operations) of memory device 100 based on control signals on line (e.g., control line) 120. Examples of signals on line 120 include column access strobe signal RAS*, row access strobe signal CAS*, write enable signal WE*, chip select signal CS*, clock signal CK, and clock enable signal CKE. These signals may be part of the signals provided to the DRAM device.

[0020] like Figure 1As shown, memory device 100 may include lines (e.g., global data lines) 112 capable of carrying signals DQ0 to DQN. During a read operation, the value (e.g., "0" or "1") of information provided to line 112 (read from memory cell 102) (in the form of signals DQ0 to DQN) may be based on the value of a signal on data line 105. During a write operation, the value (e.g., "0" or "1") of information provided to data line 105 (to be stored in memory cell 102) may be based on the value of signals DQ0 to DQN on line 112.

[0021] Memory device 100 may include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Row access circuitry 109 may selectively activate signals on lines (e.g., selection lines) based on address signal ADDR. Selection circuitry 115 may respond to signals on line 114 to select signals on data line 105. Signals on data line 105 may represent the value of information to be stored in memory cell 102 (e.g., during a write operation) or the value of information read from memory cell 102 (e.g., sensed) (e.g., during a read operation).

[0022] I / O circuitry 116 is operable to provide information read from memory cell 102 to line 112 (e.g., during a read operation) and to provide information from line 112 (e.g., provided by an external device) to data line 105 for storage in memory cell 102 (e.g., during a write operation). Line 112 may contain nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., a hardware memory controller or hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0023] The memory device 100 may include other components, said components in Figure 1 Examples of embodiments not shown herein are not illustrated to avoid confusion with those described herein. At least a portion of memory device 100 (e.g., a portion of memory array 101) may contain components similar to or identical to those described below. Figures 2 to 29C The structure and operation of any of the described memory devices.

[0024] Figure 2 A schematic diagram illustrating a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to... Figure 1 The memory device 100. For example, the memory array 201 may be formed Figure 1 A portion of the memory array 101. For example... Figure 2As shown, memory device 200 may include memory cells 210 to 215, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements in memory cells 210 to 215 are given the same designation.

[0025] Each of memory cells 210 to 215 may include two transistors T1 and T2. Therefore, each of memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of transistors T1 and T2 may include a field-effect transistor (FET). As an example, transistor T1 may be a p-channel FET (PFET), and transistor T2 may be an n-channel FET (NFET). A portion of transistor T1 may include the structure of a p-channel metal-oxide-semiconductor (PMOS) transistor FET (PFET). Therefore, transistor T1 may operate similarly to a PMOS transistor. A portion of transistor T2 may include an n-channel metal-oxide-semiconductor (NMOS) transistor. Therefore, transistor T2 may operate similarly to an NMOS transistor.

[0026] The transistor T1 of the memory device 200 may include a charge memory-based structure (e.g., based on a floating gate). Figure 2 As shown, each of memory cells 210 to 215 may include a charge storage structure 202, which may include a floating gate of transistor T1. The charge storage structure 202 may form a memory element of a respective memory cell among memory cells 210 to 215. The charge storage structure 202 may store charge. The value of information stored in a particular memory cell among memory cells 210 to 215 (e.g., "0" or "1") may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0027] like Figure 2 As shown, the transistor T2 (e.g., the channel region of transistor T2) of a particular memory cell among memory cells 210 to 215 can be electrically coupled (e.g., directly coupled to) the charge storage structure 202 of that particular memory cell. Therefore, during operation of the memory device 200 (e.g., a write operation), a circuit path (e.g., a current path) can be directly formed between the transistor T2 of the particular memory cell and the charge storage structure 202 of that particular memory cell.

[0028] Memory cells 210 to 215 may be arranged in memory cell groups 2010 and 2011. Figure 2Two memory cell groups (e.g., 2010 and 2011) are shown as examples. However, memory device 200 may include more than two memory cell groups. Memory cell groups 2010 and 2011 may contain the same number of memory cells. For example, memory cell group 2010 may include memory cells 210, 212, and 214, and memory cell group 2011 may include memory cells 211, 213, and 215. Figure 2 Three memory cells are shown as examples in each of memory cell groups 2010 and 2011. The number of memory cells in memory cell groups 2010 and 2011 may be different from three.

[0029] The memory device 200 can perform write operations to store information in memory cells 210 to 215 and read operations to read (e.g., sense) information from memory cells 210 to 215. The memory device 200 can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a capacitor, the memory device 200 can store information in the form of a charge in a charge storage structure 202 (which may be a floating gate structure). As mentioned above, the charge storage structure 202 may be the floating gate of transistor T1. During operation of the memory device 200 (e.g., read or write operations), access lines (e.g., single access lines) and data lines (e.g., single data lines) can be used to access selected memory cells (e.g., target memory cells).

[0030] like Figure 2 As shown, memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 that can carry corresponding signals (e.g., word line signals) WL1, WL2, and WLn. Access lines 241, 242, and 243 can be used to access two memory cell groups 2010 and 2011. Each of access lines 241, 242, and 243 may be structured as at least one conductor (one conductor or multiple conductors electrically coupled (e.g., shorted) to each other). Access lines 241, 242, and 243 may be selectively activated (e.g., one at a time) during operation of memory device 200 (e.g., read or write operation) to access selected memory cells (or multiple selected memory cells) among memory cells 210 to 215. The selected cell may be referred to as the target cell. In a read operation, information can be read from the selected memory cell (or multiple selected memory cells). During a write operation, information can be stored in selected memory cells (or multiple selected memory cells).

[0031] In memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or off) transistors T1 and T2 of a corresponding memory cell during read or write operations of memory device 200. Some conventional memory devices may use multiple (e.g., two separate) access lines to control access to a corresponding memory cell during read and write operations. Compared to such conventional memory devices (which use multiple access lines for the same memory cell), memory device 200 uses a single access line (e.g., a shared access line) in memory device 200 to control two transistors T1 and T2 of a corresponding memory cell, thereby accessing the corresponding memory cell. This technique saves space and simplifies the operation of memory device 200. Additionally, some conventional memory devices may use multiple data lines to access selected memory cells (e.g., during read operations) to read information from selected memory cells. In memory device 200, a single data line (e.g., data line 221 or 222) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. This simplifies the structure, operation, or both of memory device 200 compared to conventional memory devices that use multiple data lines to access selected memory cells.

[0032] In memory device 200, the gate of each of transistors T1 and T2 may be a portion of a corresponding access line (e.g., a corresponding word line). Figure 2 As shown, the gate of each of transistors T1 and T2 in memory cell 210 may be a portion of access line 241. Similarly, the gate of each of transistors T1 and T2 in memory cell 211 may be a portion of access line 241. For example, in the structure of memory device 200, four different portions of the conductive material (or multiple materials) forming access line 241 may respectively form the gates of transistors T1 and T2 in memory cell 210 and the gates of transistors T1 and T2 in memory cell 211 (e.g., four gates).

[0033] The gate of each of transistors T1 and T2 in memory cell 212 may be a portion of access line 242. The gate of each of transistors T1 and T2 in memory cell 213 may be a portion of access line 242. For example, in the structure of memory device 200, four different portions of the conductive material (or multiple materials) forming access line 242 may respectively form the gates of transistors T1 and T2 in memory cell 212 and the gates of transistors T1 and T2 in memory cell 213 (e.g., four gates).

[0034] The gate of each of transistors T1 and T2 in memory cell 214 may be a portion of access line 243. The gate of each of transistors T1 and T2 in memory cell 215 may be a portion of access line 243. For example, in the structure of memory device 200, four different portions of the conductive material (or multiple materials) forming access line 243 may respectively form the gates of transistors T1 and T2 in memory cell 214 and the gates of transistors T1 and T2 in memory cell 215 (e.g., four gates).

[0035] Memory device 200 may include data lines (e.g., bit lines) 221 and 222 capable of carrying corresponding signals (e.g., bit line signals) BL1 and BL2. During a read operation, memory device 200 may use data line 221 to obtain information read (e.g., sensed) from selected memory cells of memory cell group 2010, and use data line 222 to read information from selected memory cells of memory cell group 2011. During a write operation, memory device 200 may use data line 221 to provide information to be stored in selected memory cells of memory cell group 2010, and use data line 222 to provide information to be stored in selected memory cells of memory cell group 2011.

[0036] Memory device 200 may include a ground connection (e.g., a ground plane) 297 coupled to each of memory cells 210 to 215. Ground connection 297 may be structured by a conductive plate (e.g., a layer of conductive material) that can be coupled to a ground terminal of memory device 200. As an example, ground connection 297 may be a common conductive plate of memory device 200 (e.g., formed below the memory cells (e.g., memory cells 210 to 215)). In this example, elements (e.g., transistors T1 and T2) of each of the memory cells (e.g., memory cells 210 to 215) of memory device 200 may be formed (e.g., vertically formed above) the common conductive plate.

[0037] like Figure 2 As shown, the transistor T1 (e.g., the channel region of transistor T1) of a specific memory cell among memory cells 210 to 215 can be electrically coupled (e.g., directly coupled to) ground connection 297 and electrically coupled (e.g., directly coupled to) the corresponding data line (e.g., data line 221 or 222). Therefore, during an operation performed on the selected memory cell (e.g., a read operation), a circuit path (e.g., a current path) can be formed between the corresponding data line (e.g., data line 221 or 222) and ground connection 297 via the transistor T1 of the selected memory cell.

[0038] Memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained via a read path coupled to the selected memory cell. In memory cell group 2010, the read path of a particular memory cell (e.g., memory cells 210, 212, or 214) may include a current path (e.g., a read current path) through the channel region of transistor T1 of that particular memory cell, data line 221, and ground connection 297. In memory cell group 2011, the read path of a particular memory cell (e.g., memory cells 211, 213, or 215) may include a current path (e.g., a read current path) through the channel region of transistor T1 of that particular memory cell, data line 222, and ground connection 297. In an example where transistor T1 is a PFET (e.g., PMOS), the current in the read path (e.g., during a read operation) may include hole conduction (e.g., hole conduction in the direction from data line 221 through the channel region of transistor T1 to ground connection 297). Since transistor T1 can be used in the read path to read information from the corresponding memory cell during a read operation, transistor T1 can be called a read transistor and the channel region of transistor T1 can be called a read channel region.

[0039] Memory device 200 may include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell via a write path coupled to the selected memory cell. In memory cell group 2010, the write path of a particular memory cell may include a transistor T2 of that particular memory cell (e.g., a write current path may be included through the channel region of transistor T2) and a data line 221. In memory cell group 2011, the write path of a particular memory cell (e.g., memory cells 211, 213, or 215) may include a transistor T2 of that particular memory cell (e.g., a write current path may be included through the channel region of transistor T2) and a data line 222. In an example where transistor T2 is an NFET (e.g., NMOS), the current in the write path (e.g., during a write operation) may include electronic conduction through the channel region of transistor T2 (e.g., electronic conduction in the direction from data line 221 to charge storage structure 202). Since transistor T2 can be used in the write path to store information in the corresponding memory cell during a write operation, transistor T2 can be called a write transistor and the channel region of transistor T1 can be called a write channel region.

[0040] Each of the transistors T1 and T2 may include a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. The values of the threshold voltages Vt1 and Vt2 may be different (unequal). For example, the value of the threshold voltage Vt2 may be greater than the value of the threshold voltage Vt1. The difference between the values of the threshold voltages Vt1 and Vt2 allows information stored in the charge storage structure 202 of the transistor T1 on the read path to be read (e.g., sensed) during a read operation without affecting (e.g., turning on) the transistor T2 on the write path (e.g., the path through the transistor T2). This may prevent charge from leaking from the charge storage structure 202 via the transistor T2 on the write path (e.g., during a read operation).

[0041] In the structure of the memory device 200, the transistors T1 and T2 may be formed (e.g., engineered) such that the threshold voltage Vt1 of the transistor T1 may be less than zero volts (e.g., Vt1 < 0V), regardless of the value of the information stored in the charge storage structure 202 of the transistor T1 (e.g., "0" or "1"), and Vt1 < Vt2. When information having a value of "0" is stored in the charge storage structure 202, the charge storage structure 202 may be in the state "0". When information having a value of "1" is stored in the charge storage structure 202, the charge storage structure 202 may be in the state "1". Thus, in this structure, the relationship between the values of the threshold voltages Vt1 and Vt2 may be expressed as follows: Vt1 for state "0" < Vt1 for state "1" < 0V, and Vt2 = 0V (or alternatively, Vt2 > 0V).

[0042] In an alternative structure of the memory device 200, the transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 for state "0" < Vt1 for state "1", where Vt1 for state "0" < 0V (or alternatively, Vt1 for state "0" = 0V), Vt1 for state "1" > 0V, and Vt1 < Vt2.

[0043] In another alternative structure, the transistors T1 and T2 may be formed (e.g., engineered) such that Vt1 (for state "0") < Vt1 (for state "1"), where Vt1 for state "0" = 0V (or alternatively, Vt1 for state "0" > 0V) and Vt1 < Vt2.

[0044] During a read operation of memory device 200, only one memory cell from the same memory cell group can be selected at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a read operation to read information from a selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a read operation to read information from a selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0045] During a read operation, memory cells from different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) can be selected simultaneously (or alternatively, sequentially). For example, memory cells 210 and 211 can be selected simultaneously during a read operation to read (e.g., read information simultaneously) from memory cells 210 and 211. Memory cells 212 and 213 can be selected simultaneously during a read operation to read (e.g., read information simultaneously) from memory cells 212 and 213. Memory cells 214 and 215 can be selected simultaneously during a read operation to read (e.g., read information simultaneously) from memory cells 214 and 215.

[0046] The value of information read from a selected memory cell in memory cell group 2010 during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path (described above), which includes data line 221, transistor T1 of the selected memory cell (e.g., memory cell 210, 212, or 214), and ground connection 297. The value of information read from a selected memory cell in memory cell group 2011 during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path, which includes data line 222, transistor T1 of the selected memory cell (e.g., memory cell 211, 213, or 215), and ground connection 297.

[0047] Memory device 200 may include a detection circuitry (not shown) operable during a read operation to detect (e.g., sense) a current (e.g., current I1, not shown) on a read path including data line 221 and a current (e.g., current I2, not shown) on a read path including data line 222. The value of the detected current may be based on the value of information stored in selected memory cells. For example, depending on the value of information stored in selected memory cells of memory cell group 2010, the value of the detected current on data line 221 (e.g., the value of current I1) may be zero or greater than zero. Similarly, depending on the value of information stored in selected memory cells of memory cell group 2011, the value of the detected current between data lines 222 (e.g., the value of current I2) may be zero or greater than zero. Memory device 200 may include a circuitry (not shown) for translating the value of the detected current into the value of information stored in the selected memory cells (e.g., "0", "1", or a combination of multiple bit values).

[0048] During a write operation of memory device 200, only one memory cell from the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a write operation to store information in selected memory cells (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a write operation to store information in selected memory cells (e.g., one of memory cells 211, 213, and 215 in this example).

[0049] During a write operation, memory cells from different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) can be selected simultaneously. For example, memory cells 210 and 211 can be selected simultaneously during a write operation to store information (e.g., simultaneously stored) in memory cells 210 and 211. Memory cells 212 and 213 can be selected simultaneously during a write operation to store information (e.g., simultaneously stored) in memory cells 212 and 213. Memory cells 214 and 215 can be selected simultaneously during a write operation to store information (e.g., simultaneously stored) in memory cells 214 and 215.

[0050] Information to be stored in selected memory cells of memory cell group 2010 during a write operation may be provided via a write path (described above) comprising data line 221 and transistor T2 of the selected memory cell (e.g., memory cell 210, 212, or 214). Information to be stored in selected memory cells of memory cell group 2011 during a write operation may be provided via a write path (described above) comprising data line 222 and transistor T2 of the selected memory cell (e.g., memory cell 211, 213, or 215). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells 210 to 215 may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0051] During a write operation, the amount of charge in the charge storage structure 202 of a selected memory cell (reflecting the value of the information stored in the selected memory cell) can be changed by applying a voltage along the write path, which includes a transistor T2 of that specific memory cell and a data line coupled to that specific memory cell (e.g., data line 221 or 222). For example, if the information to be stored in the selected memory cells 210, 212, and 214 has a value (e.g., "0"), a voltage with a value (e.g., 0V) can be applied to data line 221 (e.g., providing 0V to signal BL1). In another example, if the information to be stored in the selected memory cells 210, 212, and 214 has another value (e.g., "1"), a voltage with another value (e.g., a positive voltage) can be applied to data line 221 (e.g., providing a positive voltage to signal BL1). Therefore, information can be stored (e.g., directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on the write path (including transistor T2) of a particular memory cell.

[0052] Figure 3 Demonstrating some embodiments according to the description herein Figure 2 The memory device 200 includes instance voltages V1, V2, and V3 used during read operations of the memory device 200. Figure 3 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 211. It is assumed that memory cells 212 to 215 are unselected memory cells. This means that in Figure 3In this example, memory cells 212 to 215 are not accessed, and the information stored in memory cells 212 to 215 is not read, but information is read from memory cells 210 and 211.

[0053] exist Figure 3 In this specification, voltages V1, V2, and V3 represent different voltages applied to the corresponding access lines 241, 242, and 243 and data lines 221 and 222 during a read operation of the memory device 200. As examples, voltages V1, V2, and V3 may have values ​​of -1V, 0V, and 0.5V, respectively. The specific voltage values ​​used in this specification are merely example values. Different values ​​may be used. For example, voltage V1 may have a negative range (e.g., the value of voltage V1 may be from -3V to -1V).

[0054] exist Figure 3 In the read operation illustrated, voltage V1 may have a value (voltage value) to turn on transistor T1 of each of memory cells 210 and 211 (selected memory cells in this example) and turn off (disable) transistor T2 of each of memory cells 210 and 211. This allows information to be read from memory cells 210 and 211. Voltage V2 may have a value such that transistors T1 and T2 of each of memory cells 212 to 215 (unselected memory cells in this example) are turned off (e.g., disabled). Voltage V3 may have a value such that current (e.g., read current) can be formed on the read path of transistor T1 containing data line 221 and memory cell 210 and the read path of transistor T1 containing data line 222 and memory cell 212 (separate read paths). This allows the current coupled to the read paths of memory cells 210 and 211 to be detected separately. The detection circuitry system (not shown) of memory device 200 is operable to translate the value of the detected current (during information reading from a selected memory cell) into the value of the information read from the selected memory cell (e.g., a combination of "0", "1", or multiple bit values). Figure 3 In the example, the values ​​of the detected currents on data lines 221 and 222 can be translated into the values ​​of information read from memory units 210 and 211, respectively.

[0055] exist Figure 3In the read operation illustrated, in addition to transistor T1 in each of memory cells 210 and 211 (selected memory cells), the voltages applied to the corresponding access lines 241, 242, and 243 can turn off (or remain off) transistors T1 and T2 in each of memory cells 212 to 215. Depending on the value of the threshold voltage Vt1 of transistor T1 in memory cell 210 (selected memory cell), transistor T1 in memory cell 210 may or may not be turned on. Depending on the value of the threshold voltage Vt1 of transistor T1 in memory cell 211 (selected memory cell), transistor T1 in memory cell 211 may or may not be turned on. For example, if the transistor T1 of each of the memory cells (e.g., 210 to 215) of the memory device 200 is configured (e.g., structured) such that the threshold voltage of the transistor T1 is less than zero (e.g., Vt1 < -1V) without regard to the value (e.g., state) of the information stored in the corresponding memory cell 210, then in this example, the transistor T1 of the memory cell 210 can be turned on and conduct current on the data line 221 (via the transistor T1 of the memory cell 210). In this example, the transistor T1 of the memory cell 211 can also be turned on and conduct current on the data line 222 (via the transistor T1 of the memory cell 211). The memory device 200 can determine the value of the information stored in the memory cells 210 and 211 based on the values ​​of the currents on the data lines 221 and 222, respectively. As described above, the memory device 200 may include a detection circuitry system to measure the values ​​of the currents on the data lines 221 and 222 during a read operation.

[0056] Figure 4 Demonstrating some embodiments according to the description herein Figure 2 The memory device 200 includes instance voltages V4, V5, V6 and V7 used during write operations of the memory device 200. Figure 4 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a write operation to store information in memory cells 210 and 211. It is assumed that memory cells 212 to 215 are unselected memory cells. This means that in Figure 4 In the example, memory cells 212 to 215 are not accessed, and information is not stored in memory cells 212 to 215, but in memory cells 210 and 211.

[0057] exist Figure 4In this context, voltages V4, V5, V6, and V7 represent different voltages applied to the corresponding access lines 241, 242, and 243, and data lines 221 and 222, during a write operation of the memory device 200. As an example, voltages V4 and V5 may have values ​​of 3V and 0V, respectively. These are example values; different values ​​may be used.

[0058] Depending on the value of the information to be stored in memory cells 210 and 211 (e.g., "0" or "1"), the values ​​of voltages V6 and V7 may be the same or different. For example, if memory cells 210 and 211 are to store information with the same value, then the values ​​of voltages V6 and V7 may be the same (e.g., V6 = V7). As an example, if the information to be stored in each memory cell 210 and 211 is "0", then V6 = V7 = 0V, and if the information to be stored in each memory cell 210 and 211 is "1", then V6 = V7 = 1V to 3V.

[0059] In another example, if memory cells 210 and 211 are to store information with different values, then the values ​​of voltages V6 and V7 can be different (e.g., V6 ≠ V7). For example, if "0" is to be stored in memory cell 210 and "1" is to be stored in memory cell 211, then V6 = 0V and V7 = 1V to 3V. For another example, if "1" is to be stored in memory cell 210 and "0" is to be stored in memory cell 211, then V6 = 1V to 3V and V7 = 0V.

[0060] A voltage range of 1V to 3V is used here as an example. Different voltage ranges can be used. Alternatively, instead of applying 0V (e.g., V6 = 0V or V7 = 0V) to a specific write data line (e.g., data line 221 or 222) to store information with a value of "0" into a memory cell (e.g., memory cell 210 or 211) coupled to that specific write data line, a positive voltage (e.g., V6 > 0V or V7 > 0V) can be applied to that specific data line.

[0061] exist Figure 4During a write operation of the memory device 200, voltage V5 may have a value that turns off (e.g., disables) transistors T1 and T2 of each of memory cells 212 to 215 (unselected memory cells in this example). Voltage V4 may have a value that turns on transistor T2 of each of memory cells 210 and 211 (selected memory cells in this example), forming a write path between the charge storage structure 202 of memory cell 210 and the data line 221, and a write path between the charge storage structure 202 of memory cell 211 and the data line 222. A current (e.g., a write current) may be formed between the charge storage structure 202 of memory cell 210 (selected memory cell) and the data line 221. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of memory cell 210 to reflect the value of the information to be stored in memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of memory cell 211 (selected memory cell) and the data line 222. This current can affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the value of the information to be stored in the memory cell 211.

[0062] exist Figure 4 In the instance write operation, the value of voltage V6 can cause the charge storage structure 202 of memory cell 210 to discharge or be charged, such that the resulting charge on the charge storage structure 202 of memory cell 210 (e.g., the charge remaining after the discharge or charge operation) reflects the value of the information stored in memory cell 210. Similarly, in this example, the value of voltage V7 can cause the charge storage structure 202 of memory cell 211 to discharge or be charged, such that the resulting charge on the charge storage structure 202 of memory cell 211 (e.g., the charge remaining after the discharge or charge operation) reflects the value of the information stored in memory cell 211.

[0063] Figure 5 , Figure 6 , Figure 7 and Figure 8 Demonstrating some embodiments described herein with respect to the X, Y, and Z directions Figure 2 Different views of the structure of the memory device 200. Figure 5 and Figure 6 Different 3D views (e.g., isometric views) of the memory device 200 relative to the XY and Z directions are shown. Figure 7 A side view (e.g., cross-sectional view) of the memory device 200 relative to the XZ direction is shown. Figure 8 Display along Figure 7 The view taken by line 8-8 (e.g., a cross-sectional view).

[0064] For simplicity, Figure 5 and Figure 6 The structure of memory unit 210 is shown. Figure 2 The structure of other memory cells (e.g., memory cells 211 to 215) of the memory device 200 may be similar to or the same as that of the memory device 200. Figure 5 and Figure 6 The structure of memory cell 210 shown in the figure. Figure 2 and Figures 5 to 8 In this context, identical components are given the same reference number.

[0065] See the following description Figures 5 to 8 For simplicity, in Figures 5 to 8 The description of the same component will not be repeated in detail. Also, for simplicity, from... Figures 5 to 8 And other diagrams in the schemata described herein (e.g., Figures 9 to 29C Most of the elements shown in the drawings omit cross-sectional lines (e.g., shaded lines). Some elements of the memory device 200 may be omitted from specific drawings to avoid confusion in the description of elements (or elements) depicted in that particular drawing. The dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not drawn to scale.

[0066] like Figure 5 As shown, memory device 200 may include a substrate 599, and memory cells 210 (and other memory cells of memory device 200 (not shown)) may be formed on said substrate. Transistors T1 and T2 of memory cells 210 may be formed perpendicular to substrate 599. Substrate 599 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrate. The Z direction (e.g., the vertical direction) is a direction perpendicular to substrate 599 (e.g., outward from the substrate). The Z direction is also perpendicular to the X and Y directions (e.g., extending perpendicularly from the X and Y directions). The X and Y directions are perpendicular to each other.

[0067] like Figures 5 to 8 As shown, ground connection 297 may include a material structure (e.g., a sheet (e.g., a layer)) located above substrate 599. Examples of materials for ground connection 297 include metal sheets, conductive doped polysilicon, or other conductive materials. Ground connection 297 may be coupled to a ground terminal (not shown) of memory device 200.

[0068] Figures 5 to 8 A ground connection 297 that contacts (e.g., is directly coupled to) substrate 599 is shown as an example. In an alternative configuration, memory device 200 may include a dielectric (e.g., a dielectric material layer, not shown) between ground connection 297 and substrate 599.

[0069] like Figures 5 to 8 As shown, memory device 200 may include semiconductor material 596 formed over ground connection 297. Semiconductor material 596 may include a structure of silicon, polysilicon or other semiconductor materials (e.g., a wafer (e.g., a layer)) and may include doped regions (e.g., p-type doped regions).

[0070] from Figure 5 and Figure 6 Some parts of the memory device 200 (e.g., gate oxide and cell isolation structure) are omitted to avoid confusion. Figure 5 and Figure 6 The structure of the components shown in the image.

[0071] like Figures 5 to 8 As shown, each of data lines 221 and 222 (associated with signals BL1 and BL2, respectively) may have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Each of data lines 221 and 222 may contain a conductive material (or combination of materials) that can be structured into wires (e.g., conductive regions). Example materials for data lines 221 and 222 include metals, conductive doped polysilicon, or other conductive materials.

[0072] Access line 241 (associated with signal WL1) can be structured (may include) by a combination of portions 541F and 541B (e.g., front and rear conductive portions relative to the Y direction). Each of portions 541F and 541B may contain a conductive material (or combination of materials) that can be structured as a conductor (e.g., a conductive region) having a length that extends continuously in the X direction. Thus, portions 541F and 541B may be portions of conductors that are opposite each other (e.g., opposite each other in the Y direction).

[0073] Each of portions 541F and 541B may comprise a structure (e.g., a sheet, layer) of a conductive material (e.g., a metal, conductive doped polysilicon, or other conductive material). Each of portions 541F and 541B may have a length in the X direction ( Figure 5 (as shown in the image), width in the Z direction ( Figure 5 (as shown in the image) and thickness in the Y direction ( Figure 8 (As shown in the image).

[0074] Parts 541F and 541B may be electrically coupled to each other. For example, memory device 200 may include conductive material (e.g., not shown) that is accessible (e.g., electrically coupled to) parts 541F and 541B, such that parts 541F and 541B (which are portions of a single access line 241) may be simultaneously subjected to the same signal (e.g., signal WL1).

[0075] In an alternative configuration of the memory device 200, portion 541F or portion 541B can be omitted, allowing access line 241 to contain only portion 541F or portion 541B. Figure 5 The structure shown includes two parts, 541F and 541B, which can help to preferably control the transistor T1 in each of the memory cells 210 and 211 during read operations (e.g., Figure 2 Transistor T1 is shown schematically in the diagram.

[0076] The charge storage structure 202 may include a charge storage material (or a combination of materials), which may comprise a semiconductor material (e.g., polysilicon) wafer (e.g., a layer), a metal wafer (e.g., a layer), or a material (or multiple materials) wafer capable of capturing charge. The materials used for portions 541F and 541B of the charge storage structure 202 and access line 241 may be the same or different. Figure 5 As shown, the charge storage structure 202 may include a portion (e.g., a bottom portion) that is closer to the substrate 599 (e.g., extends closer to the substrate in the Z direction) than each of the portions 541F and 541B of the access line 241.

[0077] Figures 5 to 8 The top edge of the charge storage structure 202 is separated from the edges (e.g., the bottom edge) of each of the portions 541F and 541B of the access line 241 by a specific distance (e.g., Figure 5 Examples of distances shown in the diagram. However, the distance between the top edge of the charge storage structure 202 and the edge (e.g., the bottom edge) of each of portions 541F and 541B can vary.

[0078] Figures 5 to 8 Examples are shown where portions of 541F and 541B overlap with charge storage structure 202 (in the Z direction). However, portions of 541F and 541B may not overlap with charge storage structure 202.

[0079] The memory device 200 may include material 520 located between the data line 221 and the charge storage structure 202. For example... Figure 5 As shown, material 520 can be electrically coupled to data line 221 and charge storage structure 202 of memory cell 210. As described above, charge storage structure 202 of memory cell 210 can form memory element of memory cell 210. Therefore, memory cell 210 can include memory element (which is charge storage structure 202) located between substrate 599 and material 520 relative to the Z direction, and memory element contacting (e.g., directly coupled to) material 520.

[0080] Material 520 can form the source (e.g., source terminal), drain (e.g., drain terminal), and channel region (e.g., write channel region) between the source and drain of transistor T2 in memory cell 210. Therefore, as... Figure 5 As shown, the source, channel region, and drain of transistor T2 in memory cell 210 can be formed from a single piece of the same material (or alternatively, a single piece of the same combination of materials) of material 520. Therefore, the source, drain, and channel region of transistor T2 in memory cell 210 can be formed from the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type).

[0081] like Figure 7 As shown, the memory device 200 may include material 521, which may form the source (e.g., source terminal), drain (e.g., drain terminal), and channel region (e.g., write channel region) between the source and drain of the transistor T2 of the memory cell 211. Therefore, as Figure 5 As shown, the source, channel region and drain of transistor T2 in memory cell 211 can be formed from a single piece of the same material as material 521 (or alternatively, a single piece of the same combination of materials).

[0082] Materials 520 and 521 may be the same. For example, each of materials 520 and 521 may comprise a semiconductor material structure (e.g., a wafer (e.g., a layer)). In an example where transistor T2 is an NFET (as described above), materials 520 and 521 may comprise an n-type semiconductor material (e.g., n-type silicon).

[0083] In another example, the semiconductor material forming material 520 or material 521 may comprise a sheet of oxide material. Examples of oxide materials used for materials 520 and 521 include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0084] As an example, each of materials 520 and 521 may include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y Oz Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0085] The use of the materials listed above in memory device 200 provides improvements and benefits to memory device 200. For example, during a read operation, in order to read information from a selected memory cell (e.g., memory cell 210 or 211), charge from the charge storage structure 202 of the selected memory cell may leak to the transistor T2 of the selected memory cell. Using the materials listed above in the channel region of transistor T2 (e.g., materials 520 or 521) can reduce or prevent this leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device 200) described herein.

[0086] The materials listed above are examples of materials 520 and 521. However, other materials different from those listed above (e.g., materials with relatively high band gaps) may be used.

[0087] exist Figure 5 In one embodiment, the material 520 of the memory cell 210 and the charge storage structure 202 are electrically coupled (e.g., directly coupled) to each other, such that the material 520 can contact the charge storage structure 202 of the memory cell 210 without any intermediate material (e.g., no conductive material) between the charge storage structure 202 of the memory cell 210 and the material 520. In another embodiment, the material 520 is electrically coupled to the charge storage structure 202 of the memory cell 210, such that the material 520 is not directly coupled to (does not contact) the charge storage structure 202 of the memory cell 210, but is connected via an intermediate material (e.g., conductive material) between the material 520 and the charge storage structure 202 of the memory cell 210. Figure 5 The charge storage structure 202 (not shown) is coupled to (e.g., indirectly contacted) the memory cell 210.

[0088] like Figure 5 As shown, memory cell 210 may include portions 510A and 510B electrically coupled to each other. Each of portions 510A and 510B may include a semiconductor material structure (e.g., a wafer (e.g., a layer)). Examples of materials used for each of portions 510A and 510B include silicon, polycrystalline silicon (e.g., undoped or doped polycrystalline silicon), germanium, silicon-germanium or other semiconductor materials, and semiconducting oxide materials (oxide semiconductors, such as SnO or other oxide semiconductors).

[0089] See above. Figure 2 As described, the transistor T1 of the memory cell 210 includes a channel region (e.g., a read channel region). Figure 5 In the memory cell 210, the channel region of transistor T1 may include portions 510A and 510B (e.g., may be formed by a combination of said portions). Portions 510A and 510B may be electrically coupled to data line 221. See above. Figure 2 As described, memory cell 210 may include a read path. Figure 5In this configuration, portions 510A and 510B (e.g., read channel regions of transistor T1 in memory cell 210) may form parts of a read path for memory cell 210, which may carry current (e.g., read current) during a read operation to read information from memory cell 210. For example, during a read operation, in order to read information from memory cell 210, portions 510A and 510B may conduct current (e.g., read current) between data line 221 and ground connection 297 (via a portion of semiconductor material 596). The direction of the read current may be from data line 221 to ground connection 297 (via portions 510A, portions 510B, and portions of semiconductor material 596). In an example where transistor T1 is a PFET and transistor T2 is an NFET, the materials forming portions 510A and 510B may have a different conductivity type than materials 520 or 521. For example, portions 510A and 510B may include regions of p-type semiconductor material (e.g., p-type silicon), and materials 520 and 521 may include regions of n-type semiconductor material (e.g., n-type gallium phosphide (GaP)).

[0090] like Figure 5 , Figure 6 and Figure 7 As shown, memory cell 210 may include dielectrics 515A and 515B. Dielectrics 515A and 515B may be gate oxide regions electrically separating charge storage structure 202 from portions 510A and 510B and electrically separating material 520 from portions 510A. Examples of materials used for dielectrics 515A and 515B include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials. In example structures of memory device 200, dielectrics 515A and 515B comprise high-k dielectric materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide). Using this high-k dielectric material (instead of silicon dioxide) can improve the performance of memory device 200 (e.g., reduce current leakage, increase the drive capability of transistor T1, or both).

[0091] like Figure 7 As shown, a portion of 541F may span (e.g., overlap in the X direction) a portion of 510A and a portion of material 520. As described above, portion 510A may form a portion of the read channel region of transistor T1, and material 520 may form a portion of the write channel region of transistor T2. Therefore, as Figure 7 As shown, portions of the 541F can respectively span (e.g., overlap) portions of both the read and write channels of transistors T1 and T2 (e.g., on the Y-direction side (e.g., the front side)). Although from Figure 7 The view shown in the image is hidden (but as shown in the image) Figure 5(As can be seen), but a portion of 541B may cross (e.g., overlap in the X direction) a portion of 510A (e.g., on the other side in the Y direction (e.g., the rear side opposite the front side)) and a portion of material 520. Figure 7 As shown, access line 241 may also cross (e.g., overlap in the X direction) a portion of portion 511A (e.g., a portion of the read channel region of transistor T1 of memory cell 211) and a portion of material 521 (e.g., a portion of the write channel region of transistor T2 of memory cell 211).

[0092] Access line 241, spanning (e.g., overlapping) portion 510A and material 520, allows access line 241 (a single access line) to control (e.g., turn on or off) two transistors T1 and T2 of memory cell 210 and two transistors of memory cell 211. Similarly, access line 241, spanning (e.g., overlapping) portion 511A and material 521, allows access line 241 (a single access line) to control (e.g., turn on or off) two transistors T1 and T2 of memory cell 211.

[0093] like Figure 7 As shown, memory device 200 may include dielectric material 526, which may form a structure (e.g., dielectric) that partially electrically separates (e.g., isolates) two adjacent memory cells (in the X direction) of memory device 200. For example, dielectric material 526 may electrically separate material 520 (e.g., the write channel region of transistor T2 of memory cell 210) from material 521 (e.g., the write channel region of transistor T2 of memory cell 211), and electrically separate the charge storage structure 202 of memory cell 210 from the charge storage structure 202 of memory cell 211.

[0094] like Figure 7 As shown, memory device 200 may include dielectric portions 531 and 532, wherein memory cells 210 and 211 may be located between dielectric portions 531 and 532. Dielectric portion 531 electrically isolates memory cell 210 from another memory cell of memory cell 210 (e.g., the memory cell on the left side (not shown)). Dielectric portion 532 electrically isolates memory cell 211 from another memory cell (e.g., the memory cell on the right side of memory cell 211 (not shown)). The region defined by dielectric portions 531 and 532 and semiconductor material 596 may be a portion of a trench (not labeled) formed during the process of forming memory device 200. Therefore, memory cells 210 and 211 may be formed in the portion of the trench.

[0095] Some portions (e.g., materials) of memory cells 210 and 211 may be formed adjacent to (e.g., formed on) the respective sidewalls of dielectric portions 531 and 532 (e.g., the portion perpendicular to the Z direction). For example, such as Figure 7 As shown, a portion 510A of the memory cell 210 (e.g., a semiconductor material portion) may be formed adjacent to (e.g., formed on) the sidewall (not labeled) of the dielectric portion 531. In another example, as... Figure 7 As shown, a portion 511A of the memory cell 210 (e.g., a semiconductor material portion) may be formed adjacent to (e.g., on) the sidewall (not labeled) of the dielectric portion 532.

[0096] like Figure 8 As shown, memory device 200 may include dielectrics 518F and 518B (e.g., oxide regions) to electrically separate portions 541F and 541B of access lines 241 from other elements of memory cells 210 and 211 (e.g., portions 510A and 511A (e.g., read channel regions), charge storage structure 202, and materials 520 and 521). The materials (or materials) used for dielectrics 518F and 518B may be the same as (or alternatively, different from) the materials (or materials) used for dielectrics 515A and 515B. Examples of materials used for portions 518F and 518B may include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0097] like Figure 8 As shown, portions 541F and 541B may be adjacent to corresponding sides of the material 520 and charge storage structure 202 of memory cell 210. For example, portion 541F may be adjacent to one side of a portion of each of the material 520 and charge storage structure 202 (e.g., in...). Figure 8 In the view, on the right side in the X direction). In another example, portion 541B may be adjacent to the other side of a portion of each of material 520 and charge storage structure 202 (e.g., in Figure 8 In the view, on the left side in the X direction (opposite to the right side)).

[0098] The above description focuses on the structure of memory cell 210. Memory cell 211 may contain elements structured in a manner similar to or identical to the elements of memory cell 210 described above. For example, such as Figure 7As shown, memory cell 211 may include charge storage structure 202, channel region (e.g., write channel region) 521, portions 511A and 511B (e.g., read channel regions), and dielectrics 525A and 525B. The material (or multiple materials) used for dielectrics 525A and 525B may be the same as the material (or multiple materials) used for dielectrics 515A and 515B.

[0099] See above. Figures 2 to 8 As described, the connectivity and structure of memory device 200 allow cross-point operation because a single access line (e.g., access line 241) and a single data line (e.g., data line 221) can be used to access memory cells (e.g., memory cell 210) of memory device 200 during operation of memory device 200 (e.g., read or write operations). This cross-point operation is achieved in part by coupling the terminals (e.g., source terminals) of transistor T1 in each of the memory cells (e.g., memory cells 210 to 215) to a ground connection (e.g., ground connection 297). This ground connection allows the voltage level at the terminals (e.g., source terminals) of transistor T1 of the selected memory cell to remain constant (e.g., remain at 0V without switching), thereby allowing cross-point operation. Compared to some conventional volatile memory devices (e.g., DRAM devices), the cross-point operation and structure of memory device 200 provide superior memory performance.

[0100] Figures 9 to 22 Different views of elements during the process of forming memory device 900 according to some embodiments described herein are shown. Some or all of the processes used to form memory device 900 can be used to form the above-described memory device 900. Figures 2 to 8 The memory device 200 described.

[0101] Figure 9 The memory device 900 is shown after different material levels (e.g., layers) are formed in the Z direction on a substrate 999, with corresponding levels (e.g., layers) of the memory device 900. The different material levels include dielectric material 930, semiconductor material 996, and conductive material 997. Dielectric material 930, semiconductor material 996, and conductive material 997 may be formed on the substrate 999 in a sequential manner, one material following another. For example, Figure 9 The process used may include: forming (e.g., depositing) a conductive material 997 on a substrate 999; forming (e.g., depositing) a semiconductor material 996 on the conductive material 997; and forming (e.g., depositing) a dielectric material 930 on the semiconductor material 996.

[0102] Substrate 999 may be similar to or the same as Figure 5The substrate 599. The conductive material 997 may contain similar or identical components to those used in the memory device 200. Figures 5 to 8 The material (or multiple materials) of the grounding connection 297. For example, the conductive material 997 may comprise a metal, conductive doped polysilicon, or other conductive materials.

[0103] Semiconductor material 996 contains materials similar to or identical to those used in memory device 200. Figures 5 to 8 The semiconductor material 996 is a material of various materials. For example, the semiconductor material 996 may comprise silicon, polysilicon, or other semiconductor materials, and may include doped regions (e.g., p-type doped regions). As described below in subsequent processes for forming the memory device 900, the semiconductor material 996 may be structured to form portions of the channel regions (e.g., read channel regions) of the respective memory cells of the memory device 900.

[0104] Figure 9 The dielectric material 930 may comprise a nitride material (e.g., silicon nitride (e.g., Si3N4)), an oxide material (e.g., SiO2), or other dielectric materials. As described below in subsequent processes for forming the memory device 900, the dielectric material 930 may be processed into a dielectric portion to form part of a cell isolation structure that electrically isolates one memory cell from another memory cell of the memory device 900.

[0105] Figure 10 A memory device 900 is shown after trenches (e.g., openings) 1001 and 1002 have been formed. Forming trenches 1001 and 1002 may include removing (e.g., by patterning) dielectric material 930 at locations where trenches 1001 and 1002 have been removed. Figure 9 The remaining portions (e.g., dielectric portions) 1031, 1032, and 1033 (which are the remaining portions of dielectric material 930) are left, such as... Figure 10 As shown in the image.

[0106] Each of trenches 1001 and 1002 may have a length in the Y direction, a width (shorter than the length) in the X direction, and a bottom (not marked) resting on a corresponding portion of the semiconductor material 996 (e.g., defined by the corresponding portion). Each of trenches 1001 and 1002 may include opposing sidewalls (e.g., vertical sidewalls) formed by corresponding portions 1031, 1032, and 1033. For example, trench 1001 may include sidewall 1011 (formed by portion 1031) and sidewall 1012 (formed by portion 1032). Trench 1002 may include sidewall 1013 (formed by portion 1032) and sidewall 1014 (formed by portion 1033).

[0107] Figure 11A memory device 900 is shown after material 1110' and material 1110" are formed (e.g., deposited) in trenches 1001 and 1002, respectively. Figure 11 As shown, material 1110' may be formed on the sidewalls 1011 and 1012 and the bottom (e.g., a portion of semiconductor material 996) of trench 1001. Material 1110" may be formed on the sidewalls 1013 and 1014 and the bottom (e.g., another portion of semiconductor material 996) of trench 1002.

[0108] Materials 1110' and 1110" may be the same material. Examples of materials 1110' and 1110" include semiconductor materials. Materials 1110' and 1110" may have the same characteristics as those used in the formation of semiconductor materials. Figures 5 to 8 The materials of portions 510A, 510B, 511A, and 511B (e.g., read channel regions) of the transistors T1 of the corresponding memory cells of the memory device 200 are of the same nature. This is as described below in subsequent processes forming the memory device 900 (e.g., Figure 19 As described in [the document], materials 1110' and 1110" can be structured to form channel regions (e.g., read channel regions) of transistors (e.g., transistor T1) of corresponding memory cells of memory device 900. Therefore, each of materials 1110' and 1110" can conduct current (e.g., conduct holes) during operation (e.g., read operation) of memory device 900.

[0109] The process of forming materials 1110' and 1110" may include a doping process. This doping process may include introducing dopant into materials 1110' and 1110" to allow the transistors (e.g., transistor T1) of the respective memory cells of the memory device 900 to have a specific structure. For example, Figure 9 The doping process used may involve introducing dopants with different dopant concentrations to different portions of materials 1110' and 1110" (e.g., using a laser annealing process), such that the transistor containing material 1110' (or material 1110") can have a PFET structure. In this PFET structure, portions of material 1110' (or material 1110") may form channel regions (e.g., read channel regions) to conduct current (e.g., holes) during operation of the memory device 900 (e.g., read operations).

[0110] Figure 12A memory device 900 is shown after dielectric materials (e.g., oxide materials) 1215' and 1215" are formed (e.g., deposited) on materials 1110' and 1110" respectively. The dielectric materials 1215' and 1215" are deposited such that the dielectric materials 1215' and 1215" are conformally constitutive to materials 1110' and 1110" respectively. Materials 1215' and 1215" may have the same shape as those formed on the materials 1110' and 1110". Figures 5 to 8 The dielectric materials (e.g., oxide materials) of the memory device 200 515A, 515B, 525A and 525B have the same properties.

[0111] Figure 13 A memory device 900 is shown after materials (e.g., charge storage materials) 1302', 1302”, 1302”', and 1302”” are formed on the respective sidewalls of materials 1215' and 1215”. Materials 1302', 1302”, 1302”', and 1302”” are electrically separated from each other. This is illustrated in the subsequent processes of forming the memory device 900 below. Figure 19 As described in [the original text], each of materials 1302', 1302”, 1302”', and 1302”” can be structured to form a charge storage structure for a corresponding memory cell of memory device 900. Materials 1302', 1302”, 1302”', and 1302”” may contain elements similar to or identical to those in memory device 200. Figures 5 to 8 The material of the charge storage structure 202 of the memory cell (e.g., memory cell 210 or 211) is polysilicon.

[0112] Figure 14 The image shows a memory device 900 after dielectric materials 1426' and 1426" have been formed (e.g., filled) in open spaces within trenches 1001 and 1002, respectively. Dielectric materials 1426' and 1426" may comprise oxide materials. As described below in subsequent processes for forming the memory device 900, dielectric materials 1426' and 1426" may form portions of an isolation structure that electrically isolates portions (e.g., charge storage structures) of two adjacent (in the X direction) memory cells of the memory device 900.

[0113] Figure 15 A memory device 900 is shown after the formation of dielectric materials 1526' and 1526" is performed. Forming dielectric materials 1526' and 1526" may include removing dielectric materials 1426' and 1426" (e.g., by using an etching process). Figure 14 A portion (e.g., the top portion) of each of the dielectric materials 1426' and 1426'', such that the remaining portions of dielectric materials 1426' and 1426''' are dielectric materials 1526' and 1526''', respectively. Figure 15 ).

[0114] Figure 16 A memory device 900 is shown after the formation of materials 1602', 1602”, 1602”', and 1602””. The formation of materials 1602', 1602”, 1602”', and 1602”” may include the removal (e.g., by using an etching process) of dielectric materials 1302', 1302”, 1302”', and 1302””. Figure 13 The portions of each of the materials (e.g., the top portion) are such that the remaining portions of materials 1302', 1302”, 1302”' and 1302”” are materials 1602', 1602”, 1602”' and 1602”” respectively. Figure 16 ).

[0115] exist Figure 14 , Figure 15 and Figure 16 In the middle, as seen in the following Figure 15 and Figure 16 The described separation process (e.g., multiple steps) removes dielectric materials 1426' and 1426" Figure 14 The portion of the material (e.g., the top portion) and the material 1302', 1302”, 1302”', 1302”” Figure 13 (e.g., the top portion). However, a single process (e.g., a single step) can be used to remove dielectric material 1426' and 1426"". Figure 14 The parts of ) and materials 1302', 1302”, 1302”', 1302”” Figure 13 () part.

[0116] Figure 17 A memory device 900 is shown after the formation of materials 1720', 1721', 1720”, and 1721”. Forming materials 1720', 1721', 1720”, and 1721” may include depositing initial materials (or multiple materials) onto dielectric materials 1526' and 1526” and materials 1602', 1602”, 1602”', and 1602””. Then, Figure 17 The process used may include removing (e.g., by using an etching process) a portion of the initial material at locations 1701 and 1702. Materials 1720', 1721', 1720”, and 1721” are the remaining portions of the initial material. Figure 17 As shown, materials 1720', 1721', 1720” and 1721” are electrically separated from each other. However, materials 1720', 1721', 1720” and 1721” are electrically coupled to (e.g., directly coupled to) materials 1602', 1602”, 1602”' and 1602”, respectively.

[0117] Materials 1720', 1721', 1720" and 1721" may contain materials similar to or identical to Figures 5 to 8 The material of transistor T2 in memory device 200 (e.g., the write channel region) is 520 or 521. Figure 5 The material used in the subsequent processes of forming the memory device 900 is as follows. Figure 19 As described in [the original text], each of materials 1720', 1721', 1720”, and 1721” can form the channel region (e.g., write channel region) of the transistor (e.g., transistor T2) of the corresponding memory cell of the memory device 900. Therefore, each of materials 1720', 1721', 1720”, and 1721” can conduct current (e.g., conduct electrons) during operation (e.g., write operation) of the memory device 900.

[0118] Figure 18 The dielectric materials 1826' and 1826" are formed at locations 1701 and 1702. Figure 17 The memory device 900 is located after the location (e.g., filled in the area). Dielectric materials 1826' and 1826" may be the same as dielectric materials 1426' and 1426". As described below in the subsequent processes for forming the memory device 900, dielectric materials 1826' and 1826" may form portions of an isolation structure that electrically isolates portions (e.g., write channel regions) of two adjacent (in the X direction) memory cells of the memory device 900.

[0119] Figure 19 The memory device 900 is shown after the formation of trenches 1911, 1912, and 1913 (in the X direction) across the material of the memory device 900. Each of trenches 1911, 1912, and 1913 may have a length in the X direction, a width in the Y direction (shorter than the length), and a bottom (not labeled) resting on a corresponding portion of semiconductor material 996 (e.g., defined by the corresponding portion). Alternatively, each of trenches 1911, 1912, and 1913 may have a bottom (not labeled) resting on a corresponding portion of conductive material 997 (rather than semiconductor material 996) (e.g., defined by the corresponding portion). Forming trenches 1911, 1912, and 1913 may include removing (e.g., by cutting (e.g., etching)) portions of the material of the memory device 900 at the locations of trenches 1911, 1912, and 1913 and leaving... Figure 19 The memory device 900 shown in the figure has a portion of its structure (e.g., a layer).

[0120] After removing (e.g., cutting) portions of the memory device 900 (at the locations of trenches 1911, 1912, and 1913), the remaining portion may form portions of memory cells of the memory device 900. For example, the memory device 900 may include memory cells 210', 211', 210" and 211" arranged in a row along the X direction, and cells 212', 213', 212" and 213" arranged in another row along the X direction. Memory cells 210' and 211' may correspond to memory device 200 (…). Figure 2 and Figure 7 ) memory units 210 and 211. Figure 19 The memory cells 212' and 213' in the memory can respectively correspond to the memory device 200 ( Figure 2 ) memory units 212 and 213.

[0121] For simplicity, only mark Figure 19 Some of the similar elements (e.g., portions) in the memory device 900. For example, the memory device 900 may include dielectric portions (e.g., cell isolation structures) 1931, 1932, 1933, 1934, 1935, and 1936, and dielectric materials 1926A and 1926B. Dielectric portions 1931 and 1932 may correspond to, respectively Figure 7 The dielectric portions 531 and 532 of the memory device 200.

[0122] like Figure 19 As shown, memory cell 210' may include portions 1910A and 1910B (which may be portions of the read channel region of memory cell 210'), dielectrics 1915A and 1915B, material (e.g., write channel region) 1920, and charge storage structure 1902 (directly below material 1920). Memory cell 211' may include portions 1911A and 1911B (which may be portions of the read channel region of memory cell 211'), dielectrics 1925A and 1925B, material (e.g., write channel region) 1921, and charge storage structure 1902 (directly below material 1921).

[0123] See above. Figures 9 to 19 As described, portions of each of the memory cells in the memory device 900 may be formed by a self-aligned process, which may include forming trenches 1001 and 1002 in the Y direction and trenches 1911, 1912, and 1913 in the X direction. The self-aligned process may improve (e.g., increase) memory cell density, improve the process (e.g., provide a higher process range), or both. As described above, the self-aligned process includes a reduced number of key masks that allow multiple stacks of memory cells to be formed in the same memory device. See below. Figures 29A to 29C Describe an example of a multi-stack memory device.

[0124] Figure 20 A memory device 900 is shown after the formation of dielectrics 2018F, 2018B, 2018F', and 2018B' (e.g., oxide regions). The materials (or materials) used for dielectrics 2018F, 2018B, 2018F', and 2018B' may be the same as (or alternatively, different from) the materials (or materials) used for dielectrics 515A, 515B, 525A, and 525B. Example materials used for dielectrics 2018F, 2018B, 2018F', and 2018B' may include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0125] Figure 21 A memory device 900 is shown after the formation of wires (e.g., conductive regions) 2141F, 2141B, 2142F, and 2142B. Each of the wires 2141F, 2141B, 2142F, and 2142B may comprise a metal, conductive doped polysilicon, or other conductive material. Figure 21 As shown, wires 2141F, 2141B, 2142F and 2142B are electrically separated from other components of the memory device 900 via dielectrics 2018F, 2018B, 2018F' and 2018B', respectively.

[0126] Wires 2141F and 2141B may form portions of access lines (e.g., word lines) 2141 to control the read and write transistors (e.g., transistors T1 and T2, respectively) of corresponding memory cells 210', 211', 210" and 211" of the memory device 900. For example, wires 2141F and 2141B may form the front conductive portion and the rear conductive portion of access line 2141, respectively. Wires 2142F and 2142B may form portions of access lines (e.g., word lines) 2142 to access memory cells 212', 213', 212" and 213" of the memory device 900. For example, wires 2142F and 2142B may form the front conductive portion and the rear conductive portion of access line 2142, respectively. Access lines 2141 and 2142 may correspond to... Figure 2 Access lines 214 and 242 of memory device 200.

[0127] form Figure 21The process of forming the memory device 900 may include forming a conductive connection 2141' (which may include a conductive material (e.g., a metal)) to electrically couple wires 2141F and 2141B to each other. This allows wires 2141F and 2141B to form portions of a single access line (e.g., access line 2141) or to form a single access line. Similarly, the process of forming the memory device 900 may include forming a conductive connection 2142' to electrically couple wires 2142F and 2142B to each other. This allows wires 2142F and 2142B to form portions of a single access line (e.g., access line 2142).

[0128] Figure 22 A memory device 900 is shown after data lines 2221, 2222, 2223, and 2224 are formed. Each of the data lines 2221, 2222, 2223, and 2224 may have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Data lines 2221 and 2222 may correspond to memory device 200 respectively. Figure 2 and Figure 7 Data cables 221 and 222.

[0129] exist Figure 22 In this configuration, data lines 2221, 2222, 2223, and 2224 can be electrically coupled (e.g., contacted) in the Y direction of the memory device 900 to a corresponding portion of each of the memory cells. For example, data line 2221 can be electrically coupled to portion 1910A (a portion of the read channel region of memory cell 210') and material 1920 (a portion of the write channel region of memory cell 210'). Data line 2221 can also be electrically coupled to the read channel region (not labeled) and the write channel region (not labeled) of memory cell 212'.

[0130] See Figures 9 to 22 The description of forming the memory device 900 may include other processes used to form the entire memory device. These processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0131] Compared to some conventional processes, the process for forming the memory device 900, as described above, can have a relatively smaller number of masks (e.g., a smaller number of key masks). For example, by using... Figure 10 In the associated processes, trenches 1001 and 1002 are formed and in Figure 19 The formation of trenches 1911, 1912, and 1913 in the process reduces the number of critical masks used to form the memory cells of the memory device 900. This reduction in the number of masks simplifies the process of forming the memory device 900 and reduces costs, or both.

[0132] Figures 23 to 28 This document illustrates a process for forming a memory device 2300 according to some embodiments described herein, the memory device including a shielding structure between adjacent memory cells. The process for forming the memory device 2300 may be for forming a memory device 900 (…). Figures 9 to 22 The process is a variation of the process. Therefore, similar elements (with the same markings) between the processes of forming memory devices 900 and 2300 are not repeated.

[0133] Figure 23 The display can be used to form Figures 9 to 19 The elements of memory device 2300 are formed using similar or identical processes to those of memory device 900. Therefore, Figure 23 The components of the memory device 2300 shown herein can be similar to Figure 19 The components of the memory device 900 shown in the figure.

[0134] Figure 24 A memory device 2300 is shown after the removal of dielectric materials 1926A and 1926B between memory cells 210' and 211' (e.g., write channel regions) 1920 and 1921 and between charge storage structures 1902. Figure 24 The process also removes other similar dielectric materials between the write channel regions of other memory cells of the memory device 2300 and between charge storage structures.

[0135] Figure 25 A memory device 2300 is shown after the formation of dielectrics 2518F, 2518B, 2518F', and 2518B' (e.g., oxide regions). The materials (or multiple materials) used for dielectrics 2518F, 2518B, 2518F', and 2518B' are compatible with dielectrics 2518F, 2518B, 2518F', and 2518B'. Figure 20 The materials (or multiple materials) used for dielectrics 2518F, 2518B, 2518F' and 2518B' are the same. Examples of materials used for dielectrics 2518F, 2518B, 2518F' and 2518B' may include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3) or other dielectric materials.

[0136] Figure 26A memory device 2300 is shown after the formation (e.g., deposition) of conductive wires (e.g., conductive regions) 2641F, 2641B, 2642F, and 2642B, and conductive portions 2641M and 2642M. The conductive wires 2641F, 2641B, 2642F, and 2642B, and the conductive portions 2641M and 2642M can be formed from the same material in the same process (e.g., the same step). For example, materials can be deposited simultaneously (e.g., in the same step) to form the conductive wires 2641F, 2641B, 2642F, and 2642B, and the conductive portions 2641M and 2642M. Example materials used for the conductive wires 2641F, 2641B, 2642F, and 2642B, and the conductive portions 2641M and 2642M include metals, conductive doped polysilicon, or other conductive materials. Figure 26 As shown, wires 2641F, 2641B, 2642F and 2642B, and conductive portions 2641M and 2642M are electrically separated from other components of the memory device 2300 by dielectrics 2018F, 2018B, 2018F' and 2018B', respectively.

[0137] Conductors 2641F and 2641B, and conductive portion 2641M, may form portions of access lines (e.g., word lines) 2641 to access memory cells 210', 211', 210" and 211" of the memory device 2300. For example, conductors 2641F and 2641B may form the front and rear conductive portions of access line 2641, respectively. Conductors 2642F and 2642B, and conductive portion 2642M, may form portions of access lines (e.g., word lines) 2642 to access memory cells 212', 213', 212" and 213" of the memory device 2300. For example, conductors 2642F and 2642B may form the front and rear conductive portions of access line 2642, respectively. Access lines 2641 and 2612 may correspond to... Figure 2 Access lines 241 and 242 of memory device 200.

[0138] form Figure 26 The process of forming the memory device 900 may include forming a conductive connection 2641' (which may include a conductive material (e.g., a metal)) to electrically couple wires 2641F and 2641B to each other. Similarly, the process of forming the memory device 900 may include forming a conductive connection 2642' to electrically couple wires 2642F and 2642B to each other.

[0139] Figure 27The memory device 2300 is shown after the data lines 2221, 2222, 2223, and 2224 are formed. Each of the data lines 2221, 2222, 2223, and 2224 may have a length in the Y direction, a width in the X direction, and a thickness in the Z direction. Data lines 2221 and 2222 may correspond to memory device 200 respectively. Figure 2 and Figure 7 Data cables 221 and 222.

[0140] Figure 28 A side view (e.g., a cross-sectional view) of a portion of the memory device 2300 is shown, including the portion of the conductive portion 2641M between memory cells 210' and 211'. For simplicity, details are not repeated. Figure 28 The description of the components of the memory device 2300 shown in the figure. Figure 28 In this configuration, the conductive portion 2641M may be located between the charge storage structures 1902 of memory cells 210' and 211' to form a shielding structure. This shielding structure can improve the operation of the memory device 2300 (e.g., reduce coupling interference between charge storage structures of adjacent memory cells).

[0141] See Figures 23 to 28 The description of forming memory device 2300 may include other processes used to form the entire memory device. These processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0142] Figure 29A , Figure 29B and Figure 29C Different views are shown illustrating the structure of a memory device 2900 according to some embodiments described herein, the memory device comprising multiple stacks of memory cells. Figure 29A An exploded view of the memory device 2900 is shown (e.g., in the Z direction). Figure 29B The memory device 2900 is shown in a side view (e.g., a cross-sectional view) in the X and Z directions. Figure 29C The memory device 2900 is shown in a side view (e.g., a cross-sectional view) in the Y and Z directions.

[0143] like Figure 29A As shown, the memory device 2900 may comprise stacks (stacks of memory cells) 29050, 29051, 29052, and 29053, shown separately in the exploded view to facilitate easy inspection of the stack structure of the memory device 2900. In practice, stacks 29050, 29051, 29052, and 29053 may be attached to each other on a substrate (e.g., a semiconductor (e.g., silicon) substrate) 2999 in an arrangement where one stack may be formed on (e.g., stacked on) another stack. For example, as... Figure 29A As shown, stacks 29050, 29051, 29052 and 29053 can be formed in the Z direction perpendicular to the substrate 2999 (e.g., formed perpendicularly to the Z direction relative to the substrate 2999).

[0144] like Figure 29A As shown, each of stacks 29050, 29051, 29052, and 29053 may have memory cells arranged in both the X and Y directions (e.g., in columns in the X direction and in rows in the Y direction). For example, stack 29050 may include memory cells 29100, 29110, 29120, and 29130 (e.g., arranged in columns), memory cells 29200, 29210, 29220, and 29230 (e.g., arranged in columns), and memory cells 29300, 29310, 29320, and 29330 (e.g., arranged in columns).

[0145] Stack 29051 may include memory cells 29101, 29111, 29121 and 29131 (e.g., arranged in a column), memory cells 29201, 29211, 29221 and 29231 (e.g., arranged in a column), and memory cells 29301, 29311, 29321 and 29331 (e.g., arranged in a column).

[0146] Stack 29052 may include memory cells 29102, 29112, 29122 and 29132 (e.g., arranged in a column), memory cells 29202, 29212, 29222 and 29232 (e.g., arranged in a column), and memory cells 29302, 29312, 29322 and 29332 (e.g., arranged in a column).

[0147] Stack 29053 may include memory cells 29103, 29113, 29123 and 29133 (e.g., arranged in a row), memory cells 29203, 29213, 29223 and 29233 (e.g., arranged in a row), and memory cells 29303, 29313, 29323 and 29333 (e.g., arranged in a row).

[0148] like Figure 29AAs shown, stacks 29050, 29051, 29052, and 29053 may be located on layers (e.g., portions) 2950, ​​2951, 2952, and 2953 of the memory device 2900 (e.g., formed vertically in the Z direction). The arrangement of stacks 29050, 29051, 29052, and 29053 forms a 3D structure of the memory cells of the memory device 2900, because different layers of the memory cells of the memory device 2900 may be located (e.g., formed on) different layers (e.g., different vertical portions) 2950, ​​2951, 2952, and 2953 of the memory device 2900.

[0149] Stacks 29050, 29051, 29052, and 29053 can be formed one stack at a time. For example, stacks 29050, 29051, 29052, and 29053 can be formed sequentially in the order of stacks 29050, 29051, 29052, and 29053 (e.g., stack 29050 is formed first and stack 29053 is formed last). In this example, the memory cells of one stack (e.g., stack 29051) can be formed after the memory cells of another stack (e.g., stack 29050) are formed or before the memory cells of another stack (e.g., stack 29052) are formed. Alternatively, stacks 29050, 29051, 29052, and 29053 can be formed simultaneously (e.g., synchronously) so that memory cells of stacks 29050, 29051, 29052, and 29053 can be formed simultaneously. For example, memory cells in levels 2950, ​​2951, 2952, and 2953 of memory device 2900 can be formed simultaneously.

[0150] The structure of the memory cells in each of stacks 29050, 29051, 29052, and 29053 may include the structure described above. Figures 1 to 28 The structure of the memory cells described. For example, the structure of the memory cells in stacks 29050, 29051, 29052 and 29053 may include the structure of the memory cells in memory devices 200, 900 and 2300.

[0151] Memory device 2900 may include data lines (e.g., bit lines) and access lines (e.g., word lines) to access memory cells of stacks 29050, 29051, 29052, and 29053. For simplicity, from Figure 29A The data lines and access lines of the memory cells are omitted. However, the data lines and access lines of the memory device 2900 can be similar to those described above. Figures 1 to 28 The data lines and access lines of the described memory device.

[0152] Figure 29AA memory device 2900 comprising four stacks (e.g., 29050, 29051, 29052, and 29053) is shown as an example. However, the number of stacks may be different from four. Figure 29A Each of stacks 29050, 29051, 29052, and 29053 is shown as an example containing one level (e.g., a layer) of memory cells. However, at least one of the stacks (e.g., one or more of stacks 29050, 29051, 29052, and 29053) may have two (or more) levels of memory cells. Figure 29A Examples of stacks 29050, 29051, 29052, and 29053 are shown, each containing four memory cells (e.g., in a column) in the X direction and three memory cells (e.g., in a row) in the Y direction. However, the number of memory cells in a column, a row, or both can vary.

[0153] The description of devices (e.g., memory devices 100, 200, 900, 2300, and 2900) and methods (e.g., operation of memory devices 100 and 200 and methods of forming memory devices 900 and 2300) is intended to provide a general understanding of the structure of the various embodiments and is not intended to provide a complete description of all elements and features of devices that may utilize the structures described herein. Devices herein refer to, for example, apparatus (e.g., any of memory devices 100, 200, 900, 2300, and 2900) or systems (e.g., electronic articles that may include any of memory devices 100, 200, 900, 2300, and 2900).

[0154] See above Figures 1 to 29C Any of the components described can be implemented in a variety of ways, including via software simulation. Therefore, a portion of any device (e.g., memory devices 100, 200, 900, 2300, and 2900) or any of the memory devices described above can be characterized herein as a “multiple module” (or “module”). Depending on need and / or suitability for specific implementations of various embodiments, such modules may include hardware circuitry systems, single-processor and / or multi-processor circuitry, memory circuitry, software program modules and objects and / or firmware, and combinations thereof. For example, such modules may be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitor-inductor simulation packages, power / heat dissipation simulation packages, signal transmit-receive simulation packages, and / or combinations of software and hardware for operating or simulating the operation of various possible embodiments.

[0155] The memory devices described herein (e.g., memory devices 100, 200, 900, 2300, and 2900) may be included in devices (e.g., electronic circuit systems) such as: high-speed computers, communication and signal processing circuit systems, single-processor or multi-processor modules, single or multiple embedded processors, multi-core processors, message exchangers, and dedicated modules comprising multi-layer, multi-chip modules. Such devices may be further included as sub-components within a variety of other devices (e.g., electronic systems) such as: televisions, cellular phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0156] See above Figures 1 to 29C The described embodiments include an apparatus and a method of forming said apparatus. One of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductor. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The conductor is electrically separated from the first and second regions and crosses a portion of the first region of the first transistor and a portion of the second region of the second transistor, forming the gates of the first and second transistors. Other embodiments including additional apparatus and methods are described.

[0157] In the embodiments and claims, the term "on" (one on another) used with respect to two or more elements (e.g., materials) means at least some contact between the elements (e.g., between materials). The term "over" means that the elements (e.g., materials) are close together, but may have one or more additional intervening elements (e.g., materials) that make contact possible but not required. Unless stated otherwise, neither "on" nor "over" implies any directionality as used herein.

[0158] In the embodiments and claims, a list of items joined by the term "at least one of..." can mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0159] In the embodiments and claims, a list of items joined by the term "one of..." can mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0160] The foregoing description and figures illustrate some embodiments of the subject matter of this invention to enable those skilled in the art to practice these embodiments. Other embodiments may incorporate structural changes, logical changes, electrical changes, process changes, and other modifications. Examples represent only possible variations. Parts and features of some embodiments may be included in or replace those parts and features of other embodiments. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the foregoing description.

Claims

1. A memory device comprising: Data cable; A memory cell coupled to the data line, the memory cell comprising: A first transistor includes a first channel region contacting the data line and a charge storage structure separate from the first channel region; and The second transistor includes a second channel region that contacts the charge storage structure and the data line; and A ground connection is formed, which is coupled to the first channel region of the first transistor; and A wire electrically separated from the first channel region and the second channel region, a portion of the wire crossing a portion of the first channel region of the first transistor and a portion of the second channel region of the second transistor and forming the gate of the first transistor and the second transistor.

2. The memory device of claim 1, wherein the first channel region comprises a p-type semiconductor material and the second channel region comprises an n-type semiconductor material.

3. The memory device of claim 1, wherein the second channel region comprises a semiconductive oxide material.

4. The memory device of claim 1, wherein the first transistor and the second transistor have different threshold voltages.

5. The memory device of claim 1, wherein the second transistor has a threshold voltage greater than the threshold voltage of the first transistor.

6. The memory device of claim 1, wherein when the charge storage structure is in a first state, the first transistor has a first threshold voltage less than zero, and when the charge storage structure is in a second state, the first transistor has a second threshold voltage less than zero, and the first state and the second state represent different values ​​of information stored in the memory cell.

7. The memory device according to claim 1, further comprising: Additional data cable; and Additional memory unit, the additional memory unit comprising: A first additional transistor includes a first additional region electrically coupled to the additional data line and the ground connection, and an additional charge storage structure separate from the first additional region; and The second additional transistor includes a second additional region electrically coupled to the additional charge storage structure and the additional data line, wherein The wire is electrically separated from the first additional region and the second additional region, and a portion of the wire crosses a portion of the first additional region of the first additional transistor and a portion of the second additional region of the second additional transistor.

8. The memory device of claim 1, further comprising additional memory cells, wherein the memory cells are included in a first stack of memory cells of the memory device, the additional memory cells are included in a second stack of additional memory cells of the memory device, and the first stack of memory cells and the second stack of memory cells are located in different levels of the memory device.

9. A memory device comprising: A conductive plate located in the first layer of the memory device; A conductive region located in the second layer of the memory device; A memory cell, located between the first layer and the second layer and coupled to the conductive region and the conductive plate, the memory cell comprising: Memory elements; The channel region contacts the memory element and the conductive region; and A semiconductor material electrically coupled to the conductive region and the conductive plate; and A wire electrically separated from the memory element, the channel region, and the semiconductor material, a portion of the wire crossing the semiconductor material and a portion of the channel region.

10. The memory device of claim 9, wherein the semiconductor material has a different conductivity type than the channel region.

11. The memory device of claim 9, wherein the conductive region is a portion of the data line of the memory device, and the conductor is a portion of the word line of the memory device.

12. The memory device of claim 11, wherein the conductive plate comprises a ground plane of the memory device.

13. The memory device according to claim 9, wherein: The memory element includes a first material located in a third layer of the memory device between the first layer and the second layer; and The channel region contains a second material located in a fourth layer of the memory device, between the second layer and the third layer.

14. The memory device of claim 9, further comprising: An additional conductive region, which is located in the second layer of the memory device and electrically separated from the conductive region; An additional memory cell, located between the first layer and the second layer and coupled to the additional conductive region and the conductive plate, the additional memory cell comprising: Additional memory elements; An additional channel region that contacts the additional memory element and the additional conductive region; and Additional semiconductor material, coupled to the additional conductive region and the conductive plate, wherein... The conductor is electrically separated from the additional memory element, the additional channel region, and the additional semiconductor material, and an additional portion of the conductor crosses a portion of the additional semiconductor material and the additional channel region.

15. The memory device of claim 14, wherein: The conductive area is a portion of the first data line of the memory device; The additional conductive region is a portion of the second data line of the memory device; and The conductor is a portion of the word line of the memory device.

16. The memory device of claim 15, further comprising: First dielectric section; The second dielectric portion, wherein the memory cell and the additional memory cell are located between the first dielectric portion and the second dielectric portion, and wherein, The semiconductor material of the memory cell is adjacent to the sidewall of the first dielectric portion; and The additional semiconductor material of the additional memory cell is adjacent to the sidewall of the second dielectric portion.

17. The memory device of claim 15, further comprising an additional wire opposite to the wire, wherein: The additional conductor is electrically separated from the memory element, the channel region, and the semiconductor material, and a first portion of the additional conductor crosses a portion of the semiconductor material and the channel region; and The additional conductor is electrically separated from the additional memory element, the additional channel region, and the additional semiconductor material, and a second portion of the additional conductor crosses a portion of the additional semiconductor material and the additional channel region.

18. The memory device of claim 17, further comprising a conductive portion located between the channel region and the additional channel region of the memory cell, wherein the conductive portion contacts the wire and the additional wire.

19. The memory device of claim 18, wherein the conductive portion, the wire, and the additional wire are made of the same material.

20. The memory device of claim 9, wherein the channel region comprises at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

21. A method of forming a memory device, the method comprising: A material hierarchy is formed above a substrate, the material hierarchy comprising a dielectric material; A first trench is formed in the dielectric material by removing a portion of the material layer to provide a first remaining portion of the material layer, such that each of the first trenches includes a length in a first direction, a first sidewall formed by a first portion of the dielectric material, and a second sidewall formed by a second portion of the dielectric material; Material is formed in the first trench; and A second trench is formed across the first remaining portion of the material layer to form memory cells from the second remaining portion of the material layer, such that a first memory cell in the memory cells is adjacent to a portion of the first sidewall of the trench in the first trench, and a second memory cell in the memory cells is adjacent to a portion of the second sidewall of the trench in the first trench.

22. The method of claim 21, wherein each of the memory cells includes a first transistor coupled to a second transistor, the first transistor including a first portion of the material, and the second transistor including a second portion of the material.

23. The method of claim 21, wherein forming the material in the first trench includes forming an additional dielectric material in each of the first trenches, such that a portion of the additional dielectric material is located between the first memory cell and the second memory cell after the second trench is formed.

24. The method of claim 21, wherein forming the material hierarchy comprises: A conductive material is formed on the substrate; A semiconductor material is formed on top of the conductive material; and The dielectric material is formed on top of the semiconductor material.

25. The method of claim 21, wherein the conductive material is formed such that each of the memory cells includes a portion electrically coupled to the conductive material.

26. The method of claim 21, wherein each of the memory cells comprises a charge storage structure formed of the material.

27. The method of claim 26, wherein each of the memory cells comprises a portion formed of a portion of the material in the first trench, and the portion of each of the memory cells comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

28. The method of claim 21, further comprising: After the second trench is formed, access lines are formed such that each of the access lines is electrically isolated from the memory cell.

29. The method of claim 28, further comprising: After the access line is formed, a data line is formed such that each of the data lines has a length in the first direction, and each of the data lines is electrically coupled to at least a portion of the remainder of the material layer.

30. The method of claim 21, further comprising: A first conductor is formed in the first trench within the second trench; A second conductor is formed in the second trench within the second trench; and A conductive portion is formed that is electrically coupled to the first wire and the second wire, wherein the conductive portion is located between the first memory cell and the second memory cell.

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