Sensor modules for scanning electron microscopy applications

Abstract

A scanning electron microscope (SEM) system is disclosed. The SEM system includes an electron source configured to generate an electron beam and a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes. The SEM system includes a first detector module positioned at the one or more imaging planes, wherein the first detector module includes a multi-pixel solid-state sensor configured to convert scattered particles, such as electrons and / or x-rays, from the sample into a set of equivalent signal charges. The multi-pixel solid-state sensor is connected to two or more application-specific integrated circuits (ASICs) configured to process the set of signal charges from one or more pixels of the sensor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 892,545, filed on August 28, 2019, with Marcel Trimpl as the inventor, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates generally to the field of scanning electron microscopy, and more particularly to a multipurpose sensor module for scanning electron microscopy applications that provides adaptive clustering and distributed digitization schemes. Background Art

[0004] The manufacture of semiconductor devices, such as logic and memory devices, typically involves processing a substrate, such as a semiconductor wafer, using a number of semiconductor manufacturing processes to form the various features and multiple layers of the semiconductor device. As semiconductor device sizes become smaller, the development of enhanced semiconductor device and photomask inspection and re-inspection equipment has become increasingly important. Scanning electron microscope (SEM) systems are one such technology used for inspecting and re-inspecting samples. SEM systems incorporate particle detectors for detecting secondary electrons, backscattered electrons, and x-rays that are scattered from or emitted by the sample in response to a primary electron beam scanned across the sample. To improve the efficiency and accuracy of SEM systems, it would be desirable to provide improved particle (e.g., electron and x-ray) sensor devices and methods. Summary of the Invention

[0005] A scanning electron microscope system is disclosed. In one illustrative embodiment, the system includes an electron source configured to generate an electron beam. In another illustrative embodiment, the system includes a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes. In another illustrative embodiment, the system includes a first detector module positioned at the one or more imaging planes. In another illustrative embodiment, the first detector module includes a multi-pixel solid-state sensor configured to convert scattered particles from the sample into a set of equivalent signal charges. In another illustrative embodiment, the multi-pixel solid-state sensor is connected to two or more application-specific integrated circuits (ASICs) configured to process the set of signal charges from one or more pixels of the sensor.

[0006] An additional and / or alternative scanning electron microscope is disclosed. In one illustrative embodiment, the system includes an electron source configured to generate an electron beam. In another illustrative embodiment, the system includes a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes. In another illustrative embodiment, the system includes a first detector module positioned at the one or more imaging planes. In another illustrative embodiment, the first detector module includes a multi-pixel application-specific integrated circuit (ASIC). In another illustrative embodiment, each pixel of the multi-pixel ASIC includes a photodiode configured to convert particles scattered by the sample into an equivalent electrical signal, and each pixel of the multi-pixel ASIC includes circuitry for processing the equivalent electrical signal.

[0007] A method for inspecting a sample is disclosed. In one illustrative embodiment, the method includes generating a scan clock signal. In another illustrative embodiment, the method includes generating a first electron beam. In another illustrative embodiment, the method includes deflecting the first electron beam in synchronization with the scan clock signal to scan an area on the sample. In another illustrative embodiment, the method includes directing a signal generated by the sample in response to the electron beam to a cluster comprising two or more pixels. In another illustrative embodiment, the method includes detecting charge collected by the cluster in a first time interval, wherein the first time interval is synchronized with the scan clock to generate a first electrical signal corresponding to the charge collected by the cluster in the first time interval, and converting the first electrical signal into a first digital signal. In another illustrative embodiment, the method includes detecting charge collected by the cluster in a second time interval, wherein the second time interval is synchronized with the scan clock to generate a second electrical signal corresponding to the charge collected in the second time interval, and converting the second electrical signal into a second digital signal, wherein conversion of the second electrical signal begins before conversion of the first electrical signal is completed. In another illustrative embodiment, the method includes determining the presence of a defect by analyzing the first digital signal and the second digital signal.

[0008] An additional and / or alternative method for inspecting a sample is disclosed. In one illustrative embodiment, the method includes generating a scan clock signal. In another illustrative embodiment, the method includes generating a first electron beam. In another illustrative embodiment, the method includes deflecting the first electron beam to a first position on the sample. In another illustrative embodiment, the method includes directing a signal generated by the sample in response to the first electron beam to a pixel. In another illustrative embodiment, the method includes detecting charge collected by the pixel to generate an electrical signal corresponding to the charge collected by the pixel. In another illustrative embodiment, the method includes comparing the electrical signal to a first threshold and a second threshold and determining the presence of an element if the electrical signal is greater than the first threshold and the electrical signal is less than the second threshold.

[0009] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and do not necessarily limit the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Many of the advantages of the present disclosure may be better appreciated by those skilled in the art by referencing the accompanying drawings.

[0011] Figure 1 A scanning electron microscope system according to one or more embodiments of the present disclosure is described.

[0012] Figure 2A A multi-pixel detector module configured as a secondary electron detector according to one or more embodiments of the present disclosure is described.

[0013] Figure 2B A multi-pixel detector module configured as a backscattered electron and / or x-ray detector in accordance with one or more embodiments of the present disclosure is described.

[0014] Figure 2C A multi-pixel detector module arranged in a multi-electron beam configuration according to one or more embodiments of the present disclosure is described.

[0015] Figures 3A to 3D The combination of clusters delivered to a selected number of channels by an ASIC is described in accordance with one or more embodiments of the present disclosure.

[0016] Figure 4A A block diagram illustrating the connections between a sensor and an ASIC and the operations within one readout channel according to one or more embodiments of the present disclosure.

[0017] Figure 4BConceptual diagram illustrating a rough plan view of a sensor pixel according to one or more embodiments of the present disclosure.

[0018] Figures 5A to 5B The physical assembly of a detector module according to one or more embodiments of the present disclosure is separately described.

[0019] Figures 5C to 5D The physical assembly of a detector module according to one or more additional and / or alternative embodiments of the present disclosure is individually described.

[0020] Figure 6A A conceptual diagram illustrating the timing of a distributed digitization scheme using several ADCs within an ASIC to process a cluster, according to one or more embodiments of the present disclosure.

[0021] Figure 6B Conceptual diagram illustrating the application of sample-and-hold circuitry to signals from one or more pixels and subsequent analog-to-digital conversion of the signals in accordance with one or more embodiments of the present disclosure.

[0022] Figure 7 A block diagram illustrating an analog-to-digital conversion (ADC) unit implemented within a pixel of a readout ASIC in accordance with one or more embodiments of the present disclosure.

[0023] Figure 8 A flow chart depicting a method of testing a sample is illustrated in accordance with one or more embodiments of the present disclosure.

[0024] Figure 9 A flow chart depicting a method of testing a sample is illustrated according to one or more additional and / or alternative embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] The present disclosure has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments described herein are to be considered illustrative rather than restrictive. It will be readily apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present disclosure. Reference will now be made in detail to the disclosed subject matter as illustrated in the accompanying drawings.

[0026] Embodiments of the present disclosure relate to multi-purpose sensor modules and methods suitable for scanning electron microscopy applications with adaptive clustering and distributed digitization schemes.

[0027] Figure 1A conceptual diagram illustrating a scanning electron microscope (SEM) system 100 according to one or more embodiments of the present disclosure. The SEM system 100 can be configured as an inspection and / or re-inspection tool. In this regard, the SEM system 100 can be used to re-inspect and / or inspect a sample 128 for defects and reveal the material composition of the sample 128 and / or the defects. Alternatively, the SEM system 100 can be configured as an imaging-based overlay metrology tool. In this regard, the SEM system 100 can be used to acquire images of an overlay metrology target disposed on the sample 128, which can then be used to determine overlay errors between successive layers of the sample 128.

[0028] In one embodiment, the SEM system 100 includes an electron source 102. The electron source 102 may include any electron source suitable for generating one or more electron beams 150. The electron source 102 may include one or more electron emitters 101. For example, the one or more electron emitters 101 may include a single electron emitter. By way of another example, the one or more electron emitters 101 may include a plurality of electron emitters. The one or more electron emitters 101 may include any electron emitter known in the electron emission art. The electron source 102 may include one or more extractors 103.

[0029] In one embodiment, the SEM system 100 includes an electron optical system 111, which includes a set of electron optical devices arranged in an electron optical column. The electron optical system 111 may include one or more focusing optics for focusing the electron beam 106 onto the sample 128. The electron optical system 111 may include one or more deflection optics configured to scan the beam 106 across the sample 128. The electron optical system 111 may include any focusing and deflection optics known in the art of scanning electron microscopy. For example, the one or more focusing optics may include, but are not limited to, one or more condenser lenses 107 and one or more objective lenses 110. The one or more deflection optics may include, but are not limited to, one or more deflectors (e.g., scanning coils). For example, the electron optical system 111 may include one or more deflectors 105 and one or more lower deflectors 109. During operation, the electron source 102 generates the electron beam 106. The electron beam 106 may be focused and deflected onto a sample 128 positioned on a moving stage 130 by a plurality of focusing and deflecting optics 105, 107, 109, 110 of an electron optical system 111. In an embodiment, the electron source 102 may generate a plurality of beams that are deflected and focused onto the sample 128. It should be noted that the electron source 102 and the electron optical column 111 may be arranged in a single beam configuration or in a multi-beam configuration including multiple sources / columns.

[0030] In an embodiment, the system 100 includes one or more detector modules positioned at one or more selected locations within the electron optical system 111. The one or more detector modules each include one or more multi-pixel solid-state sensors. For example, the detector modules 122a, 122b, and / or 122c may each include one or more solid-state sensors. For example, the first multi-pixel detector module 122a may be positioned away from the sample 128 to collect secondary electrons 129 scattered from the sample and collected by the electrode 121 and accelerated to the detector plane of the one or more multi-pixel solid-state sensors of the detector module 122a. In another example, the detector modules 122b and / or 122c may be positioned close to the sample 128 to collect particles, such as (but not limited to) backscattered electrons, x-rays, and / or Auger electrons (e.g., particles emitted from the sample at very high solid angles) emitted from the sample 128. As Figure 1 As shown in FIG, one or more of the detector modules 122a to 122c may be positioned within an electron optical column. Figure 1 The positions or number of detector modules depicted in and any number of multi-pixel detector modules and any number of positions may be implemented within system 100.

[0031] In an embodiment, one or more of the multi-pixel solid-state sensors of detector modules 122a, 122b, and / or 122c are connected to two or more logic elements. For example, one or more of the multi-pixel solid-state sensors may be connected to two or more application-specific integrated circuits (ASICs). In an embodiment, the two or more logic elements are configured to process the set of signal charges from the pixels of a given multi-pixel solid-state sensor. While it should be noted that one or more detector modules can utilize any suitable logic element known in the art to process the signal charges from the pixels, for the purpose of simplicity, the detector modules are described in the context of an ASIC. This configuration should not be interpreted as limiting the scope of the present disclosure.

[0032] Figures 2A to 2C Different configurations of multi-pixel detector module 122 suitable for use in system 100 are described in accordance with one or more embodiments of the present disclosure. Figure 2A A multi-pixel detector module configuration suitable for use as a secondary electron detector is described. Figure 2B A multi-pixel detector module configuration suitable for use as a backscattered electron and / or x-ray detector is described. Figure 2C A multi-pixel detector module configuration for a multiple electron beam system is described, wherein deflection signals from all electron beams are detected simultaneously by the multi-pixel detector module.

[0033] In an embodiment, Figure 2A, the multi-pixel detector module 122 includes a substrate carrier 201. For example, the substrate carrier 201 may include a ceramic material on which the multi-pixel solid-state sensor read out by the ASIC is mounted. The substrate carrier 201 includes a set of electrical contacts 203 for manipulating and controlling voltages and provides a data path, allowing data to be collected by the module. Area 202 represents the area covered by one ASIC. For example, Figure 2B , area 202 represents the area covered by an ASIC having a size of 4 mm x 4 mm that may contain 16 x 16 pixel readout channels. Figure 2A The number, size, or location of the pixel ASIC clustering shown in FIG limit the scope of this disclosure. Rather, it should be noted that different ASIC clustering configurations can be implemented for different use cases. The cluster sizes and resulting cluster conversion rates are illustrated in Table 1.

[0034] Table I. Cluster conversion rates for various cluster sizes.

[0035]

[0036]

[0037] The examples used 250 μm sensor pixels, and a total of 16×16 sensor pixels per ASIC readout and a data converter with a conversion rate of 3 MHz incorporated into each readout pixel.

[0038] exist Figure 2A In the example of , a cluster size of 8×8 pixels is configured and a total of 4 clusters per ASIC are generated. This configuration can be particularly useful in the case of secondary electron detectors. The conversion rate per cluster in this configuration is approximately 200 MHz. In addition, the clusters generated by the ASIC can be further processed in the downstream data path to generate one or more sub-channels of the detector. It should be noted that Figure 2B A case is described in which 5 channels are generated by a module.

[0039] In an embodiment, Figure 2B As shown in , multiple detector modules can be implemented. Figure 2B In the example depicted in FIG, a plurality of detector modules 122 (e.g., 2, 3, 4, 5, 6, N detector modules) are arranged around the primary beam 106 to form a through aperture 205 close to the sample plane (e.g., the wafer plane) to collect backscattered electrons and / or other particles, such as x-rays or Auger electrons, at a high solid angle. In embodiments, each detector module 122 may be configured differently depending on the purpose of detection. Figure 2BIn one application shown in FIG, three detector modules are configured to have a cluster size of 2×2, and one detector module (top right) is configured to detect x-rays emitted by the sample. It should be noted that the arrangement, number, and cluster size are not limited to the previous description. Rather, it should be noted that Figure 2B The set of detector modules shown in FIG20 can include any number of modules 122 arranged in any pattern to form aperture 205, and the modules can have any cluster size. It should be noted that a cluster size of 4×4 can be used, which yields a cluster slew rate approaching 50 MHz. For x-ray detection, the detector modules can be configured to read out each pixel individually (e.g., a 1×1 cluster) at a slow slew rate (e.g., but not limited to, 3 MHz).

[0040] In an embodiment, one or more of the detector modules 122 may include a screen 204. The screen 204 may be inserted on top of one or more modules 122. The screen may be formed of a thin material with a low atomic number. For example, the screen 204 may include, but is not limited to, a 50 μm to 150 μm thin beryllium screen. For example, the screen may be a 100 μm beryllium screen. By way of another example, the screen may include a layer of material formed directly onto the sensor module 122. For example, the screen may include, but is not limited to, a layer of boron or carbon or aluminum deposited directly onto the sensor module 122. During operation, the screen 204 absorbs electrons scattered by the sample during scanning and allows most of the x-rays generated by the sample during scanning to pass through, thereby providing more efficient detection. The screen 204 may be added to one or more of the detector modules and it may be permanently installed or may be inserted and retracted to change the configuration of the module 122. It should be noted that the utilization of the screen 204 is not limited to Figure 2B The configuration depicted in FIG and one or more screens 204 may be utilized with any number of detection modules 122 and in any arrangement.

[0041] In an embodiment, Figure 2C , the ASIC of the detector module 122 is configured with a cluster size of 4 x 4. It should be noted that if such a detector module is implemented in a multi-beam configuration of the SEM system 100, then such a module would be employed to detect a total of 400 scattered beams at a rate approaching 50 MHz.

[0042] Figures 3A to 3D The combination of clusters delivered to a selected number of channels by an ASIC according to one or more embodiments of the present disclosure is illustrated. It should be noted that the SEM system 100 may be adapted for different use cases. Figures 3A to 3D For example, the formation of multiple channels is shown in Figure 3A, illustrating a configuration with one central channel 301 and four side channels 302a, 302b, 302c, 302d. The clustering can be performed dynamically during scanning, whereby the shape and size of the channels can be changed within the module 122. This feature can accommodate changes in the scattered beam 129 during scanning, such as changes in the focus / defocus of the main beam 106 or deviations of the scattered beam 129. For example, Figure 3B The cluster configuration is to accommodate situations in which the scattered electron beam 129 is offset or drifted (moved from a central position of the module to a non-central position).

[0043] By way of another example, it is possible to implement Figure 3C To accommodate scenarios where a larger central channel is required. By way of another example, one can implement Figure 3D Cluster configurations can be used to accommodate scenarios where a smaller central channel is desired. By way of another example, multiple individual clusters can be combined into a single central channel.

[0044] Figure 4A A block diagram illustrating the connections between a sensor and an ASIC and the operations within one readout channel according to one or more embodiments of the present disclosure.

[0045] In one embodiment, sensor 401 is attached to one or more ASICs 402 using at least one connection per pixel. In one configuration, sensor pixel 403 can consist of a floating diffusion node (FD), such as a floating diffusion capacitor, that collects charge generated within the pixel in a volume connected to the gate of an amplifier stage. In this example, the amplifier stage can be biased by a common voltage, VOD (voltage on drain). The output (OS) of the amplifier stage can be connected to an individual readout pixel 404 of the ASIC for further processing. In one embodiment, the amplifier in the sensor pixel can be connected so that the source potential is biased at a constant voltage and the signal is read out at the drain.

[0046] In an embodiment, the voltage of the floating diffusion node is controlled by a reset stage. In this configuration, the reset stage may include a simple reset transistor, whereby the drain of the transistor is connected to a global reset voltage (RD). The reset stage may be controlled via a reset gate (RG).

[0047] In an embodiment, the reset gate may provide a global signal common to all pixels of the sensor array.

[0048] In embodiments, an additional contact per pixel may be provided between the reset gate of the pixel of the sensor layer and the reset circuit unit within each pixel of the ASIC.

[0049] The top sensor stack 401 of the assembly may be a sensor layer utilizing resistive gate and floating diffusion technology as described in U.S. Patent No. 9,767,986, issued to Brown et al. on September 19, 2017, entitled “Scanning Electron Microscope and Method for Inspecting and Re-inspecting Specimens,” which is incorporated herein by reference in its entirety.

[0050] In an embodiment, instead of using a sensor layer 401 attached to a readout ASIC, a photodiode may be implemented in each pixel of the ASIC to detect particles deflected from the sample 128 during scanning. The photodiode may be implemented by deep implantation using a high voltage (HV) process with a power rail above 10V.

[0051] In one embodiment, the pixel of the readout ASIC 404 receives a signal from a sensor pixel using an input stage. Parasitic impedance between the amplifier output and the input stage can be kept to a minimum to achieve maximum processing speed at a given power consumption. The input stage is connected through a cluster summing circuit that sums the signals from this pixel and adjacent pixels into a cluster. Figure 4A The connections from the center pixel and its two immediate neighbors are shown, indicating additional input from other nearby pixels. A practical size for a cluster should be in the range of 1 to 10 pixels, where cluster 1 means that summation is disabled and each pixel is processed individually (e.g., see the example given in Table 1). The cluster signal can then be further processed by digitization and additional processing. The digitization step can include standard analog-to-digital conversion with equidistant quantization steps or a multi-threshold chemical element search, such as Figure 7 For applications involving the detection of individual events, a timestamp unit can be implemented to record the arrival of each event using the scan clock and assign the event to a scan position on the sample. It should be noted that part of the post-processing involves the data stream manipulation necessary to evacuate the data from each pixel from each ASIC. The summation of the pixel values ​​can be performed in the post-processing unit after digitization.

[0052] In embodiments, a reset circuit can be triggered by a digitizing unit to control the voltage of the reset gate of a sensor pixel. The reset circuit can use high-voltage process components to provide sufficient voltage to enable the reset stage to function (e.g., 10V to 30V). Control of the reset gate can take the form of a reset pulse to reset the floating diffusion. A pixel-by-pixel reset can indefinitely extend the dynamic range of the sensor pixel and accommodate variations in particle flux between pixels within the sensor. This reset pulse can be synchronized for all pixels of the sensor to mimic the functionality of a global reset. Utilizing a pixel-by-pixel reset allows for extremely fast resets at low power because much smaller capacitance is driven compared to a global reset routed throughout the sensor array. The reset circuit can also provide an analog voltage to form a closed feedback loop control of the floating diffusion to enhance immunity to pixel-to-pixel transistor variations and thermal drift.

[0053] Figure 4B Conceptual diagram illustrating a rough plan view of a sensor pixel according to one or more embodiments of the present disclosure. Figure 4B Depicts a rough plan view of a sensor pixel with reset gate (RG) and output signal (OS) connections to the readout ASIC and other bias points, the reset drain (RD) and voltage drain (VOD) of the sensor pixel routed as global signals for the entire sensor array. In embodiments, where a reset gate (RG) is not provided for each pixel from the ASIC, the reset gate (RG) can be routed similarly to the reset drain and voltage drain signals, either row by row or globally across the sensor.

[0054] Figures 5A to 5B The physical assembly of the detector module 122 according to one or more embodiments of the present disclosure is separately described.

[0055] Figure 5A Depicts a backside view of one embodiment of a multi-pixel detector module with several ASICs 507 connected to the sensor. View onto the backside of the ASICs. Figure 5B A side view of a detector module 122 is depicted, including a multi-pixel solid-state sensor 502 with backside processing 501. In an embodiment, the backside processing may include a boron coating. In an embodiment, the sensor layer is connected to a through-silicon via interposer (TSI) 504 via solder bumps. Other assembly techniques, such as direct bond interconnect (DBI), may be utilized. A TSI of approximately 100 μm thickness may utilize fine pitch (10 μm to 20 μm). Through-silicon vias 505 may electrically connect the front side of the TSI to the back side. The pitch of the TSVs in the TSI may be much denser than the pixel pitch in the sensor or ASIC. A multi-metal redistribution layer (RDL) comprising multiple metal layers 506 (e.g., 4 or more) is used on the backside of the TSI to route different pixel outputs from the sensor to the inputs of the ASIC 507, which may be at different pitches. For example, a 250 μm × 250 μm pixel on the sensor layer may be matched to an approximately 180 μm × 180 μm pixel in the ASIC.

[0056] In an embodiment, Figure 5B , the ASIC may implement TSVs and the inputs and outputs of the ASIC may be connected on the backside of the ASIC to electrical connections on the mechanical substrate 509. With 16x16 pixels covered by each ASIC, the difference in pixel size between the ASIC and the sensor may leave approximately 1 mm of space between the ASICs as assembly margin.

[0057] In an embodiment, the ASIC may not contain TSVs. In this case, Figure 5C and 5DAs shown in FIG, an alternative assembly can be implemented. In this embodiment, a row of ASICs 511 at the side of the sensor is offset so that the wire bond pads are exposed and accessible for connection to the substrate. The transmission of operating signals and data from one ASIC to other ASICs below the sensor area can be accomplished via additional solder connections to the TSI and routed within the TSI's RDL to the other ASICs.

[0058] It should be noted that in embodiments where the detector module 122 utilizes one or more TSVs in an ASIC, it is possible to construct an indefinitely scalable detector module without creating gaps within the sensitive area of ​​the module.

[0059] The following procedures can be used to produce Figure 5D The assembly depicted in .

[0060] TSI 504 can be manufactured with a selected thickness (e.g., approximately 100 μm), ASIC 507 can be thinned to a selected thickness (e.g., approximately 100 μm), and an unthinned sensor 502 can be provided. First, a handle wafer (not shown) can be attached to the front side of sensor 502 (i.e., as shown in FIG. Figure 5D ). Next, the back side of the sensor 502 may be thinned. After thinning, the back side of the sensor 502 may be processed. For example, the back side of the sensor 502 may be processed using a boron implantation process to form a boron implanted layer 501. Next, a handle wafer (not shown) may be attached to the back side of the sensor 502 (i.e., as shown in FIG. 1 ). Figure 5D 509). The handle wafer can then be removed from the front side of sensor 502. The front side of sensor 502 can then be electrically connected to the front side of the TSI via one or more connection mechanisms 503 (e.g., using solder bumps or direct bonding (DBI) techniques). Additionally, ASIC 507 can be electrically connected to the back side of TSI 504 using redistribution layer 506. Finally, the handle wafer can be removed from the back side of sensor 502 and the sensor / TSI / ASIC assembly can be attached to substrate 509. The handle wafer can be removed after the sensor / TSI / ASIC assembly is attached to substrate 509.

[0061] It should be noted that for manufacturing Figure 5B The procedure for the assembly depicted in the example may be similar to that used for Figure 5D In the method of the assembly process described in the Figure 5B The assembly may include an ASIC with TSVs (through silicon vias) and additional steps whereby a handle wafer is used to thin and mount the ASIC 507 to the substrate 509 and electrically connect the pads with the solder bumps 513 .

[0062] Figure 6AConceptual diagram 600 illustrating the timing of a distributed digitization scheme using several ADCs within an ASIC to process a cluster according to one or more embodiments of the present disclosure. Note that the distributed digitization scheme may employ any number of ADCs, such as, but not limited to, 256. Figure 6B A conceptual diagram 610 depicts a sample-and-hold (S&H) circuit for a signal from one or more pixels and the subsequent analog-to-digital conversion of the signal. Figure 6B As shown in Figure 1, each digitizer can employ fast S&H circuitry that can maintain analog values ​​at the speed of the sample scan clock t1, at which the electron beam is rastered across the sample. Each ADC can then convert the analog value to a digital value within a conversion time t2, which is significantly slower than t1. The conversion time t2 is compatible with the number of sample scans and the number of pixels (and therefore ADCs) grouped into a cluster. In one example, a sensor's 8×8 pixels can be grouped into a cluster, and 64 ADCs used for conversions in this cluster. In this example, a single conversion frequency of 3 MHz can then support a wafer scan clock of 192 MHz.

[0063] Figure 7 The analog-to-digital conversion (ADC) unit 700 within each pixel of a readout ASIC according to one or more embodiments of the present disclosure is illustrated. In embodiments, an initial S&H unit stores the acquired signal from the detector for each clock cycle of the sample scan. The ADC 700 can then be used for classic analog-to-digital conversion following the SAR (Successive Approximation Register) ADC principle. In 'ADC mode,' the DAC (Digital-to-Analog Converter) is fed by a lookup table (LUT), which is a standard conversion table containing standard conversion steps from a binary search that results in equidistant digitization.

[0064] In embodiments, the DAC may also be driven by a lookup table (LUT) containing reference levels equivalent to upper and lower thresholds (defining an energy window) for chemical elements that may be present during a sample scan (e.g., silicon, aluminum, copper, titanium, and other elements). The result of comparing each signal to the energy window yields the presence of a specific chemical element. This mode may be referred to as 'element ID mode.' In embodiments, the ADC unit 700 may be switched between ADC mode and element ID mode. It should be noted that switching between ADC mode and element ID mode may simply require a different configuration of the lookup table used in the ADC. The ADC unit may contain multiple comparators, one for the upper threshold and one for the lower threshold, defining an energy window for each specific element to be detected.

[0065] Figure 8A flow chart illustrating a method 800 for testing a sample according to one or more embodiments of the present disclosure is provided. It should be noted herein that the steps of method 800 may be implemented in whole or in part by system 100. However, it should be further appreciated that method 800 is not limited to system 100, as additional or alternative system-level embodiments may implement all or a portion of the steps of method 800.

[0066] In step 802, the method includes generating a scan clock signal. In step 804, the method includes generating a first electron beam. In step 806, the method includes deflecting the first electron beam in synchronization with the scan clock signal to scan an area on a sample. In step 808, the method includes directing a signal generated by the sample in response to the electron beam to a cluster comprising two or more pixels. In step 810, the method includes detecting charge collected by the cluster in a first time interval, wherein the first time interval is synchronized with the scan clock to generate a first electrical signal corresponding to the charge collected by the cluster in the first time interval, and converting the first electrical signal into a first digital signal. In step 812, the method includes detecting charge collected by the cluster in a second time interval, wherein the second time interval is synchronized with the scan clock to generate a second electrical signal corresponding to the charge collected in the second time interval, and converting the second electrical signal into a second digital signal, wherein conversion of the second electrical signal begins before conversion of the first electrical signal is completed. In step 814, the method includes determining the presence of a defect by analyzing the first digital signal and the second digital signal.

[0067] Figure 9 A flow chart illustrating a method 900 for testing a sample according to one or more additional and / or alternative embodiments of the present disclosure is provided. It should be noted herein that the steps of method 900 may be implemented in whole or in part by system 100. However, it should be further appreciated that method 900 is not limited to system 100, as additional or alternative system-level embodiments may implement all or a portion of the steps of method 900.

[0068] In step 902, the method includes generating a scan clock signal. In step 904, the method includes generating a first electron beam. In step 906, the method includes deflecting the first electron beam to a first position on the sample. In step 908, the method includes directing a signal generated by the sample in response to the first electron beam to a pixel. In step 910, the method includes detecting charge collected by the pixel to generate an electrical signal corresponding to the charge collected by the pixel. In step 912, the method includes comparing the electrical signal to a first threshold and a second threshold and determining the presence of an element if the electrical signal is greater than the first threshold and the electrical signal is less than the second threshold.

[0069] Reference again Figure 1In one embodiment, the system 100 includes a controller 140. The controller 140 may be used to provide one or more control signals C to the electron source 102, the electron optical column 111, and / or the detector assemblies 122a-122c. In this regard, the controller 140 may control any aspect of the SEM system 100. In one embodiment, the controller 140 may receive one or more image data signals ID1, ID2 from the detector assemblies 122a-122c that are indicative of or contain one or more characteristics of the sample 128 (e.g., defects, pattern features, metrology targets, and the like). The controller 140 may include one or more processors configured to execute program instructions maintained in a memory medium. In this regard, the one or more processors of the controller 140 may perform any of the various process steps described throughout this disclosure.

[0070] All methods described herein may include storing the result of one or more steps of method embodiments in a memory. The result may include any one of the results described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the result has been stored, the result may be accessed in the memory and used by any one of the method or system embodiments described herein, formatted to display to the user, used by another software module, method or system, and the like. In addition, the result may be "permanent", "semi-permanent", "temporary" or stored within a certain period of time. For example, the memory may be a random access memory (RAM), and the result may not necessarily remain in the memory indefinitely.

[0071] It is further contemplated that each of the embodiments of the method described above may include any other step(s) of any other method(s) described herein. In addition, each of the embodiments of the method described above may be performed by any of the systems described herein.

[0072] Those skilled in the art will recognize that the components, operations, devices, objects, and accompanying discussions described herein are used as examples for conceptual clarity and are contemplated to include various configuration modifications. Therefore, as used herein, the specific examples and accompanying discussions set forth are intended to represent their more general class. In general, the use of any specific example is intended to represent its class, and the omission of specific components, operations, devices, and objects should not be considered limiting.

[0073] As used herein, directional terms such as "top," "bottom," "above," "below," "up," "upward," "down," "downwardly," and "downwardly" are intended to provide relative positions for descriptive purposes and are not intended to specify an absolute frame of reference. Various modifications to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments.

[0074] With respect to the use of substantially any plural and / or singular terms herein, those skilled in the art can translate from the plural to the singular and / or from the singular to the plural depending on the context and / or application. For clarity, various singular / plural permutations are not explicitly set forth herein.

[0075] The subject matter described herein sometimes describes different components contained within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and in fact many other architectures that achieve the same functionality can be implemented. In a conceptual sense, any component arrangement used to achieve the same functionality is effectively "associated" so that the desired functionality is achieved. Therefore, any two components combined herein to achieve a specific functionality can be considered to be "associated" with each other so that the desired functionality is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered to be "connected" or "coupled" to each other to achieve the desired functionality, and any two components that can be so associated can also be considered to be "coupleable" to each other to achieve the desired functionality. Specific examples of coupleable include, but are not limited to, components that can be physically matched and / or physically interact and / or components that can wirelessly interact and / or wirelessly interact and / or components that logically interact and / or components that can logically interact.

[0076] Furthermore, it should be understood that the present invention is defined by the appended claims. Those skilled in the art will understand that, in general, the terms used herein, and particularly in the appended claims (e.g., the bodies of the appended claims), are generally intended to be "open-ended" terms (e.g., the term "comprising" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including, but not limited to," and the like). Those skilled in the art will further understand that if a specific number of introduced claim recitations is intended, such intention will be explicitly recited in the claims, and in the absence of such recitation, such intention is not present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as implying that a claim recitation introduced by the indefinite article "a" or "an" limits any particular claim containing the introduced claim recitation to the invention containing only that recitation, even if the same claim contains the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be construed to mean "at least one" or "one or more"); the foregoing applies equally to the use of definite articles to introduce claim recitations. In addition, even if a specific number of introduced claim recitations is explicitly recited, those skilled in the art will recognize that this recitation should generally be construed to mean at least that number of recitations (e.g., simply reciting "two recitations" without other modifiers generally means at least two recitations or two or more recitations). Furthermore, in those instances where conventional expressions similar to “at least one of A, B, and C, and the like” are used, such construction generally means what one skilled in the art would understand the conventional expression to mean (e.g., “a system having at least one of A, B, and C” would include, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or both A, B, and C, and the like). In those instances where conventional expressions similar to “at least one of A, B, or C, and the like” are used, such construction generally means what one skilled in the art would understand the conventional expression to mean (e.g., “a system having at least one of A, B, or C” would include, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or both A, B, and C, and the like). Those skilled in the art will further understand that virtually any transitional conjunction and / or phrase, whether in the description, claims, or drawings, presenting two or more alternative items should be understood to encompass the possibility of including one, either, or both of the items.For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0077] It is believed that the present disclosure and its many attendant advantages will be understood from the foregoing description, and it will be appreciated that various changes may be made in the form, construction, and arrangement of components without departing from the disclosed subject matter or sacrificing all of its material advantages. The forms described are for illustration only, and the appended claims are intended to cover and encompass such changes. Furthermore, it should be understood that the invention is defined by the appended claims.

Claims

1. A scanning electron microscope system comprising: an electron source configured to generate an electron beam; a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes; and a first detector module positioned at the one or more imaging planes, wherein the first detector module comprises a multi-pixel solid-state sensor configured to convert scattered particles from the sample into a set of equivalent signal charges, wherein the multi-pixel solid-state sensor is connected to two or more application specific integrated circuits (ASICs) configured to process the set of equivalent signal charges from one or more pixels of the sensor, wherein each ASIC comprises a plurality of clusters, wherein each cluster comprises at least four pixels, and wherein each ASIC is configured to: detecting charges collected by the corresponding cluster in a first time interval, wherein the first time interval is synchronized with a scan clock to generate a first electrical signal corresponding to the charges collected by the corresponding cluster in the first time interval, and converting the first electrical signal into a first digital signal; as well as detecting charges collected by the respective clusters in a second time interval, wherein the second time interval is synchronized with the scan clock to generate a second electrical signal corresponding to the charges collected in the second time interval and converting the second electrical signal into a second digital signal, wherein converting the second electrical signal begins before completing converting the first electrical signal.

2. The scanning electron microscope system of claim 1 , wherein respective pixels of the multi-pixel solid-state sensor comprise: a floating diffusion capacitor node for collecting the equivalent signal charge and generating an equivalent voltage; a reset stage for controlling the voltage of the floating diffusion capacitor node; and an amplifier to drive the voltage at the floating diffusion capacitance node to inputs of the two or more ASICs.

3. The scanning electron microscope system of claim 2, wherein the respective pixels of the multi-pixel solid-state sensor of the first detector module include second contacts connected to the reset stage of the respective pixels and controlled by the two or more ASICs.

4. The scanning electron microscope system of claim 1, wherein the electron source comprises a multi-beam electron source configured to generate a second electron beam, wherein the set of electron optics is further configured to scan the second electron beam across the sample.

5. A scanning electron microscope system according to claim 4, wherein the set of electron optical devices is further configured to focus electrons from the electron beam scattered by the sample to a first pixel of the multi-pixel solid-state sensor, and to focus electrons from the second electron beam second scattered by the sample to a second pixel of the multi-pixel solid-state sensor.

6. The scanning electron microscope system of claim 1 , wherein the first detector module comprises a multi-pixel solid-state sensor layer and an ASIC layer fabricated on different wafers and directly connected by at least one of 100 μm to 200 μm pitch micro-solder bumps or direct bonding interface connections, wherein one or more ASICs are attached to a substrate and at least one of the inputs or outputs of the one or more ASICs is connected to electrical traces on the substrate by wire bonding. 7 . The scanning electron microscope system of claim 1 , wherein the multi-pixel solid-state sensor and the two or more ASICs are connected via a through-silicon interposer (TSI).

8. The scanning electron microscope system of claim 1, wherein the two or more ASICs further comprise through-silicon vias (TSVs) to connect one or more inputs and one or more outputs of the two or more ASICs to traces on a substrate.

9. The scanning electron microscope system of claim 1 , further comprising: At least a second detector module is substantially coplanar with the first detector module, wherein the first and at least second detector modules are configured to form an aperture for the electron beam and the set of electron optics is configured such that the electron beam passes through the aperture.

10. The scanning electron microscope system of claim 1 , wherein at least one of the two or more ASICs comprises: a lookup table (LUT) configured to store a first threshold value and a second threshold value; and a comparator configured to compare signal charges with the first threshold and the second threshold, wherein the comparator is configured to generate a result indicating whether each signal charge is within the first threshold and the second threshold.

11. The scanning electron microscope system of claim 1 , wherein the first detector module comprises one or more screens, wherein the one or more screens are formed of at least one of beryllium, carbon, boron, magnesium, or aluminum.

12. The scanning electron microscope system of claim 1, wherein the first detector module is configured to detect backscattered electrons from the sample.

13. The scanning electron microscope system of claim 1, wherein the first detector module is configured to detect secondary electrons from the sample.

14. The scanning electron microscope system of claim 1, wherein the first detector module is configured to detect x-rays from the sample.

15. A scanning electron microscope system comprising: an electron source configured to generate an electron beam; a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes; and a first detector module positioned at the one or more imaging planes, wherein the first detector module comprises one or more multi-pixel application specific integrated circuits (ASICs), wherein each pixel of the one or more multi-pixel ASICs comprises a photodiode configured to convert particles scattered by the sample into an equivalent electrical signal, and each pixel of the one or more multi-pixel ASICs comprises circuitry for processing the equivalent electrical signal, wherein each multi-pixel ASIC comprises a plurality of clusters, wherein each cluster comprises at least four pixels, and wherein each ASIC is configured to: detecting charges collected by the corresponding cluster in a first time interval, wherein the first time interval is synchronized with a scan clock to generate a first electrical signal corresponding to the charges collected by the corresponding cluster in the first time interval, and converting the first electrical signal into a first digital signal; as well as detecting charges collected by the respective clusters in a second time interval, wherein the second time interval is synchronized with the scan clock to generate a second electrical signal corresponding to the charges collected in the second time interval and converting the second electrical signal into a second digital signal, wherein converting the second electrical signal begins before completing converting the first electrical signal.

16. The scanning electron microscope system of claim 15, wherein the electron source comprises a multi-beam electron source configured to generate a second electron beam, wherein the set of electron optics is further configured to scan the second electron beam across the sample.

17. The scanning electron microscope system of claim 16, wherein the set of electron optical devices is further configured to focus electrons from the electron beam scattered by the sample to a first pixel of a multi-pixel solid-state sensor, and to focus electrons from the second electron beam second scattered by the sample to a second pixel.

18. The scanning electron microscope system of claim 15, wherein the multi-pixel application specific integrated circuit (ASIC) further comprises through silicon vias (TSVs) to connect one or more inputs and one or more outputs of the multi-pixel application specific integrated circuit (ASIC) to traces on a substrate.

19. The scanning electron microscope system of claim 15, further comprising: At least a second detector module is substantially coplanar with the first detector module, wherein the first and at least second detector modules are configured to form an aperture for the electron beam and the set of electron optics is configured such that the electron beam passes through the aperture.

20. The scanning electron microscope system of claim 15, wherein the ASIC comprises: a lookup table (LUT) configured to store a first threshold value and a second threshold value; and a comparator configured to compare signal charges with the first threshold and the second threshold, wherein the comparator is configured to generate a result indicating whether each signal charge is within the first threshold and the second threshold.

21. The scanning electron microscope system of claim 15, wherein the first detector module comprises one or more screens, wherein the one or more screens are formed of at least one of beryllium, carbon, boron, magnesium, or aluminum.

22. The scanning electron microscope system of claim 15, wherein the first detector module is configured to detect backscattered electrons from the sample.

23. The scanning electron microscope system of claim 15, wherein the first detector module is configured to detect secondary electrons from the sample.

24. The scanning electron microscope system of claim 15, wherein the first detector module is configured to detect x-rays from the sample.

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