semiconductor devices

Abstract

A semiconductor device includes a first insulating substrate and a first semiconductor element bonded to the first insulating substrate via a first conductive spacer. The first insulating substrate includes a first insulating layer and a first inner conductive layer provided on one side of the first insulating layer. The surface of the first inner conductive layer includes a first region and a second region surrounding the first region and having a greater surface roughness than the first region. The first conductive spacer is bonded to the first region of the first inner conductive layer via a first bonding layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device. Background Art

[0002] Japanese Patent Application Laid-Open No. 2008-166626 discloses a semiconductor device. The device includes a semiconductor element and a pair of conductor plates facing each other with the semiconductor element interposed therebetween. A conductor spacer is interposed between one of the conductor plates and the semiconductor element, and the conductor spacer is bonded to the conductor plate via a solder layer. A groove is provided in the conductor plate to surround the solder layer. The groove prevents the molten solder from wetting and spreading during soldering between the conductor spacer and the conductor plate. Summary of the Invention

[0003] Problems to be solved by the invention

[0004] In a semiconductor device such as the one described above, it is conceivable to use an insulating substrate for at least one of the conductor plates. The so-called insulating substrate refers to a substrate for a power circuit in which a conductor layer (e.g., a metal plate) is provided on one or both sides of an insulating layer (e.g., a ceramic substrate). Typical examples of insulating substrates include, but are not particularly limited to, DBC (Direct Bonded Copper) substrates, DBA (Direct Bonded Aluminum) substrates, and AMB (Active Metal Brazed Copper) substrates. By using an insulating substrate, the heat dissipation of the semiconductor device can be maintained and its insulation can be improved. However, since the conductor layer of the insulating substrate is relatively thin, it is difficult to provide the above-mentioned grooves in the conductor layer of the insulating substrate. In the conductor layer of the insulating substrate, a technology is required that can control the wetting and spreading of bonding materials such as soldering materials.

[0005] Means used to solve problems

[0006] The semiconductor device disclosed in this specification includes a first insulating substrate and a first semiconductor element bonded to the first insulating substrate via a first conductive spacer. The first insulating substrate includes a first insulating layer and a first inner conductive layer provided on one side of the first insulating layer. The surface of the first inner conductive layer includes a first region and a second region surrounding the first region and having a greater surface roughness than the first region. The first conductive spacer is bonded to the first region of the first inner conductive layer via a first bonding layer.

[0007] In this semiconductor device, a first region and a second region having a surface roughness greater than that of the first region are provided on the surface of the first inner conductor layer, and the first region is surrounded by the second region. The first region having a smaller surface roughness has a higher wettability to the molten bonding material. In contrast, the second region having a larger surface roughness has a lower wettability to the molten bonding material. Therefore, when a bonding material (e.g., solder) is used to bond the first conductor spacer to the first region, the molten bonding material wets and spreads well within the first region and is prevented from wettably spreading to the second region. Therefore, by appropriately designing the boundary between the first region and the second region, the wetting and spreading of the bonding material within the first inner conductor layer can be intentionally controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 1 is a diagram showing the appearance of a semiconductor device 10 according to an embodiment.

[0009] Figure 2 yes Figure 1 Cross-sectional view at line II-II in FIG.

[0010] Figure 3 yes Figure 1 Cross-sectional view at line III-III in FIG.

[0011] Figure 4 It is a perspective view showing the internal structure of the semiconductor device 10 with the sealing body 52 omitted.

[0012] Figure 5 This is a perspective view showing the internal structure of the semiconductor device 10 omitting the sealing body 52 and the first insulating substrate 20 .

[0013] Figure 6 is a circuit diagram of the semiconductor device 10 .

[0014] Figure 7 1 is a diagram showing the first inner conductive layer 24 of the first insulating substrate 20 .

[0015] Figure 8 1 is a diagram showing the second inner conductor layer 34 of the second insulating substrate 30 . DETAILED DESCRIPTION

[0016] In one embodiment of the present technology, the area of ​​the first region of the first inner conductor layer can be larger than the area of ​​the surface of the first conductor spacer facing the first region. With this structure, the first bonding layer contacts the first region over a sufficient area, thereby achieving a secure bond between the first conductor block and the first inner conductor layer. In particular, during the process of roughening the surface of the second region, foreign matter scattered from the second region may adhere to the first region. Even in such cases, by designing the first region larger than the size of the first conductor spacer, it is possible to suppress a reduction in bonding strength due to such foreign matter.

[0017] In the above embodiment, the area of ​​contact between the first bonding layer and the first inner conductor layer can be larger than the area of ​​contact between the first bonding layer and the one surface of the first conductor spacer. With this structure, the first bonding layer has a suitable chamfered shape, thereby suppressing thermal stress generated within the semiconductor device (particularly, the first bonding layer and its surroundings). However, in other embodiments, the area of ​​contact between the first bonding layer and the first inner conductor layer can also be smaller than the area of ​​contact between the first bonding layer and the one surface of the first conductor spacer.

[0018] In one embodiment of the present technology, the first bonding layer can reach at least a portion of the boundary between the first region and the second region on the surface of the first inner conductive layer. With this configuration, it can be determined that the size of the first region is generally appropriate relative to the size of the first conductive spacer. However, in other embodiments, the first region may be designed to be sufficiently large relative to the size of the first conductive spacer, resulting in the first bonding layer not reaching the boundary between the first region and the second region.

[0019] In the above embodiment, the first bonding layer may extend over the entire first region of the surface of the first inner conductive layer. With this configuration, the size of the first region is considered to be more appropriate relative to the size of the first conductive spacer, and the wetting and extension of the first bonding layer can be accurately controlled by the second region.

[0020] In the above embodiment, the first bonding layer may or may not extend to the second region on the surface of the first inner conductor layer. In other words, the second region may completely prohibit or merely suppress the wetting and spreading of the molten bonding material.

[0021] In one embodiment of the present technology, the first bonding layer may be made of a solder material. However, the material constituting the first bonding layer is not limited to the solder material, and may be another conductive bonding material.

[0022] In one embodiment of the present technology, the first insulating substrate may further include a first outer conductive layer provided on the other side of the first insulating layer (i.e., on the side opposite the first inner conductive layer). This structure can improve the heat dissipation of the first insulating substrate. Furthermore, the structural symmetry of the two sides of the first insulating layer is improved, thereby suppressing warping of the first insulating substrate associated with thermal deformation. Regarding this point, while there are no particular limitations on the first inner conductive layer and the first outer conductive layer, both can be formed with identical patterns.

[0023] In one embodiment of the present technology, the semiconductor device may further include a sealing body that seals the first semiconductor element. In this case, the sealing body may be in contact with the second region of the first inner conductive layer. The second region of the first inner conductive layer has a relatively high surface roughness, thereby enabling secure adhesion to the sealing body, for example, through an anchoring effect. Therefore, when the semiconductor device includes the sealing body, the second region of the first inner conductive layer not only controls the wetting and spreading of the bonding material but also improves the sealing performance of the sealing body with respect to the first semiconductor element.

[0024] In one embodiment of the present technology, the second area of ​​the first inner conductor layer can be an area whose surface is roughened by at least one of laser irradiation, electron beam irradiation, sputtering, chemical etching, and shot peening. According to such a structure, a second area with small bumps can be uniformly formed on the surface of the first inner conductor layer. Here, there is no particular limitation on the specific surface roughness of the second area. As mentioned above, the wettability of the molten bonding material (the material constituting the first bonding layer) only needs to be no lower in the second area than in the first area. That is, the contact angle of the molten bonding material in the second area only needs to be no smaller than the contact angle of the molten bonding material in the first area. For example, relative to the case where the contact angle in the first area is less than 90 degrees, the contact angle in the second area only needs to be greater than 90 degrees.

[0025] In one embodiment of the present technology, the semiconductor device may further include a second insulating substrate disposed opposite the first insulating substrate across from the first semiconductor element. In this case, the second insulating substrate may include a second insulating layer and a second inner conductive layer disposed on one side of the second insulating layer. The surface of the second inner conductive layer may include a third region and a fourth region surrounding the third region and having a greater surface roughness than the third region. Furthermore, the first semiconductor element may be bonded to the third region of the second inner conductive layer via a second bonding layer. Thus, when the semiconductor device further includes a second insulating substrate, the structure of the first insulating substrate of the present technology can be employed for the second insulating substrate as well.

[0026] In one embodiment of the present technology, the second insulating substrate may further include a second outer conductive layer provided on the other side of the second insulating layer. This structure, similar to the first insulating substrate described above, can improve the heat dissipation of the second insulating substrate and suppress warping associated with thermal deformation of the second insulating substrate.

[0027] In one embodiment of the present technology, the semiconductor device may further include a second semiconductor element bonded to the first insulating substrate via a second conductive spacer. In this case, the first inner conductive layer of the first insulating substrate may include a fifth region and a sixth region surrounding the fifth region and having a greater surface roughness than the fifth region. Furthermore, the second conductive spacer may be bonded to the fifth region of the first inner conductive layer via a third bonding layer. Here, the fifth region may be separate from or continuous with the aforementioned first region. Additionally or alternatively, the sixth region may be separate from or continuous with the aforementioned second region.

[0028] In the above embodiment, the first inner conductive layer of the first insulating substrate may include a first portion and a second portion separated from each other on the first insulating layer. In this case, the first and second regions may be located in the first portion of the first inner conductive layer, while the fifth and sixth regions may be located in the second portion of the first inner conductive layer. This structure allows the first semiconductor element and the second semiconductor element to be electrically isolated within the shared first insulating substrate.

[0029] In the above embodiment, the semiconductor device may further include a second insulating substrate disposed opposite the first insulating substrate via a second semiconductor element. In this case, the second insulating substrate may include a second insulating layer and a second inner conductive layer disposed on one side of the second insulating layer. The surface of the second inner conductive layer may include a seventh region and an eighth region surrounding the seventh region and having a greater surface roughness than the seventh region. Furthermore, the second semiconductor element may be bonded to the seventh region of the second inner conductive layer via a fourth bonding layer. In this manner, the same structure as the first insulating substrate of the present technology can be employed for the second semiconductor element as well.

[0030] In one embodiment of the present technology, the first semiconductor element and / or the second semiconductor element may have an upper surface electrode and a lower surface electrode, and may be a switching element that switches conduction between the upper surface electrode and the lower surface electrode. In this case, the switching element is not particularly limited, but may be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0031] Example

[0032] A semiconductor device 10 according to an embodiment will be described with reference to the accompanying drawings. Semiconductor device 10 is used, for example, in a power control device for an electric vehicle and can constitute at least a portion of a power conversion circuit such as a converter or inverter. The term "electric vehicle" herein broadly refers to any vehicle that has a motor that drives the wheels, and includes examples such as electric vehicles charged with external power, hybrid vehicles that have an engine in addition to the motor, and fuel cell vehicles powered by fuel cells.

[0033] like Figures 1-6 As shown, the semiconductor device 10 includes a first semiconductor element 12, a second semiconductor element 14, and a sealing body 52. ​​The first semiconductor element 12 and the second semiconductor element 14 are sealed within the sealing body 52. ​​The sealing body 52 is made of an insulating material. Although not particularly limited, in this embodiment, the sealing body 52 is made of a thermosetting resin such as epoxy resin. The sealing body 52 has a generally plate-like shape and has an upper surface 52a and a lower surface 52b located opposite the upper surface 52a.

[0034] The first semiconductor element 12 includes a semiconductor substrate 12a, an upper surface electrode 12b, a lower surface electrode 12c, and a plurality of signal electrodes 12d. The upper surface electrode 12b and the plurality of signal electrodes 12d are located on the upper surface of the semiconductor substrate 12a, and the lower surface electrode 12c is located on the lower surface of the semiconductor substrate 12a. Although not specifically limited, the first semiconductor element 12 is a switching element that switches on and off the connection between the upper surface electrode 12b and the lower surface electrode 12c, specifically an RC-IGBT. That is, in addition to the IGBT, the first semiconductor element 12 also has a built-in return diode. Note that, as another embodiment, the first semiconductor element 12 can also be a MOSFET.

[0035] Similarly, the second semiconductor element 14 includes a semiconductor substrate 14a, an upper surface electrode 14b, a lower surface electrode 14c, and a plurality of signal electrodes 14d. The upper surface electrode 14b and the plurality of signal electrodes 14d are located on the upper surface of the semiconductor substrate 14a, and the lower surface electrode 14c is located on the lower surface of the semiconductor substrate 14a. Although not specifically limited, the second semiconductor element 14 is also a switching element that switches the upper surface electrode 14b and the lower surface electrode 14c on and off, specifically, an RC-IGBT. That is, in addition to the IGBT, the second semiconductor element 14 also has a built-in freewheeling diode. Note that, as another embodiment, the second semiconductor element 14 can also be a MOSFET.

[0036] Although not particularly limited, semiconductor elements having the same structure are used for the first semiconductor element 12 and the second semiconductor element 14. However, as another embodiment, semiconductor elements having different structures may be used for the first semiconductor element 12 and the second semiconductor element 14. For example, switching elements having different structures may be used for the first semiconductor element 12 and the second semiconductor element 14. Alternatively, the first semiconductor element 12 may be a switching element and the second semiconductor element 14 may be a diode element. Various types of power semiconductor elements may be used for the first semiconductor element 12 and the second semiconductor element 14, and are not limited to switching elements. In addition, as for the semiconductor substrates 12a and 14a of the first semiconductor element 12 and the second semiconductor element 14, although not particularly limited, they may be, for example, silicon substrates, silicon carbide substrates, or nitride semiconductor substrates.

[0037] The semiconductor device 10 further includes a first insulating substrate 20 and a second insulating substrate 30. The first insulating substrate 20 opposes the second insulating substrate 30 with the first semiconductor element 12 and the second semiconductor element 14 interposed therebetween. The first insulating substrate 20 and the second insulating substrate 30 are held together by a sealing member 52, with the space between the first insulating substrate 20 and the second insulating substrate 30 being filled with the sealing member 52. Note that the first insulating substrate 20 may be composed of two or more insulating substrates, not just a single insulating substrate. In addition to or in lieu of this, the second insulating substrate 30 may also be composed of two or more insulating substrates, not just a single insulating substrate.

[0038] The first insulating substrate 20 includes a first insulating layer 22, a first inner conductive layer 24 provided on one side of the first insulating layer 22, and a first outer conductive layer 26 provided on the other side of the first insulating layer 22. The first inner conductive layer 24 is electrically connected to the first semiconductor element 12 and the second semiconductor element 14 within the sealing body 52. ​​Meanwhile, the first outer conductive layer 26 is exposed to the outside at the upper surface 52a of the sealing body 52. ​​Thus, the first insulating substrate 20 not only constitutes a portion of the circuit but also functions as a heat sink that dissipates heat from the first semiconductor element 12 and the second semiconductor element 14 to the outside.

[0039] The first inner conductive layer 24 of the first insulating substrate 20 includes a first portion 24X and a second portion 24Y. The first portion 24X and the second portion 24Y are separated from each other and electrically insulated by the first insulating layer 22. The first portion 24X of the first inner conductive layer 24 is electrically connected to the top surface electrode 12b of the first semiconductor element 12 via the first conductive spacer 16. Specifically, the first portion 24X of the first inner conductive layer 24 is bonded to the first conductive spacer 16 via a bonding layer 60A, and the first conductive spacer 16 is bonded to the top surface electrode 12b of the first semiconductor element 12 via a bonding layer 60B. Meanwhile, the second portion 24Y of the first inner conductive layer 24 is electrically connected to the top surface electrode 14b of the second semiconductor element 14 via the second conductive spacer 18. Specifically, the second portion 24Y of the first inner conductive layer 24 is bonded to the second conductive spacer 18 via a bonding layer 60D, and the second conductive spacer 18 is bonded to the top surface electrode 14b of the second semiconductor element 14 via a bonding layer 60E. Here, the bonding layers 60A, 60B, 60C, and 60D are made of a solder material, although not particularly limited.

[0040] The first outer conductive layer 26 of the first insulating substrate 20 also includes a first portion 26X and a second portion 26Y. The first portion 26X of the first outer conductive layer 26 has the same shape as the first portion 24X of the first inner conductive layer 24. These two first portions 24X and 26X face each other across the first insulating layer 22. Similarly, the second portion 26Y of the first outer conductive layer 26 has the same shape as the second portion 24Y of the first inner conductive layer 24. These two second portions 24Y and 26Y face each other across the first insulating layer 22. Thus, if the first insulating substrate 20 has a symmetrical structure on both sides of the first insulating layer 22, warping of the first insulating substrate 20 caused by thermal deformation can be effectively suppressed. However, as another embodiment, the first outer conductive layer 26 of the first insulating substrate 20 can be composed of a single portion, rather than being divided into multiple portions 26X and 26Y.

[0041] The second insulating substrate 30 includes a second insulating layer 32, a second inner conductive layer 34 provided on one side of the second insulating layer 32, and a second outer conductive layer 36 provided on the other side of the second insulating layer 32. The second inner conductive layer 34 is electrically connected to the first semiconductor element 12 and the second semiconductor element 14 within the sealing body 52. ​​Meanwhile, the second outer conductive layer 36 is exposed to the outside at the lower surface 52b of the sealing body 52. ​​Thus, the second insulating substrate 30 not only constitutes a part of the circuit but also functions as a heat sink that dissipates heat from the first semiconductor element 12 and the second semiconductor element 14 to the outside.

[0042] The second inner conductor layer 34 of the second insulating substrate 30 includes a first portion 34X, a second portion 34Y, and a third portion 34Z. The first portion 34X, the second portion 34Y, and the third portion 34Z are separated from each other and electrically insulated on the second insulating layer 32. The first portion 34X of the second inner conductor layer 34 is bonded to the lower surface electrode 12c of the first semiconductor element 12 via a bonding layer 60C and is electrically connected to the lower surface electrode 14c. Meanwhile, the second portion 34Y of the second inner conductor layer 34 is bonded to the lower surface electrode 14c of the second semiconductor element 14 via a bonding layer 60F and is electrically connected to the lower surface electrode 14c. While not particularly limited, the bonding layers 60E and 60F are formed of a solder material.

[0043] The second outer conductor layer 36 of the second insulating substrate 30 also includes a first portion 36X, a second portion 36Y, and a third portion 36Z. The first portion 36X of the second outer conductor layer 36 has the same shape as the first portion 34X of the second inner conductor layer 34. These two first portions 34X and 36X face each other across the second insulating layer 32. Similarly, the second portion 36Y of the second outer conductor layer 36 has the same shape as the second portion 34Y of the second inner conductor layer 34. These two second portions 34Y and 36Y face each other across the second insulating layer 32. Furthermore, the third portion 36Z of the second outer conductor layer 36 has the same shape as the third portion 34Z of the second inner conductor layer 34. These two third portions 34Z and 36Z face each other across the second insulating layer 32. Thus, if the second insulating substrate 30 has a symmetrical structure on both surfaces of the second insulating layer 32, warping of the second insulating substrate 30 caused by thermal deformation can be effectively suppressed. However, as another embodiment, the second outer conductive layer 36 of the second insulating substrate 30 may be composed of a single portion, and does not need to be divided into the plurality of portions 36X, 36Y, and 36Z.

[0044] As an example, the first insulating substrate 20 and the second insulating substrate 30 in this embodiment are AMB (Active Metal Brazed Copper) substrates. The insulating layers 22 and 32 are made of ceramics such as aluminum oxide, silicon nitride, and aluminum nitride. Meanwhile, the inner conductor layers 24 and 34 and the outer conductor layers 26 and 36 are made of copper. Furthermore, the inner conductor layers 24 and 34 are nickel-plated and gold-plated on their surfaces. However, the two insulating substrates 20 and 30 may each be, for example, a DBC (Direct Bonded Copper) substrate or a DBA (Direct Bonded Aluminum) substrate, and are not limited to AMB substrates. The specific structures of the insulating substrates 20 and 30 are not particularly limited. Furthermore, the insulating substrates 20 and 30 each only need to have at least the insulating layers 22 and 32 and the inner conductor layers 24 and 34; the outer conductor layers 26 and 36 are not necessarily required.

[0045] The semiconductor device 10 further includes a connecting member 40. The connecting member 40 is located between the first insulating substrate 20 and the second insulating substrate 30 within the sealing body 52. ​​The upper surface of the connecting member 40 is bonded to the first portion 24X of the first inner conductive layer 24 via a bonding layer 60G. The lower surface of the connecting member 40 is bonded to the second portion 34Y of the second inner conductive layer 34. The connecting member 40 is made of metal (e.g., copper) or another conductor and electrically connects the first portion 24X of the first inner conductive layer 24 to the second portion 34Y of the second inner conductive layer 34. As a result, the first semiconductor element 12 and the second semiconductor element 14 are electrically connected in series within the sealing body 52.

[0046] The semiconductor device 10 further includes a first power terminal 42, a second power terminal 44, and a third power terminal 46. These three power terminals 42, 44, and 46 protrude from the sealing body 52 in the same direction and extend parallel to each other. The three power terminals 42, 44, and 46 are formed of a conductor such as copper or another metal. While not particularly limited, during the manufacturing stage of the semiconductor device 10, the three power terminals 42, 44, and 46 can be prepared together with the first signal terminal 48 and the second signal terminal 50, described later, on a single lead frame.

[0047] The first power terminal 42 is bonded to the second insulating substrate 30 within the sealing body 52. ​​Specifically, the first power terminal 42 is bonded to the first portion 34X of the second inner conductive layer 34 via a bonding layer (not shown). This electrically connects the first power terminal 42 to the lower surface electrode 12c of the first semiconductor element 12. The second power terminal 44 is bonded to the first insulating substrate 20 within the sealing body 52. ​​Specifically, the second power terminal 44 is bonded to the second portion 24Y of the first inner conductive layer 24 via a bonding layer 60I. This electrically connects the second power terminal 44 to the upper surface electrode 12b of the second semiconductor element 14. The third power terminal 46 is bonded to the second insulating substrate 30 within the sealing body 52. ​​Specifically, the third power terminal 46 is bonded to the second portion 34Y of the second inner conductive layer 34 via a bonding layer (not shown). This electrically connects the third power terminal 46 to the upper surface electrode 12b of the first semiconductor element 12 and the lower surface electrode 14c of the second semiconductor element 14.

[0048] The semiconductor device 10 also includes a plurality of first signal terminals 48 and a plurality of second signal terminals 50. These signal terminals 48 and 50 protrude from the sealing body 52 in the same direction and extend parallel to each other. The plurality of signal terminals 48 and 50 are made of a conductor such as copper or other metal. The plurality of first signal terminals 48 are electrically connected to the plurality of signal electrodes 12d of the first semiconductor element 12 inside the sealing body 52. ​​The plurality of second signal terminals 50 are electrically connected to the plurality of signal electrodes 14d of the second semiconductor element 14 inside the sealing body 52. ​​Although not particularly limited, each of the signal terminals 48 and 50 in this embodiment is connected to the corresponding signal electrode 12d via a bonding wire (not shown) made of a metal such as aluminum or copper. However, the connection between the signal terminals 48 and 50 and the signal electrodes 12d and 14d can also be made using, for example, the inner conductor layer 24 and 34 of the first insulating substrate 20 or the second insulating substrate 30, and is not limited to bonding wires.

[0049] Next, refer to Figure 7 、 Figure 8 The structures of the first inner conductor layer 24 of the first insulating substrate 20 and the second inner conductor layer 34 of the second insulating substrate 30 will be described. Figure 7As shown, in the first insulating substrate 20, the surface of the first inner conductor layer 24 is locally roughened. Consequently, a first portion 24X of the first inner conductor layer 24 is formed with a plurality of non-roughened regions NR1 and NR2 and a surrounding roughened region RG1. Roughened regions RG1 are roughened, for example, by laser irradiation, and the surface roughness of roughened regions RG1 and RG2 is greater than that of the non-roughened regions NR1 and NR2. The first conductor spacer 16 is bonded to one non-roughened region NR1 via a bonding layer 60A, while the connection component 40 is bonded to the other non-roughened region NR2 via a bonding layer 60G. The second portion 24Y of the first inner conductor layer 24 is also formed with a plurality of non-roughened regions NR3 and NR4 and a surrounding roughened region RG2. The second conductor spacer 18 is bonded to one non-roughened region NR3 via a bonding layer 60D, while the second power terminal 44 is bonded to the other non-roughened region NR4 via a bonding layer 60I.

[0050] like Figure 8 As shown, in the second insulating substrate 30, the surface of the second inner conductive layer 34 is also partially roughened. Consequently, a plurality of non-roughened regions NR5 and NR6 are formed in the first portion 34X of the second inner conductive layer 34, along with a surrounding roughened region RG3. The first semiconductor element 12 is bonded to one non-roughened region NR5 via a bonding layer 60C, while the first power terminal 42 is bonded to the other non-roughened region NR6 via a bonding layer (not shown). The second portion 34Y of the second inner conductive layer 34 also has a plurality of non-roughened regions NR7, NR8, and NR9, along with a surrounding roughened region RG4. The second semiconductor element 14 is bonded to one non-roughened region NR7 via a bonding layer 60F. The connecting component 40 is bonded to the other non-roughened region NR8 via a bonding layer 60H. Furthermore, the third power terminal 46 is bonded to yet another non-roughened region NR9 via a bonding layer (not shown).

[0051] As described above, in the semiconductor device 10 of this embodiment, a non-roughened region NR1 (first region) and a roughened region RG1 (second region) having a surface roughness greater than that of the non-roughened region NR1 are provided on the surface of the first inner conductive layer 24 of the first insulating substrate 20. The non-roughened region NR1 is surrounded by the roughened region RA1. The non-roughened region NR1, having a smaller surface roughness, has a higher wettability with the molten bonding material. In contrast, the roughened region RG1, having a larger surface roughness, has a lower wettability with the molten bonding material. Therefore, when a bonding material (e.g., solder) is used to bond the first conductive spacer 16 to the non-roughened region NR1, the molten bonding material wets and spreads well within the non-roughened region NR1 while being prevented from wettably spreading into the roughened region RG1. Therefore, by appropriately designing the boundary between the non-roughened region NR1 and the roughened region RG1, the wettability and spread of the bonding material in the first inner conductive layer 24 can be intentionally controlled.

[0052] In the semiconductor device 10 of this embodiment, the area of ​​the non-roughened region NR1 of the first portion 24X of the first inner conductor layer 24 is larger than the area of ​​the upper surface 16a of the first conductor spacer 16 that faces the non-roughened region NR1. This structure allows the bonding layer 60A (hereinafter referred to as the first bonding layer 60A) between the first inner conductor layer 24 and the first conductor spacer 16 to contact the non-roughened region NR1 of the first inner conductor layer 24 over a sufficient area. This ensures a strong bond between the first conductor spacer 16 and the first inner conductor layer 24. In particular, during the process of forming the roughened region RG1, foreign matter may sometimes adhere to the non-roughened region NR1. Even in such cases, by designing the non-roughened region NR1 larger than the size of the first conductor spacer 16, a reduction in bonding strength due to such foreign matter can be suppressed.

[0053] With the above structure, in the semiconductor device 10 of this embodiment, the area of ​​contact between the first bonding layer 60A and the first inner conductor layer 24 is larger than the area of ​​contact between the first bonding layer 60A and the upper surface 16a of the first conductor spacer 16. Thus, the first bonding layer 60A has a suitable chamfered shape, which can suppress thermal stress generated within the semiconductor device 10 (particularly, the bonding layer 60A and its surroundings). Here, the first bonding layer 60A extends over the entire non-roughened region NR1 on the surface of the first inner conductor layer 24. However, this is not limiting; the first bonding layer 60A on the surface of the first inner conductor layer 24 may only extend to at least a portion of the boundary between the non-roughened region NR1 and the roughened region RG1. Here, the first bonding layer 60A on the surface of the first inner conductor layer 24 may or may not extend into the roughened region RG1. In other words, the roughened region RG1 may either completely prohibit or merely suppress the wetting and spreading of the molten bonding material.

[0054] Depend on Figure 7 It is understood that the margin (dimensional difference) of the non-roughened region NR1 relative to the first conductor spacer 16 may be locally increased. In this case, while not particularly limited, it is preferable to increase the margin of the non-roughened region NR1 relative to the first conductor spacer 16 in the portion where the distance from the first conductor spacer 16 to the outer periphery of the first inner conductor layer 24 is large. In other words, it is preferable to decrease the margin of the non-roughened region NR1 relative to the first conductor spacer 16 in the portion where the distance from the first conductor spacer 16 to the outer periphery of the first inner conductor layer 24 is small. Thus, even in this portion where the distance is small, the roughened region RG1 can be formed with a sufficient width outside the non-roughened region NR1.

[0055] In semiconductor device 10 of this embodiment, each bonding layer 60A-60I can be formed of a solder material. However, the material forming bonding layers 60A-60I can also be another conductive bonding material, not limited to solder. Regardless of the type of bonding material, the surface roughness required for roughened regions RG1-RG4 can be designed to suppress wetting and spreading of the molten bonding material. Furthermore, roughened regions RG1-RG4 can be formed by methods such as electron beam irradiation, sputtering, chemical etching, and shot peening, not limited to laser irradiation.

[0056] The effects of non-roughened region NR1 are also achieved in the other non-roughened regions NR2-NR9. For example, in the second portion 24Y of the first inner conductive layer 24, when the second conductive spacer 18 is bonded to the non-roughened region NR2 (fifth region), the molten bonding material wets and spreads well within the non-roughened region NR2, while being prevented from wettably spreading to the roughened region RG2 (sixth region). In the first portion 34X of the second inner conductive layer 34, when the first semiconductor element 12 is bonded to the non-roughened region NR5 (third region), the molten bonding material wets and spreads well within the non-roughened region NR5, while being prevented from wettably spreading to the roughened region RG3 (fourth region). In the second portion 34Y of the second inner conductive layer 34, when the second semiconductor element 14 is bonded to the non-roughened region NR7 (seventh region), the molten bonding material wets and spreads well within the non-roughened region NR7, while being prevented from wettably spreading to the roughened region RG4 (eighth region). In the remaining non-roughened regions NR2 , NR4 , NR6 , NR8 , and NR9 , the roughened regions RG1 - RG4 also suppress the wetting and spreading of the molten bonding material when bonding the corresponding connection components 40 or power terminals 42 , 44 , and 46 .

[0057] Note that the remaining non-roughened regions NR2, NR4, NR6, NR8, and NR9 are located near the outer periphery of the inner conductor layers 24 and 34. Such non-roughened regions NR2, NR4, NR6, NR8, and NR9 may partially reach the outer periphery of the inner conductor layers 24 and 34, where they are not surrounded by the roughened regions NG1-NG4. With such a structure, the outer periphery of the inner conductor layers 24 and 34 can also be used to prevent the molten solder from wetting and spreading. However, in such an embodiment, it is also effective to suppress the wettability of the side surfaces (outer periphery) of the inner conductor layers 24 and 34 by omitting the gold plating of the inner conductor layers 24 and 34.

[0058] While the specific examples of the technology disclosed in this specification have been described in detail above, they are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations to the specific examples exemplified above. The technical elements described in this specification or the drawings demonstrate technical practicality individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically practical.

[0059] Description of Reference Numerals

[0060] 10: Semiconductor devices

[0061] 12: First semiconductor element

[0062] 14: Second semiconductor element

[0063] 16: First conductor spacer

[0064] 18: Second conductor spacer

[0065] 20: First insulating substrate

[0066] 22: First insulation layer

[0067] 24: First inner conductor layer

[0068] 24X: First part of the first inner conductor layer

[0069] 24Y: Second part of the first inner conductor layer

[0070] 26: First outer conductor layer

[0071] 26X: First part of the first outer conductor layer

[0072] 26Y: Second part of the first outer conductor layer

[0073] 30: Second insulating substrate

[0074] 32: Second insulation layer

[0075] 34: Second inner conductor layer

[0076] 34X: First part of the second inner conductor layer

[0077] 34Y: Second portion of the second inner conductor layer

[0078] 36: Second outer conductor layer

[0079] 36X: First part of the second outer conductor layer

[0080] 36Y: Second part of the second outer conductor layer

[0081] 40: Connecting parts

[0082] 42: First power terminal

[0083] 44: Second power terminal

[0084] 46: Third power terminal

[0085] 48: First signal terminal

[0086] 50: Second signal terminal

[0087] 52: Sealed body

[0088] 60A-60I: Bonding layer

Claims

1. A semiconductor device comprising: a first insulating substrate (20); and A first semiconductor element (12) is bonded to the first insulating substrate via a first conductive spacer (16); The first insulating substrate comprises a first insulating layer (22) and a first inner conductor layer (24) provided on one side of the first insulating layer. The surface of the first inner conductor layer includes a first region (NR1) and a second region (RG1), the second region surrounding the first region and having a surface roughness greater than that of the first region. The first conductor spacer is bonded to the first region of the first inner conductor layer via a first bonding layer (60A). When the first inner conductor layer is viewed from above, the margin of the first region relative to the first conductor spacer is partially enlarged. In the portion where the margin is enlarged, the distance from the first conductor spacer to the peripheral edge of the first inner conductor layer is greater than in the other portions.

2. The semiconductor device according to claim 1, wherein The area of ​​the first region of the first inner conductive layer is larger than the area of ​​a surface of the first conductive spacer facing the first region.

3. The semiconductor device according to claim 2, wherein An area where the first bonding layer contacts the first inner conductor layer is larger than an area where the first bonding layer contacts the one surface of the first conductor spacer.

4. The semiconductor device according to claim 1, wherein The first bonding layer reaches at least a portion of a boundary between the first region and the second region on the surface of the first inner conductor layer.

5. The semiconductor device according to claim 4, wherein The first bonding layer extends over the entire first region on the surface of the first inner conductor layer. The semiconductor device according to claim 1 , wherein: The first bonding layer does not extend to the second region on the surface of the first inner conductor layer.

7. The semiconductor device according to claim 1, wherein The first bonding layer is composed of a solder material.

8. The semiconductor device according to claim 1, wherein The first insulating substrate further includes a first outer conductor layer (26) provided on the other side of the first insulating layer.

9. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a sealing body (52) for sealing the first semiconductor element. The sealing body is in contact with the second region of the first inner conductor layer.

10. The semiconductor device according to claim 1, wherein The second region of the first inner conductive layer is a region whose surface is roughened by at least one of laser irradiation, electron beam irradiation, sputtering, chemical etching, and shot blasting.

11. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a second insulating substrate (30) facing the first insulating substrate with the first semiconductor element interposed therebetween. The second insulating substrate comprises a second insulating layer (32) and a second inner conductor layer (34) provided on one side of the second insulating layer. The surface of the second inner conductor layer has a third region (NR5) and a fourth region (RG3), the fourth region surrounding the third region and having a surface roughness greater than that of the third region. The first semiconductor element is bonded to the third region of the second inner conductor layer via a second bonding layer (60C).

12. The semiconductor device according to claim 11, wherein The second insulating substrate further includes a second outer conductor layer (36) provided on the other side of the second insulating layer.

13. The semiconductor device according to any one of claims 1 to 12, wherein The semiconductor device further comprises a second semiconductor element (14) bonded to the first insulating substrate via a second conductive spacer (18). The first inner conductor layer of the first insulating substrate has a fifth region (NR2) and a sixth region (RG2), the sixth region surrounding the fifth region and having a surface roughness greater than that of the fifth region. The second conductor spacer is bonded to the fifth region of the first inner conductor layer via a third bonding layer (60D).

14. The semiconductor device according to claim 13, wherein The first inner conductor layer of the first insulating substrate has a first portion (24X) and a second portion (24Y) separated from each other on the first insulating layer. The first region and the second region are located in the first portion of the first inner conductor layer. The fifth region and the sixth region are located in the second portion of the first inner conductor layer.

15. The semiconductor device according to claim 13, wherein The semiconductor device further comprises a second insulating substrate (30) facing the first insulating substrate with the second semiconductor element interposed therebetween. The second insulating substrate comprises a second insulating layer (32) and a second inner conductor layer (34) provided on one side of the second insulating layer. The surface of the second inner conductor layer has a seventh region (NR7) and an eighth region (RG4), the eighth region surrounding the seventh region and having a surface roughness greater than that of the seventh region. The second semiconductor element is bonded to the seventh region of the second inner conductive layer via a fourth bonding layer (60F).

16. The semiconductor device according to claim 14, wherein The semiconductor device further comprises a second insulating substrate (30) facing the first insulating substrate with the second semiconductor element interposed therebetween. The second insulating substrate comprises a second insulating layer (32) and a second inner conductor layer (34) provided on one side of the second insulating layer. The surface of the second inner conductor layer has a seventh region (NR7) and an eighth region (RG4), the eighth region surrounding the seventh region and having a surface roughness greater than that of the seventh region. The second semiconductor element is bonded to the seventh region of the second inner conductive layer via a fourth bonding layer (60F).

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