semiconductor devices

Abstract

A semiconductor device according to a technical solution of the present invention comprises: a plurality of wiring layers (M1 to M3); a first wiring (11); and a second wiring (12), which is not connected to the first wiring (11) and is redundantly provided for transmitting the same signal level as the first wiring (11); the first wiring (11) and the second wiring (12) belong to different wiring layers; and the distance between the first wiring (11) and the second wiring (12) is greater than the interlayer distance c between adjacent wiring layers.

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a latch circuit. Background Art

[0002] In semiconductor devices, soft errors in latch circuits (also called flip-flop circuits) within logic circuits are a problem. Soft errors are temporary errors caused by noise entering the latch circuit due to particle beams such as cosmic rays, which cause the latch state to flip.

[0003] As a circuit with high soft error tolerance, for example, the Figure 2 The latch circuit shown here has four inverter circuits, creating a redundant circuit structure. The gates of the PMOS and NMOS transistors in each inverter circuit receive the same data but are connected to different nodes. Even if noise, which could cause a soft error, enters one of these four nodes, it can be recovered through the other nodes.

[0004] Patent Document 2 discloses a semiconductor device with a high-sensitivity and short-time inspection method for detecting electrical faults in a large-scale integrated circuit (LSI). The semiconductor device includes a basic wiring pattern comprising a first U-shaped wiring having a pair of parallel comb-shaped conductors; and a second U-shaped wiring arranged in a nested manner relative to the first wiring and having a pair of parallel comb-shaped conductors.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 5369771

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2007-103598 Summary of the Invention

[0009] Problems to be solved by the invention

[0010] However, according to the above-mentioned conventional technology, when a short circuit occurs in a redundant wiring pair having the same signal level, there is a problem that the short circuit cannot be detected during the inspection stage although the soft error tolerance is degraded.

[0011] The present invention provides a semiconductor device that reduces degradation of soft error tolerance caused by a short circuit of a redundant wiring pair.

[0012] Means used to solve problems

[0013] A semiconductor device according to a technical solution of the present invention comprises: a plurality of wiring layers; a first wiring; and a second wiring, which is not connected to the first wiring and is provided for transmitting the same signal level as the first wiring; the first wiring and the second wiring belong to different wiring layers; and the distance between the first wiring and the second wiring is greater than the interlayer distance between adjacent wiring layers.

[0014] Effects of the Invention

[0015] According to the semiconductor device of the present invention, it is possible to reduce the degradation of soft error tolerance caused by a short circuit of a redundant wiring pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing an example of a circuit formed in the semiconductor device according to the first embodiment.

[0017] Figure 2 This is a diagram showing a first example of a wiring layout between wiring layers.

[0018] Figure 3A This is a diagram showing a second example of the wiring layout between wiring layers.

[0019] Figure 3B It is a diagram showing a modification of the second example of the wiring layout between wiring layers.

[0020] Figure 4 This is a diagram showing a first example of a wiring layout within a wiring layer.

[0021] Figure 5 This is a diagram showing a second example of the wiring layout within the wiring layer.

[0022] Figure 6 This is a diagram showing a third example of the wiring layout within the wiring layer.

[0023] Figure 7 This is a diagram showing a fourth example of the wiring layout within the wiring layer.

[0024] Figure 8 This is a diagram showing a fifth example of the wiring layout within the wiring layer.

[0025] Figure 9 This is a diagram showing a sixth example of the wiring layout within the wiring layer.

[0026] Figure 10 This is a diagram showing a seventh example of the wiring layout within the wiring layer.

[0027] Figure 11 This is a diagram showing an eighth example of the wiring layout within the wiring layer.

[0028] Figure 12This is a diagram showing another example of a circuit formed in the semiconductor device of the first embodiment.

[0029] Figure 13 Yes Figure 12 A circuit diagram showing an example of a C element in FIG.

[0030] Figure 14 It is an explanatory diagram showing an example of a short circuit in a latch circuit of a comparative example. DETAILED DESCRIPTION

[0031] (Understanding that forms the basis of the present invention)

[0032] The inventors of the present invention have discovered that the following problems may occur in the circuit with high soft error tolerance described in the "Background Art" column. Figure 14 The following will be described in detail.

[0033] Figure 14 It is an explanatory diagram showing a short-circuit example of a latch circuit according to a comparative example. Figure 14 The latch circuit shown in (a) includes four PMOS transistors and four NMOS transistors. A pair of PMOS transistors and NMOS transistors connected in series constitutes an inverter circuit.

[0034] A conventional latch circuit has two inverter circuits. Figure 14 (a) has four inverter circuits. Figure 14 The latch circuit of (a) has improved soft error tolerance by having a double redundant structure.

[0035] exist Figure 14 In (a), the four inverter circuits are connected by four wirings w1 to w4. Wiring w1 and wiring w3 form a redundant wiring pair, independent wirings that have the same signal level. Similarly, wiring w2 and wiring w4 form a redundant wiring pair, independent wirings that have the same signal level.

[0036] In this figure, the wirings w1 and w3 of the redundant wiring pair are depicted with thin lines, showing an example of a low level, while the wirings w2 and w4 of another redundant wiring pair are depicted with thick lines, showing an example of a high level.

[0037] The gates of the PMOS and NMOS transistors in each inverter circuit receive the same signal level, but are connected to different wiring. Specifically, the gate of the PMOS transistor is connected to one side of the redundant wiring pair, while the gate of the NMOS transistor is connected to the other side of the redundant wiring pair. This loop is formed by four inverter circuits, so even if the output of one inverter circuit flips, the other three inverter circuits maintain the correct value. This improves the soft error tolerance of the latch circuit shown in this figure.

[0038] Figure 14 (b) As shown in the dotted box sh1, it shows that the wiring w1 and the wiring w3 are short-circuited. Figure 14 (c) shows a short circuit between the wiring w2 and the wiring w4, as shown by the dotted-line frame sh2. Such a short circuit may occur during the manufacturing process of a semiconductor device including a latch circuit due to the intrusion of conductive foreign matter such as metal particles.

[0039] Whether in Figure 14 (b) or in Figure 14 In (c), both redundant wiring pairs are short-circuited. That is, the wiring pairs short-circuited in the dotted-line boxes sh1 and sh2 are independent wirings that are not connected to each other, but they always have the same signal level during the operation of the latch circuit. Figure 14 (b) or in Figure 14 In (c), the latch circuits all operate normally without showing any abnormality. However, since the redundancy of the wiring pair is lost due to the short circuit, there is a problem of deterioration in soft error tolerance.

[0040] Furthermore, the short circuits of the dotted-line boxes sh1 and sh2 cannot be detected during the inspection phase of the semiconductor device manufacturing process. In other words, there is a problem that the degradation of the soft error tolerance caused by the short circuits of the dotted-line boxes sh1 and sh2 cannot be detected.

[0041] Therefore, the present invention provides a semiconductor device that reduces degradation of soft error tolerance caused by a short circuit of a redundant wiring pair.

[0042] In order to solve such problems, a semiconductor device of a technical solution of the present invention comprises: multiple wiring layers; a first wiring; and a second wiring, which is not connected to the above-mentioned first wiring and is redundantly provided to transmit the same signal level as the above-mentioned first wiring; the above-mentioned first wiring and the above-mentioned second wiring belong to different wiring layers; the distance between the above-mentioned first wiring and the above-mentioned second wiring is larger than the inter-layer distance between adjacent wiring layers.

[0043] This reduces the degradation of soft error tolerance caused by short circuits in redundant wiring pairs. This is because, when a foreign object of similar size to the distance between wirings is introduced, a short circuit between the first or second wiring and another wiring is more likely to occur than a short circuit between the first wiring and the second wiring. This prevents the occurrence of undetectable short circuits—in other words, the occurrence of short circuits in redundant wiring pairs.

[0044] If the first wiring or the second wiring is short-circuited with other wiring due to foreign matter, the probability of causing abnormal operation is high, so the short circuit can be detected during the inspection stage before factory shipment.

[0045] In this way, it is possible to reduce the degradation of soft error tolerance caused by a short circuit of the redundant wiring pair.

[0046] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0047] In addition, the embodiments described below all represent general or specific examples. The numerical values, shapes, materials, constituent elements, configuration positions of constituent elements and connection forms, steps, the order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present invention. In addition, among the constituent elements of the following embodiments, the constituent elements that are not described in the independent claims representing the implementation form of a technical solution of the present invention are described as arbitrary constituent elements. The implementation form of the present invention is not limited to the current independent claims, and can also be expressed through other independent claims.

[0048] (Implementation 1)

[0049] [1 Circuit Example of Semiconductor Device]

[0050] Figure 1 This is a diagram showing an example of a circuit formed in the semiconductor device according to the first embodiment.

[0051] The circuit example in this figure includes a latch circuit L1 having first to fourth inverting circuits i1 to i4. Each of the first to fourth inverting circuits i1 to i4 includes four first-type MOS transistors pt1 to pt4 and four second-type MOS transistors nt1 to nt4. This latch circuit L1 represents a so-called DICE (Dual Interlocked Storage Cell) latch circuit as an example of a circuit having a redundant wiring pair.

[0052] The first inverting circuit i1 includes a first-type MOS transistor pt1 , a second-type MOS transistor nt1 , and an output node o1 connected to the drain of the first-type MOS transistor pt1 and the drain of the second-type MOS transistor nt1 .

[0053] The second inverting circuit i2 includes a first-type MOS transistor pt2, a second-type MOS transistor nt2, and an output node o2 connected to the drain of the first-type MOS transistor pt2 and the drain of the second-type MOS transistor nt2.

[0054] The third inversion circuit i3 includes a first-type MOS transistor pt3, a second-type MOS transistor nt3, and an output node o3 connected to the drain of the first-type MOS transistor pt3 and the drain of the second-type MOS transistor nt3.

[0055] The fourth inversion circuit i4 includes a first-type MOS transistor pt4, a second-type MOS transistor nt4, and an output node o4 connected to the drain of the first-type MOS transistor pt4 and the drain of the second-type MOS transistor nt4.

[0056] The sources of the first type MOS transistors of the first to fourth inversion circuits i1 to i4 are connected to a power supply line of potential VDD, and the sources of the second type MOS transistors are connected to a GND (ground) line of potential VSS.

[0057] In addition, type 1 refers to one conductivity type between P type and N type. Type 2 refers to the other conductivity type between P type and N type. Figure 1 In the example, the first type is P-type and the second type is N-type. Hereinafter, the first type is sometimes referred to as P and the second type is sometimes referred to as N. Furthermore, the first type MOS transistor is sometimes referred to as a PMOS transistor and the second type MOS transistor is sometimes referred to as an NMOS transistor.

[0058] The first through fourth flip circuits are connected by four wirings: w11, w12, w21, and w22. Wirings w11 and w12 form a redundant wiring pair, independent wirings that have the same signal level but are not interconnected. Similarly, wirings w21 and w22 form a redundant wiring pair, independent wirings that have the same signal level but are not interconnected. Furthermore, the wirings that make up a redundant wiring pair are a series of conductive bodies that include not only the metal wiring portions within a wiring layer, but also the through-hole contacts between wiring layers, the gate, source, and drain electrodes of transistors, and the terminal electrodes of circuit components. Hereinafter, through-hole contacts may sometimes be simply referred to as through-holes.

[0059] The wiring w11 connects the output node o1 of the first inverting circuit i1 to the gate g2 of the first type MOS transistor pt2 of the second inverting circuit i2 and to the gate of the second type MOS transistor nt4 of the fourth inverting circuit i4.

[0060] The wiring w21 connects the output node o2 of the second inverting circuit i2 to the gate g3 of the first type MOS transistor pt3 of the third inverting circuit i3 and to the gate of the second type MOS transistor nt1 of the first inverting circuit i1.

[0061] The wiring w12 connects the output node o3 of the third inverting circuit i3 to the gate g4 of the first type MOS transistor pt4 of the fourth inverting circuit i4 and to the gate of the second type MOS transistor nt2 of the second inverting circuit i2.

[0062] The wiring w22 connects the output node o4 of the fourth inverting circuit i4 to the gate g1 of the first-type MOS transistor pt1 of the first inverting circuit i1 and to the gate of the second-type MOS transistor nt3 of the third inverting circuit i3.

[0063] With this connection, four inverter circuits form a loop. Therefore, even if the output of one inverter circuit flips due to a soft error, the other three inverter circuits can maintain the correct value. Thus, the latch circuit L1 shown in this figure has improved soft error tolerance.

[0064] Figure 1 The latch circuit L1 shown constitutes a portion of a semiconductor circuit formed on a semiconductor substrate within a semiconductor device. The semiconductor circuit formed on the semiconductor substrate includes multiple p-type impurity regions, multiple n-type impurity regions, multiple wiring layers, and multiple contacts connecting the wiring layers.

[0065] As Figure 1 The redundant wiring pairs constituting the latch circuit L1 are formed in one or more wiring layers. In this embodiment, the redundant wiring pairs are arranged so as to prevent short circuits from occurring in the redundant wiring pairs due to the intrusion of foreign matter during the semiconductor device manufacturing process.

[0066] Next, the arrangement layout of redundant wiring pairs between different wiring layers will be described.

[0067] [2.1 Example 1 of Wiring Layout Between Wiring Layers]

[0068] Figure 2 This is a diagram showing a first example of a wiring layout between wiring layers. Figure 2 (a) shows a wiring layout obtained by planarly viewing a semiconductor substrate on which the latch circuit L1 is formed. Figure 2 (b) indicates Figure 2 The cross section of line AA in (a) includes three wiring layers M1 to M3. This figure is a schematically enlarged view of the portion of the wiring formed in the wiring layers M1 to M3 that is associated with the redundant wiring pair. Figure 2 1 and 12 of a redundant wiring pair are shown in FIG.

[0069] like Figure 2 As shown, the wiring 11 and the wiring 12 of the redundant wiring pair belong to different wiring layers. That is, the wiring 11 belongs to the wiring layer M3, and the wiring 12 belongs to the wiring layers M2 and M1, including via contacts.

[0070] Redundant wiring pairs in different wiring layers are arranged to satisfy the following relationship. Specifically, when wiring 11 and wiring 12 are in different wiring layers, the distance a between wiring 11 and wiring 12 is greater than the interlayer distance c between adjacent wiring layers. In this figure, three distances a1, a2, and a3 are shown as the distances between wiring 11 and wiring 12, but the distance a between wiring 11 and wiring 12 is the smallest, a1 or a3. Wiring 11 and wiring 12 are arranged to satisfy a > c.

[0071] In more detail, Figure 2 In the plan view of the semiconductor device, the wiring 11 and the wiring 12 have overlapping portions and cross each other. The wiring 12 has a first partial wiring 12b corresponding to the overlapping portion, a second partial wiring 12a connected to one end of the first partial wiring 12b, and a third partial wiring 12c connected to the other end of the first partial wiring 12b. The first partial wiring 12b belongs to the wiring layer M1. The second partial wiring 12a and the third partial wiring 12c belong to a wiring layer M2 different from the wiring layer M1, and are connected to the first partial wiring 12b via through-hole contacts v1 and v2. The wiring 11 belongs to the wiring layer M3 which is farther away from the wiring layer M1 than the wiring layer M2. With this configuration layout, the above-mentioned relationship (i.e., a>c) can be easily satisfied. Figure 2 In the arrangement, the distance a2 between the wiring 11 and the wiring 12 in the overlapping portion satisfies at least twice the interlayer distance c.

[0072] according to Figure 2 This layout can mitigate the degradation of soft error tolerance caused by short circuits in the redundant wiring pair. This is because, if foreign matter of a size comparable to the interlayer distance c enters, a short circuit between wiring 11 and wiring 12 is less likely to occur. This prevents the occurrence of short circuits in the redundant wiring pair.

[0073] in addition, Figure 2 The wiring layers M1 to M3 may be any three of the plurality of wiring layers as long as they are arranged in this order. However, the interlayer distance c is not limited to Figure 2 The distance between the wiring layer M2 and the wiring layer M3 is the minimum distance between two adjacent wiring layers.

[0074] [2.2 Example 2 of Wiring Layout Between Wiring Layers]

[0075] Figure 3A This is a diagram showing a second example of the wiring layout between wiring layers. Figure 3A (a) shows a wiring layout obtained by planarly viewing a semiconductor substrate on which the latch circuit L1 is formed. Figure 3A (b) indicates Figure 3AThe cross section of line BB in (a) includes two wiring layers M2 and M3. This figure is a schematically enlarged view of the portion of the wiring formed in the wiring layers M2 and M3 that is associated with the redundant wiring pair. Figure 3A , wiring 11 and wiring 12 of a redundant wiring pair are shown.

[0076] exist Figure 3A In the plan view of (a), the wiring 12 is arranged so as to go around the end of the wiring 11 so that the wiring 11 and the wiring 12 do not overlap.

[0077] With this arrangement layout, the above-mentioned relationship (ie, a>c) can be easily satisfied.

[0078] according to Figure 3A This layout can mitigate the degradation of soft error tolerance caused by short circuits in the redundant wiring pair. This is because, if foreign matter of a size comparable to the interlayer distance c enters, a short circuit between wiring 11 and wiring 12 is less likely to occur. This prevents the occurrence of short circuits in the redundant wiring pair.

[0079] [2.3 Modification of the Second Example of Wiring Layout Between Wiring Layers]

[0080] Figure 3B This figure shows a modified example of the second example of the wiring layout between wiring layers. Figure 3A The difference is that it includes wiring 31. The following description focuses on the difference. Wiring 31 is arranged near wiring 11 or wiring 12 and includes a through-hole contact portion v1 and an extension portion e1. The through-hole contact portion v1 connects the wiring 31 portion of another wiring layer M4 to the wiring 31 of the wiring layer M3. The extension portion e1 extends from the through-hole contact portion v1. In addition, the following extension rule can also be set. That is, the length e1 from the through-hole v1 to the end of the extension portion e1 is greater than the minimum dimension of the wiring in the design rule of the semiconductor device. In addition, this extension rule can also be applied to the extension portions of other figures.

[0081] exist Figure 3B In FIG. 1 , the extended portion e1 of wiring 31 is arranged adjacent to one wiring of the redundant wiring pair within the same wiring layer and adjacent to the other wiring of the redundant wiring pair within a different wiring layer. Furthermore, the distance a is greater than the distance between wiring 11 and wiring 31, and greater than the distance between wiring 12 and wiring 31.

[0082] According to the wiring design CAD, if you want to achieve without wiring 31 Figure 3A If the wiring 31 is appropriately arranged near the wiring 11 or the wiring 12, the arrangement of the redundant wiring pair can be easily designed. As a result, it is easy to realize Figure 3B Such a redundant wiring pair layout.

[0083] exist Figure 2 、 Figure 3A 、 Figure 3B , an example of the arrangement layout of redundant wiring pairs between wiring layers is shown. The following describes the wiring layout of redundant wiring pairs within one wiring layer.

[0084] [3.1 Example 1 of Wiring Layout in a Wiring Layer]

[0085] Figure 4 This is a diagram showing a first example of a wiring layout in a wiring layer of a semiconductor device. Figure 1 FIG. 1 is a diagram showing a plan view of a semiconductor substrate of a latch circuit L1. Figure 4 This is a diagram schematically showing an enlarged portion of a plurality of wirings formed in one wiring layer. Figure 4 The layout of four wirings 11, 12, 21, and 22 is shown in FIG.

[0086] The wiring 11 and the wiring 12 represent a redundant wiring pair. Specifically, the wiring 12 is not connected to the wiring 11 and is redundantly provided to transmit the same signal level as the wiring 11. The wiring 11 and the wiring 12 are, for example, Figure 1 The wirings w11 and w12 correspond to each other.

[0087] The wiring 21 is another wiring different from the wiring 11 and the wiring 12. The wiring 22 is also another wiring different from the wiring 11 and the wiring 12.

[0088] In the figure, a represents the distance between wiring 11 and wiring 12. b1 represents the distance between wiring 11 and wiring 21. b2 represents the distance between wiring 12 and wiring 21. b3 represents the distance between wiring 11 and wiring 22. b4 represents the distance between wiring 12 and wiring 22. These distances are the minimum distances between wirings.

[0089] The layout of these wirings satisfies the following relationship.

[0090] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 .

[0091] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 .

[0092] The distance a between the wiring 11 and the wiring 12 is greater than the distance b3 between the wiring 11 and the wiring 22 .

[0093] The distance a between the wiring 11 and the wiring 12 is greater than the distance b4 between the wiring 12 and the wiring 22 .

[0094] This is because, by satisfying this relationship, if foreign matter is introduced, a short circuit between wiring 11 or wiring 12 and the other wiring (21, 22) is more likely to occur than a short circuit between wiring 11 and wiring 12, which form a redundant wiring pair. As a result, the occurrence of undetectable short circuits, in other words, the occurrence of short circuits in the redundant wiring pair, is suppressed.

[0095] Since a short circuit between the wiring 11 or the wiring 12 and the other wirings (21, 22) is more likely to occur, the short circuit can be detected. Therefore, the degradation of the soft error tolerance caused by the short circuit of the redundant wiring pair can be reduced.

[0096] exist Figure 4 In order to satisfy the above relationship, the wiring 22 includes an extension portion e1 extending from the through hole v2 connected to the main portion of the wiring 22. The end of the extension portion e1 may be an open end that is not connected within the wiring layer.

[0097] in addition, Figure 4 The wiring 21 and the wiring 22 may be, for example, Figure 1 Alternatively, the wiring 21 and the wiring 22 may be either a power line or a ground line.

[0098] [3.2 Example 2 of Wiring Layout within a Wiring Layer]

[0099] Figure 5 : is a diagram showing a second example of a wiring layout in a wiring layer. This diagram schematically enlarges a portion of a plurality of wirings formed in one wiring layer. Figure 5 The layout of wirings 11, 12, and 21 is shown in FIG. In the figure, v1 represents a through-hole contact portion connecting wiring 21 to wirings in other wiring layers. e1 represents an extension portion of wiring 21.

[0100] Wiring 11 and wiring 12 represent a redundant wiring pair. Wiring 21 is another wiring different from wiring 11 and wiring 12. Wiring 11 and wiring 12 of the redundant wiring pair have a parallel section arranged in parallel within the wiring layer, and sandwich the other wiring 21 throughout the parallel section.

[0101] Figure 5 The wiring layout example and Figure 4 Likewise, the following relationship is satisfied.

[0102] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 .

[0103] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 .

[0104] exist Figure 5In the example, wiring 11 and wiring 12 of the redundant wiring pair are arranged so as to sandwich wiring 21 throughout the parallel section where wiring 11 and wiring 12 are arranged in parallel. To this end, wiring 21 has an extended portion e1. Specifically, wiring 21 includes an extended portion e1 extending from a via v1 connected to the main portion of wiring 21. This extended portion e1 is arranged between wiring 11 and wiring 12 within the parallel section. Furthermore, the ends of the extended portion e1 may be open ends that are not connected within the wiring layer.

[0105] according to Figure 5 In the wiring layout example shown in FIG2 , if foreign matter is introduced, wire 11 or wire 12 is likely to short with another wire 21 before wires 11 and 12, which form a redundant wiring pair, short. In other words, the probability that a redundant wiring pair short will be replaced by another detectable short is high. This can mitigate the degradation of soft error tolerance caused by redundant wiring pair shorts.

[0106] in addition, Figure 5 The wiring 21 can be, for example, Figure 1 The wiring corresponding to one of the wirings w21 and w22 may be a power line or a ground line.

[0107] [3.3 Example 3 of Wiring Layout in a Wiring Layer]

[0108] Figure 6 : is a diagram showing a third example of a wiring layout in a wiring layer. This diagram schematically enlarges a portion of a plurality of wirings formed in one wiring layer. Figure 6 1 shows the layout of the wirings 11, 12, and 21. v1 in the figure represents a via contact portion that connects the wiring 21 to wirings in other wiring layers.

[0109] Wiring 11 and wiring 12 represent a redundant wiring pair. Wiring 21 is another wiring different from wiring 11 and wiring 12. Wiring 11 and wiring 12 of the redundant wiring pair have a parallel section arranged in parallel within the wiring layer, and sandwich the other wiring 21 throughout the parallel section.

[0110] Figure 6 The wiring layout example is also similar to Figure 4 Likewise, the following relationship is satisfied.

[0111] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 .

[0112] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 .

[0113] exist Figure 6In the redundant wiring pair, the wiring 11 and the wiring 12 are arranged so as to sandwich the other wiring 21 throughout the parallel section in which the wiring 11 and the wiring 12 are arranged in parallel. For this purpose, the wiring 21 has extension portions e1 to e3. That is, the wiring 21 includes extension portions e1 to e3 extending from the through-hole v1 connected to the main portion of the wiring 21. The extension portions e1 to e3 are one continuous wiring and are arranged in a manner that bypasses the end portion of the wiring 11 in the wiring layer. A portion of the extension portion e3 is arranged in a manner that is sandwiched by the wiring 11 and the wiring 12 throughout the parallel section. In addition, the end portion of the extension portion e3 may be an open end that is not connected in the wiring layer. In addition, Figure 6 The distances b1 and b2 may be the minimum spacing between wirings according to the design rules of the semiconductor device. In addition, the distance a between the wiring 11 and the wiring 12 is larger than the minimum spacing between wirings according to the design rules.

[0114] according to Figure 6 In the wiring layout example shown above, if foreign matter is introduced, wire 11 or wire 12 is more likely to short with another wire 21 before wires 11 and 12, which form the redundant wiring pair, short. In other words, the probability that a short in the redundant wiring pair will be replaced by another detectable short is high. This can mitigate the degradation of soft error tolerance caused by a short in the redundant wiring pair.

[0115] in addition, Figure 6 The wiring 21 can be, for example, Figure 1 The wiring corresponding to one of the wirings w21 and w22 may be a power line or a ground line.

[0116] [3.4 Example 4 of Wiring Layout within a Wiring Layer]

[0117] Figure 7 : is a diagram showing a fourth example of a wiring layout in a wiring layer. This diagram schematically enlarges a portion of a plurality of wirings formed in one wiring layer. Figure 7 1 shows the layout of the wirings 11, 12, 21, and 22. v1 in the figure indicates a via contact portion that connects the wiring 21 to wirings in other wiring layers.

[0118] Wiring 11 and wiring 12 represent a redundant wiring pair. Also, wiring 21 and wiring 22 represent a redundant wiring pair. The wiring of wiring 11 and wiring 12 is symmetrically referred to as the first redundant pair, and the wiring of wiring 21 and wiring 22 is symmetrically referred to as the second redundant pair. Figure 7 In the example, the four wires 11, 12, 21, and 22 are arranged in the order of wire 11 of one of the first redundant pair, wire 21 of one of the second redundant pair, wire 12 of the other of the first redundant pair, and wire 22 of the other of the second redundant pair. In other words, the wires of the two redundant pairs are arranged alternately, and wires of the same signal level are not adjacent to each other.

[0119] Figure 7 The wiring layout example is also similar to Figure 4 Likewise, the following relationship is satisfied.

[0120] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 .

[0121] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 .

[0122] Figure 7 The wirings 11, 12, 21, and 22 can be the main body of the wiring or the extended part.

[0123] according to Figure 7 In the example wiring layout, if foreign matter is introduced, wire 11 or 12 is likely to short with another wire 21 or 22 before wires 11 and 12, which form a redundant wire pair, short. In other words, the probability that a redundant wire pair short will be replaced by another detectable short is high. This can mitigate the degradation of soft error tolerance caused by a redundant wire pair short.

[0124] Alternatively, it could be, Figure 7 The wiring 11 and the wiring 12 are connected with Figure 1 The wiring w11 and w12 correspond to the wiring, and the wiring 21 and wiring 22 are the same as Figure 1 The wiring w21 and w22 correspond to the wiring.

[0125] [3.5 Example 5 of Wiring Layout within a Wiring Layer]

[0126] Figure 8 : is a diagram showing the fifth example of the wiring layout in the wiring layer. This figure is a diagram schematically enlarging a portion of the plurality of wirings formed in one wiring layer. Figure 8 The layout of wirings 11, 12, and 21 is shown in FIG. In the figure, v1 and v2 denote via contacts connecting wiring 21 to wirings in other wiring layers. e1 denotes an extension of wiring 21.

[0127] Wiring 11 and wiring 12 represent a redundant wiring pair. Wiring 21 is another wiring different from wiring 11 and wiring 12. Wiring 11 and wiring 12 of the redundant wiring pair have a parallel section arranged in parallel within the wiring layer, and other wiring 21 is sandwiched across the parallel section.

[0128] Figure 8 The wiring layout example and Figure 4 Likewise, the following relationship is satisfied.

[0129] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 .

[0130] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 .

[0131] exist Figure 8 In the example, wiring 11 and wiring 12 of the redundant wiring pair are arranged so as to sandwich wiring 21 throughout the parallel section where wiring 11 and wiring 12 are arranged in parallel. To this end, wiring 21 has an extension portion e1. Specifically, wiring 21 includes an extension portion e1 extending from the main portion of wiring 21. This extension portion e1 is arranged between wiring 11 and wiring 12 within the parallel section. Furthermore, the ends of extension portion e1 may be open ends that are not connected within the wiring layer.

[0132] according to Figure 8 In the wiring layout example, if foreign matter is introduced, a short circuit between wiring 11 or wiring 12 and another wiring 21 is more likely to occur than a short circuit between wiring 11 and wiring 12, which form the redundant wiring pair. In other words, the probability of a redundant wiring pair short being replaced by another detectable short circuit is higher. This can mitigate the degradation of soft error tolerance caused by a redundant wiring pair short circuit.

[0133] in addition, Figure 8 The wiring 21 can be, for example, Figure 1 The wiring corresponding to one of the wirings w21 and w22 may be a power line or a ground line.

[0134] [3.6 Example 6 of Wiring Layout within a Wiring Layer]

[0135] Figure 9 This figure shows the sixth example of the wiring layout in the wiring layer. Figure 8 The difference lies in that the main portion of the wiring 21 belongs to another wiring layer and that the extended portion e1 extends from the main portion of the wiring 21 through the via v3. The following description focuses on these differences.

[0136] As indicated by the dotted line in the figure, the main portion of the wiring 21 belongs to a wiring layer different from the wiring layer to which the wirings 11 and 12 belong.

[0137] The extension portion e1 extends from the main portion of the wiring 21 belonging to another wiring layer through the via v3. Thus, the wiring 11 and the wiring 12 of the redundant wiring pair have a parallel section arranged in parallel within the wiring layer, and the extension portion e1 of the other wiring 21 is sandwiched throughout the parallel section.

[0138] according to Figure 9 The wiring layout example is Figure 8Likewise, it is possible to reduce the degradation of soft error tolerance caused by a short circuit of the redundant wiring pair.

[0139] [3.7 Example 7 of Wiring Layout within a Wiring Layer]

[0140] Figure 10 This figure shows the seventh example of the wiring layout in the wiring layer. Figure 5 The difference is the addition of power supply wiring. The following description focuses on this difference.

[0141] The wiring 21 is a power wiring having extensions e1 and e2 extending from the main portion of the power wiring. The power wiring may be arranged in a wiring layer to surround all or part of the latch circuit L1, or may be a shield wiring formed in another wiring layer.

[0142] according to Figure 10 The wiring layout example is Figure 5 Likewise, it is possible to reduce the degradation of soft error tolerance caused by a short circuit of the redundant wiring pair.

[0143] [3.8 Example 8 of Wiring Layout within a Wiring Layer]

[0144] Figure 11 : is a diagram showing the eighth example of the wiring layout in the wiring layer. This diagram is a schematically enlarged diagram of a portion of the plurality of wirings formed in one wiring layer. Figure 11 The layout of wirings 11, 12, 21, and 22 is shown in FIG. In the figure, v1 represents a via contact connecting wiring 21 to wirings in other wiring layers. v2 represents a via contact connecting wiring 22 to wirings in other wiring layers. e1 represents an extension of wiring 21. e2 represents an extension of wiring 22.

[0145] Wiring 11 and wiring 12 represent a redundant wiring pair. Wiring 21 is a different wiring than wiring 11 and wiring 12. Wiring 22 is yet another wiring different than wiring 11 and wiring 12. Wiring 21 and wiring 22 are not a redundant wiring pair. Wiring 11 and wiring 12 of the redundant wiring pair have a parallel section arranged in parallel within the wiring layer, with wiring 21 and wiring 22 sandwiched across most of the parallel section. Wiring 21 and wiring 22 are arranged on the same straight line, separated by a gap d1.

[0146] Figure 11 The wiring layout example and Figure 4 Likewise, the following relationship is satisfied.

[0147] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 or the wiring 22 .

[0148] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 or the wiring 22 .

[0149] Furthermore, in Figure 11 , the distance a between wiring 11 and wiring 12 is greater than the distance d1 between wiring 21 and wiring 22. In other words, the distance d1 between wiring 11 and wiring 12 in the adjacent and parallel section (i.e., the section not sandwiching other wirings) is smaller than the distance a between wiring 11 and wiring 12.

[0150] exist Figure 11 In the example, wires 11 and 12 of the redundant wiring pair are arranged so as to sandwich wire 21 or 22 across the majority of the parallel section where wires 11 and 12 are arranged in parallel. To this end, wire 21 has an extended portion e1, and wire 22 has an extended portion e2. In other words, the ends of extended portions e1 and e2 can be open ends that are not connected within the wiring layer.

[0151] according to Figure 11 The wiring layout example is Figure 5 Likewise, it is possible to reduce the degradation of soft error tolerance caused by a short circuit of the redundant wiring pair.

[0152] in addition, Figure 11 The wiring 21 can be, for example, a power line or a ground line. The wiring 22 can also be, for example, a power line or a ground line.

[0153] [4 Other Circuit Examples of Semiconductor Devices]

[0154] Next, another circuit example having a redundant wiring pair will be described.

[0155] Figure 12 This diagram shows another example of a circuit formed in the semiconductor device of Embodiment 1. The semiconductor device in this diagram shows an example of the configuration of a BISER (Built in Soft Error Resilience) type flip-flop circuit as a circuit having soft error resilience.

[0156] The trigger circuit in this figure includes a delay circuit DL, an inverter IV, main latches ML0, ML1, a main C element CM, sub latches SL0, SL1, a sub C element CS, a main weak holding circuit WM and a sub weak holding circuit WS, and has a dual main-sub structure. Figure 12 The redundant wiring pair in is a wiring connected to the output Qn of the sub latch SL0 and a wiring connected to the output Qn of the sub latch SL1.

[0157] The delay circuit DL delays the input data D input to the master latch ML0 by a time τ and outputs the delayed data to the master latch ML1 .

[0158] The inverter IV outputs a clock signal Cn obtained by inverting the clock signal Cp.

[0159] Master latch ML0 is synchronized with clock signals Cp and Cn, latches input data D, and outputs data Qp. Output data Qp is non-inverted output data of the same logic level as data D.

[0160] The master latch ML1 is synchronized with the clock signals Cp and Cn, latches the delayed input data D, and outputs data Qp. The output data Qp is non-inverted output data of the same logic level as the data D.

[0161] The main C element CM is a 2-input 1-output inversion circuit. When the two inputs are at the same predetermined logic level, the circuit outputs an inverted version of the logic level. When the two inputs are not at the same predetermined logic level, the circuit becomes high impedance.

[0162] The main weak hold circuit WM is a weak keeper circuit that holds the logic level output by the main C-element CM. When the output of the main C-element CM is high impedance, the main weak hold circuit WM outputs the logic level held immediately before the high impedance.

[0163] The sub latch SL0 latches input data D and outputs data Qn in synchronization with the clock signals Cp and Cn. The output data Qn is data with a logic level that is the inverted value of the data D.

[0164] The sub latch SL1 latches input data D and outputs data Qn in synchronization with the clock signals Cp and Cn. The output data Qn is the inverted data D.

[0165] The sub-C element CS is a 2-input 1-output inversion circuit. When the two inputs are at the same predetermined logic level, the inverted logic level is output. When the two inputs are not at the same predetermined logic level, the circuit becomes high impedance. Figure 13 The circuit example of the sub-C element CS is shown in FIG. The sub-C element CS in this figure is composed of two PMOS transistors and two NMOS transistors. The two PMOS transistors and the two NMOS transistors are connected in series. In addition, the main C element CM can also be connected to Figure 13 same.

[0166] The sub weak hold circuit WS is a weak keeper circuit that holds the same logic level as the logic level output by the sub C element CS. When the output of the sub C element CS is high impedance, it outputs the logic level held immediately before the high impedance.

[0167] In such a trigger circuit, if one of the two sets of main and sub latches flips due to a soft error, the output of the main C element CM or the sub C element CS becomes high impedance, but the correct data can be maintained through the logic level maintained by the main weak holding circuit WM or the sub weak holding circuit WS.

[0168] Figure 12 The redundant wiring pair in the flip-flop circuit includes a wiring connecting the output terminal of sub-latch SL0 to one of the two input terminals of sub-C element CS, and a wiring connecting the output terminal of sub-latch SL1 to the other of the two input terminals of sub-C element CS. In other words, the output wiring of sub-latch SL0 and the output wiring of sub-latch SL1 form a redundant wiring pair.

[0169] The wiring pair meets the Figures 2 to 11 The relationship between the configuration layout described in . Figure 12 Deterioration of soft error tolerance caused by short circuit of redundant wiring pairs within the trigger circuit.

[0170] in addition, Figure 12 The output wiring of the master latch ML0 and the output wiring of the master latch ML1 in the same manner as the redundant wiring pair can also be processed. Figures 2 to 11 The relationship between the configuration layout described in .

[0171] The input data D of the master latch ML1 is delayed by a time τ compared to the input data D of the master latch ML0. Therefore, the output data Qp of the master latch ML1 is delayed by a time τ compared to the output data Qp of the master latch ML0. In this specification, it is defined as "a redundant wiring pair is an independent wiring that has the same signal level but is not connected to each other." The output wiring of the master latch ML0 and the output wiring of the master latch ML1 do not meet this definition. However, the output wiring of the master latch ML0 and the output wiring of the master latch ML1 may be Figure 14 The problem of wiring short circuit shown in FIG. 1 is that the output wiring of the master latch ML0 and the output wiring of the master latch ML1 meet the definition of a redundant wiring pair except for the delay time τ. Figures 2 to 11 The relationship of the configuration layout described in can reduce the degradation of soft error tolerance.

[0172] In addition, in the embodiment, a duplex example is shown as a redundant wiring pair, but a combination of two wirings in a plurality of wirings with three or more multiplexing can also be regarded as a wiring pair. In this case, the two wirings regarded as a wiring pair meet the following conditions: Figures 2 to 11 The relationship of the configuration layout described in .

[0173] As described above, the semiconductor device of the embodiment comprises: a plurality of wiring layers; a first wiring 11; and a second wiring 12, which is not connected to the first wiring 11 and is provided for transmitting the same signal level as the first wiring 11; the first wiring 11 and the second wiring 12 belong to different wiring layers; and the distance a1 between the first wiring 11 and the second wiring 12 is larger than the interlayer distance c between adjacent wiring layers.

[0174] This reduces the degradation of soft error tolerance caused by a short circuit in the redundant wiring pair. This is because, if a foreign object of similar size to the distance between the wirings enters, a short circuit between the first and second wirings is less likely to occur. In other words, the occurrence of a short circuit in the redundant wiring pair is suppressed.

[0175] Here, in the plan view of the semiconductor device, the first wiring 11 and the second wiring 12 may have an overlapping portion, and the distance between the first wiring 11 and the second wiring 12 in the overlapping portion may be more than twice the interlayer distance c.

[0176] Here, it may be that in a planar view of the semiconductor device, the first wiring 11 and the second wiring 12 intersect at the overlapping portion; the second wiring 12 has: a first partial wiring 12b corresponding to the overlapping portion; a second partial wiring 12a connected to one end of the first partial wiring 12b; and a third partial wiring 12c connected to the other end of the first partial wiring 12b; the first partial wiring 12b belongs to the first wiring layer M1; the second partial wiring 12a and the third partial wiring 12c belong to the second wiring layer M2 different from the first wiring layer M1, and are connected to the first partial wiring 12b via through-hole contacts v1 and v2; the first wiring 11 belongs to the third wiring layer M3 which is farther away from the first wiring layer M1 than the second wiring layer M2.

[0177] Here, the second wiring 12 may be arranged so as to bypass the end portion of the first wiring 11 so that the first wiring 11 and the second wiring 12 do not overlap in a planar view of the semiconductor integrated circuit.

[0178] Here, the semiconductor device may further include a third wiring 31 facing at least one of the first wiring 11 and the second wiring 12 between wiring layers or within a wiring layer; and the third wiring 31 may include an extending portion e1 extending from the via contact v1.

[0179] Here, the length of the extension portion e1 may be greater than the minimum dimension of the design rule of the semiconductor device.

[0180] Here, the first wiring 11 and the second wiring 12 can constitute a DICE (Dual Interlocked Storage Cell) latch circuit.

[0181] Here, the first wiring 11 and the second wiring 12 can constitute a BISER (Built in Soft Error Resiliency) flip-flop circuit.

[0182] In addition, the semiconductor device of the embodiment includes: a first wiring 11; a second wiring 12, which is not connected to the first wiring 11 and is provided to transmit the same signal level as the first wiring 11; and other wirings, which are wirings different from the first wiring 11 and the second wiring 12; within the wiring layer, the distance a between the first wiring 11 and the second wiring 12 is greater than the distance between the first wiring 11 and the other wirings, and greater than the distance between the second wiring 12 and the other wirings.

[0183] This reduces the degradation of soft error tolerance caused by short circuits in redundant wiring pairs. This is because, when a foreign object of similar size to the distance between wirings is introduced, a short circuit between the first or second wiring and another wiring is more likely to occur than a short circuit between the first wiring and the second wiring. This prevents the occurrence of undetectable short circuits—in other words, the occurrence of short circuits in redundant wiring pairs.

[0184] Here, the first wiring 11 and the second wiring 12 may have a parallel section arranged in parallel within the wiring layer, and another wiring may be sandwiched between the parallel sections.

[0185] Here, the other wiring may include an extension portion e1 extending from a main portion of the other wiring in the wiring layer, and the extension portion e1 may be sandwiched between the first wiring 11 and the second wiring 12 in the parallel section in the wiring layer.

[0186] Here, the other wiring may include an extension portion e1 extending from a through-hole connected to a main portion of the other wiring, and the extension portion e1 may be sandwiched between the first wiring 11 and the second wiring 12 in the parallel section within the wiring layer.

[0187] Here, the other wiring may have an extension portion e1 branching from a main portion of the other wiring in the wiring layer and extending therefrom, and the extension portion e1 may be sandwiched between the first wiring 11 and the second wiring 12 in the parallel section in the wiring layer.

[0188] Here, the end of the extending portion e1 may be an open end that is not connected within the wiring layer.

[0189] Here, the extended portions e1 to e3 may bypass the end portion of the first wiring 11 in the wiring layer and further be arranged in the parallel section.

[0190] Here, the semiconductor device may further include: a third wiring; and a fourth wiring that is not connected to the first wiring 11 and is provided to transmit the same signal level as the third wiring; and the other wiring may be the third wiring.

[0191] Here, part of the first wiring 11 to the fourth wiring may be arranged in the order of the first wiring 11 , the third wiring, the second wiring 12 , and the fourth wiring within the wiring layer.

[0192] Thus, the wiring of one of the first redundant pair, the wiring of one of the second redundant pair, the wiring of the other of the first redundant pair, and the wiring of the other of the second redundant pair are arranged in this order, thereby preventing or reducing short circuits of the redundant pairs.

[0193] Here, the through hole may connect the extended portion to the main body portion of the other wirings 21 and 22 in a wiring layer different from the above-mentioned wiring layer.

[0194] Here, the length of the extended portion may be larger than the minimum dimension of the design rule of the semiconductor device.

[0195] Here, it may be that the first wiring 11 and the second wiring 12 include an interval configured in parallel within the wiring layer in a manner of sandwiching other wirings 21, 22 and yet other wirings, and the distance d1 between the other wirings 21, 22 and yet other wirings within the interval is smaller than the distance between the first wiring 11 and the second wiring 12.

[0196] While the semiconductor device according to one or more technical solutions has been described above based on the embodiments, the present invention is not limited to these embodiments. Various modifications conceived by those skilled in the art to the present embodiment, or combinations of components from different embodiments, may also be included within the scope of one or more technical solutions, without departing from the spirit of the present invention.

[0197] Industrial applicability

[0198] The present invention can be used in a semiconductor device including a latch circuit or a flip-flop circuit.

[0199] Description of labels

[0200] 11, 12, 21, 22 wiring

[0201] e1~e3 extension

[0202] g1~g4 gate

[0203] i1 1st inversion circuit

[0204] i2 2nd inversion circuit

[0205] i3 3rd inversion circuit

[0206] i4 4th flip circuit

[0207] nt1~nt4 NMOS transistors

[0208] o1~o4 output nodes

[0209] pt1~pt4 PMOS transistors

[0210] v1~v3 through holes

[0211] w11, w12, w21, w22 wiring

[0212] CM Main C Component

[0213] CS Sub C Component

[0214] L1 latch circuit

[0215] M1~M3 wiring layer

[0216] ML0, ML1 master latches

[0217] SL0, SL1 slave latches

[0218] WM main weak hold circuit

[0219] WS auxiliary weak holding circuit

Claims

1. A semiconductor device, characterized in that: have: A plurality of wiring layers, including at least three wiring layers, wherein adjacent wiring layers are configured to be spaced apart from each other; a first wiring; and a second wiring line that is not connected to the first wiring line and is provided to transmit the same signal level as the first wiring line; The first wiring and the second wiring belong to at least adjacent different wiring layers; The distance between the first wiring and the second wiring is greater than the interlayer distance between adjacent wiring layers; In a plan view of the semiconductor device, the first wiring and the second wiring have an intersecting and overlapping portion; The overlapping portion belongs to a wiring layer different from the adjacent different wiring layers to which the first wiring and the second wiring belong; The distance between the first wiring and the second wiring in the overlapping portion is at least twice the interlayer distance.

2. The semiconductor device according to claim 1, wherein The second wiring includes a first partial wiring corresponding to the overlapping portion, a second partial wiring connected to one end of the first partial wiring, and a third partial wiring connected to the other end of the first partial wiring; The first part of the wiring mentioned above belongs to the first wiring layer; The second portion of wiring and the third portion of wiring belong to a second wiring layer different from the first wiring layer, and are connected to the first portion of wiring via a through-hole contact portion; The first wiring belongs to a third wiring layer that is farther from the first wiring layer than the second wiring layer.

3. The semiconductor device according to claim 1, wherein The second wiring is arranged so as to bypass an end portion of the first wiring so that the first wiring and the second wiring do not overlap in a plan view of the semiconductor device.

4. The semiconductor device according to any one of claims 1 to 3, wherein further comprising a third wiring facing at least one of the first wiring and the second wiring between wiring layers or within a wiring layer; The third wiring has an extension portion extending from the through-hole contact portion.

5. The semiconductor device according to claim 4, wherein The length of the extension portion is greater than a minimum dimension of a design rule of the semiconductor device.

6. The semiconductor device according to any one of claims 1 to 5, wherein The first wiring and the second wiring constitute a DICE (Dual Interlocked Storage Cell) latch circuit.

7. The semiconductor device according to any one of claims 1 to 5, wherein The first wiring and the second wiring constitute a BISER (Built-in Soft Error Resiliency) trigger circuit.

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