A port multiplexing test circuit design method

Abstract

The present invention discloses a port multiplexing test circuit design method, which belongs to the field of semiconductor integrated circuits. When no valid test signal appears, the system remains in the initial state and the circuit works normally. When a valid test signal appears, the signal to be tested inside the chip is selected by configuring the test state, and the signal can be measured at the chip pin. The present invention can transmit multiple internal signals to the pin port for testing, which can reduce the difficulty of testing, increase the comprehensiveness of test parameters and will not occupy too much top-level area; at the same time, the method adopts the port multiplexing method without adding additional test pins.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a port multiplexing test circuit design method. Background Art

[0002] Chip circuit design is not always successful at the first try. The circuit that is taped out for the first time may have some functions fail or the entire circuit may be non-functional. Therefore, it is necessary to find out the errors in the faulty chip circuit.

[0003] A common method is to test the signal on the chip directly. Currently, there are generally the following test methods: during the mid-test, the signal to be tested can be tested with a probe card, the signal to be tested can be bonded to the circuit board through soft encapsulation for testing, and microscope needle testing. All three test methods require the placement of the signal PAD to be tested on the TOP layer, which will not be conducive to reducing the chip area. Although the PAD area required for the microscope needle test is very small, it requires manual testing and the testing process is more cumbersome. Due to the limitations of the peripheral circuits of the mid-test, it is often used to test open-loop parameters, so the mid-test test parameters are limited. Although the soft encapsulation is bonded to the circuit board for testing, the test process is simple and the parameters are comprehensive, but the required PAD area is much larger than the previous two, and more chip area is consumed.

[0004] The above method is to test the signal directly. This method requires a certain area of ​​test area to be reserved on the top layer, which not only consumes chip area, but also cannot be tested after packaging. Another method is to bond the test signal directly to the pin. Although this method is simple and intuitive, it requires additional pins of the chip. Summary of the invention

[0005] The object of the present invention is to provide a port multiplexing test circuit design method to solve the problem that the current chip test method occupies the top layer area and needs to add additional test pins.

[0006] In order to solve the above technical problems, the present invention provides a port multiplexing test circuit design method, which adds a test circuit module on the chip to detect the internal signal to be tested from the chip pin end; the test circuit module includes a signal detection part, a state control part and a signal selection part;

[0007] The signal detection part detects whether a valid test signal appears at the chip pin end. When the input signal meets the test signal requirement, the signal detection part will provide a valid trigger signal to the state control part.

[0008] The output state of the state control part switches regularly between a finite number of states, its trigger signal is controlled by the signal detection part, and its output state controls the switch position of the signal selection part;

[0009] The signal selection part connects the signal to be tested inside the chip to the external pin end of the chip, and its switch position is determined by the output state of the state control part;

[0010] When the test state and signal selection configuration are completed, the detection pin can input normal signals, and the internal circuit of the chip also responds to the input signals normally.

[0011] Optionally, the input end of the signal detection part is connected to the chip pin end Pin1, and the output ends out1 and out2 thereof are respectively connected to the input ends sigA and sigB of the state control part;

[0012] The input terminals sigA and sigB of the state control part are connected to the output terminals out1 and out2 of the signal detection part, and the output terminals s1, s2...sm are connected to the control terminals c1, c2...cm of the signal selection part respectively;

[0013] The input terminals t1, t2...tn of the signal selection part are connected to the signals to be tested inside the chip, the output terminal out is connected to the chip pin terminal Pin2, and the control terminals c1, c2...cm are connected to the output terminals s1, s2...sm of the state control part.

[0014] Optionally, the output state of the state control part has a total of y states: state 1, state 2, ..., state y-1 and state y; the relationship between the number of states y and the test point signal is 1≤n≤y≤2 m ;

[0015] When a trigger signal appears at the input terminal sigA, the current state w switches to state w+1, 1≤w≤y-1, and if w=y, it switches to the initial state 1;

[0016] When a trigger signal appears at the input terminal sigB, the current state w switches to state w-1, 2≤w≤y. If the initial state is w=1, it switches to state y;

[0017] If there is no valid trigger signal, the output state remains in the initial state, i.e., state 1.

[0018] Optionally, the output end of the signal selection part is connected to the chip pin end Pin2 through a driving module.

[0019] Optionally, the test signal has current capability, pulse width and margin to prevent signal interference, and its level value is higher than the highest voltage VSS for normal operation of the circuit. max , or lower than the minimum voltage VSS for normal operation min .

[0020] Optionally, the test signal is level triggered, edge triggered or other triggering modes.

[0021] In the port multiplexing test circuit design method provided by the present invention, when no valid test signal appears, the system remains in the initial state and the circuit works normally. When a valid test signal appears, the signal to be tested inside the chip is selected by configuring the test state, and the signal can be measured at the chip pin. The present invention can transmit multiple internal signals to the pin port for testing, which can reduce the difficulty of testing, increase the comprehensiveness of test parameters and will not occupy too much top-level area; at the same time, the method adopts the port multiplexing method without adding additional test pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of a port multiplexing test circuit design method provided by the present invention;

[0023] Figure 2 It is a conversion logic diagram of the state control provided by the present invention. DETAILED DESCRIPTION

[0024] The following is a further detailed description of a port multiplexing test circuit design method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] The schematic diagram of adding a test circuit module on the chip provided by the present invention is as follows Figure 1 As shown, the test circuit module detects the internal signal to be tested from the chip pin end; the test circuit module includes a signal detection part, a state control part and a signal selection part.

[0026] The input end of the signal detection part is connected to the chip pin end Pin1, and its output ends out1 and out2 are respectively connected to the input ends sigA and sigB of the state control part; the input ends sigA and sigB of the state control part are connected to the output ends out1 and out2 of the signal detection part, and the output ends s1, s2...sm are respectively connected to the control ends c1, c2...cm of the signal selection part; the input ends t1, t2...tn of the signal selection part are connected to the signal to be tested inside the chip, and the output end out is connected to the chip drive module, and the drive module is then connected to the chip pin end Pin2. If there is no drive module inside the chip, the output end of the signal selection part can be directly connected to the chip pin Pin2, and the control ends c1, c2...cm of the signal selection part are respectively connected to the output ends s1, s2...sm of the state control part. Pin1, Pin2 and Pinx refer to the external pins of the chip, and their serial numbers are not the real serial numbers of the chip.

[0027] The present invention provides a method for designing a port multiplexing test circuit, and the specific control method is as follows:

[0028] The main function of the signal detection part is to detect whether there is a valid test signal at the chip pin end Pin1. When the input signal meets the test signal requirements, the signal detection part can provide a valid trigger signal to the state control part. A valid test signal is a necessary condition for triggering the test state change. At the same time, it is also necessary to ensure that the circuit will not trigger the test mode when it is working normally. Therefore, the test signal cannot select a level signal in the normal working voltage range, and its level value should be higher than the highest voltage VSS of the normal working voltage. max Or below the minimum voltage VSS min In fact, when the circuit is working normally, there is a certain probability that the voltage higher than VSS will appear at Pin1. max and below VSS min Therefore, the effective test signal also needs to have a certain current capability, pulse width and margin to prevent signal interference. When a valid test signal is detected, the signal detection part will provide a trigger signal to the state control part. The designer can choose level trigger, edge trigger or other trigger modes as the trigger signal according to the needs.

[0029] The output state of the state control part is converted between a finite number of states according to a certain rule, such as Figure 2As shown, there are y states in total: state 1, state 2, ..., state y-1 and state y; when the trigger signal sigA appears at the input terminal sigA, the current state w switches to state w+1 (1≤w≤y-1), and if w=y, it switches to the initial state 1. Similarly, when the trigger signal sigB appears at the input terminal sigB, the current state w switches to state w-1 (2≤w≤y), and if it is the initial state w=1, it switches to state y. Figure 2 The relationship between the number of states y and the test point signal is as follows: 1≤n≤y≤2 m , if no valid trigger signal is detected, the output state remains in the initial state, i.e., state 1, and the signal selection part selects the t1 signal; Figure 2 There are two trigger signals, sigA and sigB. When there is only one trigger state, sigA, it takes y-1 signal triggers to switch from state 2 to state 1. The same is true for sigB. When sigA and sigB exist at the same time, it only takes one trigger to switch from state 2 to state 1. If there are not many test states, the designer only needs one trigger signal.

[0030] The input end of the signal selection part is connected to the signal that needs to be tested inside the chip, such as common test signals such as reference enable signal, temperature enable signal, overvoltage enable signal, internal clock signal and other logic signals. At the same time, the signal at this location in the initial state is also a logic signal. The output end of the signal selection part is connected to the input of the driving module, and the output of the driving module is connected to the chip pin Pin2. If there is no driving module inside the chip, the output end of the signal selection part is directly connected to the chip pin Pin2. When the internal structure of the chip meets certain conditions, an analog signal such as a reference voltage can also be sent as a test signal to the chip pin end Pin2 for testing. The output state of the state control part determines the switch position of the signal selection part. When the test state and signal selection configuration are completed, the detection pin Pin1 can input a normal signal, and the internal circuit of the chip also responds normally to the input signal.

[0031] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A port multiplexing test circuit design method, characterized in that: Add a test circuit module on the chip to detect the internal signal to be tested from the chip pin end; the test circuit module includes a signal detection part, a state control part and a signal selection part; The signal detection part detects whether a valid test signal appears at the chip pin end. When the input signal meets the test signal requirement, the signal detection part will provide a valid trigger signal to the state control part. The output state of the state control part switches regularly between a finite number of states, its trigger signal is controlled by the signal detection part, and its output state controls the switch position of the signal selection part; The signal selection part connects the signal to be tested inside the chip to the external pin end of the chip, and its switch position is determined by the output state of the state control part; When the test state and signal selection configuration are completed, the detection pin can input normal signals, and the internal circuit of the chip also responds to the input signals normally.

2. The port multiplexing test circuit design method according to claim 1, characterized in that: The input end of the signal detection part is connected to the chip pin end Pin1, and the output ends out1 and out2 thereof are respectively connected to the input ends sigA and sigB of the state control part; The input terminals sigA and sigB of the state control part are connected to the output terminals out1 and out2 of the signal detection part, and the output terminals s1, s2...sm are connected to the control terminals c1, c2...cm of the signal selection part respectively; The input terminals t1, t2...tn of the signal selection part are connected to the signals to be tested inside the chip, the output terminal out is connected to the chip pin terminal Pin2, and the control terminals c1, c2...cm are connected to the output terminals s1, s2...sm of the state control part.

3. The port multiplexing test circuit design method according to claim 2, characterized in that: The output state of the state control part has a total of y states: state 1, state 2, ..., state y-1 and state y; the relationship between the number of states y and the test point signal is 1≤n≤y≤2 m ; When a trigger signal appears at the input terminal sigA, the current state w switches to state w+1, 1≤w≤y-1, and if w=y, it switches to the initial state 1; When a trigger signal appears at the input terminal sigB, the current state w switches to state w-1, 2≤w≤y. If the initial state is w=1, it switches to state y; If there is no valid trigger signal, the output state remains in the initial state, i.e., state 1.

4. The port multiplexing test circuit design method according to claim 2, characterized in that: The output end of the signal selection part is connected to the chip pin end Pin2 through the driving module.

5. The port multiplexing test circuit design method according to claim 1, characterized in that: The test signal has current capability, pulse width and margin to prevent signal interference, and its level value is higher than the highest voltage VSS for normal operation of the circuit. max , or lower than the minimum voltage VSS for normal operation min .

6. The port multiplexing test circuit design method according to claim 5, characterized in that: The test signal is level triggered, edge triggered or in other triggering modes.

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