Encapsulated target current automatic trimming circuit and integrated chip

Abstract

The present invention belongs to the technical field of integrated chips, and particularly relates to a target current automatic trimming circuit and an integrated chip after packaging. Among them, the target current automatic trimming circuit includes a reference circuit, an impedance compensation circuit, a voltage comparison circuit, and a logic trimming circuit. The logic trimming circuit automatically outputs a trimming control signal to the impedance compensation circuit according to the test signal, so that the impedance compensation circuit realizes impedance compensation for the packaging copper wire, and the voltage of the second pin gradually rises to the voltage value of the first pin. When the two are equal, the logic trimming circuit receives the preset level after inversion, and thus stops trimming and locks the current resistance value and the current logic value. The logic value can be stored in the register in the integrated chip, so that the integrated chip is trimmed to the target current magnitude, without being affected by the packaging copper wire, and the trimming accuracy is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated chips, and particularly relates to a post-packaging target current automatic trimming circuit and an integrated chip. Background Art

[0002] Due to the rapid development of the semiconductor industry, the production capacity of wafer fabs has become increasingly insufficient, resulting in soaring wafer prices. At this time, the test cost of chips begins to become important.

[0003] Traditional chip trimming technology relies on the equipment of wafer test manufacturers for testing and trimming. During the test process, since it is in an unpackaged state, packaging influencing factors such as copper wire impedance are ignored, and there is a deviation between the trimming result and after packaging, resulting in a decrease in trimming accuracy. Summary of the Invention

[0004] The purpose of the present invention is to provide a post-packaging target current automatic trimming circuit, aiming to solve the problem that the traditional trimming scheme performs trimming when the chip is unpackaged, resulting in a decrease in trimming accuracy.

[0005] A first aspect of an embodiment of the present invention provides a post-packaging target current automatic trimming circuit. The target current automatic trimming circuit is disposed in an integrated chip of a packaging structure. The integrated chip is provided with a first pin and a second pin. The first pin is directly connected to a test pin on a packaging substrate of the packaging structure, and the second pin is connected to the test pin through a packaging copper wire in the integrated chip. The second pin is a test contact of the integrated chip. The test pin is used to input a target current. The target current automatic trimming circuit includes:

[0006] A reference circuit for outputting a reference voltage;

[0007] An impedance compensation circuit, the input end of the impedance compensation circuit is connected to the output end of the reference circuit, the output end of the impedance compensation circuit is connected to the second pin, and the impedance compensation circuit is triggered by a trimming control signal to trim the size of an internal compensation resistor to compensate for the impedance of the packaging copper wire between the second pin and the test pin, and output a voltage signal of a corresponding size;

[0008] A voltage comparison circuit, the first input end of the voltage comparison circuit is connected to the first pin, and the second input end of the voltage comparison circuit is connected to the output end of the impedance compensation circuit;

[0009] A logic trimming circuit, wherein the feedback terminal of the logic trimming circuit is connected to the output terminal of the voltage comparison circuit, the output terminal of the logic trimming circuit is connected to the controlled terminal of the impedance compensation circuit, the logic trimming circuit receives a trimming control signal that changes according to the output of the test signal, and locks the magnitude of the trimming control signal after the output level of the voltage comparison circuit flips to a preset level, so as to lock the resistance value of the impedance compensation circuit and the logic value of the current trimming control signal.

[0010] Optionally, the packaged target current automatic trimming circuit further includes:

[0011] A current detection circuit, which is respectively connected to the test pin, the first pin and the second pin, and is used for detecting the current direction of the target current and outputting a voltage signal with a corresponding polarity to the first pin and the second pin.

[0012] Optionally, the impedance compensation circuit includes a plurality of series resistors and a plurality of switching tubes respectively connected to both ends of each resistor;

[0013] Both ends of the plurality of series resistors form the input end and the output end of the impedance compensation circuit, and the controlled terminals of the plurality of switching tubes are used for inputting the trimming control signal and conducting or turning off correspondingly.

[0014] Optionally, the voltage comparison circuit includes a comparator, the positive-phase input terminal of the comparator is connected to the second pin, the negative-phase input terminal of the comparator is connected to the first pin, and the output terminal of the comparator is connected to the feedback terminal of the logic trimming circuit.

[0015] Optionally, the logic trimming circuit includes a pre-trimming circuit, a fuse circuit and a logic gate output circuit;

[0016] The input terminal of the pre-trimming circuit and the input terminal of the fuse circuit are commonly connected and simultaneously receive the test signal and the output level of the voltage comparison circuit. The output terminal of the pre-trimming circuit and the output terminal of the fuse circuit are respectively connected to the input terminal of the logic gate output circuit, and the output terminal of the logic gate output circuit is connected to the controlled terminal of the impedance compensation circuit;

[0017] The pre-trimming circuit is controlled by the test signal to trigger and output a pre-trimming signal to the logic gate output circuit;

[0018] The fuse circuit is controlled by the output level of the voltage comparison circuit to trigger and output a locking control signal to the logic gate output circuit when the output level flips;

[0019] The logic gate output circuit is used to output the pre - trimming signal to the impedance compensation circuit to perform impedance step - trimming on the impedance compensation circuit, and output the locking control signal to the impedance compensation circuit to lock the impedance value of the current impedance compensation circuit.

[0020] Optionally, the pre - trimming circuit includes a first shift register.

[0021] Optionally, the fusing circuit includes a fuse;

[0022] The fuse is blown when the output level of the voltage comparison circuit flips, and outputs a locking control signal.

[0023] Optionally, the logic gate output circuit includes multiple groups of logic gate sets, and each logic gate set includes at least one correspondingly connected logic gate.

[0024] A second aspect of the embodiments of the present invention provides an integrated chip, including the packaged target current automatic trimming circuit as described above.

[0025] Optionally, the integrated chip further includes a general - purpose pin, and a test signal is input through the general - purpose pin;

[0026] Or the integrated chip further includes a signal generation module, the signal generation module is connected to the first pin or the enable pin, and the signal generation module is triggered by the test current or the enable signal of the enable pin to output the test signal.

[0027] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above - mentioned target current automatic trimming circuit is provided with a reference circuit, an impedance compensation circuit, a voltage comparison circuit, and a logic trimming circuit. The logic trimming circuit automatically outputs a trimming control signal to the impedance compensation circuit according to the test signal, so that the impedance compensation circuit realizes impedance compensation for the package copper wire, making the voltage of the second pin gradually rise to the voltage value of the first pin. When the two are equal, the logic trimming circuit receives the flipped preset level, thereby stopping trimming and locking the current resistance value and the current logic value. The logic value can be stored in the register in the integrated chip, so that the integrated chip is trimmed to the target current magnitude, not affected by the package copper wire, and the trimming accuracy is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of the package structure provided by the embodiments of the present invention;

[0029] Figure 2 It is a first schematic structural diagram of the target current automatic trimming circuit provided by the embodiments of the present invention;

[0030] Figure 3The second structural schematic diagram of the target current automatic trimming circuit provided by the embodiment of the present invention;

[0031] Figure 4 For Figure 2 The circuit schematic diagram of the impedance compensation circuit in the target current automatic trimming circuit provided by the embodiment;

[0032] Figure 5 The third structural schematic diagram of the target current automatic trimming circuit provided by the embodiment of the present invention;

[0033] Figure 6 The circuit schematic diagram of the pre-trimming circuit provided by the embodiment of the present invention;

[0034] Figure 7 The first partial circuit schematic diagram of the fuse circuit provided by the embodiment of the present invention;

[0035] Figure 8 The second partial circuit schematic diagram of the fuse circuit provided by the embodiment of the present invention;

[0036] Figure 9 The circuit schematic diagram of the logic gate output circuit provided by the embodiment of the present invention;

[0037] Figure 10 The circuit schematic diagram of the current detection circuit provided by the embodiment of the present invention. Detailed implementation manners

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0040] The first aspect of the embodiment of the present invention proposes a packaged target current automatic trimming circuit 10.

[0041] Such as Figure 1As shown, the target current automatic trimming circuit 10 is disposed within the integrated chip 100 of the packaging structure 1. The integrated chip 100 is disposed on a packaging substrate, and the packaging substrate is further provided with test pins 11. The integrated chip 100 obtains an external input signal through the test pins 11, which is mainly used to input a target current. At the same time, a plurality of pins are disposed within the integrated chip 100, mainly including a first pin 40 and a second pin 30. The first pin 40 is directly connected to the test pin 11 on the packaging substrate, and the second pin 30 is connected to the test pin 11 through a packaging copper wire within the integrated chip 100. At the same time, when the integrated chip 100 performs wafer testing, the second pin 30 within the integrated chip 100 is a test contact, and a specification actual value is obtained through the trimming contact, and the trimming of the target value is achieved through the internal target current automatic trimming circuit 10.

[0042] When the integrated chip 100 obtains the target current through the second pin 30, due to the impedance effect of the packaging copper wire, the voltage at this point is inconsistent with the voltage value input by the test pin 11, resulting in a difference between the actual target current obtained and the target current of the test pin 11. Taking this current as the specification current, such as the overcharge protection current threshold or the over-discharge protection current threshold, when the integrated chip 100 is operating, the integrated chip 100 cannot operate at the accurate protection current threshold, causing the current protection to fail.

[0043] Therefore, on the basis of trimming, in order to avoid the influence of the packaging copper wire, at the same time, reduce the trimming cost and improve the trimming accuracy, in this embodiment, a target current automatic trimming circuit 10 is proposed, as Figure 2 shown, the target current automatic trimming circuit 10 includes:

[0044] A reference circuit 11, the reference circuit 11 is used to output a reference voltage;

[0045] An impedance compensation circuit 12, the input end of the impedance compensation circuit 12 is connected to the output end of the reference circuit 11, the output end of the impedance compensation circuit 12 is connected to the second pin 30, and the impedance compensation circuit 12 is triggered by a trimming control signal to trim the magnitude of the internal compensation resistor to compensate for the impedance of the packaging copper wire between the second pin 30 and the test pin 11, and output a voltage signal of corresponding magnitude;

[0046] A voltage comparison circuit 13, the first input end of the voltage comparison circuit 13 is connected to the first pin 40, and the second input end of the voltage comparison circuit 13 is connected to the output end of the impedance compensation circuit 12;

[0047] The logic trimming circuit 14, the feedback terminal of the logic trimming circuit 14 is connected to the output terminal of the voltage comparison circuit 13, the output terminal of the logic trimming circuit 14 is connected to the controlled terminal of the impedance compensation circuit 12, the logic trimming circuit 14 outputs a trimming control signal according to the change of the test signal TEST, and locks the magnitude of the trimming control signal after the output level of the voltage comparison circuit 13 flips to a preset level, so as to lock the resistance value of the impedance compensation circuit 12 and the logic value of the current trimming control signal.

[0048] In this embodiment, the target current is input to the integrated chip 100 through the test pin 11, the first pin 40 is connected to the test pin 11 on the package structure 1. At this time, the voltage value of the first pin 40 is the target voltage, the target current flows into the second pin 30 through the package copper wire, and the voltage value of the second pin 30 is the actual target voltage value received inside the integrated chip 100, corresponding to the actual target current value. By trimming the voltage value of the second pin 30 to the voltage value of the first pin 40, that is, the actual target current value of the second pin 30 is trimmed to the target current value of the test pin 11, so that the integrated chip 100 obtains the target current value required by the package structure 1 inside, and the integrated chip 100 uses this target current value as the overcurrent protection threshold to achieve current protection.

[0049] When trimming is performed, the target current is input to the first pin 40 and the second pin 30 through the test pin 11. At this time, the voltage of the second pin 30 is less than the voltage of the first pin 40. The test signal TEST is generated automatically by the integrated chip 100 or input through another multiplexing pin, and the target current automatic trimming circuit 10 automatically enters the trimming operation.

[0050] Specifically, the logic trimming circuit 14 outputs a trimming control signal to the impedance compensation circuit 12 according to the test signal TEST. The trimming control signal changes according to a preset trimming step, for example, sequentially changes from 0000 to 1111, or sequentially changes from 1111 to 0000. The specific change mode of the trimming step is not limited. According to the changing trimming control signal, the impedance of the impedance compensation circuit 12 changes, realizing the compensation of the impedance of the package copper wire. In the initial state, the voltage of the first pin 40 is greater than the voltage of the second pin 30. At this time, the voltage comparison circuit 13 outputs a first level, for example, a low level. When the logic trimming circuit 14 receives the first level, it continues to output a changing trimming control signal. When the impedance of the impedance compensation circuit 12 gradually changes, the voltage value of the second pin 30 gradually rises. When it rises to the voltage of the first pin 40, the output level of the voltage comparison circuit 13 flips, for example, outputs a high level. After the logic trimming circuit 14 receives the flipped level, it determines that the trimming is completed. The logic trimming circuit 14 locks the logic value of the current trimming control signal, thereby locking the impedance of the impedance compensation circuit 12 to a preset value, that is, locking the voltage and current of the second pin 30 to the voltage and current of the first pin 40, so that the voltage of the test contact of the integrated chip 100 is trimmed to the voltage of the test pin 11 of the package structure 1. The integrated chip 100 performs subsequent current protection with this current value as the protection current threshold.

[0051] The logic value can be stored in the register 20 inside the integrated chip 100, so that the integrated chip 100 is trimmed to the target current magnitude. The trimming result is not affected by the package copper wire, improving the trimming accuracy.

[0052] Among them, the impedance compensation circuit 12 can be composed of a switch structure and a resistor structure. The resistor structure can be multiple series-parallel resistors. The switch structure corresponds to the series-parallel connection of the resistor structure. The switch structure conducts and turns off correspondingly according to the received trimming control signal, so as to realize short-circuit and short-circuit control of different resistor structures, and then form different resistance values, and finally compensate the impedance of the package copper wire of the second pin 30, so that the voltage and current of the second pin 30 gradually rise to the voltage and current of the first pin 40, completing the trimming work.

[0053] The voltage comparison circuit 13 can adopt a comparator U1 and corresponding peripheral components, such as Figure 5 As shown, optionally, the voltage comparison circuit 13 includes a comparator U1. The positive input terminal of the comparator U1 is connected to the second pin 30, the negative input terminal of the comparator U1 is connected to the first pin 40, and the output terminal of the comparator U1 is connected to the feedback terminal of the logic trimming circuit 14.

[0054] During the initial trimming, the voltage of the first pin 40 is greater than the voltage of the second pin 30. The voltage at the non-inverting input terminal of the comparator U1 is less than the voltage at the inverting input terminal of the comparator U1. The comparator U1 outputs a low level. During the gradual trimming process, the voltage of the second pin 30 gradually rises. When the voltage of the first pin 40 is equal to the voltage of the second pin 30, the comparator U1 outputs a high level. At this time, the logic trimming circuit 14 locks the logic value of the current trimming control signal, and further locks the impedance of the impedance compensation circuit 12.

[0055] The reference circuit 11 can adopt a corresponding reference voltage source. The reference circuit 11 is connected to the power supply pin in the integrated chip 100 and converts and outputs a reference voltage source. The impedance compensation circuit 12 gradually outputs a voltage signal of corresponding magnitude to the second pin 30, so that the voltage and current of the second pin 30 are gradually trimmed to the target voltage and current.

[0056] The logic trimming circuit 14 can adopt corresponding structures such as a shift register, a D flip-flop, a fuse FUSE, etc. The specific structure is set according to requirements.

[0057] As Figure 3 shown, optionally, the packaged target current automatic trimming circuit 10 further includes:

[0058] A current detection circuit 15, which is respectively connected to the test pin 11, the first pin 40 and the second pin 30. The current detection circuit 15 is used to detect the current direction of the target current and output a voltage signal of corresponding polarity to the first pin 40 and the second pin 30.

[0059] In this embodiment, after the target current flows into the integrated chip 100 through the test pin 11, it first passes through the current detection circuit 15. The current detection circuit 15 identifies the current direction, that is, identifies whether the current target current is the discharge target threshold current or the charge target current threshold, and determines the positive and negative input states of the voltage comparison circuit 13.

[0060] Among them, the current detection circuit 15 can adopt a corresponding detection circuit. As Figure 10 shown, the current detection circuit 15 includes a first comparator COMP, a plurality of inverters and a plurality of switches. Taking the charging current as the positive current and the discharging current as the negative current, when the target current is a positive current or a negative current, the first comparator COMP outputs high and low levels correspondingly, and controls the plurality of switches to conduct and turn off correspondingly through the inverters, so as to output voltage signals of different polarities to the subsequent first pin 40 and second pin 30. At the same time, a corresponding current direction detection signal is output to the register 20.

[0061] As Figure 4As shown, optionally, the impedance compensation circuit 12 includes a plurality of series resistors and a plurality of switching transistors respectively connected to both ends of each resistor;

[0062] Both ends of the plurality of series resistors form the input end and the output end of the impedance compensation circuit 12, and the controlled ends of the plurality of switching transistors are used to input trimming control signals and conduct or turn off correspondingly.

[0063] In this embodiment, one end of the series resistor is connected to the output end of the reference circuit 11, and the other end is connected to the second pin 30. The plurality of switching transistors receive the corresponding logic values in the trimming control signal and conduct or turn off respectively, so as to form an effective trimming resistor in series and output the corresponding impedance to compensate the impedance of the package copper wire. Among them, the number of switches is set correspondingly according to the number of bits of the trimming control signal or the level combination state. For example, when both the switching transistor and the resistor include 4, when the logic value is 1111, all the switching transistors conduct; when the logic value is 1100, the first two or the last two switching transistors conduct, so as to form different impedances and output different voltage signals to the second pin 30.

[0064] Please continue to refer to Figure 5 , optionally, the logic trimming circuit 14 includes a pre-trimming circuit 141, a fusing circuit 142, and a logic gate output circuit 143;

[0065] The input end of the pre-trimming circuit 141 and the input end of the fusing circuit 142 are commonly connected and simultaneously receive the test signal TEST and the output level of the voltage comparison circuit 13. The output end of the pre-trimming circuit 141 and the output end of the fusing circuit 142 are respectively connected to the input end of the logic gate output circuit 143, and the output end of the logic gate output circuit 143 is connected to the controlled end of the impedance compensation circuit 12;

[0066] The pre-trimming circuit 141 is triggered by the test signal TEST to output a pre-trimming signal to the logic gate output circuit 143;

[0067] The fusing circuit 142 is triggered to output a locking control signal to the logic gate output circuit 143 when the output level of the voltage comparison circuit 13 flips;

[0068] The logic gate output circuit 143 is used to output the pre-trimming signal to the impedance compensation circuit 12 to finely adjust the impedance of the impedance compensation circuit 12 step by step, and output the locking control signal to the impedance compensation circuit 12 to lock the impedance value of the current impedance compensation circuit 12.

[0069] In this embodiment, the pre-trimming circuit 141 and the fusing circuit 142 simultaneously receive the test signal TEST and the feedback voltage comparison signal. During the logic trimming process, when the voltage of the second pin 30 is less than that of the first pin 40, at this time, the pre-trimming circuit 141 is the main target current automatic trimming circuit, and outputs a changing pre-trimming signal to the logic gate output circuit 143. The logic gate output circuit 143 realizes AND or NAND output, and inputs the pre-trimming signal directly or in reverse to the impedance compensation circuit 12, so as to realize the impedance adjustment of the impedance compensation circuit 12, and then change the voltage of the second pin 30. When the voltage comparison circuit 13 outputs a flipped level, at this time, the fusing circuit 142 cuts in and outputs a locking control signal. At this time, the logic gate output circuit 143 only outputs the locking control signal to the impedance compensation circuit 12, locks and solidifies the switch states of the impedance compensation circuit 12, and is not interfered by other signals, so as to lock the corresponding resistance value and the voltage value output by the impedance compensation circuit 12. The register 20 can obtain the logic value of the current locking control signal.

[0070] The pre-trimming circuit 141 receives the test signal TEST and converts it into a pre-trimming signal with corresponding changing logic values, such as changing from 0000 to 1111, etc. Optionally, as Figure 6 shown, the pre-trimming circuit 141 includes a shift register U2. The number of shift registers U2 is at least one, and the output ports of the shift register U2 correspond to the number of resistors and switching transistors in the impedance compensation circuit 12. For example, as Figure 6 shown, it includes one shift register U2, and one shift register U2 has 8 output ports. When the number of resistors and switching transistors in the impedance compensation circuit 12 increases, the number of shift registers U2 or the output ports increase correspondingly.

[0071] The fusing circuit 142 can adopt corresponding trigger, fuse FUSE and other structures, as Figure 8 shown. Optionally, the fusing circuit 142 includes a fuse FUSE;

[0072] The fuse FUSE is blown when the output level of the voltage comparison circuit 13 flips, and outputs a locking control signal.

[0073] In this embodiment, when detecting the flipped level, that is, the high level, the fusing circuit 142 burns out the fuse FUSE, so as to fix the resistance value and the output voltage of the impedance compensation circuit 12 to the target resistance value and the target voltage value, and complete the trimming. The whole trimming process is automatically completed inside the integrated chip 100, which greatly shortens the product development cycle.

[0074] Among them, according to the number of resistors and switching transistors in the impedance compensation circuit 12, the fusing circuit 142 is correspondingly provided with a plurality of fuses FUSE and peripheral circuits correspondingly connected to the fuses FUSE. Each fuse FUSE and the peripheral circuit correspondingly connected to the fuse FUSE output one of the lock control signals to control one of the switching transistors.

[0075] Meanwhile, as Figure 7 shown, the fusing circuit 142 further includes a first converter U3 and a second converter U4, and further includes a corresponding switching transistor connected to the fuse, a D flip-flop U5 and other structures. The first converter U3 and the second converter U4 are used to realize the conversion and output of a single-channel test signal, and output multiple logic values to the peripheral circuit corresponding to one fuse FUSE, so as to control the corresponding fusing or suspension of fusing of the fuse FUSE.

[0076] Optionally, the logic gate output circuit 143 includes multiple groups of logic gate sets. Each logic gate set includes at least one correspondingly connected logic gate. As Figure 9 shown, the logic gate output circuit 143 includes AND gates and / or NAND gates. By realizing the AND gate and NAND gate logic conversion output of the output signals of the pre-trimming circuit 141 and the fusing circuit 142, meanwhile, according to the number of resistors and switching transistors in the impedance compensation circuit 12, the logic gate output circuit 143 includes multiple groups of logic gate sets, and each group of logic gate sets completes the output of one logic value, so as to realize the on-off control of each switching transistor, and change the impedance and output voltage value of the impedance compensation circuit 12.

[0077] The present invention also proposes an integrated chip 100. The integrated chip 100 includes the packaged target current automatic trimming circuit 10. The specific structure of the packaged target current automatic trimming circuit 10 refers to the above embodiments. Since the integrated chip 100 of the present invention adopts all the technical solutions of the above all embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated herein one by one.

[0078] The integrated chip 100 of the present invention is internally provided with a target current automatic trimming circuit 10, which can complete automatic trimming according to the target current input from its own port, directly skipping the middle test step. It can be tested and trimmed after the integrated chip 100 is packaged, and only needs to input the target current through one pin to realize the automatic trimming function, shortening the product development cycle and improving the product yield. Meanwhile, through the internal impedance compensation circuit 12, the compensation of the impedance of the packaging copper wire is realized, and the trimming accuracy is improved.

[0079] Optionally, the integrated chip 100 further includes a general-purpose pin. During trimming, the target current is input through the first pin 40 and the second pin 30, and the test signal TEST is input through the general-purpose pin to achieve synchronous trimming control. Alternatively, the integrated chip 100 further includes a signal generation module. The signal generation module is connected to the first pin 40 or the enable pin. The signal generation module is triggered by the test current or the enable signal of the enable pin to output the test signal TEST, directly realizing the triggering and output of the test signal TEST inside the integrated chip 100 without additionally multiplexing the pins of the integrated chip 100, improving the test reliability. Among them, the signal generation module can be a corresponding signal source, a logic conversion circuit, etc.

[0080] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. An encapsulated target current automatic trimming circuit, the target current automatic trimming circuit is arranged in an integrated chip of a packaging structure, the integrated chip is provided with a first pin and a second pin, the first pin is directly connected to a test pin on a packaging substrate of the packaging structure, the second pin is connected to the test pin through a packaging copper wire in the integrated chip, the second pin is a test contact of the integrated chip, and the test pin is used for inputting a target current. Characterized in that, The target current automatic trimming circuit includes: A reference circuit for outputting a reference voltage; An impedance compensation circuit, the input end of the impedance compensation circuit is connected to the output end of the reference circuit, the output end of the impedance compensation circuit is connected to the second pin, the impedance compensation circuit is triggered by a trimming control signal to trim the size of an internal compensation resistor to compensate for the impedance of the packaging copper wire between the second pin and the test pin, and outputs a voltage signal of corresponding size; A voltage comparison circuit, the first input end of the voltage comparison circuit is connected to the first pin, and the second input end of the voltage comparison circuit is connected to the output end of the impedance compensation circuit; A logic trimming circuit, the feedback end of the logic trimming circuit is connected to the output end of the voltage comparison circuit, the output end of the logic trimming circuit is connected to the controlled end of the impedance compensation circuit, the logic trimming circuit receives a trimming control signal whose output changes with the test signal, and locks the size of the trimming control signal after the output level of the voltage comparison circuit flips to a preset level, so as to lock the resistance value of the impedance compensation circuit and the logic value of the current trimming control signal.

2. The encapsulated target current automatic trimming circuit according to claim 1, Characterized in that, The encapsulated target current automatic trimming circuit further includes: A current detection circuit, the current detection circuit is respectively connected to the test pin, the first pin and the second pin, and the current detection circuit is used for detecting the current direction of the target current and outputting a voltage signal of corresponding polarity to the first pin and the second pin.

3. The encapsulated target current automatic trimming circuit according to claim 1, Characterized in that, The impedance compensation circuit includes a plurality of series resistors and a plurality of switching tubes respectively connected to both ends of each resistor; Both ends of the plurality of series resistors form the input end and the output end of the impedance compensation circuit, and the controlled ends of the plurality of switching tubes are used for inputting the trimming control signal and conducting or turning off correspondingly.

4. The encapsulated target current automatic trimming circuit according to claim 1, Characterized in that, The voltage comparison circuit includes a comparator, the positive-phase input end of the comparator is connected to the second pin, the negative-phase input end of the comparator is connected to the first pin, and the output end of the comparator is connected to the feedback end of the logic trimming circuit.

5. The encapsulated target current automatic trimming circuit according to claim 1, Characterized in that, The logic trimming circuit includes a pre-trimming circuit, a fusing circuit and a logic gate output circuit; The input end of the pre-adjustment circuit and the input end of the fusing circuit are commonly connected and simultaneously receive the test signal and the output level of the voltage comparison circuit. The output end of the pre-adjustment circuit and the output end of the fusing circuit are respectively connected to the input end of the logic gate output circuit. The output end of the logic gate output circuit is connected to the controlled end of the impedance compensation circuit; The pre-adjustment circuit is controlled by the test signal to trigger and output a pre-adjustment signal to the logic gate output circuit; The fusing circuit is triggered to output a locking control signal to the logic gate output circuit when the output level of the voltage comparison circuit flips; The logic gate output circuit is used to output the pre-adjustment signal to the impedance compensation circuit to finely adjust the impedance step of the impedance compensation circuit, and output the locking control signal to the impedance compensation circuit to lock the impedance value of the current impedance compensation circuit and the logic value of the current trimming control signal.

6. The packaged target current automatic trimming circuit according to claim 5, characterized in that, the pre-adjustment circuit includes a first shift register.

7. The packaged target current automatic trimming circuit according to claim 5, characterized in that, the fusing circuit includes a fuse; the fuse is blown when the output level of the voltage comparison circuit flips and outputs a locking control signal.

8. The packaged target current automatic trimming circuit according to claim 5, characterized in that, the logic gate output circuit includes multiple groups of logic gate groups, and each logic gate group includes at least one correspondingly connected logic gate.

9. An integrated chip, characterized in that, it includes the packaged target current automatic trimming circuit according to any one of claims 1 to 8.

10. The integrated chip according to claim 9, characterized in that, the integrated chip further includes a general-purpose pin, and the test signal is input through the general-purpose pin; or the integrated chip further includes a signal generation module, the signal generation module is connected to the first pin or the enable pin, and the signal generation module is triggered by the test current or the enable signal of the enable pin to output the test signal.

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