A register configuration circuit and an integrated circuit chip

Abstract

The present application discloses a register configuration circuit, including: a clock switching module, which is used to output a target clock signal consistent with the clock signal of the target functional module according to a target control signal when the register of the target functional module in the target integrated circuit chip needs to be configured; an asynchronous bridge, which is connected to the clock switching module, is used to perform cross-clock domain processing on the register configuration request signal under the source clock domain sent by the target host, so as to convert the register configuration request signal under the source clock domain into a register configuration request signal under the target clock domain; a protocol processing module, which is connected to the asynchronous bridge, is used to configure the target register according to the register configuration request signal under the target clock domain. The register configuration circuit can not only solve the metastable problem existing in the register configuration circuit, but also reduce the structural complexity and area overhead of the register configuration circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a register configuration circuit and an integrated circuit chip. Background Art

[0002] There are usually many functional modules in a large integrated circuit chip, and these functional modules often include multiple registers. In order for these functional modules to work properly, it is usually necessary to configure appropriate values ​​for these registers. Since these functional modules may be in different clock domains, the system host needs to consider the cross-clock problem when configuring the registers of these functional modules. In the prior art, the following two circuit structures are often used to configure registers.

[0003] See also Figure 1 , Figure 1 This is a structural diagram of a configuration circuit of an existing register. Figure 1 In the circuit structure shown, the bus protocol processing circuit is directly used to configure and process the registers of different functional modules, and the configured register signals are directly sent to the various functional modules of the integrated circuit chip as synchronization signals. Since the circuit does not have a signal processing architecture across clock domains, there is a risk of metastable state in the configuration circuit during use. In order to avoid this risk, the application scenarios of the registers can only be restricted, which will greatly reduce the user experience. In addition, when the entire integrated circuit chip is checked across clock domains, the test tool may report a large number of alarm messages. In this case, designers are required to identify and process these alarm messages one by one, which will waste a lot of time and energy of designers.

[0004] See also Figure 2 , Figure 2 This is a structural diagram of another configuration circuit for the existing register. Figure 2 In the configuration circuit shown, the bus protocol processing circuit is first used to configure the register, and the single-bit cross-clock domain processing circuit or the multi-bit cross-clock domain processing circuit is used to perform cross-clock domain processing on the configured register, and finally the processed register signal is sent to each functional module of the integrated circuit chip. However, the process of processing each clock signal by this configuration circuit is very complicated. Not only the different processing methods of single-bit signals and multi-bit signals need to be considered, but also the speed of the source clock signal and the target clock signal need to be considered. In particular, when multi-bit signals are synchronously processed, a FIFO (First Input First Output) memory is required, which results in a large area overhead of the register configuration circuit.

[0005] In summary, how to solve the metastable state of the register configuration circuit while reducing the complexity and area overhead of the register configuration circuit is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide a register configuration circuit and an integrated circuit chip, so as to solve the metastable problem of the register configuration circuit and reduce the structural complexity and area overhead of the register configuration circuit. The specific scheme is as follows:

[0007] A register configuration circuit, comprising:

[0008] A clock switching module, used for outputting a target clock signal consistent with the clock signal of the target functional module according to a target control signal when the register of the target functional module in the target integrated circuit chip needs to be configured;

[0009] an asynchronous bridge, connected to the clock switching module, for performing cross-clock domain processing on a register configuration request signal in a source clock domain sent by a target host, so as to convert the register configuration request signal in the source clock domain into a register configuration request signal in a target clock domain;

[0010] The protocol processing module is connected to the asynchronous bridge and is used to configure the target register according to the register configuration request signal under the target clock domain.

[0011] Preferably, the protocol processing module is also used to configure the target register based on the bus protocol requirements and the register configuration request signal under the target clock domain, and the bus protocol is specifically an APB bus protocol or an AHB bus protocol or a user-defined bus protocol.

[0012] Preferably, the clock switching module is specifically a signal selector.

[0013] Preferably, the clock switching module is specifically a clock switching circuit constructed by logic gate circuits.

[0014] Preferably, the number of input ports of the clock switching module is greater than or equal to the number of different clock signals provided to all functional modules in the target integrated circuit chip.

[0015] Preferably, the clock switching module comprises: a first selector, a second selector, a third selector, a D flip-flop and a state control module having an idle state and a working state, and the state control module jumps from the idle state to the working state when detecting that the clock switching request signal is in a valid state;

[0016] Wherein, the output end of the first selector is connected to the second input end of the second selector, the selection port of the second selector is respectively connected to the output end of the state control module and the selection port of the third selector, the clock signal port of the state control module is connected to the clock signal port of the D flip-flop, and the output end of the third selector is connected to the D port of the D flip-flop;

[0017] Correspondingly, the enable port of the first selector is used to receive a clock selection signal, the input end of the first selector is used to receive a clock signal to be selected, the first input end of the second selector is used to receive a high-level signal, the first input end and the second input end of the third selector are used to receive a low-level signal and a high-level signal respectively, the output end of the D flip-flop is used to output a clock valid indication signal, and the output end of the second selector is used to output the target clock signal.

[0018] Preferably, the target integrated circuit chip is specifically a SOC chip.

[0019] Correspondingly, the present invention also discloses an integrated circuit chip, including a register configuration circuit as disclosed above.

[0020] In the register configuration circuit provided by the present invention, an asynchronous bridge is provided for converting the register configuration request signal in the source clock domain sent by the target host into the register configuration request signal in the target clock domain. Therefore, the metastable problem existing in the register configuration circuit can be solved by such a setting. In addition, since a clock switching circuit is also provided in the register configuration circuit, the asynchronous bridge can be multiplexed, thereby effectively reducing the structural complexity and area overhead of the register configuration circuit. Correspondingly, an integrated circuit chip provided by the present invention also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0022] Figure 1 A structural diagram of a configuration circuit for an existing register;

[0023] Figure 2 A structural diagram of another configuration circuit for an existing register;

[0024] Figure 3 A structural diagram of a register configuration circuit provided by an embodiment of the present invention;

[0025] Figure 4 It is a structural diagram of a clock switching module in the prior art;

[0026] Figure 5 for Figure 4 The timing diagram of the clock switching module shown;

[0027] Figure 6 is a structural diagram of another clock switching module in the prior art;

[0028] Figure 7 A structural diagram of a clock switching module provided by an embodiment of the present invention;

[0029] Figure 8 for Figure 7 The timing diagram of the clock switching module is shown. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] See also Figure 3 , Figure 3 A structural diagram of a register configuration circuit provided by an embodiment of the present invention, the configuration circuit comprising:

[0032] A clock switching module, used for outputting a target clock signal consistent with the clock signal of the target functional module according to a target control signal when the register of the target functional module in the target integrated circuit chip needs to be configured;

[0033] an asynchronous bridge, connected to the clock switching module, for performing cross-clock domain processing on a register configuration request signal in a source clock domain sent by a target host, so as to convert the register configuration request signal in the source clock domain into a register configuration request signal in a target clock domain;

[0034] The protocol processing module is connected to the asynchronous bridge and is used to configure the target register according to the register configuration request signal under the target clock domain.

[0035] In this embodiment, a register configuration circuit is provided. By configuring the register through the configuration circuit, not only the metastable problem existing in the register configuration circuit can be solved, but also the structural complexity and area overhead of the register configuration circuit can be reduced.

[0036] Specifically, a clock switching module, an asynchronous bridge and a protocol processing module are provided in the configuration circuit of the register. When the system is powered on, if the register of the target functional module in the target integrated circuit chip is to be configured, the clock switching module will output a target clock signal consistent with the clock signal of the target functional module according to the target control signal and send it to the asynchronous bridge module. The target functional module refers to any functional module in the target integrated circuit chip.

[0037] When the asynchronous bridge receives the register configuration request signal in the source clock domain sent by the target host and the target clock signal output by the clock switching module, the asynchronous bridge will perform cross-clock domain processing on the register configuration request signal in the source clock domain sent by the target host and convert it into a register configuration request signal in the target clock domain; after the asynchronous bridge outputs the register configuration request signal required by the target functional module, the protocol processing module configures the target register accordingly according to the register configuration request signal in the target clock domain. The register configuration request signal is usually a set of signals that conform to a certain bus protocol, including the register address to be configured and the corresponding register configuration value.

[0038] It can be understood that in the register configuration circuit provided in this embodiment, since an asynchronous bridge is provided for converting the register configuration request signal in the source clock domain sent by the target host into the register configuration request signal in the target clock domain, the metastable problem existing in the register configuration circuit can be solved by such a setting method. Secondly, the asynchronous bridge can be multiplexed by the clock switching circuit, so compared with the register configuration circuit in the prior art, the circuit setting method provided by this embodiment can effectively reduce the structural complexity and area overhead of the register configuration circuit.

[0039] In order to enable those skilled in the art to more clearly understand the implementation principle of this embodiment, a specific example is used here to explain in detail. Assuming that the register configuration of the functional module 0 in the target integrated circuit chip is required, the clock switching module will output the clock signal a which is the same as the clock signal of the functional module 0 under the action of the target control signal. At this time, the asynchronous bridge will perform cross-clock domain processing on the register configuration request signal under the source clock domain sent by the target host, and convert the register configuration request signal under the source clock domain sent by the target host into the register configuration request signal under the clock domain of the clock signal a; finally, the protocol processing module will configure the register according to the register configuration request signal under the clock domain of the clock signal a, so that the configured register can be directly provided to the functional module 0 for use, and there will be no metastable problem.

[0040] If it is necessary to configure the register of the functional module X in the target integrated circuit chip, the clock switching module will output the clock signal b which is the same as the clock signal of the functional module X under the action of the target control signal. At this time, the asynchronous bridge will process the register configuration request signal under the source clock domain sent by the target host across clock domains, and convert the register configuration request signal under the source clock domain sent by the target host into the register configuration request signal under the clock domain of the clock signal b; finally, the protocol processing module will configure the register according to the register configuration request signal under the clock domain of the clock signal b, so that the configured register can be directly provided to the functional module X for use.

[0041] In the register configuration circuit provided in this embodiment, an asynchronous bridge is provided for converting the register configuration request signal in the source clock domain sent by the target host into the register configuration request signal in the target clock domain. Therefore, the metastable problem existing in the register configuration circuit can be solved by such a setting. In addition, since a clock switching circuit is also provided in the register configuration circuit, the asynchronous bridge can be multiplexed, thereby effectively reducing the structural complexity and area overhead of the register configuration circuit.

[0042] Based on the above embodiment, the present embodiment further illustrates the technical solution. In a specific embodiment, the protocol processing module is further used to configure the target register according to the register configuration request signal under the target clock domain based on the bus protocol requirements. The bus protocol is specifically an APB bus protocol or an AHB bus protocol or a user-defined bus protocol or other bus protocols suitable for register configuration. Usually, the bus protocol used remains unchanged before and after the cross-clock domain processing.

[0043] Specifically, when the protocol processing module configures the target register, it needs to transmit data according to the requirements of the bus protocol to realize the configuration of the register. Specifically, the APB (Advance Peripheral Bus) bus protocol can be used to transmit the register configuration request data, because the APB protocol is often used on peripheral devices with low bandwidth and low speed requirements.

[0044] Alternatively, in actual applications, the AHB (Advanced High Performance Bus) bus protocol can also be used to transmit data, because the AHB protocol is mainly designed for high-efficiency, high-bandwidth and fast system modules. It can connect microprocessors, on-chip or off-chip memory modules, and high-efficiency modules such as DMA (Direct Memory Access).

[0045] Alternatively, in actual applications, a user-defined bus protocol or other bus protocols suitable for register configuration may be used to transmit the register configuration request signal, as long as the requirements of the actual application can be achieved, which will not be described in detail here.

[0046] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the clock switching module is specifically a signal selector.

[0047] It is understandable that, because the signal selector can not only achieve the purpose of selecting and outputting the clock signal, but also occupies a small amount of space, in practical applications, the clock switching module can be set as the signal selector. Obviously, this setting method can further reduce the space occupied by the register configuration circuit.

[0048] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the clock switching module is specifically a clock switching circuit constructed by logic gate circuits.

[0049] In practical applications, logic gate circuits can also be used to build a clock switching module. Since logic gate circuits are inexpensive, when logic gate circuits are used to build a clock switching module, the capital cost of the register configuration circuit can be further reduced.

[0050] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the number of input ports of the clock switching module is greater than or equal to the number of different clock signals provided to all functional modules in the target integrated circuit chip.

[0051] In this embodiment, when setting the clock switching module, the number of input ports of the clock switching module is set to be greater than or equal to the number of different clock signals provided to all functional modules in the target integrated circuit chip. It can be imagined that, through such a setting, each input port of the clock switching module can correspond to a class of functional modules with the same clock signal in the target integrated circuit. Under this setting, the clock signal to be selected input to the input port of the clock switching module can be directly selected according to the target control signal.

[0052] In a specific embodiment, the target control signal may include n candidate clock signals, a clock selection signal, and a clock switching request signal, where n is greater than or equal to 2. The clock switching module selects a clock signal consistent with the target functional module clock signal from the n candidate clock signals according to the selection signal and outputs it as the target clock signal.

[0053] Obviously, the technical solution provided by this embodiment can relatively improve the convenience of people in using the register to configure the circuit.

[0054] See also Figure 4 , Figure 4 A clock switching module in the prior art is shown in FIG. Figure 4 The clock switching module shown is provided with a 2-to-1 selector. The advantages of this circuit are simple circuit structure and small footprint. The disadvantage is that this circuit may generate glitches when performing clock switching. For details, please refer to Figure 5 , Figure 5 for Figure 4 The timing diagram of the clock switching module is shown in Figure 1. Since glitches can bring many unexpected signal output effects to users during actual operation, it is usually necessary to Figure 4 The clock switching module shown is modified.

[0055] See also Figure 6 , Figure 6 FIG. 1 is a structural diagram of another clock switching module in the prior art. Figure 6In the clock switching module shown, in order to reduce the burrs generated in the output signal, two triggers DFF1 and DFF2 are added. These two triggers are triggered by the falling edges of CLK1 and CLK2 respectively. Because DFF1 and DFF2 need to sample the SELECT signal, and the SELECT signal is an asynchronous signal for CLK1 and CLK2. At this time, in order to avoid the system from generating metastable phenomena, it is usually necessary to synchronize the SELECT signal with two-stage triggers, so triggers DFF3, DFF4, DFF5 and DFF6 are added to the circuit structure.

[0056] From the above, we can see that Figure 6 In the clock switching module shown, in order to avoid the occurrence of burrs, three triggers need to be added to each clock processing path. Sometimes, in order to achieve better signal output effects, clock gating circuits or more triggers may be added to the circuit structure. Obviously, although this setting method can avoid the burrs generated by the clock switching module, it will also greatly increase the occupied area required by the clock switching module.

[0057] In order to avoid the influence of burrs and reduce the circuit area, this embodiment provides a new clock switching module. Figure 7 , Figure 7 A structural diagram of a clock switching module provided by an embodiment of the present invention. The clock switching module includes: a first selector (first MUX), a second selector (second MUX), a third selector (third MUX), a D flip-flop, and a state control module with an idle state and a working state, and when the state control module detects that the clock switching request signal (REQ) is in a valid state, it will jump from the idle state to the working state;

[0058] The output end of the first selector is connected to the second input end of the second selector, the strobe port of the second selector is connected to the output end of the state control module and the strobe port of the third selector respectively, the CLK of the state control module is connected to the CLK of the D flip-flop, and the output end of the third selector is connected to the D port of the D flip-flop;

[0059] Correspondingly, the enable port of the first selector is used to receive a clock selection signal (SELECT signal), the input end of the first selector is used to receive a selected clock signal (CLK1, CLK2), the first input end of the second selector is used to receive a 1-bit high-level signal, the first input end and the second input end of the third selector are used to receive a 1-bit low-level signal and a 1-bit high-level signal respectively, the output end of the D flip-flop is used to output a clock valid indication signal (CLKOUT_VLD), and the output end of the second selector is used to output a target clock signal (CLKOUT).

[0060] exist Figure 7 In the clock switching module shown, the state control module has two states, an idle state and a working state. When the state control module detects that the clock switching request signal is in an invalid state, the state control module will be in an idle state, and when the state control module detects that REQ is in a valid state, the state control module will be in a working state. In addition, because the state control module provided in this embodiment only involves two states, an idle state and a working state, in actual applications, the state control module can be constructed by several 2-to-1 selectors and a trigger. Since this operation is well known to those skilled in the art, it will not be described in detail here.

[0061] See also Figure 8 , Figure 8 for Figure 7 The timing diagram of the clock switching module is shown in FIG. 1 . When the state control module detects that the REQ signal is in an invalid state, the state control module is in an idle state. At this time, the CLKOUT output is fixed to 1. For the subsequent modules, this can reduce power consumption. When the state control module detects that the REQ signal is in a valid state, the state control module enters the working state. At this time, the first selector selects one clock signal from multiple clock signals to be selected and outputs it from CLKOUT through the SELECT signal. At this time, the CLKOUT signal may still have glitches. In order to avoid the influence of glitches on the subsequent circuit modules, the influence of glitches on the subsequent circuit modules can be avoided through the CLKOUT_VLD output by the D flip-flop.

[0062] Specifically, when the state control module is in the working state, the CLKOUT_VLD output by the D flip-flop will not jump to a valid signal immediately, but will become a valid signal after a delay of one system clock, and this delayed clock cycle contains a glitch signal. Figure 8 It can be seen from the timing diagram shown that when the REQ signal and the CLKOUT_VLD signal are both valid, the CLKOUT signal output by the second selector is a stable clock signal.

[0063] Therefore, in actual operation, the adverse effects of clock glitches on the entire system can be avoided by instructing the system host to initiate a register configuration request signal when both the REQ signal and the CLKOUT_VLD signal are in a valid state. Figure 6 As for the clock switching module shown, the clock switching module provided by the embodiment of the present invention not only has a simple structure, but also does not need to occupy too much space.

[0064] Based on the technical content disclosed in the above embodiments, this embodiment describes in detail the specific process of register configuration of the target functional module in the target integrated circuit chip. Figure 3 The register configuration circuit shown is the overall framework and will Figure 3 The clock switching module in the Figure 7 The structural form shown is specifically described.

[0065] Assuming that in the actual operation process, it is necessary to configure the register of the functional module 0 in the target integrated circuit chip, the target host will initiate the SELECT signal and the REQ signal, and the clock switching module will output the same clock signal a as the functional module 0 to the asynchronous bridge module; when the CLKOUT_VLD output by the D flip-flop in the clock switching module is in a valid state, the target host will initiate a register configuration request signal to avoid the adverse effects of the clock switching module output glitches on the entire system. At this time, the asynchronous bridge will perform cross-clock domain processing on the register configuration request signal under the source clock domain sent by the target host.

[0066] When the asynchronous bridge converts the register configuration request signal in the source clock domain sent by the target host into the register configuration request signal in the clock domain of clock signal a, the protocol processing module configures the target register according to the register configuration request signal in the target clock domain.

[0067] If it is necessary to configure the registers of other functional modules in the target integrated chip, it is necessary to re-initiate the SELECT signal and REQ signal in the clock switching module after canceling the REQ signal for at least one clock cycle, and repeat the above steps to configure the registers of other functional modules in the target integrated chip. No further details are given here.

[0068] Obviously, in the configuration circuit, since an asynchronous bridge is provided for converting the register configuration request signal in the source clock domain sent by the target host into the register configuration request signal in the target clock domain, the metastable problem existing in the register configuration circuit can be solved by such a setting. On the other hand, since a clock switching circuit is also provided in the register configuration circuit, the asynchronous bridge can be reused, thereby effectively reducing the structural complexity and area overhead of the register configuration circuit. Moreover, the clock switching module described in this embodiment not only has a simple structure and a small area overhead, but also can avoid the adverse effects of glitches on the entire system.

[0069] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the target integrated circuit chip is specifically a SOC chip.

[0070] In practical applications, the target integrated circuit chip can be set as a SOC (System on a Chip) chip, because the SOC chip not only has a shorter development cycle, but also can effectively reduce the system development cost, so the SOC chip has been widely used in actual production. Therefore, when the target integrated circuit chip is set as a SOC chip, the universality of people using the register to configure the circuit can be improved.

[0071] Correspondingly, an embodiment of the present invention further discloses an integrated circuit chip, including a configuration circuit of a register as disclosed above.

[0072] An integrated circuit chip provided by an embodiment of the present invention has the beneficial effects of the aforementioned register configuration circuit.

[0073] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0074] The above is a detailed introduction to a register configuration circuit and an integrated circuit chip provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A register configuration circuit, characterized in that: include: A clock switching module, used for outputting a target clock signal consistent with the clock signal of the target functional module according to a target control signal when the register of the target functional module in the target integrated circuit chip needs to be configured; an asynchronous bridge, connected to the clock switching module, for performing cross-clock domain processing on a register configuration request signal in a source clock domain sent by a target host, so as to convert the register configuration request signal in the source clock domain into a register configuration request signal in a target clock domain; A protocol processing module, connected to the asynchronous bridge, configured to configure the target register according to the register configuration request signal under the target clock domain; The clock switching module includes: a first selector, a second selector, a third selector, a D flip-flop, and a state control module having an idle state and a working state, and the state control module jumps from the idle state to the working state when detecting that the clock switching request signal is in a valid state; Wherein, the output end of the first selector is connected to the second input end of the second selector, the selection port of the second selector is respectively connected to the output end of the state control module and the selection port of the third selector, the clock signal port of the state control module is connected to the clock signal port of the D flip-flop, and the output end of the third selector is connected to the D port of the D flip-flop; Correspondingly, the enable port of the first selector is used to receive a clock selection signal, the input end of the first selector is used to receive a clock signal to be selected, the first input end of the second selector is used to receive a high-level signal, the first input end and the second input end of the third selector are used to receive a low-level signal and a high-level signal respectively, the output end of the D flip-flop is used to output a clock valid indication signal, and the output end of the second selector is used to output the target clock signal.

2. The configuration circuit according to claim 1, characterized in that: The protocol processing module is also used to configure the target register according to the register configuration request signal under the target clock domain based on the bus protocol requirements. The bus protocol is specifically the APB bus protocol or the AHB bus protocol or a user-defined bus protocol.

3. The configuration circuit according to claim 1, characterized in that: The clock switching module is specifically a signal selector.

4. The configuration circuit according to claim 1, characterized in that: The clock switching module is specifically a clock switching circuit constructed by logic gate circuits.

5. The configuration circuit according to claim 1, characterized in that: The number of input ports of the clock switching module is greater than or equal to the number of different clock signals provided to all functional modules in the target integrated circuit chip.

6. The configuration circuit according to any one of claims 1 to 5, characterized in that: The target integrated circuit chip is specifically a SOC chip.

7. An integrated circuit chip, characterized in that: A configuration circuit comprising a register as claimed in any one of claims 1 to 6.

Images