Hold-up capacitor health measurement with current leakage detection

Abstract

The present invention discloses a circuit for measuring the leakage current of one or more capacitors coupled to a power line that supplies power to a device such as a storage device. In one embodiment, the circuit includes first and second resistors located between the power line and corresponding first and second switches connected to ground. A controller can charge the voltage line to a first voltage. The controller then discharges the first voltage to a second voltage via the first resistor during a first identification time. After recharging the voltage line, the controller then discharges the first voltage to the second voltage via at least the second resistor during a second identification time. The controller uses the first identification time and the second identification time to determine a parasitic resistance and then determines the leakage current from the parasitic resistance. Eliminating the leakage current factor from subsequent measurements can greatly improve test accuracy and avoid false positives during testing that would otherwise require the removal of a driver or other properly functioning system.

Description

Background Art

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 092155, filed on October 15, 2020, entitled “Hold-Up Capacitance Health Measurement With Current Leakage Detection,” the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates generally to electronic devices and, more particularly, to energy leakage detection in holding capacitors. Background Art

[0005] Capacitors are often connected to voltage sources or supply nodes to protect the integrity of data exchanged through circuits that receive power from the supply node in the event of a power failure. An example of such a circuit includes non-volatile memory (NVM), such as solid-state disk drives. After receiving multiple write requests from a host device, but before all write operations are completed, the drive may experience a power failure. In this case, a hold-up capacitor can help maintain sufficient energy at the supply node just long enough to allow the drive to complete all pending write operations before the device fails.

[0006] These hold-up capacitors can undergo periodic "health" testing to ensure they can maintain the necessary hold-up energy for a specified duration during a power-off event. The health test can use firmware to measure the leakage current flowing through the capacitors; if the leakage current is exceeded, performance is deemed insufficient, resulting in a "failed" drive. For example, if the magnitude of the leakage current is sufficiently high relative to the typical operating current flowing through a standard load resistor of the driver, the leakage current in these cases can be considered insufficient.

[0007] However, in many cases, the same leakage current that caused the test to fail can still cause the holdup capacitor to perform correctly under the same threshold conditions of an actual power failure, meaning that the test in these cases incorrectly predicted a failure. These "false positives" occur because the magnitude of the leakage current is small compared to the large current required to maintain drive energy. In other words, these tests often result in failures, even when the same holdup capacitor would have functioned perfectly well during the power leakage event. In these cases, reconfiguring the driver or removing the perfectly good driver from service is expensive and unnecessary. Summary of the Invention

[0008] This document discloses an aspect of a circuit. The circuit includes a capacitor located between a voltage line and ground and having a parasitic resistance. The circuit also includes a first resistor and a second resistor located between the voltage line and respective first and second switches connected to ground. The circuit also includes a controller. The controller is configured to charge the voltage line to a first voltage. Thereafter, the controller is configured to discharge the first voltage to a second voltage via the first resistor during a first identification time. When the voltage line is recharged to the first voltage, the controller is then configured to discharge the first voltage to a second voltage via at least the second resistor during a second identification time. The controller is configured to use the first and second identification times to determine the parasitic resistance.

[0009] Another aspect of a circuit is disclosed herein. The circuit includes a capacitor located between a voltage line and ground and having a parasitic resistance. The circuit also includes a first resistor located between the voltage line and a first switch connected to ground. The circuit also includes a second resistor located between the first switch and a second switch connected to ground. The circuit also includes a controller. The controller is coupled to the voltage line and configured to charge the voltage line to a first voltage. The controller is further configured to discharge the first voltage to a second voltage via the first resistor during a first identification time. After recharging the voltage line to the first voltage, the controller is configured to discharge the first voltage to a second voltage via the first resistor and the second resistor during a second identification time. The controller is then configured to use the first identification time and the second identification time to determine the parasitic resistance.

[0010] Another aspect of a circuit is disclosed herein. The circuit includes a circuit located between a voltage line and ground and having a parasitic current sink (pi s The circuit also includes a first current sink and a second current sink (i s The controller is configured to charge the voltage line to a first voltage. The controller is then configured to charge the voltage line to a first voltage during a first identification time via a first i s After recharging the voltage line to the first voltage, the controller is configured to, during a second identification time, s The first voltage is discharged to the second voltage. The circuit is configured to use the first identification time and the second identification time to determine the current flowing through the pi s of current.

[0011] It should be understood that other aspects of the storage device and method will be apparent to those skilled in the art from the following detailed description, in which various aspects of the device and method are shown and described in an illustrative manner. As will be appreciated, these aspects can be implemented in other and different forms, and several details thereof can be modified in various other respects. Therefore, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various aspects of the present invention will now be presented in detail by way of example and not limitation with reference to the accompanying drawings, in which:

[0013] Figure 1A is a block diagram illustrating an exemplary embodiment of a holding capacitor between a VDD supply node and ground, and a plurality of (solid state drive) SSD drivers between VDD and ground.

[0014] Figure 1B Is used for testing Figure 1B A block diagram of the circuit of the holding capacitor in the circuit.

[0015] Figure 2 This is a circuit diagram for a capacitor test circuit that uses a switch to measure the different discharge times through two parallel resistors to determine leakage current.

[0016] Figure 3 An alternative circuit configuration for performing a holding capacitor test using the discharge time of two series resistors and a resistor to ground.

[0017] Figure 4 is a circuit diagram illustrating charging a holding capacitor to a first voltage using a switch.

[0018] Figure 5 is a circuit diagram showing a method of discharging a holding capacitor through a first resistor and a bleed resistor using a switch.

[0019] Figure 6 is a circuit diagram showing a method of discharging a holding capacitor through a second resistor and a bleed resistor using a switch.

[0020] Figure 7 is a circuit diagram showing a method of discharging a holding capacitor through first and second resistors connected in parallel and a bleed resistor using a switch.

[0021] Figure 8 is a circuit diagram showing the use of a switch to discharge a holding capacitor through two series resistors and a bleed resistor.

[0022] Figure 9 It shows the use of Figure 8A circuit diagram of a switch discharging the holding capacitor through a first resistor and a leakage resistor.

[0023] Figure 10 is a circuit diagram showing the discharge of a holding capacitor through a bleed resistor.

[0024] Figure 11 is a circuit diagram showing a circuit for discharging a holding capacitor through a load resistor and a bleed resistor using a switch.

[0025] Figure 12 is a circuit diagram showing a circuit for testing a holding capacitor using a pair of parallel and series current sinks, each with a switch. DETAILED DESCRIPTION

[0026] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various exemplary embodiments of the present invention and are not intended to represent the only embodiments in which the present invention can be practiced. The specific embodiments include specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring the concepts of the invention. Acronyms and other descriptive terms may be used only for convenience and clarity and are not intended to limit the scope of the present invention.

[0027] The words "exemplary" or "example" are used herein to mean serving as an example, instance, or illustration. Any exemplary embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other exemplary embodiments. Likewise, the term "exemplary embodiment" of an apparatus, method, or article does not require that all exemplary embodiments of the invention include the described component, structure, feature, function, process, advantage, benefit, or mode of operation.

[0028] The principles of the present disclosure can be implemented by different types of controllers that can be coupled to the test circuits described herein. These controllers and their components can be implemented using electronic hardware, computer software, or any combination thereof.

[0029] For example, the elements, components or any combination thereof of a controller can be implemented using one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SoCs), baseband processors, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gating logic, discrete hardware circuits and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors can be a part of a workstation or server computer configured to perform routines described herein. One or more processors can execute software and firmware. Software and firmware should be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., whether referred to as software, firmware, middleware, object code, source code or other.

[0030] Therefore, in one or more exemplary embodiments, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on a computer-readable medium or encoded as one or more instructions or codes on a computer-readable medium.

[0031] The present disclosure relates to capacitor-based circuits for protecting data in devices during power failures. For the purposes of this disclosure, unless otherwise specified, the term capacitor shall include within its scope one or more capacitors. Thus, for example, a capacitor, as referred to herein and generally (but not necessarily) designated as "C," may describe any quantity, including a single capacitor, several capacitors, a bank of capacitors, and the like. Where a capacitor is positioned between two nodes according to this definition, net capacitance is understood to be conventionally used and known by practitioners in the art, e.g., it can be calculated by one skilled in the art in parallel or in series, without providing additional configuration information herein, which may include multiple elements positioned between the two nodes. In one set of embodiments, the capacitor may be positioned between a power supply node (e.g., 5 volts, 28 volts, etc., depending on the nature of the circuit and its power requirements) and ground. However, in other embodiments, the power supply may be connected to a voltage node other than the power supply node or the ground node. For the purposes of this disclosure, a circuit or circuits may also be coupled (directly or indirectly) to a power supply, e.g., for performing data transactions. While the circuits discussed need not be of a specific type, in one embodiment, an enterprise solid-state power supply is used. The capacitance value of the capacitor (or capacitor bank) is selected based on the requirements of the attached circuit and the value of the supply voltage.

[0032] For example, a circuit may be in the process of exchanging data. After the circuit has begun exchanging data, but before the change is complete, the power node may experience a sudden voltage glitch or a complete power failure. In these situations, it is desirable to complete each of the data transactions initiated before the circuit lost power. For example, in one embodiment, the circuit may be one or more enterprise-class solid-state storage drives used to back up data. During normal operation, one of the drives may receive a write request from a host device. After acknowledging the request, but before the actual data is written, suppose a sudden power loss occurs, causing power to no longer be provided to the power node. To this end, a capacitor is coupled between the power supply and ground. The capacitor is configured to slow the energy discharge at the power node, allowing the drive sufficient time to complete any unfinished writes before the node loses a threshold amount of power that would render the drive inoperable. Thereafter, when the write is complete and the data integrity is maintained, the device can be powered off until power is restored.

[0033] In this example, if the capacitor is absent or its capacitance (or the net capacitance of more than one capacitor) is of insufficient value, the data will be lost. Thus, if the performance of the capacitor degrades over time, eventually it will no longer effectively maintain the energy of the power node at a sufficient amount to enable the write to complete.

[0034] To this end, periodic "health" tests of capacitors can be performed over time to ensure they are functioning correctly. In the example of a storage drive, if the capacitors pass the periodic health tests, the drive will continue to ensure correct writes, even in the event of a power outage. In contrast, a test failure would likely mean the drive can no longer guarantee write completion in the event of a power failure. At best, the data on the drive could be rendered "read-only."

[0035] The premise of this type of health test is that by partially discharging a capacitor (capacitor bank) through a known resistance, the time to reach a set voltage can be measured. The power supply node can then be recharged and the capacitor can be partially charged again, but this time under a different load, for reasons that will become apparent below. Therefore, in one embodiment, a firmware routine can initiate a health test by initiating a discharge and monitoring the time it takes for the capacitor to decay to a specified voltage. This time can typically be set to be greater than some specified threshold. Otherwise, in the case of a storage device, the host write is terminated and an error is reported. Generally speaking, the discharge technique should ensure, through relevant calculations, that the capacitor can maintain some required energy threshold for a specified time to ensure data integrity in the event of an energy interruption.

[0036] One potential issue with this technique is that capacitor leakage current varies with temperature, component age, component population, and capacitor type. Especially at the wrong edge of a process corner, the parasitic resistance of each capacitor can draw enough current to alter the discharge test results by significantly increasing the discharge rate. The discharge time is thus shortened, and the available holding energy in this situation can be significantly underestimated. This underestimation can lead to false test failures or false positives, meaning that in some cases the driver is deemed completely inoperable or defective and may be removed from service. Each of these results is suboptimal, to say the least.

[0037] The leakage current discussed above is generally not a problem during the discharge test because, typically, its magnitude is similar to the magnitude of the current consumed by the circuit's set load resistor during normal operation. That is, leakage current is generally not a problem during an input power failure because the magnitude of the leakage current is very small in proportion to the large drive energy required to properly hold the node, and therefore the magnitude of the current required to prematurely discharge the node is large. However, in many cases, the nature of the discharge test is to use minimal energy consumption. This is because using minimal energy consumption means that the circuits served by the capacitor bank (e.g., drivers) can continue to be available and operational even during the health test. However, because the inventors have determined that capacitor leakage current can be large compared to the measured consumption through the set load resistor during normal operation, but only consumes a small proportion of the total current at the beginning of an actual power outage, the tests currently configured by many manufacturers may not produce accurate results.

[0038] Therefore, in one aspect of the present disclosure, techniques are disclosed to increase the accuracy of retention measurements by detecting and accounting for the leakage resistance of capacitors. Rather than performing a single discharge and taking a measurement, for example, the techniques described herein combine results from multiple capacitor discharge tests to eliminate the common leakage current component generated by the net parasitic resistance of the capacitor bank. In various embodiments, each discharge test is performed with a different bleeder resistor. As shown herein, these multiple measurements can be mathematically combined to cancel out the effects of capacitor leakage that would otherwise be present in each individual test.

[0039] Figure 1A is a block diagram 100 illustrating an exemplary embodiment of a holding capacitor 100 located between a VDD supply node and ground, and a plurality of (solid state drive) SSD drivers located between VDD and ground. Figure 1AThe present invention is intended to provide an overview of an exemplary circuit in which the embodiments of the present invention may be employed. A power supply VDD may power node 110, which in this example serves as a power supply node. A lead resistor R is also shown as a load resistor under normal operation. Four SSD driver circuit boards 102, 104, 106, 108 are shown between VDD and ground (GND). Each of the circuit boards may include multiple storage drives. In actual operation, there may be intervening circuit elements between node 110 and the SSD board. Finally, capacitor C is a capacitor or capacitor bank that serves as a holding device. In the case where capacitor C is actually a plurality of capacitors connected in series, in parallel, or in both configurations, the capacitor bank will have a net parasitic resistance in parallel with the capacitor bank and will cause a net leakage current to flow through the parasitic resistance.

[0040] Figure 1B Is used for testing Figure 1B The holding capacitor C in the circuit 保持 A block diagram of the circuit 110 is shown. In the embodiment shown, R2 is similar to Figure 1A Module 112 is a removable controller that, in this embodiment, can be used for test purposes, such as controlling the voltage at vhold and controlling switches FET1 and FET2, where the switches are assumed here to be MOSFET transistors. Oval area 116 represents an optional load, including an optional transistor and resistor used during the circuit discharge test, as shown in more detail with reference to the following figure. Parasitic resistance R L It is not an actual physical resistor, but rather has a value in parallel with the hold capacitor. Also note that while controller 114 is not shown connected to load resistor R1, this example assumes that controller 114 controls both FETs. After charging the capacitors using the FETs, the controller can selectively discharge them through R1 and individually through R2, and record the discharge time through each capacitor. The leakage resistor is in parallel with the known load resistor, but the leakage resistor is common to both tests. Also note that, referring to FET1, a diode operates between the gate and source, with the gate connected to the drain to enable the controller to set Vhold to any desired voltage, such as VDD.

[0041] Controller 114 and / or module 112 may be an external controller that can be used during operation, in which case it may be removable (e.g., a "hot-swappable" controller, etc.). In other embodiments, controller 114 and / or module 112 may be an integrated part of the circuit structure. In addition, controller 114 may be part of a flash memory controller. In other embodiments, part of the functionality of controller 114 may be incorporated into the device (e.g., as part of one of the circuit boards), and other parts may be attachable and / or removable. In other embodiments, controller 114 may be an external controller coupled to some external device connected to the FET. Controller 114 may also include one or more processors and memory for performing calculations and performing time measurements and other measurements associated with the hold test. Module 112 and / or controller 114 may also have networking capabilities and be controllable from another location. Controller 114 is also capable of determining pass and fail as needed.

[0042] The controller 114 may also be configured to 保持 Therefore, for example, when FET1 and FET2 are turned off and on, respectively, to discharge the capacitive load through R1, the total load resistance of the circuit is Ra=R1||RL (where "a" represents test run a). Similarly, after the capacitor is recharged, and when FET1 and FET2 are turned off and on, respectively, to discharge the capacitive load through R2, the total load resistance of the circuit is Rb=R2||R L .

[0043] Generally speaking, for discharging a capacitor from voltage V1 to voltage V2, the discharge time for two cases can be calculated using the well-known formula:

[0044] T1=(Ra)(C)ln(V1 / V2) and

[0045] T2 = (Rb)(C)ln(V1 / V2).

[0046] Solving for (C)ln(V1 / V2)=T1 / Ra=T2 / Rb, since the quantity (C)ln(V2 / V2) can be held constant.

[0047] Solving for the leakage resistance yield:

[0048] R L =(T1-T2) / ((T2 / R2)-((R1-R2) / R1))

[0049] Therefore, in one embodiment, the calculated leakage resistance (R L ) can be used later to change the discharge time threshold corresponding to the capacitance range. Also note that once R is known L, the calculation of leakage current is very simple.

[0050] The general description above can be extended to various ways to calculate the parasitic resistance of a capacitor bank as well as the leakage current using the identified formulas, after which the discharge time threshold for a given capacitance range can be set in such a way that a capacitor bank that maintains the required energy at the supply node for the necessary time can no longer be determined to cause a "false alarm".

[0051] Figure 2 200 is a circuit diagram for a capacitor test circuit for determining leakage current using a switch to measure the different discharge times through two parallel resistors. This example is similar to Figure 1B An example of a circuit is provided, but since the key nodes and exemplary circuit layouts have already been discussed, the example is performed in a more general manner. For example, transistors are now referred to as switches, because in practice these switches need not be limited to field-effect transistors. Bipolar junction transistors, as well as manual switches and almost any type of IC switch (fast enough to operate at a reasonable rate to pass field testing) may be equally suitable. The switches can be discrete and can also be implemented as discrete components on, for example, a circuit board.

[0052] Throughout this disclosure, resistors are generally referred to using their symbolic values. A general requirement for resistors is that they are well matched. For the purposes of this disclosure, resistors can be originally discrete components, resistors implemented in a chip (e.g., using metal or transistors), and in fact any type of device that can be used as a resistor with sufficiently matched characteristics can be used in conjunction with this disclosure. In addition, the capacitor used for holding can be a discrete device. If implemented in a chip on a smaller scale, the capacitor can be, for example, a suitably configured transistor.

[0053] Now see Figure 2 , the power supply node can be identified as the V_ node. The circuit is modeled with Vin to provide power, with C as a capacitor and RL as a parasitic resistance based on a capacitive load, with two parallel resistors R1 and R2, each in series with switches S2 and S3, respectively. The V_ node is disconnected from Vin by switch S1. Therefore, in normal operation, the circuit in question will be powered by Vin at the V_ node, with S1 closed. There may also be a load resistor, which for the purposes of this example may include R1 or R2; however, it will be understood by those skilled in the art that the load resistor may be present elsewhere in the circuit. For simplicity and to avoid unduly obscuring the concepts of the present disclosure, conventional circuits (e.g., SSD drives) are omitted from this illustration, and only the model for the test device is shown. Figure 2 More details of the test operation of the test circuit in will be described below, where similar figures with specific switch states are shown.

[0054] Figure 3 is an alternative circuit configuration 300 for performing a holding capacitor test using the discharge time of two series resistors and a ground resistor. When the base circuit (omitted for clarity) undergoes normal operation, Figure 3 With Figure 2 Almost the same operating principle. That is, a circuit to exchange data can exist between the VDD node (also identified here as V_node) and ground, and one or both of R1 and R2 can be used to provide similar load resistance as needed. Figure 2 and Figure 3 The key difference between the two is the positioning of resistors R1 and R2 and the state of switches S2 and S3. For example, refer back to Figure 2 , when discharging R1 from the voltage at the V_ node, S2 is closed and S3 remains open, and vice versa when discharging R2 (S3 is closed and S2 remains open).

[0055] As described below, S1 also remains open during discharge. Figure 3 , the two discharge nodes that will be used for testing are: (1) R1 discharging to ground; and (2) the series combination of R1 and R2 discharging to ground. To achieve the former, S2 is open and S3 is closed. In this case, R1 will bypass R2 and discharge directly to ground due to the closed circuit at S3. In contrast, with S3 open and S2 closed, the V_ node or the charged capacitor will see the resistive path as the series combination of R1 and R2 (in addition to the RL parasitic path). Therefore, R1 and R2 can be Figure 3 1 is used for one discharge event, and R1 itself can be used for another discharge event. These tests are discussed in further detail below.

[0056] Figure 4 is a circuit diagram 400 illustrating charging a holding capacitor C to a first voltage V_node using a switch. Figure 4 Configuration and Figure 2 The configuration is the same as that of FIG1 , except for the configuration of the switches and the test states shown. It is assumed that the firmware of the circuit has temporarily suspended certain circuits so that they are not operational during the test, but this is not necessary, for example, in the case of less discharge or to make alternative nodes available for providing backup power. To charge the capacitor, although any voltage can be used, in one embodiment, the upper rail or V1 = VDD is selected for simplicity. It is also assumed that all three switches are open immediately before the test. The firmware can charge C (for example, using Figure 1BThe test is started by closing S1 and opening S2 and S3 to charge the V_ node to a voltage of V1. When S1 is closed, the voltage source Vin causes current to flow through the capacitor / capacitor bank C (and, in some cases, through the typically higher R L value), as shown by arrows 402, 404 and 406.

[0057] Figure 5 The figure shows the use of a switch through the first resistor R1 and the leakage resistor R L Circuit diagram 500 for discharging holding capacitor C. Since the capacitor is Figure 4 has been charged to V1, Figure 5 The first part of the test in is to discharge this voltage V1 through a first resistance value (and RL) and identify the discharge time it takes for C to discharge to a second specified voltage (i.e. V2). Figure 5 In the example of , the V_ node corresponds to the power supply node VDD as usual. Figure 4 In the previous configuration of , the switches are positioned so that S1 is closed and S2 and S3 are open. This enables C to charge to a predetermined value V1 (e.g., VDD). Figure 5 In the , the controller opens S1 and S3 and closes S2. This configuration then shuts off the V_ node from the power supply while providing a current path through R1. The discharge of the current flowing through the parasitic resistance RL is Figure 5 , which are shown by arrows 502, 504, and 506, which represent the path of current through RL. The discharge of current through R1 is shown by arrows 502, 504, 508, and 510, which, in turn, represent the path of current through R1. Discharge continues until the voltage at the V_ node reaches a predetermined voltage, V2. The voltage at the V_ node can be monitored, for example, by controller 114, or by another controller that can record the discharge time (T1), which corresponds to the time from V1 to V2 at the V_ node. Therefore, at this point, the controller has the values ​​of V1, V2, C, R1, R2, and T1.

[0058] The next desired operation of circuit 500 is to recharge the V_ node to a value V1 (ie, the same value used in the previous step) and then discharge V1 through another resistive path to determine a second discharge time T2. To accomplish this, see again Figure 4 , where circuit 400 shows the initial charging of C to voltage V1. Similarly, the capacitor that loses energy due to the first discharge is recharged to V1. For example, the controller may open S2. S3 has been opened in the last discharge step ( Figure 5 ), so that now both S2 and S3 are open. The controller can close S1. Once again, the presence of Vin at V_node causes current to flow through the capacitor, and the controller allows charging to continue until V_node = V1.

[0059] Figure 6 1 is a circuit diagram showing a circuit for discharging a holding capacitor through a second resistor and a leakage resistor using a switch. Figure 4 For example, Figure 6 The V_ node in the circuit is again at value V1. The controller is now ready to perform a second discharge at the V_ node, from voltage V1 to voltage V2, now using resistor R2. The controller can open S1, keep S2 open, and close S3. The current from C discharges partially through RL, but primarily through R2. The controller monitors the voltage at the V_ node and opens S3 once V_ node decreases to exactly V2. The controller identifies discharge time T2 for the discharge through resistor R2.

[0060] At this point, the controller has the discharge times T1 and T2, the resistance values ​​corresponding to the discharges R1 and R2, and the voltage values ​​V1 and V2 determined at the beginning. The controller can now perform the necessary calculations to identify the parasitic resistance RL and the leakage current. Furthermore, the controller can independently verify the discharge times to ensure that the calculations match the measured values.

[0061] The controller can now calculate the discharge time (T1) of the capacitor (C) to the load (R1) from voltage V1 to V2 using equation (i) below, thereby first verifying its discharge time measurement:

[0062]

[0063] The controller can then perform the same calculation using another resistor R2 and the same voltage range and capacitance to determine the second discharge time T2 using the following equation (ii):

[0064]

[0065] Since the natural logarithm of the product of the capacitances and the voltage ratio is the same in both formulas, the first formula can be divided by the second formula to obtain the ratio of the discharge time to the load resistance, or to obtain formula (iii):

[0066]

[0067] Because the capacitor has leakage, the load has an equivalent resistor (R L ). R1 ​​is actually:

[0068]

[0069] And R2 is actually:

[0070]

[0071] So we have:

[0072]

[0073] Through some arithmetic operations, we get formula (iv):

[0074] RL=(R2*((T1 / T2)-1)) / (1-((T1*R2) / (T2*R1))) (iv)

[0075] The discharge times T1 and T2 in the simulation can be applied to equation (iv) to obtain the parasitic resistance or leakage resistance due to capacitor C. Therefore, using the test time of two known resistance loads, the parasitic resistance of capacitor C can be determined. A simple way is to use Ohm's law to determine the leakage current i flowing through the parasitic resistance L Once the leakage current is known, one can consider determining whether the energy threshold at the V_ node is sufficient to maintain data integrity in the event of a power outage.

[0076] For example, the following values ​​are possible.

[0077] C=500uF

[0078] R1 = 8.869K (9.1K (2, 18.2KΩ each, in parallel), in parallel with the 350KΩ in the feedback network)

[0079] R2 = 4.435K (4.55K (4, 18.2KΩ each, in parallel) in parallel with 350K)

[0080] R L = 27.3K (average value of 1mA in 95% discharge range from 28V to 26.6V)

[0081] Based on the above values, a simulation can then be run as described in this disclosure to identify T1 and T2. Once T1 and T2 are obtained, we can use equation (iv) to calculate the leakage resistance. Thus, using the test time for two known resistance loads determined based on the simulation, the leakage resistance can be determined. Ohm's law provides the leakage current i L .

[0082] Figure 7 is a circuit diagram 700 illustrating discharging a holding capacitor through first and second resistors in parallel and a bleed resistor using a switch. Figure 7 Shown Figures 4 to 6 An alternative embodiment of the embodiment described in . Figure 7 C to V1 charging and recharging with Figure 4 In addition, Figure 7 The initial use of R1 as the first resistor discharge path is also the same as Figure 5However, in this embodiment, instead of using R2 as the second resistor, a parallel combination of R1 and R2 is used as the second resistor. Therefore, the capacitor (capacitor bank) is initially charged to a first value V1, such as Figure 4 Then, S1 and S3 are opened and the first discharge occurs through R1, as shown in Figure 5 After the first discharge is completed and the discharge time T1 is measured by the controller, the controller then closes S1 and opens S2 and S3 to recharge the capacitor C back to the value V1. Figure 7 In the example, S1 is opened again, but this time the controller simultaneously closes both S2 and S3. The capacitor is then discharged again, this time through the parallel combination of R1 and R2. That is, the capacitor discharges via arrows 702, 704, 706 in the first branch, 702, 704, 708, 710 in the second branch (R1), and 702, 704, 708, 712, 714 in the third branch (R2). It can be assumed that the measured discharge time T2 to reach the specified voltage V2 is shorter because the net resistance is lower and current can flow through both paths.

[0083] In reference Figure 7 After the controller performs discharge time measurements T1 and T2, the same calculations including equations (i) to (iv) are applied to determine RL, this time using only as the second resistance value. Figure 7 It is demonstrated that numerous variations in resistance values ​​are possible and achieve the same objective without departing from the spirit and scope of the present disclosure.

[0084] Figure 8 FIG. 8 is a circuit diagram 800 showing the use of a switch to discharge a holding capacitor through two series resistors and a bleed resistor. As described above, Figure 8 The measurement in the case of involves using the series combination of R1+R2 as the first resistor (where the controller opens S3 and closes S2), and using R1 as the second resistor (where the controller opens S2 and closes S3). Figure 8 For the purposes of the embodiments in FIG. 1 , it is assumed that capacitor C has been precharged to voltage V_node=V1 in the usual manner, i.e., the controller opens S2 and S3 and closes S1 to charge the capacitor. Next, Figure 8The first discharge of the capacitor is shown. The controller opens S1 and closes S2 (with S3 remaining open), and measures the discharge time for the voltage at the V_ node to drop from V1 to V2. It should be noted that, as in the previous case, the parasitic resistance or leakage resistance RL represents a resistive path from the V_ node to ground, so some current flows through RL during each discharge cycle. That is, as shown by arrows 802, 804, and 806, a portion of the current flows through the parasitic resistance RL of C. The majority of the current flows through arrows 802, 804, 808, and 810, and flows through R1 and R2. Figure 8 The situation is also called light load, where the capacitor discharges through the larger resistance value of R1+R2.

[0085] Figure 9 It shows the use of Figure 8 A circuit diagram 900 is provided for discharging the holding capacitor a second time through a first resistor and a leakage resistor. First, a recharging step is performed, whereby the controller allows Vin (or an equivalent power source) to charge capacitor C (which may be a plurality of capacitors between the V_ node and ground) to V1. Then, as shown in FIG. Figure 9 As shown, the controller opens S2, thereby disconnecting R2 from ground. The discharge current flows through RL as usual via arrows 902, 904, 906, and also through R1 via 902, 904, 908, 910, 912, 914. As before, the controller measures the time it takes for the circuit to discharge from V1 to V2. Figure 9 The implementation is considered to be heavy load. In short, the controller uses the series combination of R1 and R2 as Figure 8 The resistance of T1 is measured and the controller uses R1 as Figure 9 Measure the resistance of T2.

[0086] As mentioned previously, the controller can also calculate the time it takes for a capacitor (C) to discharge from voltage V1 to V2 into the load (R a ) discharge time (T1):

[0087]

[0088] Next, the controller can use different loads (R b ) to obtain:

[0089]

[0090] The controller can use this ratio to obtain:

[0091]

[0092] As in the previous embodiment, the capacitor has leakage, so the load has an equivalent resistor (R L ).

[0093] R a Actually:

[0094]

[0095] R b Actually:

[0096]

[0097] In this case, Ra is 1+R2 and Rb is R1. Therefore, the ratio of the discharge times is:

[0098]

[0099] Similarly, through arithmetic operations, the following expression can be obtained:

[0100] RL=ΔT*(R1 2 *R2+R1*R2 2 ) / (T2*R2 2 -ΔT*R1*R2),

[0101] Where ΔT=T1-T2

[0102] If R1=R2=R, then the formula is simplified to:

[0103] RL=(ΔT*2*R) / (T2-ΔT)

[0104] In summary, using the test times of two known resistive loads identified through simulation, the leakage resistance can be determined, and direct application of Ohm's law allows the controller to obtain the leakage current.

[0105] In another embodiment, the hold test can be performed using only one external load. For example, the leakage of the capacitor can be isolated as the first load, and the external load can be used as the second load. The math becomes simpler, but the test duration will be relatively long because the natural leakage of the capacitor is low, or in other words, the equivalent resistance is very high. Because the longer test time with natural leakage makes it more likely that a power failure will occur during this time (and the capacitor is less than fully charged), this configuration is best used in systems with a limited number of tests or for circuit configurations with potentially less urgent consequences.

[0106] Figure 10 An example of this embodiment is shown in FIG. Figure 10FIG1 is a circuit diagram 1000 showing a method for discharging a holding capacitor through a bleed resistor using a switch. As usual, the supply node V_node is charged to a first voltage V1. Switches S1 and S2 are both open, and the measurement capacitor is connected to the bleed resistor R1. L The time for discharging to the second voltage is as follows: The current discharge path is directly from 1002 across 1004 and the leakage resistance path 1006.

[0107] Figure 11 FIG1 is a circuit diagram 1100 showing the use of switches to discharge a holding capacitor through a load resistor and a bleed resistor. Alternatively, the V_ node is recharged by opening S2 and closing S1. S1 is then opened and S2 is closed, and T2 is measured after the capacitor has discharged to V2. When S2 is closed, in addition to discharging through RL as described above, the discharge of R via paths 1102, 1104, 1110, and 1112, as well as the time for both RL and R to discharge from V1 to V2, can also be measured.

[0108] The controller 112 can calculate the time it takes for the capacitor (C) to discharge from voltage V1 to V2 into the load (R a ) discharge time (T1):

[0109]

[0110] If the controller 112 uses different loads (R b ) to make the same measurement, the result is:

[0111]

[0112] If the controller adopts this ratio, the result is:

[0113]

[0114] Because the capacitor has leakage, the load has an equivalent resistor (R L ). If leakage is taken as the first load, Ra is the only RL, as Figure 10 Moreover, as shown in Figure 11 The circuit shown, R b yes

[0115]

[0116] In this case, Ra is R L And Rb is just R, so the formula simplifies to the following:

[0117]

[0118] The controller may then use the measured value to determine the leakage resistance or parasitic resistance.

[0119] In another aspect of the present disclosure, instead of a resistor as a load, the test may implement a current load or sink. Figure 12 An example of this configuration is shown in . Figure 12 1 is a circuit diagram 1200 showing a circuit for testing a holding capacitor using a pair of current sinks connected in parallel and in series, each with a switch. The current sinks can be physically implemented using any known technology. For example, the current sinks can be discrete integrated circuits or a set of custom designed components. In other configurations, the current sinks can be generated in a chip using CMOS, for example, using an operational amplifier with an output in a feedback loop and one or more current mirrors. The current sinks can also be implemented using bipolar junction transistors. In situations involving high currents, the current sinks will likely be implemented as discrete devices.

[0120] Now see Figure 12 , shows the same input stage with Vin, S1, and supply node V_node. The test circuit 1200 shown has a capacitor C (which can be multiple capacitors as previously described) and, in this embodiment, has two current sinks i1 and i2 implemented in parallel with switches S2 and S3 connected in series with each respective current sink i1, i2. The capacitor can be charged and discharged according to the previous embodiment, i.e., the controller closes S1 and keeps S2 and S3 open to charge C to its V1 value. During the first discharge, S2 is closed (S1 and S3 are open), and the discharge time T1 for V_node to reach V2 is measured. After V_node recharges back to V1, when V2 of I2 is reached, the process is repeated to obtain T2.

[0121] In summary, for a constant current load, when switch S1 is closed and switches S2 and S3 are open, the voltage source Vin charges capacitor C to voltage V1. Normal capacitor leakage is represented by the current sink I L By opening S1 and closing S2, capacitor C is discharged to V2 with I1. The discharge time from V1 to V2 (ΔV) is stored as T1 (ΔT1). By opening S2 and closing S1, the capacitor is recharged to V1. By opening S1 and closing S3, the capacitor is discharged to V2 with I2. The discharge time from V1 to V2 (ΔV) is stored as T2 (ΔT2). It should also be noted that, as previously described, the second load can configure both switches (S1 and S2) to be closed simultaneously.

[0122] The current (I) flowing through a capacitor (C) having a voltage that changes at a rate of ΔV / ΔT is given below.

[0123] I1=C*(ΔV / ΔT1)

[0124] If the measurement is made with a second load in the same voltage range, the result is:

[0125] I2=C*(ΔV / ΔT2)

[0126] If the ratio of the measurement results is used, Δ can be eliminated as follows:

[0127]

[0128] Since the capacitor has leakage, the load has an equivalent load (I L ). For example, I1 is actually:

[0129] I1+IL

[0130] And I2 is actually:

[0131] I2+IL

[0132] Therefore, adopt this change: (I1+I L ) / (I2+I L )=T2 / T1

[0133] As usual, after some arithmetic operations, the result becomes

[0134] (I2*T2-I1*T1) / (T1-T2)

[0135] For example, using the following values, the controller can perform the following calculations and then use the resulting test time to calculate the unknown leakage current.

[0136] For C = 1000uF

[0137] I1=50mA

[0138] I2=100mA

[0139] I L =5mA

[0140] In short, using the test times from two known constant current loads, we can determine the unknown leakage current. Discharging from 28V to 26.6V:

[0141] The simulation shows:

[0142] T1=25.45mS

[0143] T2=13.33mS

[0144] If we substitute these results into the formula, we get

[0145] I L=4.9917mA

[0146] Since the currents are strictly additive, another combination of loads, such as I1 + I2, can be used and its value just replaces the value of I2 above.

[0147] The various aspects of the present disclosure are provided to enable a person of ordinary skill in the art to practice the present invention. Various modifications to the exemplary embodiments presented throughout this disclosure will be apparent to those of ordinary skill in the art, and the concepts disclosed herein may be extended to other magnetic storage devices. Therefore, the claims are not intended to be limited to the various aspects of the present disclosure, but are intended to be given the full scope consistent with the language of the claims. All structural equivalents and functional equivalents of the various components of the exemplary embodiments described throughout this disclosure that are already known or later known to a person of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, regardless of whether this disclosure is explicitly recited in the claims, the content disclosed herein is not intended to be contributed to the general public. No claim element will be interpreted under the provisions of 35 USC § 112, paragraph 6, of the United States, or similar statutes or rules of law in another jurisdiction, unless the phrase "means for..." is used to expressly recite the element, or in the case of a method claim, the phrase "step for..." is used to recite the element.

Claims

1. A circuit, comprising: A capacitor located between a voltage line and ground and having parasitic resistance; a first resistor and a second resistor between the voltage line and respective first and second switches connected to ground; and a controller configured to: charge the voltage line to a first voltage; discharging the first voltage to a second voltage via the first resistor during a first identification time; discharging the first voltage to the second voltage via at least the second resistor during a second identification time; and determining the parasitic resistance using the first identification time and the second identification time. 2 . The circuit of claim 1 , wherein the controller is further configured to determine a leakage current flowing through the capacitor based on the parasitic resistance. 3 . The circuit of claim 2 , wherein the controller is further configured to determine whether the capacitor maintains a specified energy for at least a power-off discharge time determined based on the leakage current. 4 . The circuit of claim 3 , wherein the controller is further configured to provide a pass indication when the capacitor maintains the designated energy for at least the power-off discharge time, and provide a fail indication otherwise.

5. The circuit of claim 1 , wherein the controller is further configured to: performing the discharging via the first resistor when the first switch is closed and the second switch is open; and When the first switch is open and the second switch is closed, the discharging is performed via the second resistor.

6. The circuit of claim 1 , wherein the controller comprises a voltage source configured to: charge the voltage line to the first voltage to enable the discharge via the first resistor; and recharge the voltage line to the first voltage to enable the discharge via the second resistor.

7. The circuit according to claim 6, wherein The voltage source is coupled to the voltage line via a third switch; and The controller is configured to charge the voltage line to the first voltage when the third switch is closed and the first switch and the second switch are open.

8. The circuit of claim 1 , wherein discharging the first voltage to the second voltage via at least the second resistor during a second identification time comprises discharging the first voltage to the second voltage via a parallel combination of the first resistor and the second resistor during the second identification time.

9. A circuit, comprising: A capacitor located between a voltage line and ground and having parasitic resistance; a first resistor between the voltage line and a first switch connected to ground; a second resistor located between the first switch and a second switch connected to ground; and a controller coupled to the voltage line and configured to: charge the voltage line to a first voltage; discharging the first voltage to a second voltage via the first resistor during a first identification time; discharging the first voltage to the second voltage via the first resistor and the second resistor during a second identification time; and determining the parasitic resistance using the first identification time and the second identification time. 10 . The circuit of claim 9 , wherein the controller is further configured to determine a leakage current flowing through the capacitor based on the parasitic resistance.

11. The circuit of claim 9, wherein the controller is further configured to: performing the discharging via the first resistor when the first switch is closed and the second switch is open; and When the first switch is open and the second switch is closed, the discharging is performed via the first resistor and the second resistor.

12. The circuit of claim 9 , wherein the controller comprises a voltage source configured to: (1) charge the voltage line to the first voltage to enable the discharge via the first resistor, and (2) recharge the voltage line to the first voltage to enable the discharge via the first resistor and the second resistor.

13. The circuit of claim 12, wherein The voltage source is coupled to the voltage line via a third switch; and The controller is configured to charge the voltage line to the first voltage when the third switch is closed and the first switch and the second switch are open.

14. The circuit of claim 9, wherein the capacitor comprises a capacitor bank of two or more capacitors organized in one or both of series and parallel between the voltage line and ground, the net parasitic resistance of the capacitor bank comprising the parasitic resistance.

15. The circuit of claim 9, wherein the resistor comprises one or more transistors in a chip or as discrete components.

16. A circuit, comprising: a capacitor located between the voltage line and ground and having a parasitic current sink; a first current sink and a second current sink between the voltage line and respective first and second switches connected to ground; as well as a controller configured to: charge the voltage line to a first voltage; discharging the first voltage to a second voltage via the first current sink during a first identification time; discharging the first voltage to the second voltage via at least the second current sink during a second identification time; and determining a current flowing through the parasitic current sink using the first identification time and the second identification time. The circuit of claim 16 , wherein the controller is coupled to the voltage line via a third switch.

18. The circuit of claim 17, wherein the controller is further configured to: charging and recharging the voltage line to the first voltage when the third switch is closed and the first switch and the second switch are open; discharging the voltage line via the first current sink when the second switch and the third switch are opened and the first switch is closed; as well as When at least the third switch is open and the second switch or one or both of the first switch and the second switch are closed, the voltage line is discharged via at least the second current sink.

19. The circuit of claim 16, wherein the switch comprises a field effect transistor.

20. The circuit of claim 16, wherein the controller is further configured to determine whether a specified amount of energy remains on the voltage line for at least a discharge time determined using the determined current flowing through the parasitic current sink.

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