A verification test method for high-speed serial port SRIO based on HAPS platform

Abstract

The present invention relates to a verification and testing method for a high-speed serial port SRIO based on a HAPS platform, comprising the following steps: HAPS platform configuration of a design prototype of the high-speed serial port SRIO; debugging interaction of the high-speed serial port SRIO; and verification of the modifiable and hardware configurable application scenarios of the high-speed serial port SRIO. The verification and testing method of the present invention adopts a full-chip design verification method of a more flexible iterative SRIO interface function of the HAPS platform, which reduces the cost of chip samples, shortens the time for chip design verification, and enables software development work to be carried out as early as possible; designs, edits, modifies, and verifies the validity of test data based on basic functions and user application scenarios, which can verify the scenarios and boundary conditions of basic functions on the one hand, and has the function of user scenario expansion on the other hand; during debugging interaction, uses a serial port tool to input test content according to prompts, and outputs functional information, functional flow, and register configuration information, test comparison, and test results when testing SRIO at runtime, etc.

Description

Technical Field

[0001] The present invention relates to chip design verification technology, and in particular to a verification and testing method for a high-speed serial port SRIO based on a HAPS platform. Background Art

[0002] With the continuous development of embedded systems, more and more high-performance embedded systems use the open interconnection technology standard RapidIO as the interconnection method between chips and boards. RapidIO is a high-performance, low-pin-count, packet-switching-based interconnection structure. Currently, as the only international standard in the field of embedded system data transmission, RapidIO technology introduces mechanical standard specifications such as VPX as the standard interconnection technology between boards.

[0003] Since the release of version 1.0 in 1999, RapidIO has a history of more than 20 years and has successfully released version 4.0, with an interface throughput of up to 400G. RapidIO's applications involve more and more fields and have been widely used in military, wireless base stations, industrial control, high-performance cloud computing, video surveillance, test and measurement, and other fields.

[0004] SRIO IP based on RapidIO protocol is increasingly incorporated into the design of high-performance chips. In particular, users are very keen to customize SRIO interface chips that meet performance requirements based on their own application scenarios. Currently, many chips such as Tsi721, PowerPC, DSP and Xilinx series products have high-speed serial port SRIO. Domestic research on these chips is more focused on their application scenarios and simulation tests. There is still a lot of room for exploration in chip verification and testing methods and systems for self-developed high-speed serial port SRIO. Summary of the invention

[0005] To this end, the technical problem to be solved by the present invention is to overcome the problem of low chip verification and testing method and system working efficiency of the self-developed high-speed serial port SRIO in the prior art, thereby providing a verification and testing method of high-speed serial port SRIO based on the HAPS platform.

[0006] In order to solve the above technical problems, a verification test method of a high-speed serial port SRIO based on a HAPS platform of the present invention comprises the following steps:

[0007] Step S1: HAPS platform configuration of the design prototype of the high-speed serial port SRIO, including the import of the design prototype of the chip containing the SRIO interface, the interface configuration of different storage media, the configuration of the information exchange serial port, and the configuration of the debugging interface;

[0008] Step S2: debugging interaction of the high-speed serial port SRIO, in which the storage of basic function data frames is completed, the instruction switching of different basic functions is completed, the real-time output of the basic function verification test process is completed, and the comparison output of the verification test results is completed;

[0009] Step S3: Verify that the high-speed serial port SRIO application scenario is modifiable and the hardware is configurable, which includes completing the design and storage of the application scenario data frame, completing the modifiable compilation of the SRIO application scenario function, and completing the different hardware scenario tests of the SRIO interface function.

[0010] In one embodiment of the present invention, the design prototype HAPS platform configuration of the high-speed serial port SRIO in step S1 includes:

[0011] Importing the SRIO interface chip design prototype: First, the HAPS platform configures the project, and then loads the SRIO interface chip design prototype file into the HAPS platform configuration;

[0012] Configuration of different storage media: configure the clock, reset, and voltage according to the I / O pins of the storage medium;

[0013] Serial port configuration: configure the serial port clock, baud rate, and checksum according to the serial port I / O pins;

[0014] Configuration of the JTAG interface: According to the I / O allocation of the JTAG pins, use the compilation and debugging software dedicated to the design prototype to connect to the HAPS platform through the JTAG simulation debugger, and select the connection configuration type to perform online verification testing on the HAPS platform for the software compilation results and the SRIO interface chip prototype.

[0015] In one embodiment of the present invention, the debugging interaction of the high-speed serial port SRIO in step S2 includes:

[0016] Storage of basic function data frames: According to the basic functions of SRIO, design relevant test data, store them in the corresponding storage medium address, and verify their correctness;

[0017] Instruction switching of different basic functions: refer to the functions of RapidIO protocol and SRIO IP, divide the basic functions of SRIO, identify and verify the basic application functions through different instructions during verification test, and implement test switching of each basic function through serial port tools;

[0018] Real-time output of basic function verification test process: The verification test of high-speed serial port SRIO can output the process identification of each basic function and the configuration of the registers involved according to the real-time output when each basic function is running, to assist in judging the validity of the application scenario configuration;

[0019] Comparative output of verification test results: The data during each basic functional scenario verification test is compared with the data generated during the actual test; if the results are consistent, a success message is output, otherwise a failure message is output.

[0020] In one embodiment of the present invention, the high-speed serial port SRIO application scenario modifiable and hardware configurable verification in step S3 includes:

[0021] Design and storage of application scenario data frames: For different application scenarios, data frames that comply with the RapidIO protocol can be designed and stored as data sources for verifying application scenarios.

[0022] Modifiable compilation of SRIO application scenario functions: Chips designed for different application scenarios do not need to implement all SRIO functions. Instead, they can tailor and modify the required SRIO functions according to the application scenarios.

[0023] Different hardware scenario tests of SRIO interface functions: This verification test platform can be used for self-loop testing, and can also be connected to different SRIO interface devices, such as some products in the PowerPC series and DSP series. For different interface forms, such as SFP, SMA, and PCIE, different interface daughter cards are configured according to the interface characteristics of the HAPS platform to match different tests.

[0024] The above technical scheme of the present invention has the following advantages over the prior art: the verification and testing method of the present invention adopts a more flexible full-chip design verification method of iterative SRIO interface functions of the HAPS platform, which reduces the cost of chip samples, shortens the time of chip design verification, and starts software development work as early as possible; the validity of test data is designed, edited, modified and verified according to basic functions and user application scenarios, which can verify the scenarios and boundary conditions of basic functions on the one hand, and has the function of user scenario expansion on the other hand; during debugging interaction, the serial port tool is used to input the test content according to the prompt, and the functional information, functional flow and register configuration information, test comparison and test results of the test SRIO runtime are output; the online compilation and debugging software is adopted, so that the verification of SRIO functions is progressively detailed, and the verification code is also progressively detailed, which can be used as the basis for software development, and the software functions are continuously increased from basic functional scenarios to user scenarios; different external interface circuits can make the system very convenient to perform functional tests with many mature SRIO chip platforms, such as PowerPC, DSP and Xilinx series products, etc., to realize the use case circuit design of chip design prototypes and the verification of actual application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0026] Figure 1 A verification system diagram of a high-speed serial port SRIO of the present invention;

[0027] Figure 2 A diagram of the HAPS prototype configuration process for the chip design prototype of the present invention;

[0028] Figure 3 It is a verification and testing flow chart of the SRIO basic function scenario of the present invention;

[0029] Figure 4 The figure is a flow chart of designing and generating SRIO test data of the present invention. DETAILED DESCRIPTION

[0030] like Figure 1 As shown, this embodiment provides a verification test method for a high-speed serial port SRIO based on a HAPS platform, comprising the following steps:

[0031] Step S1: HAPS platform configuration of the design prototype of the high-speed serial port SRIO, including the import of the design prototype of the chip containing the SRIO interface, the interface configuration of different storage media, the configuration of the information exchange serial port, and the configuration of the debugging interface;

[0032] Step S2: debugging interaction of the high-speed serial port SRIO, in which the storage of basic function data frames is completed, the instruction switching of different basic functions is completed, the real-time output of the basic function verification test process is completed, and the comparison output of the verification test results is completed;

[0033] Step S3: Verify that the high-speed serial port SRIO application scenario is modifiable and the hardware is configurable, which includes completing the design and storage of the application scenario data frame, completing the modifiable compilation of the SRIO application scenario function, and completing the different hardware scenario tests of the SRIO interface function.

[0034] Furthermore, if Figure 1As shown in the figure, the HAPS platform requires a dedicated power supply. When configuring the SRIO verification platform, it is necessary to confirm the slot positions and I / O initial levels of various sub-cards, such as DDR memory, SRAM memory, UART interface card, and JTAG sub-card. In the early stage of basic function verification test, the self-loopback test mode is often used, that is, the SRIO transmitter and receiver are short-circuited. The test mode is expanded from simple to complex. The computer for verification test configuration should be configured with the corresponding software environment, such as the configuration software confpro GUI O-2018.09-2 of the HAPS platform, the chip development compilation and debugging software Eclipse for DS-5, the serial port tool SecureCRT7.2, and the debugging tool J-link, etc.

[0035] like Figure 2 As shown, the design prototype HAPS platform configuration of the high-speed serial port SRIO in step S1 includes:

[0036] Importing the SRIO interface chip design prototype: First, the HAPS platform configures the project, and then loads the SRIO interface chip design prototype file into the HAPS platform configuration;

[0037] Furthermore, using the confpro GUI O-2018.09-2 software, the HAPS platform is first configured, including system type configuration, global clock selection, phase-locked loop clock input and enable, power I / O voltage setting, and reference clock setting, etc.; then the SRIO interface chip design prototype file is loaded into the HAPS platform configuration;

[0038] Configuration of different storage media: configure the clock, reset, and voltage according to the I / O pins of the storage medium;

[0039] Specifically, such as configuring DDR memory and SRAM memory, operations such as timing, reset, and initialization are performed by software configuration;

[0040] Serial port configuration: configure the serial port clock, baud rate, and checksum according to the serial port I / O pins;

[0041] Specifically, identify the port number corresponding to the serial port according to the computer management, open the SecureCRT7.2 serial port tool to configure the baud rate, verification status, etc. of the serial port;

[0042] Configuration of the JTAG interface: According to the I / O allocation of the JTAG pins, use the compilation and debugging software dedicated to the design prototype to connect to the HAPS platform through the JTAG simulation debugger, and select the connection configuration type to perform online verification testing on the HAPS platform for the software compilation results and the SRIO interface chip prototype.

[0043] Furthermore, the Eclipse for DS-5 software is opened, connected to the HAPS platform through the J-Link simulation debugger, and the connection configuration type is selected. The Eclipse for DS-5 software is used to modify and compile the software, and the results are verified online with the SRIO interface chip prototype.

[0044] like Figure 3 As shown, the debugging interaction of the high-speed serial port SRIO in step S2 includes:

[0045] If the SRIO chip design prototype has been configured with the HAPS platform, run the Eclipse software. The DDR memory or SRAM memory completes the initialization configuration of the software. The serial port function has been integrated into the verification software. If the serial port prompts "Enter the prototype successfully", otherwise the prototype import settings are incorrect or the prototype design is incorrect and failed to run successfully.

[0046] Storage of basic function data frames: Figure 4 As shown, according to the basic functions of SRIO, design relevant test data (such as Doorbell data is designed as 0x5a5a or 0xa5a5, DMA data is tested for all bits of all 0 and all 1 respectively, etc.), store it in the corresponding storage medium address (DDR memory or SRAM memory), and check its correctness;

[0047] Instruction switching of different basic functions: refer to the functions of RapidIO protocol and SRIO IP, divide the basic functions of SRIO, identify and verify the basic application functions through different instructions during verification test, and implement test switching of each basic function through serial port tools;

[0048] The basic functions of SRIO are divided into Reset, Linkup, Doorbell, Maintenance, PIO, DMA, DME, Interrupt, Datastream, Logicflow, etc.

[0049] Real-time output of basic function verification test process: The verification test of high-speed serial port SRIO can output the process identification of each basic function and the configuration of the registers involved according to the real-time output when each basic function is running, to assist in judging the validity of the application scenario configuration;

[0050] Comparative output of verification test results: The data during each basic functional scenario verification test is compared with the data generated during the actual test; if the results are consistent, a success message is output, otherwise a failure message is output.

[0051] The high-speed serial port SRIO application scenario modifiable and hardware configurable verification in step S3 includes:

[0052] Design and storage of application scenario data frames: For different application scenarios, data frames that comply with the RapidIO protocol can be designed and stored as data sources for verifying application scenarios.

[0053] Some application scenarios require adding appropriate information headers to the data frames, while some scenarios require using fixed DMA transfer lengths and formats.

[0054] Modifiable compilation of SRIO application scenario functions: Chips designed for different application scenarios do not need to implement all SRIO functions. Instead, they can tailor and modify the required SRIO functions according to the application scenarios.

[0055] Specifically, the application scenario of some chips is that the address of the connected device is invisible. At this time, the prototype of the chip uses messages as the main function, so the required SRIO functions are more tailored and modified according to the application scenario.

[0056] Different hardware scenario tests of SRIO interface functions: This verification test platform can be used for self-loop testing, and can also be connected to different SRIO interface devices, such as some products in the PowerPC series and DSP series. For different interface forms, such as SFP, SMA, and PCIE, different interface daughter cards are configured according to the interface characteristics of the HAPS platform to match different tests.

[0057] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A verification test method for high-speed serial port SRIO based on HAPS platform, characterized in that: The steps include: Step S1: HAPS platform configuration of the design prototype of the high-speed serial port SRIO, including the import of the design prototype of the chip containing the SRIO interface, the interface configuration of different storage media, the configuration of the information exchange serial port, and the configuration of the debugging interface; Step S2: debugging interaction of the high-speed serial port SRIO, in which the storage of basic function data frames is completed, the instruction switching of different basic functions is completed, the real-time output of the basic function verification test process is completed, and the comparison output of the verification test results is completed; Step S3: Verify that the high-speed serial port SRIO application scenario is modifiable and the hardware is configurable, including completing the design and storage of the application scenario data frame, completing the modifiable compilation of the SRIO application scenario function, and completing the different hardware scenario tests of the SRIO interface function; The debugging interaction of the high-speed serial port SRIO in step S2 includes: Storage of basic function data frames: According to the basic functions of SRIO, design relevant test data, store them in the corresponding storage medium address, and verify their correctness; Instruction switching of different basic functions: refer to the functions of RapidIO protocol and SRIO IP, divide the basic functions of SRIO, identify and verify the basic application functions through different instructions during verification test, and implement test switching of each basic function through serial port tools; Real-time output of basic function verification test process: The verification test of high-speed serial port SRIO can output the process identification of each basic function and the configuration of the registers involved according to the real-time output when each basic function is running, to assist in judging the validity of the application scenario configuration; Comparative output of verification test results: Verify the data during the test of each basic functional scenario and compare it with the data generated during the actual test; if the results are consistent, output a success message, otherwise output a failure message; The high-speed serial port SRIO application scenario modifiable and hardware configurable verification in step S3 includes: Design and storage of application scenario data frames: For different application scenarios, data frames that comply with the RapidIO protocol can be designed and stored as data sources for verifying application scenarios. Modifiable compilation of SRIO application scenario functions: Chips designed for different application scenarios do not need to implement all SRIO functions. Instead, they can tailor and modify the required SRIO functions according to the application scenarios. Different hardware scenario tests of SRIO interface functions: This verification test platform can be used for self-loop testing, and can also be connected to different SRIO interface devices, including some products in the PowerPC series and DSP series. For different interface forms, including SFP, SMA, and PCIE, different interface daughter cards are configured according to the interface characteristics of the HAPS platform to match different tests.

2. The verification and testing method of a high-speed serial port SRIO based on a HAPS platform according to claim 1, characterized in that: The design prototype HAPS platform configuration of the high-speed serial port SRIO in step S1 includes: Importing the SRIO interface chip design prototype: First, the HAPS platform configures the project, and then loads the SRIO interface chip design prototype file into the HAPS platform configuration; Configuration of different storage media: configure the clock, reset, and voltage according to the I / O pins of the storage medium; Serial port configuration: configure the serial port clock, baud rate, and checksum according to the serial port I / O pins; Configuration of the JTAG interface: According to the I / O allocation of the JTAG pins, use the compilation and debugging software dedicated to the design prototype to connect to the HAPS platform through the JTAG simulation debugger, and select the connection configuration type to perform online verification testing on the HAPS platform for the software compilation results and the SRIO interface chip prototype.

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