Method and apparatus for monitoring failure of network device

Abstract

The application discloses a kind of network equipment's fault monitoring method and device, applied to the CPLD of network equipment, the network equipment also includes BMC;Including: when the received monitored signal is the first type monitored signal, the first type monitored signal is carried out edge detection;And, when the received monitored signal is the second type monitored signal, the second type monitored signal is obtained candidate digital signal by difference comparison, analog-digital conversion, and according to pre-set threshold range, the candidate digital signal is carried out over-threshold detection;When edge detection or over-threshold detection output changes along signal, determine that the monitored signal occurs signal mutation, the change along signal is output to the BMC to make the BMC according to the change along signal increase corresponding time stamp and alarm record.The embodiment of the application can solve the problem that the implementation network equipment fault monitoring cost is too high and flexibility is poor in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a network device fault monitoring method and device. BACKGROUND

[0002] Many faults of network devices occur in harsh conditions such as high and low temperatures. After the fault occurs, it is difficult to reproduce, and a lot of effort is often required to reproduce. Moreover, some signals need to be observed through an oscilloscope, and it is also very difficult to use an oscilloscope in a temperature chamber.

[0003] In recent years, design for testability has been paid more and more attention, but it is still less applied in network devices. In the development of network devices, some monitoring signals have also been added, but the monitoring method based on these monitoring signals generally depends on hardware overhead, such as implementing monitoring through a triode or a chip, but the function is incomplete or the implementation cost is generally too high. SUMMARY

[0004] The embodiments of the present application provide a network device fault monitoring method and device to solve the problem of high cost and poor flexibility in implementing network device fault monitoring in the prior art.

[0005] According to the embodiments of the present application, a network device fault monitoring method is provided, which is applied to a complex programmable logic device (CPLD) of a network device, and the network device further includes a baseboard management controller (BMC). The method comprises:

[0006] When the received monitored signal is a first type of monitored signal, edge detection is performed on the first type of monitored signal; and

[0007] When the received monitored signal is a second type of monitored signal, a candidate digital signal is obtained through differential comparison and analog-to-digital conversion on the second type of monitored signal, and over-threshold detection is performed on the candidate digital signal according to a preset threshold range;

[0008] When an edge detection or over-threshold detection output changes an edge signal, it is determined that the monitored signal has a signal mutation, and the edge signal is output to the BMC to make the BMC add a corresponding time stamp and an alarm record according to the edge signal;

[0009] The first type of monitored signal includes an alarm signal and / or a bit type signal, and the second type of monitored signal includes a power supply signal and / or a reset type signal.

[0010] Optionally, the method further comprises:

[0011] The change edge signal is counted and stored for checking when the monitored signal fault disappears.

[0012] Optionally, when the received monitored signal does not belong to the size range of the CPLD processable signal, the method further comprises:

[0013] The input assignment processing is performed on the monitored signal so that the monitored signal belongs to the size range of the CPLD processable signal.

[0014] Optionally, the candidate digital signal of the second type of monitored signal is obtained through differential comparison and analog-to-digital conversion, and specifically comprises:

[0015] The second type of monitored signal is input to the positive pin of a low-voltage differential signal (LVDS) comparator, and the signal output by the LVDS comparator after comparison is fed back to the negative pin of the LVDS comparator through a resistance and resistance-capacitance (RC) circuit.

[0016] A level amplitude identification module receives the signal output by the LVDS comparator after comparison, and outputs a candidate digital signal corresponding to the voltage of the signal according to a preset value-voltage correspondence.

[0017] Optionally, the method further comprises:

[0018] According to a preset value-voltage correspondence, a value range corresponding to the working voltage range of the chip of the network device monitored signal is determined.

[0019] It is determined whether the candidate digital signal is located within the value range.

[0020] When the candidate digital signal is located outside the value range, a change edge signal is output.

[0021] Optionally, the change edge signal is output to the BMC, and specifically comprises:

[0022] The change edge signal is output to the BMC through an interrupt pin and stored in a register for polling by the BMC.

[0023] According to an embodiment of the present application, a network device fault monitoring device is also provided, which is applied to a complex programmable logic device (CPLD) of a network device, and the network device further comprises a baseboard management control unit (BMC). The device comprises a first detection module and a second detection module, wherein:

[0024] The first detection module is configured to perform edge detection on the first type of monitored signal when the received monitored signal is the first type of monitored signal; and configured to determine that the monitored signal has a signal mutation when an edge change signal is output, and output the edge change signal to the BMC so that the BMC increases a corresponding time stamp and an alarm record according to the edge change signal.

[0025] and,

[0026] The second detection module is configured to obtain a candidate digital signal through differential comparison and analog-to-digital conversion on the second type of monitored signal when the received monitored signal is the second type of monitored signal, and perform over-threshold detection on the candidate digital signal according to a preset threshold range; and configured to determine that the monitored signal has a signal mutation when an edge change signal is output, and output the edge change signal to the BMC so that the BMC increases a corresponding time stamp and an alarm record according to the edge change signal.

[0027] The first type of monitored signal includes an alarm signal and / or a bit type signal; and the second type of monitored signal includes a power supply signal and / or a reset type signal.

[0028] Optionally, the apparatus further includes a statistical module configured to perform pulse width statistics on the edge change signal and store the pulse width statistics in a register so as to be viewed when the monitored signal fault disappears.

[0029] Optionally, when the received monitored signal does not belong to a size range of the CPLD processable signal, the apparatus further includes an input assignment processing module configured to perform input assignment processing on the monitored signal so that the monitored signal belongs to the size range of the CPLD processable signal.

[0030] Optionally, the second detection module is configured to, when performing differential comparison on the second type of monitored signal, specifically configured to input the second type of monitored signal into a positive pin of a low-voltage differential signal (LVDS) comparator, and perform negative feedback of a signal output by the LVDS comparator to a negative pin of the LVDS comparator through a resistor-capacitor (RC) circuit.

[0031] The second detection module is configured to, when performing analog-to-digital conversion to obtain a candidate digital signal, specifically configured to receive the signal output by the LVDS comparator, and output a candidate digital signal corresponding to a voltage of the signal according to a preset value-voltage correspondence.

[0032] Optionally, the second detection module is configured to, when performing over-threshold detection on the candidate digital signal according to a preset threshold range, specifically configured to:

[0033] According to the preset numerical value and voltage correspondence relationship, a numerical value range corresponding to a working voltage range of a chip corresponding to the network device monitored signal is determined;

[0034] It is judged whether the candidate digital signal is located in the numerical value range or not;

[0035] When the candidate digital signal is located outside the numerical value range, a change edge signal is output.

[0036] Optionally, when the first detection module and the second detection module output the change edge signal to the BMC, the change edge signal is specifically output to the BMC through an interrupt pin and stored in a register for polling by the BMC.

[0037] The change edge signal is output to the BMC through an interrupt pin and stored in a register for polling by the BMC.

[0038] According to the embodiment of the present application, an electronic device is also provided, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus.

[0039] The memory is used for storing a computer program.

[0040] The processor is used for executing the program stored on the memory, and realizes the method steps described above.

[0041] According to the embodiment of the present application, a computer readable storage medium is also provided, which stores a computer program, and the computer program is executed by the processor to realize the method steps described above.

[0042] The present application has the following advantages:

[0043] The fault monitoring method and apparatus for network devices provided in this invention are applied to a Complex Programmable Logic Device (CPLD) of a network device, wherein the network device further includes a Baseboard Management Controller (BMC). When the received monitored signal is a first type of monitored signal, edge detection is performed on the first type of monitored signal. And, when the received monitored signal is a second type of monitored signal, candidate digital signals are obtained from the second type of monitored signal through differential comparison and analog-to-digital conversion, and over-threshold detection is performed on the candidate digital signals according to a preset threshold range. When the edge detection or over-threshold detection outputs a changing edge signal, it is determined that a signal abrupt change has occurred in the monitored signal, and the changing edge signal is output to the BMC so that the BMC adds a corresponding timestamp and alarm record based on the changing edge signal. The first type of monitored signal includes alarm signals and / or in-place signals; the second type of monitored signal includes power signals and / or reset signals. This invention provides a method for classifying and monitoring monitored signals. The CPLD of the network device performs different detections on different types of monitored signals, and the BMC timestamps and records alarms for signals that undergo signal mutations. This allows the system to store the process of a monitored signal failure, which is beneficial for subsequent fault reproduction. This improves the testability and maintainability of the network device, and the implementation is relatively convenient and low-cost, thus enhancing the applicability and flexibility of the product. Attached Figure Description

[0044] Figure 1 This is a flowchart of a network device fault monitoring method in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the structure of the fault monitoring device for network equipment in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the structure of an embodiment of the fault monitoring device for network devices in this invention.

[0047] Figure 4 This is a schematic diagram of the structure of an electronic device shown in this application. Detailed Implementation

[0048] In view of the problems of high cost and poor flexibility of network equipment fault monitoring in the prior art, the network equipment fault monitoring method provided in the embodiments of the present application first classifies the monitored signals according to their own characteristics, realizes different monitoring processing and storage for different types of monitored signals through the CPLD of the network equipment, and realizes real-time fault monitoring when the signal mutates. Figure 1 As shown in the flow of the method of the present application applied to the CPLD of the network equipment, the network equipment further comprises a BMC, and the execution steps are as follows:

[0049] Step 101: when the received monitored signal is a first type of monitored signal, edge detection is performed on the first type of monitored signal.

[0050] Here, edge detection is a commonly used method in digital circuits, that is, the clock of the CPLD is used to sample the external input signal, and the obtained result is stored in a 2-bit shift register, and the two-bit signals of the shift register are logically operated to detect the rising edge jump or the falling edge jump.

[0051] Step 102: when the received monitored signal is a second type of monitored signal, a candidate digital signal is obtained through differential comparison and analog-to-digital conversion on the second type of monitored signal, and over-threshold detection is performed on the candidate digital signal according to a preset threshold range.

[0052] Step 103: when the edge detection or over-threshold detection outputs a change edge signal, it is determined that the monitored signal has a signal mutation, and the change edge signal is output to the BMC so that the BMC adds a corresponding time stamp and an alarm record according to the change edge signal.

[0053] Specifically, the CPLD completes edge extraction of the monitored signal, and outputs the monitored change edge signal to the BMC, and the BMC adds a corresponding time stamp and a fault record according to the change edge signal, thereby realizing fault monitoring of the network equipment.

[0054] Here, the first type of monitored signal includes an alarm signal and / or an in-place signal; and the second type of monitored signal includes a power supply signal and / or a reset signal. In the embodiments of the present application, the signals of the network equipment can be divided into two types: power supply and reset type, alarm and in-place type; wherein the power supply and reset type signal is relatively sensitive to small fluctuations in the level, and even a half-high level often causes a fault; and the alarm and in-place type signal is relatively insensitive to small fluctuations, and a half-high level has little effect on it. Therefore, in the embodiments of the present application, it is necessary to determine whether different monitoring processing is needed according to the type of the monitored signal to distinguish the signal change of small fluctuations. Those skilled in the art should understand that steps 101 and 102 do not have a strict sequence.

[0055] Preferably, the method further comprises:

[0056] The pulse width statistics of the change edge signal are stored for review when the monitored signal failure disappears. Specifically, after detecting the change edge signal, the pulse width statistics starts counting, and if the change edge signal does not disappear, the counting of the pulse width statistics is sequentially incremented until a preset maximum value is reached; if the change edge signal disappears, the pulse width statistics retains the statistical record and does not clear the previous statistical record following the disappearance of the change edge signal.

[0057] Here, the statistical record of the pulse width statistics can be stored in the register of the CPLD, and the user can view it through the I2C interface. The statistical accuracy of the pulse width statistics can be adjusted according to actual needs. For example, since the MAC voltage drop failure is usually in the order of us, the pulse width statistics accuracy of the MAC voltage signal can be adjusted to 40ns.

[0058] Further, when the received monitored signal does not belong to the size range of the CPLD processable signal, the method further comprises:

[0059] The input assignment processing is performed on the monitored signal so that the monitored signal belongs to the size range of the CPLD processable signal.

[0060] Specifically, since the highest support voltage drop of the CPLD is generally 3.3V, the voltage drop higher than 3.3V needs to be reduced to below 3.3V. Generally, a conventional resistance voltage divider can be used. For example, if the monitored signal voltage is 5V, two 10 megaohm resistors can be used to divide the voltage to 2.5V as the input signal, and if the monitored signal voltage is 2.0V, it is directly input to the pin of the CPLD.

[0061] The candidate digital signal of the second type of monitored signal is obtained through differential comparison and analog-to-digital conversion, specifically comprising:

[0062] The second type of monitored signal is input to the positive pin of the Low Voltage Differential Signaling (LVDS) comparator, and the signal output by the LVDS comparator after comparison is negatively fed back to the negative pin of the LVDS comparator through a resistance and resistance-capacitance (RC) circuit;

[0063] The level amplitude identification module receives the signal output by the LVDS comparator after comparison, and outputs a candidate digital signal corresponding to the voltage of the signal according to a preset value-voltage correspondence. Here, the level amplitude identification module realizes an analog-digital conversion function, and the output value is a candidate digital signal, which can reflect an analog voltage in the range of 0-3.3v. The accuracy of analog-digital conversion can be flexibly set as needed. For example, if the digital counter is set to 12 bits, there are 4096 numbers, and the scale can be divided into 4095 equal parts, so the accuracy is 3.3V / 4095=80.6mV.

[0064] Optionally, the over-threshold detection of the candidate digital signal according to the preset threshold range specifically includes:

[0065] According to the preset value-voltage correspondence, a value range corresponding to the working voltage range of the chip of the monitored signal of the network device is determined; here, the value range is related to the sensitivity of the chip, the working voltage range during normal operation of the network device is determined according to the high and low voltage values corresponding to the normal operation of the chip, and then the value range corresponding to the working voltage range is determined according to the preset value-voltage correspondence, so as to determine whether the candidate digital signal falls into the value range to determine whether the monitored signal fails;

[0066] It is judged whether the candidate digital signal is located in the value range;

[0067] When the candidate digital signal is located outside the value range, a change edge signal is output.

[0068] Optionally, the output of the change edge signal to the BMC includes:

[0069] The change edge signal is output to the BMC through an interrupt pin and stored in a register for polling by the BMC. Further, the register can be used to store pulse width information of the monitored change edge signal, change edge signal, assignment signal during abnormality, and the like, and the storage of the data can be set to a read-clear mode, that is, as long as the BMC does not poll the data, the data will be saved forever, and when the data is polled, the data can be cleared.

[0070] Based on the same inventive concept, the embodiments of the present application provide a fault monitoring device of a network device, which can be applied to a complex programmable logic device (CPLD) of the network device, and the network device further includes a baseboard management control unit (BMC); the structure of the device is as shown in Figure 2 The device includes a first detection module 21 and a second detection module 22; wherein,

[0071] The first detection module 21 is configured to perform edge detection on the first type of monitored signal when the received monitored signal is the first type of monitored signal, and configured to determine that the monitored signal has signal mutation when a change edge signal is output, and output the change edge signal to the BMC so that the BMC increases corresponding time stamp and alarm record according to the change edge signal.

[0072] and,

[0073] The second detection module 22 is configured to obtain a candidate digital signal through differential comparison and analog-to-digital conversion on the second type of monitored signal when the received monitored signal is the second type of monitored signal, and configured to perform over-threshold detection on the candidate digital signal according to a preset threshold range; and configured to determine that the monitored signal has signal mutation when a change edge signal is output, and output the change edge signal to the BMC so that the BMC increases corresponding time stamp and alarm record according to the change edge signal.

[0074] The first type of monitored signal includes an alarm signal and / or a bit type signal, and the second type of monitored signal includes a power supply signal and / or a reset type signal.

[0075] Optionally, the apparatus further comprises a statistical module configured to perform pulse width statistics on the change edge signal and store the pulse width statistics to a register so as to be viewed when the monitored signal fault disappears.

[0076] Optionally, when the received monitored signal does not belong to the size range of the CPLD processable signal, the apparatus further comprises an input assignment processing module configured to perform input assignment processing on the monitored signal so that the monitored signal belongs to the size range of the CPLD processable signal.

[0077] Optionally, the second detection module is configured to, when performing differential comparison on the second type of monitored signal, specifically configured to input the second type of monitored signal to a positive pin of a low-voltage differential signal (LVDS) comparator, and feed back a signal output by the LVDS comparator to a negative pin of the LVDS comparator through a resistor-capacitor (RC) circuit.

[0078] The second detection module is configured to, when performing analog-to-digital conversion to obtain a candidate digital signal, specifically configured to receive the signal output by the LVDS comparator, and output a candidate digital signal corresponding to a voltage of the signal according to a preset value-voltage correspondence.

[0079] Further, the second detection module is configured to, when performing over-threshold detection on the candidate digital signal according to a preset threshold range, specifically configured to:

[0080] According to the preset numerical value and voltage correspondence relationship, a numerical value range corresponding to a working voltage range of a chip corresponding to the network device monitored signal is determined;

[0081] It is judged whether the candidate digital signal is located in the numerical value range or not;

[0082] When the candidate digital signal is located outside the numerical value range, a change edge signal is output.

[0083] Further, when the first detection module and the second detection module output the change edge signal to the BMC, the change edge signal is output to the BMC through an interrupt pin and stored in a register for polling by the BMC.

[0084] The change edge signal is output to the BMC through an interrupt pin and stored in a register for polling by the BMC.

[0085] It should be understood that the implementation principle and process of the network device fault monitoring device provided by the embodiments of the present application are similar to those of the above Figure 1 and the embodiments shown, and will not be described here.

[0086] The network device fault monitoring method and device provided by the embodiments of the present application are applied to a complex programmable logic device (CPLD) of a network device, and the network device further includes a baseboard management controller (BMC). When a received monitored signal is a first type of monitored signal, edge detection is performed on the first type of monitored signal. When the received monitored signal is a second type of monitored signal, a candidate digital signal is obtained through differential comparison and analog-to-digital conversion on the second type of monitored signal, and super-threshold detection is performed on the candidate digital signal according to a preset threshold range. When an edge change signal is output by edge detection or super-threshold detection, it is determined that the monitored signal has signal mutation, and the edge change signal is output to the BMC so that the BMC adds a corresponding time stamp and alarm record according to the edge change signal. The first type of monitored signal includes an alarm signal and / or a bit type signal. The second type of monitored signal includes a power supply signal and / or a reset type signal. The embodiments of the present application monitor the monitored signal by type, the CPLD of the network device detects different types of monitored signals, and the BMC records the time stamp and alarm of the signal with signal mutation, which can store the process of the monitored signal fault, is beneficial to subsequent fault reproduction, improves the testability and maintainability of the network device, and is relatively convenient to implement, low in cost, improves the product applicability and flexibility.

[0087] The implementation of the network device fault monitoring device is described in detail below with a specific embodiment, with reference to Figure 3 The network device includes a CPLD and a BMC, the network device fault monitoring device can be arranged in the CPLD, and includes a first detection module, a second detection module, a statistical module and a register; the second detection module specifically can include an LVDS comparator, a level amplitude identification sub-module and an over-threshold detection sub-module;

[0088] The first detection module is used for performing edge detection on the first type of monitored signal when the received monitored signal is the first type of monitored signal; the first type of monitored signal is an alarm and in-place type signal.

[0089] The first detection module is also used for determining that the monitored signal has signal mutation when the edge detection output changes the edge signal, at this time, three actions are performed: 1. When the change edge signal is converged to the interrupt pin and output to the BMC, the BMC detects the interrupt, the corresponding timestamp and alarm record are increased; 2. The change edge signal is stored in the register, so that when the BMC polls the fault, the corresponding timestamp is increased and the alarm record is stored; 3. Input to the statistical module for pulse width statistics, specifically, the change edge signal is counted and stored in the register for viewing when the monitored signal fault disappears. For example, the alarm signal is detected to be suddenly pulled down, and the edge detection detects the falling edge signal, the falling edge signal is converged to the BMC through the interrupt and the register, the BMC increases the timestamp to record the time of the fault occurrence. The statistical module starts counting after detecting the falling edge, if the falling edge signal does not disappear, the statistical counting is performed until the maximum value; if the falling edge signal disappears, the statistical module retains the statistical value of the falling edge signal, and does not clear the falling edge signal when the fault disappears. The statistical result of the statistical module is stored in the register, so that the BMC can view through the I2C interface.

[0090] Here, the change edge signal indicates that the monitored alarm or in-place type signal has signal mutation, i.e. the possibility of failure.

[0091] And,

[0092] The second detection module is used for, when the received monitored signal is the second type of monitored signal, performing over-threshold detection on the candidate digital signal obtained by differential comparison and analog-to-digital conversion on the second type of monitored signal according to a preset threshold range; here, the second type of monitored signal includes a power signal and / or a reset type signal.

[0093] Specifically, with reference to Figure 3The LVDS comparator of the second detection module receives the second type of monitored signal through the positive pin, and the signal outputted after comparison of the LVDS comparator is negatively fed back to the negative pin of the LVDS comparator through a resistance and an RC circuit; that is, the positive input of the LVDS comparator is the monitored signal, and the negative input is the signal after comparison of the positive and negative inputs.

[0094] The level amplitude identification submodule of the second detection module receives the signal outputted after comparison of the LVDS comparator, and outputs a candidate digital signal corresponding to the voltage of the signal according to a preset value-voltage correspondence. The precision of analog-digital conversion can be flexibly set. Assuming that the digital counter is set to 12 bits, there are 4096 numbers, and the scale can be equally divided into 4095, so the precision is 3.3V / 4095=80.6mV. Table 1 lists part of the voltage corresponding values, in which 000H represents 0V, 3E8H represents 0.80V, 44CH represents 0.88V, and FFF represents 3.30V.

[0095] Hexadecimal Decimal Voltage / V 000 0 0 001 1 0.000806 064 100 0.080586 1F4 500 0.40293 384 900 0.725275 3E1 993 0.80022 410 1040 0.838095 424 1060 0.854212 44C 1100 0.886447 45E 1118 0.900952 4B0 1200 0.967033 514 1300 1.047619 578 1400 1.128205 5 DC 1500 1.208791 6A4 1700 1.369963 7D0 2000 1.611722 8 FC 2300 1.85348 9B3 2483 2.000952 A28 2600 2.095238 A8 C 2700 2.175824 BB8 3000 2.417582 C1 C 3100 2.498168 C80 3200 2.578755 D48 3400 2.739927 E10 3600 2.901099 E74 3700 2.981685 ED8 3800 3.062271 F3 C 3900 3.142857 FFF 4095 3.30

[0096] Table 1

[0097] The super-threshold value detection submodule of the second detection module determines a value range corresponding to the working voltage range of the chip corresponding to the monitored signal of the network device according to a preset value-voltage correspondence; judges whether the candidate digital signal is located in the value range; and outputs a change edge signal when the candidate digital signal is located outside the value range. For example, a reset signal complying with the LVCMOS3V3 standard, for an input standard, a high level 2.0V is set as a high threshold value, and 0.8V is set as a low threshold value. If the high level indicates that the reset is released, if the level is lower than 2.0V, the reset signal of the monitored chip falls to an uncertain level, at which time a problem is likely to occur. The threshold value of the level signal is often narrower, and the 0.88V voltage supplied by the switch MAC chip is taken as an example. If the 0.8V is reached, the MAC chip may be abnormal, and the ongoing traffic may be suddenly lost. As can be seen from Table 1, the comparison value corresponding to 2.0V is 9B3, and the comparison value corresponding to 0.8V is 3E1, so the super-threshold value detection submodule compares the data outputted by the level amplitude identification submodule with the predetermined threshold value. If the predetermined threshold value is exceeded, a change edge signal is outputted.

[0098] The threshold crossing detection submodule of the second detection module, when outputting a change edge signal, determines that the monitored signal has a signal mutation, at which time three actions are performed: 1. The change edge signal is converged to an interrupt pin and output to the BMC, so that when the BMC detects the interrupt, a corresponding timestamp and alarm record are added; 2. The change edge signal is stored in a register, so that when the BMC performs fault polling and polls the fault, a corresponding timestamp is added and an alarm record is stored; 3. Input to the statistical module for pulse width statistics, specifically, the change edge signal is subjected to pulse width statistics and stored in a register for viewing when the monitored signal fault disappears.

[0099] The statistical module starts counting after detecting a falling edge, and if the falling edge signal does not disappear, the counting is performed until a maximum value is reached; if the falling edge signal disappears, the statistical module retains the statistical value of the falling edge signal and does not clear the previous falling edge signal when the fault disappears. The statistical result of the statistical module is stored in a register for the BMC to view through an I2C interface. For example, based on the data stored in the register, fault behavior analysis can be performed, such as defining BIT0 of address FF as a MAC core voltage anomaly, and the correspondence between fault information and suspected faults is as follows:

[0100]

[0101] The embodiments of the present application also provide an electronic device, please refer to Figure 4 As shown in the figure, it includes a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520, the memory 530 complete mutual communication through the communication bus 540.

[0102] The memory 530 is used to store computer programs;

[0103] The processor 510 is used to execute the programs stored in the memory 530, and realize the fault monitoring method of the network device in any of the above embodiments.

[0104] The communication interface 520 is used for communication between the above electronic device and other devices.

[0105] The memory can include a random access memory (RAM) and a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0106] The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0107] In the scheme, by monitoring the monitored signals by type, the CPLD of the network device detects different types of monitored signals differently, and the BMC records the time stamp and alarm of the signal with signal mutation, can store the process of the monitored signal fault occurrence, is beneficial to subsequent fault reproduction, improves the testability and maintainability of the network device, and is relatively convenient to implement, has low cost, improves product applicability and flexibility.

[0108] Correspondingly, the embodiment of the application further provides a computer readable storage medium, the computer readable storage medium stores instructions, when the instructions run on the computer, the computer executes the fault monitoring method of the network device in any of the above embodiments.

[0109] In the scheme, by monitoring the monitored signals by type, the CPLD of the network device detects different types of monitored signals differently, and the BMC records the time stamp and alarm of the signal with signal mutation, can store the process of the monitored signal fault occurrence, is beneficial to subsequent fault reproduction, improves the testability and maintainability of the network device, and is relatively convenient to implement, has low cost, improves product applicability and flexibility.

[0110] Those skilled in the art can understand that the drawings are only schematic diagrams of an embodiment, and the modules or flows in the drawings are not necessarily necessary for implementing the application.

[0111] Those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary universal hardware platform through the description of the above embodiments. Based on such an understanding, the technical solutions of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

[0112] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device or system embodiments, since they are basically similar to the method embodiments, they are described more simply, and the relevant parts can be referred to the part of the method embodiments. The above-described device and system embodiments are merely illustrative, and the units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. Those skilled in the art can understand and implement without creative labor.

[0113] In addition, in some of the processes described in the above embodiments and the accompanying drawings, a plurality of operations are included in a specific order, but it should be clear that the operations can be executed or in parallel without the order in which they appear in this text. The serial numbers of the operations, such as 201, 202, 203, etc., are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes can include more or fewer operations, and the operations can be executed in sequence or in parallel. It should be noted that the "first", "second", etc. in this text are used to distinguish different messages, devices, modules, etc., and do not represent the sequence, nor do "first" and "second" represent different types.

[0114] The above-described device embodiments are merely illustrative, and the units described as separate components can be or can not be physically separated, and the components displayed as units can be or can not be physical units, that is, they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. Those skilled in the art can understand and implement without creative labor.

[0115] The present application is described in reference to the flowchart and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for carrying out the function specified by the block or blocks.

[0116] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart and / or block diagram block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for carrying out the function specified by the block or blocks.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flowchart and / or block diagram block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for carrying out the function specified by the block or blocks.

[0118] While the present application has been described with reference to the alternative embodiments, those skilled in the art will recognize that additional modifications and variations are possible within the spirit and scope of the application. Accordingly, the appended claims are intended to cover all such modifications and variations as falling within the scope of the application.

[0119] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method for fault monitoring of network devices, characterized in that, The method is applied to a complex programmable logic device (CPLD) in a network device, the network device further including a baseboard management control unit (BMC); the method includes: When the received monitored signal is a first type of monitored signal, edge detection is performed on the first type of monitored signal; and, When the received monitored signal is a second type of monitored signal, the second type of monitored signal is compared differentially and converted from analog to digital to obtain a candidate digital signal, and the candidate digital signal is detected to exceed the threshold according to a preset threshold range. When an edge detection or over-threshold detection outputs a changing edge signal, it is determined that the monitored signal has undergone a signal change. The changing edge signal is then output to the BMC so that the BMC adds a corresponding timestamp and alarm record based on the changing edge signal. The received monitored signals include either the first type of monitored signals or the second type of monitored signals; the first type of monitored signals includes alarm signals and / or presence signals; the second type of monitored signals includes power signals and / or reset signals; the first type of monitored signals are relatively insensitive to small fluctuations in level, while the second type of monitored signals are more sensitive to small fluctuations in level.

2. The method according to claim 1, characterized in that, The method further includes: The pulse width of the change along the signal is statistically analyzed and stored for later review when the fault in the monitored signal disappears.

3. The method according to claim 1, characterized in that, When the received monitored signal does not fall within the size range of signals that the CPLD can process, the method further includes: The monitored signal is processed by input assignment to ensure that the monitored signal falls within the size range of signals that the CPLD can process.

4. The method according to claim 1, characterized in that, The process of obtaining candidate digital signals from the second type of monitored signals through differential comparison and analog-to-digital conversion specifically includes: The second type of monitored signal is input to the positive pin of the low voltage differential signal LVDS comparator, and the signal output by the LVDS comparator after comparison is negatively fed back to the negative pin of the LVDS comparator through a resistor and a resistor-capacitor circuit (RC circuit). The level amplitude recognition module receives the signal output by the LVDS comparator after comparison, and outputs the candidate digital signal corresponding to the voltage of the signal according to the preset value-voltage correspondence.

5. The method according to any one of claims 1 to 4, characterized in that, The step of performing over-threshold detection on the candidate digital signal according to a preset threshold range specifically includes: Based on the preset numerical value and voltage correspondence, the numerical range corresponding to the operating voltage range of the chip corresponding to the second type of monitored signal of the network device is determined. Determine whether the candidate digital signal is within the specified numerical range; When the candidate digital signal is outside the numerical range, the change edge signal is output.

6. The method according to any one of claims 1 to 4, characterized in that, The step of outputting the change-along signal to the BMC includes: The change edge signal is output to the BMC via the interrupt pin and stored in the register for the BMC to poll.

7. The method according to claim 2, characterized in that, The step of performing pulse width statistics and storing the changes along the signal specifically includes: After detecting a changing edge signal, the pulse width statistics start counting. If the changing edge signal does not disappear, the pulse width statistics count will increase sequentially until it reaches the preset maximum value. If the changing edge signal disappears, the pulse width statistics will retain the statistical records and will not clear the previous statistical records as the changing edge signal disappears.

8. A fault monitoring device for network equipment, characterized in that, The device is applied to a complex programmable logic device (CPLD) in a network device, the network device further including a baseboard management control unit (BMC); the device includes: a first detection module and a second detection module; wherein, the first detection module is used to perform edge detection on the first type of monitored signal when the received monitored signal is a first type of monitored signal; and is also used to determine that the monitored signal has undergone a signal change when the edge detection outputs a changing edge signal, and output the changing edge signal to the BMC so that the BMC adds a corresponding timestamp and alarm record according to the changing edge signal; and... The second detection module is used to, when the received monitored signal is a second type of monitored signal, obtain candidate digital signals from the second type of monitored signal through differential comparison and analog-to-digital conversion, and perform over-threshold detection on the candidate digital signals according to a preset threshold range; it is also used to, when the over-threshold detection outputs a change-edge signal, determine that the second type of monitored signal has undergone a signal abrupt change, and output the change-edge signal to the BMC so that the BMC adds a corresponding timestamp and alarm record according to the change-edge signal; The received monitored signals include either the first type of monitored signals or the second type of monitored signals; the first type of monitored signals includes alarm signals and / or presence signals; the second type of monitored signals includes power signals and / or reset signals; the first type of monitored signals are relatively insensitive to small fluctuations in level, while the second type of monitored signals are more sensitive to small fluctuations in level.

9. The apparatus according to claim 8, characterized in that, The device further includes a statistics module, used to perform pulse width statistics on the changing edge signal and store it in a register for viewing after the monitored signal fault disappears.

10. The apparatus according to claim 8, characterized in that, When the received monitored signal does not fall within the size range of signals that the CPLD can process, the device further includes: an input assignment processing module, used to perform input assignment processing on the monitored signal so that the monitored signal falls within the size range of signals that the CPLD can process.

11. The apparatus according to claim 8, characterized in that, The second detection module is used to perform differential comparison on the second type of monitored signal. Specifically, it is used to: input the second type of monitored signal into the positive pin of the low voltage differential signal LVDS comparator, and negatively feed the signal output by the LVDS comparator after comparison to the negative pin of the LVDS comparator through a resistor and a resistor-capacitor circuit (RC circuit). The second detection module, when performing analog-to-digital conversion to obtain candidate digital signals, specifically serves to: receive the signal output by the LVDS comparator after comparison, and output the candidate digital signal corresponding to the voltage of the signal according to a preset value-voltage correspondence.

12. The apparatus according to any one of claims 8 to 11, characterized in that, The second detection module, when performing threshold detection on the candidate digital signal according to a preset threshold range, is specifically used for: Based on the preset numerical value and voltage correspondence, the numerical range corresponding to the operating voltage range of the chip corresponding to the second type of monitored signal of the network device is determined. Determine whether the candidate digital signal is within the specified numerical range; When the candidate digital signal is outside the numerical range, the change edge signal is output.

13. The apparatus according to any one of claims 8 to 11, characterized in that, The first detection module and the second detection module are used to output the change-line signal to the BMC, specifically for: The change edge signal is output to the BMC via the interrupt pin and stored in the register for the BMC to poll.

14. An electronic device, characterized in that, The electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method according to any one of claims 1-7.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-7.

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