Method and system for acquiring layout images of 3D integrated circuit structures

Abstract

This invention relates to a method and system for acquiring layout images of three-dimensional integrated circuit structures. The method includes: acquiring the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units within the structure; establishing a coordinate system and acquiring the coordinate information of each hardware unit in the coordinate system, determining the effective layout image range of each hardware unit; acquiring the layout image of each hardware unit based on the determined effective layout image range; stitching the layout images of each hardware unit together based on the coordinate information of each hardware unit to obtain a stitched graphic; and obtaining the layout image of the three-dimensional integrated circuit structure based on the stitched graphic. This method solves the problems of wasting time on high-precision imaging in areas without layout information and increasing the difficulty of stitching and alignment in layout images in areas without layout information, making the acquisition of layout images of three-dimensional integrated circuit structures more efficient and accurate, and improving the efficiency of chip layout image acquisition.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method and system for acquiring layout images of three-dimensional integrated circuit structures. Background Technology

[0002] In recent years, integrated circuits, as the core of modern information equipment, possess extremely high intellectual property value. Therefore, to protect their own rights and avoid infringement of patented layout designs, it is necessary to determine the similarity between the layout of competing chips and the layout of their own chips. Three-dimensional integrated circuits employ discrete manufacturing and heterogeneous integration methods, improving the performance and optimal size of integrated circuits and systems, while also mitigating security issues such as integrated circuit counterfeiting and the insertion of hardware malware in the manufacturing supply chain. Since the cost of layer-by-layer imaging is related to the magnification of the image, obtaining high-resolution layouts of competing chips requires photographing bare chip layers using different process technologies in heterogeneous integration, necessitating expensive imaging equipment and data processing methods. The vertical interconnect structure and high integration of three-dimensional integrated circuits create greater technical obstacles in assessing patent infringement of competing chips, and also increase the time and financial costs of layout image extraction.

[0003] Based on the above problems, existing industrial imaging methods, when using scanning electron microscopy to image de-layered chips, produce images of the central portion of the bare chip containing numerous unpatterned areas. These redundant, blank unpatterned areas waste time and resources associated with high-precision imaging, generate substantial amounts of unpatterned image data for storage, increase storage hardware costs and data processing complexity, and further complicate the stitching and alignment of images within the same layer. Therefore, traditional methods for acquiring layout images of two-dimensional planar packaged integrated circuits can no longer meet the demands of acquiring layout images for large-scale three-dimensional integrated circuits. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention presents a method and system for acquiring layout images of three-dimensional integrated circuit structures, enabling rapid and accurate acquisition of layout images of three-dimensional integrated circuit structures.

[0005] This invention provides a method for acquiring layout images of three-dimensional integrated circuit structures, the method comprising:

[0006] The three-dimensional structural information of the three-dimensional integrated circuit structure is obtained based on the architecture of the hardware units in the three-dimensional integrated circuit structure.

[0007] Establish a coordinate system and obtain the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit.

[0008] The layout image of each hardware unit is obtained based on the determined effective layout image range;

[0009] The layout images of each hardware unit are stitched together based on the coordinate information of each hardware unit to obtain a stitched graphic.

[0010] The layout image of the three-dimensional integrated circuit structure is obtained based on the stitched graphics.

[0011] In one embodiment, establishing a coordinate system and obtaining the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit includes:

[0012] Establish a coordinate system and determine its origin;

[0013] Determine the coordinates of the two diagonal points of each hardware unit in the coordinate system;

[0014] The effective layout image range of each hardware unit is determined based on the coordinates of the two diagonal points of each hardware unit in the coordinate system.

[0015] In one embodiment, the hardware unit includes a bare chip, an adapter board, and a substrate, wherein the substrate is electrically connected to the adapter board, and the bare chip is located on the side of the adapter board facing away from the substrate; the method of obtaining the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit in the three-dimensional integrated circuit structure includes:

[0016] The architecture of the hardware unit was obtained based on 3D X-ray imaging;

[0017] The three-dimensional structural information of the three-dimensional integrated circuit structure is obtained based on the architecture of the hardware unit.

[0018] In one embodiment, obtaining the layout image of each hardware unit based on a determined effective layout image range includes:

[0019] Based on the determined effective layout image range, the layout image of each hardware unit is obtained layer by layer.

[0020] In one embodiment, the three-dimensional integrated circuit structure further includes: microbumps, a redistribution layer, through-silicon vias (TSVs), solder joints, and a wiring structure; the redistribution layer is located on the opposite surface of the adapter plate; the TSVs are located within the adapter plate and penetrate the adapter plate along its thickness direction, and are connected to the redistribution layers located on the opposite surface of the adapter plate; the microbumps are located between the bare die and the redistribution layer to electrically connect the bare die and the redistribution layer; the wiring structure is located on the surface of the substrate adjacent to the adapter plate; the solder joints are located between the substrate and the redistribution layer to electrically connect the redistribution layer and the wiring structure; the step of obtaining the layout image of each hardware unit layer by layer based on the determined effective layout image range includes:

[0021] The microbumps are photographed based on the determined effective layout image range of the bare chip to obtain the layout image of the microbumps;

[0022] The redistribution layer and the through-silicon via (TSV) are photographed based on the determined effective layout image range of the adapter board to obtain the layout images of the redistribution layer and the TSV.

[0023] The solder joints are photographed based on the determined effective layout image range of the adapter board to obtain the layout image of the solder joints;

[0024] The layout image of the wiring structure is obtained based on the determined effective layout image range of the substrate.

[0025] In one embodiment, obtaining the layout image of the three-dimensional integrated circuit structure based on the stitched pattern includes:

[0026] The layout image of the three-dimensional integrated circuit structure is obtained based on the spliced ​​pattern, the layout image of the microbumps, the layout image of the redistribution layer, the layout image of the through-silicon via, the layout image of the solder joint, and the layout image of the wiring structure.

[0027] In one embodiment, obtaining the layout image of the three-dimensional integrated circuit structure based on the splicing pattern, the layout image of the microbumps, the layout image of the redistribution layer, the layout image of the through-silicon via, the layout image of the solder joint, and the layout image of the wiring structure includes:

[0028] The layout images of the spliced ​​pattern, the micro-bumps, the redistribution layer, the through-silicon via, the solder joints, and the wiring structure are aligned to obtain the layout image of the three-dimensional integrated circuit structure.

[0029] The present invention also provides a layout image acquisition system for three-dimensional integrated circuit structures, the acquisition system comprising:

[0030] The first acquisition module is used to acquire the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units in the three-dimensional integrated circuit structure.

[0031] The second acquisition module, connected to the first acquisition module, is used to establish a coordinate system and acquire the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit.

[0032] The third acquisition module, connected to the second acquisition module, is used to acquire the layout image of each hardware unit based on the determined effective layout image range;

[0033] The splicing module is connected to the second acquisition module and the third acquisition module respectively, and splices the layout images of each hardware unit based on the coordinate information of each hardware unit to obtain a spliced ​​graphic;

[0034] An integration module is connected to the splicing module to obtain a layout image of the three-dimensional integrated circuit structure based on the spliced ​​graphic.

[0035] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the layout image acquisition method for the three-dimensional integrated circuit structure described in any of the above claims.

[0036] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the layout image acquisition method for the three-dimensional integrated circuit structure described in any of the preceding claims.

[0037] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the layout image acquisition method for the three-dimensional integrated circuit structure described in any of the above claims.

[0038] The present invention has the following beneficial effects:

[0039] The present invention discloses a method and system for acquiring layout images of a three-dimensional integrated circuit structure. The method acquires the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units within the structure. It establishes a coordinate system and acquires the coordinate information of each hardware unit within the coordinate system, determining the effective layout image range of each hardware unit to reduce redundant image data during the shooting, stitching, and alignment processes. Based on the determined effective layout image range, it acquires the layout images of each hardware unit. Based on the coordinate information of each hardware unit, it stitches the layout images of each hardware unit to obtain a stitched graphic. Based on the stitched graphic, it obtains the layout image of the three-dimensional integrated circuit structure. This method solves the problems of wasting time on high-precision shooting in redundant blank areas, generating large amounts of blank image data storage, increasing storage hardware costs and data processing difficulty, and increasing the difficulty of stitching and alignment of layout images within the same layer in invalid areas. This makes the acquisition of layout images of three-dimensional integrated circuit structures more efficient and accurate, improves the efficiency of chip layout image acquisition, and accelerates the process of integrated circuit intellectual property protection. Attached Figure Description

[0040] Figure 1 This is a flowchart illustrating a method for acquiring a layout image of a three-dimensional integrated circuit structure according to an embodiment of the present invention.

[0041] Figure 2 This is a flowchart illustrating the process of establishing a coordinate system and obtaining the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit in a method for obtaining a layout image of a three-dimensional integrated circuit structure in one embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram of the three-dimensional integrated circuit structure in a method for obtaining a layout image of a three-dimensional integrated circuit structure according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram illustrating the process of obtaining three-dimensional structural information of a three-dimensional integrated circuit structure based on the architecture of hardware units in the three-dimensional integrated circuit structure, according to an embodiment of the present invention.

[0044] Figure 5 This is a schematic flowchart illustrating the process of acquiring the layout image of a three-dimensional integrated circuit structure layer by layer based on a determined effective layout image range, according to an embodiment of the present invention.

[0045] Figure 6This is a schematic diagram of the coordinate system established in a method for acquiring layout images of a three-dimensional integrated circuit structure according to an embodiment of the present invention; wherein, region A is the effective layout image region of the substrate; region B is the effective layout image region of the adapter board; region C is the effective layout image region of one of the bare chips; region D is the effective layout image region of another bare chip; and region E is the effective layout image region of yet another bare chip.

[0046] Figure 7 This is a schematic diagram of a method for obtaining a layout image of a bare chip in a three-dimensional integrated circuit structure according to an embodiment of the present invention; wherein, region C is an effective layout image region of one of the bare chips;

[0047] Figure 8 This is a schematic diagram of the method for acquiring the layout image of a three-dimensional integrated circuit structure according to an embodiment of the present invention; wherein, region B is the effective layout image region of the adapter board;

[0048] Figure 9 This is a schematic diagram of a method for acquiring a layout image of a substrate surface using a three-dimensional integrated circuit structure layout image acquisition method according to an embodiment of the present invention; wherein, region A is the effective layout image region of the substrate;

[0049] Figure 10 This is a schematic diagram of a layout image acquisition system for a three-dimensional integrated circuit structure according to one embodiment of the present invention;

[0050] Figure 11 This is an internal structural diagram of a computer device according to one embodiment of the present invention.

[0051] Explanation of reference numerals in the attached figures:

[0052] 1. Substrate; 2. Solder joint; 3. Adapter board; 4. Redistribution layer; 5. Through-silicon via; 6. Microbump; 7. Bare chip; 11. First acquisition module; 12. Second acquisition module; 13. Third acquisition module; 14. Splicing module; 15. Integration module. Detailed Implementation

[0053] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0054] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0056] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0058] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0060] In recent years, integrated circuits, as the core of modern information equipment, possess extremely high intellectual property value. Therefore, to protect their own rights and avoid infringement of patented layout designs, it is necessary to determine the similarity between the layout of competing chips and the layout of their own chips. Three-dimensional integrated circuits employ discrete manufacturing and heterogeneous integration methods, improving the performance and optimal size of integrated circuits and systems, while also mitigating security issues such as integrated circuit counterfeiting and the insertion of hardware malware in the manufacturing supply chain. Since the cost of layer-by-layer imaging is related to the magnification of the image, obtaining high-resolution layouts of competing chips requires photographing bare chip layers using different process technologies in heterogeneous integration, necessitating expensive imaging equipment and data processing methods. The vertical interconnect structure and high integration of three-dimensional integrated circuits create greater technical obstacles in assessing patent infringement of competing chips, and also increase the time and financial costs of layout image extraction.

[0061] Based on the above problems, existing industrial imaging methods, when using scanning electron microscopy to image de-layered chips, produce images of the central portion of the bare chip containing numerous unpatterned areas. These redundant, blank unpatterned areas waste time and resources associated with high-precision imaging, generate substantial amounts of unpatterned image data for storage, increase storage hardware costs and data processing complexity, and further complicate the stitching and alignment of images within the same layer. Therefore, traditional methods for acquiring layout images of two-dimensional planar packaged integrated circuits can no longer meet the demands of acquiring layout images for large-scale three-dimensional integrated circuits.

[0062] To address the aforementioned technical problems, this invention presents a method and system for acquiring layout images of three-dimensional integrated circuit structures, enabling rapid and accurate acquisition of layout images of three-dimensional integrated circuit structures.

[0063] This invention designs a method for acquiring layout images of three-dimensional integrated circuit structures, such as... Figure 1 As shown, the method for obtaining the layout image of a three-dimensional integrated circuit structure includes:

[0064] S101: Obtain the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units in the three-dimensional integrated circuit structure;

[0065] S102: Establish a coordinate system and obtain the coordinate information of each hardware unit in the coordinate system in order to determine the effective layout image range of each hardware unit;

[0066] S103: Obtain the layout image of each hardware unit based on the determined effective layout image range;

[0067] S104: Based on the coordinate information of each hardware unit, the layout images of each hardware unit are stitched together to obtain a stitched graphic.

[0068] S105: Obtain the layout image of the three-dimensional integrated circuit structure based on the stitched graphics.

[0069] The present invention provides a method for acquiring layout images of three-dimensional integrated circuit structures. Based on the architecture of hardware units within the three-dimensional integrated circuit structure, it acquires the three-dimensional structural information of the three-dimensional integrated circuit structure, establishes a coordinate system and acquires the coordinate information of each hardware unit within the coordinate system, and determines the effective layout image range of each hardware unit. This reduces redundant image data during the shooting, stitching, and alignment processes of the three-dimensional integrated circuit layout. Based on the determined effective layout image range, it acquires the layout images of each hardware unit separately. Based on the coordinate information of each hardware unit, it stitches the layout images of each hardware unit to obtain a stitched graphic. Based on the stitched graphic, it obtains the layout image of the three-dimensional integrated circuit structure. This method solves the problems of wasting time on high-precision shooting in redundant blank areas, generating a large amount of blank image data storage, increasing storage hardware costs and data processing difficulty, and increasing the difficulty of stitching and alignment of layout images within the same layer in invalid areas. Therefore, it makes the acquisition of layout images of three-dimensional integrated circuit structures more efficient and accurate, improving the efficiency of chip layout image acquisition.

[0070] In one embodiment, such as Figure 2 As shown, a coordinate system is established, and the coordinate information of each hardware unit in the coordinate system is obtained to determine the effective layout image range of each hardware unit, including:

[0071] S201: Establish a coordinate system and determine the origin of the coordinate system;

[0072] S202: Determine the coordinates of the two diagonal points of each hardware unit in the coordinate system;

[0073] S203: Determine the effective layout image range of each hardware unit based on the coordinates of the two diagonal points of each hardware unit in the coordinate system.

[0074] In one embodiment, the three-dimensional integrated circuit structure further includes a molding compound layer, within which at least some hardware units are located. The molding compound layer may be an epoxy resin layer. Before determining the coordinates of the two diagonal points of each hardware unit in the coordinate system, the step of removing the molding compound layer to expose each hardware unit may also be included.

[0075] In one embodiment, obtaining the layout image of each hardware unit based on a determined effective layout image range includes the step of obtaining the layout image of each hardware unit layer by layer based on the determined effective layout image range.

[0076] In one embodiment, such as Figure 3 As shown, the hardware unit in the three-dimensional integrated circuit structure includes a bare chip 7, an adapter board 3, and a substrate 1. The substrate 1 is electrically connected to the adapter board 3, and the bare chip 7 is located on the side of the adapter board 3 facing away from the substrate 1. Figure 1 And see Figure 4 Obtaining the three-dimensional structural information of a three-dimensional integrated circuit structure based on the architecture of its hardware units includes:

[0077] S401: Architecture of hardware unit based on 3D X-ray imaging acquisition;

[0078] S402: Obtain the three-dimensional structural information of the three-dimensional integrated circuit structure based on the hardware unit architecture.

[0079] Continue reading Figure 3 In one embodiment, the three-dimensional integrated circuit structure further includes: microbumps 6, RDL (redistribution layer 4), through-silicon vias 5, solder joints 2, and wiring structures; the redistribution layer 4 is located on the opposite surface of the adapter plate 3; the through-silicon vias 5 are located within the adapter plate 3 and penetrate the adapter plate 3 along its thickness direction, and are connected to the redistribution layer 4 located on the opposite surface of the adapter plate 3; the microbumps 6 are located between the bare die 7 and the redistribution layer 4 to electrically connect the bare die 7 and the redistribution layer 4; the wiring structures are located on the surface of the substrate 1 adjacent to the adapter plate 3; the solder joints 2 are located between the substrate 1 and the redistribution layer 4 to electrically connect the redistribution layer 4 and the wiring structures; see reference Figures 1 to 4 and combined Figure 5 The layout image of each hardware unit is obtained layer by layer based on the determined effective layout image range, including:

[0080] S501: The microbump 6 is photographed based on the determined effective layout image range of the bare chip 7 to obtain the layout image of the microbump 6.

[0081] S502: Based on the determined effective layout image range of the adapter board 3, the redistribution layer 4 and through silicon via 5 are photographed to obtain the layout image of the redistribution layer 4 and the layout image of the through silicon via 5.

[0082] S503: Take a picture of solder joint 2 based on the determined effective layout image range of adapter board 3 to obtain the layout image of solder joint 2;

[0083] S504: Obtain a layout image of the wiring structure based on the determined effective layout image range of substrate 1.

[0084] Specifically, layer-by-layer imaging can be performed by photographing one layer and then removing it to make it easier to photograph the next layer. For example, after photographing the bare chip 7, the bare chip 7 can be removed by processes such as grinding to expose the microbumps 6. The adapter board 3, through-silicon vias 5, solder joints 2, etc. are photographed layer by layer in sequence.

[0085] It should be noted that the layout image acquisition method of the three-dimensional integrated circuit structure of the present invention is not limited to the three-dimensional integrated circuit structure in the above embodiments, but can also be used for all other types of three-dimensional integrated circuit structures. The circuit structure presented in the above embodiments is not intended to limit the scope of application of the present invention.

[0086] In one embodiment, obtaining a layout image of a three-dimensional integrated circuit structure based on a stitched pattern includes the steps of obtaining a layout image of a three-dimensional integrated circuit structure based on a stitched pattern, a layout image of a microbump 6, a layout image of a redistribution layer 4, a layout image of a through-silicon via 5, a layout image of a solder joint 2, and a layout image of a wiring structure.

[0087] In one embodiment, obtaining a layout image of a three-dimensional integrated circuit structure based on the layout images of the spliced ​​pattern, the microbump 6, the redistribution layer 4, the through-silicon via 5, the solder joint 2, and the wiring structure includes the step of aligning the spliced ​​pattern, the microbump 6, the redistribution layer 4, the through-silicon via 5, the solder joint 2, and the wiring structure to obtain the layout image of the three-dimensional integrated circuit structure.

[0088] Specifically, image alignment includes aligning the image using multiple positioning points. These positioning points include those determined by the positional relationship between the die and the microbump 6, the positional relationship between the microbump 6 and the silicon substrate, the positional relationship between the silicon substrate and the solder joint 2, and the positional relationship between the solder joint 2 and the substrate 1. For ease of use, the positioning point data can be organized into coordinate points along the z-axis.

[0089] Specifically, the three-dimensional structural information includes the number and size of bare chips 7, the overall layout of interconnects of silicon interposer boards 3, etc.

[0090] Specifically, the bare chip 7 may include, but is not limited to: FPGA (Field-Programmable Gate Array) bare chip, processor chip, reduced instruction set computer chip, digital signal processing technology chip, memory chip, interface circuit chip, digital-to-analog converter chip, AI chip, or radio frequency chip.

[0091] Specifically, the material of the redistribution layer 4 may include, but is not limited to, copper, aluminum or gold; the material of the microbumps 6 may include, but is not limited to, aluminum, tin, aluminum-tin alloy, copper-tin alloy, nickel or silver; and the material of the solder joints 2 may include, but is not limited to, nickel, gold, copper or solder alloy.

[0092] In one embodiment, the through-silicon via 5 includes an annular isolation layer, the material of which may include, but is not limited to, silicon dioxide, benzocyclobutene, or polyimide resin; the through-silicon via 5 also includes a filling material, the filling material may include, but is not limited to, copper, aluminum, or tungsten; the shape of the filling material may be cylindrical.

[0093] In one embodiment, before establishing a coordinate system and obtaining the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit, the method further includes cutting and polishing the vertical cross-section of the three-dimensional integrated circuit structure and photographing the cross-sectional image to collect the cross-sectional information of the three-dimensional integrated circuit in the z-axis direction, so as to obtain the process and material information of each hardware unit of the layout of the three-dimensional integrated circuit structure. Specifically, the process information mainly includes process type and process size, etc.; specifically, the process information includes the process information of the bare die 7, the process information of the through-silicon via 5, etc.; the process information of the bare die 7 may include, but is not limited to, CMOS (Complementary Metal-Oxide-Semiconductor) process, BiCMOS process, SiN process and GaAs process; the process information of the through-silicon via 5 may include, but is not limited to, pre-via process and post-via process; the process size includes the material and thickness of the substrate 1, the thickness of the adapter plate 3, the thickness of the redistribution layer 4, the diameter of the through-silicon via 5, the solder joint 2 and the micro-bump 6, the thickness of the annular isolation layer of the through-silicon via 5, and the height and diameter of the metal pillar of the filling material of the through-silicon via 5.

[0094] For ease of understanding, in one embodiment, the three-dimensional integrated circuit structure can be a silicon stacked interconnect FPGA structure, and a schematic diagram of the silicon stacked interconnect FPGA structure is still referred to. Figure 3In this embodiment, the bare chip 7 is an FPGA bare chip, and the adapter board 3 is a silicon adapter board. The layout image acquisition method of the three-dimensional integrated circuit structure of the present invention is used to acquire the layout of this silicon stacked interconnect FPGA structure. The hardware unit of the silicon stacked interconnect FPGA structure includes the bare chip 7, micro bumps 6, redistribution layer 4, adapter board 3, solder joints 2 and substrate 1.

[0095] See Figure 3 The silicon stacked interconnect FPGA structure, from top to bottom, consists of: a bare die 7, microbumps 6, through-silicon vias 5, a redistribution layer 4, an adapter plate 3, solder joints 2, and a substrate 1. The redistribution layer 4 is located on the opposite surface of the adapter plate 3. The through-silicon vias 5 are located within the adapter plate 3, penetrating the adapter plate 3 along its thickness direction, and are connected to the redistribution layer 4 located on the opposite surface of the adapter plate 3. The microbumps 6 are located between the bare die 7 and the redistribution layer 4 to electrically connect the bare die 7 and the redistribution layer 4. The wiring structure is located on the surface of the substrate 1 adjacent to the adapter plate 3. The solder joints 2 are located between the substrate 1 and the redistribution layer 4 to electrically connect the redistribution layer 4 and the wiring structure. In this embodiment, the steps for obtaining the layout image of this silicon stacked interconnect FPGA structure using the layout image acquisition method of the present invention are as follows:

[0096] Step 1: Use 3D X-ray imaging to obtain the architecture of bare chip 7, microbumps 6, first wiring layer 4, silicon interposer 3, second wiring layer 4, solder joint 2 and substrate 1. Based on the architecture of these hardware units, obtain the three-dimensional structural information of the silicon stacked interconnect FPGA structure. The three-dimensional structural information includes the number and size of bare chips 7, the overall layout of the interconnect of interposer 3, etc.

[0097] Step 2: Cut and polish the vertical cross-section of the silicon stacked interconnect FPGA structure, and photograph the cross-sectional image to collect the z-axis profile information to obtain the process and material information of each hardware unit of the silicon stacked interconnect FPGA structure; the process information mainly includes process type and process dimensions, etc.; specifically, in this embodiment, the silicon vias 5 include both silicon vias 5 obtained by the pre-via process and silicon vias 5 obtained by the post-via process; the adapter board 3 is a silicon adapter board 3;

[0098] Step 3: Establish a coordinate system and obtain the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit. First, establish a coordinate system and determine the origin of the coordinate system. Second, determine the coordinates of the two diagonal points of each hardware unit in the coordinate system. Then, determine the effective layout image range of each hardware unit based on the coordinates of the two diagonal points of each hardware unit in the coordinate system.

[0099] like Figure 6As shown, the coordinates of the two diagonal points of substrate 1 are (x1, y1) and (x2, y2), and the effective layout image range of substrate 1 is region A composed of (x1, y1) and (x2, y2); the coordinates of the two diagonal points of adapter board 3 are (x3, y3) and (x4, y4), and the effective layout image range of adapter board 3 is region B composed of (x3, y3) and (x4, y4); the coordinates of the two diagonal points of one of the bare chips 7 are (x5, y5) and (x6, y6), and the effective layout image range of bare chip 7 is region C composed of (x5, y5) and (x6, y6), with a length of (y6-y5) and a width of (x6-x5); similarly, the effective layout image ranges of bare chips 7 at other locations can be as follows. Figure 6 Regions D and E are shown in the diagram.

[0100] Step 4: Based on the determined effective layout image range, obtain the layout image of each hardware unit layer by layer; such as... Figure 7 The diagram shown is a schematic of obtaining the layout image of bare chip 7; as shown Figure 8 The diagram shown is a schematic of obtaining the layout image of adapter board 3; as shown Figure 9 The diagram shows a schematic of obtaining a layout image of the surface of substrate 1. In this process, a layer-by-layer shooting method is used. For example, after shooting the bare chip 7, the bare chip 7 can be removed by grinding and other processes to expose the microbumps 6. Subsequently, the adapter board 3, through silicon vias 5, solder joints 2, etc. are shot layer by layer.

[0101] Step 5: Based on the coordinate information of each hardware unit, stitch together the layout images of each hardware unit to obtain a stitched graphic; align the stitched graphic with the layout images of each hardware unit to obtain a layout image of the three-dimensional integrated circuit structure; for example, multiple positioning points can be used to align the layout image, such as the positioning points determined by the positional relationship between the die and the microbump 6, the positioning points determined by the positional relationship between the microbump 6 and the silicon substrate, the positioning points determined by the positional relationship between the silicon substrate and the solder joint 2, and the positioning points determined by the positional relationship between the solder joint 2 and the substrate 1.

[0102] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0103] Based on the same inventive concept, the present invention also provides a layout image acquisition system for three-dimensional integrated circuit structures. The solution provided by this system is similar to the solution described in the above-mentioned layout image acquisition method for three-dimensional integrated circuit structures. Therefore, the specific limitations in the embodiments of the layout image acquisition system for three-dimensional integrated circuit structures provided below can be found in the limitations of the layout image acquisition method for three-dimensional integrated circuit structures described above, and will not be repeated here.

[0104] like Figure 10 As shown, the present invention also provides a layout image acquisition system for a three-dimensional integrated circuit structure, the acquisition system comprising:

[0105] The first acquisition module 11 is used to acquire the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units in the three-dimensional integrated circuit structure.

[0106] The second acquisition module 12 is connected to the first acquisition module 11 and is used to establish a coordinate system and acquire the coordinate information of each hardware unit in the coordinate system in order to determine the effective layout image range of each hardware unit.

[0107] The third acquisition module 13 is connected to the second acquisition module 12 and is used to acquire the layout image of each hardware unit based on the determined effective layout image range.

[0108] The splicing module 14 is connected to the second acquisition module 12 and the third acquisition module 13 respectively. It splices the layout images of each hardware unit based on the coordinate information of each hardware unit to obtain the spliced ​​graphic.

[0109] The integration module 15 is connected to the splicing module 14 to obtain a layout image of the three-dimensional integrated circuit structure based on the spliced ​​graphics.

[0110] Each module in the above-described layout image acquisition system for three-dimensional integrated circuit structures can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0111] The present invention discloses a method and system for acquiring layout images of a three-dimensional integrated circuit structure. The method acquires the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units within the structure. It establishes a coordinate system and acquires the coordinate information of each hardware unit within the coordinate system, determining the effective layout image range of each hardware unit to reduce redundant image data during the shooting, stitching, and alignment processes. Based on the determined effective layout image range, the method acquires the layout images of each hardware unit separately. Based on the coordinate information of each hardware unit, the layout images of each hardware unit are stitched together to obtain a stitched graphic. Based on the stitched graphic, the layout image of the three-dimensional integrated circuit structure is obtained. This method solves the problems of wasting time on high-precision shooting in redundant blank areas, generating a large amount of blank image data storage, increasing storage hardware costs and data processing difficulty, and increasing the difficulty of stitching and alignment of layout images within the same layer due to invalid areas. Furthermore, the layout image acquisition system for the three-dimensional integrated circuit structure of the present invention acquires the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units in the three-dimensional integrated circuit structure through the first acquisition module 11, establishes a coordinate system and acquires the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit, acquires the layout image of each hardware unit based on the determined effective layout image range through the third acquisition module 13, stitches the layout images of each hardware unit based on the coordinate information of each hardware unit to obtain a stitched graphic, and obtains the layout image of the three-dimensional integrated circuit structure based on the stitched graphic through the integration module 15. This makes the acquisition of the layout image of the three-dimensional integrated circuit structure more efficient and accurate, improves the efficiency of chip layout image acquisition, and accelerates the process of integrated circuit intellectual property protection.

[0112] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 11As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a method for acquiring a layout image of a three-dimensional integrated circuit structure. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0113] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0114] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method for acquiring the layout image of the three-dimensional integrated circuit structure described above.

[0115] The present invention also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the method for acquiring a layout image of a three-dimensional integrated circuit structure as described above.

[0116] The present invention also provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, it implements the steps of the method for acquiring a layout image of a three-dimensional integrated circuit structure as described above.

[0117] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method of acquiring a layout image of a three-dimensional integrated circuit structure, characterized by, The method for obtaining the layout image of the three-dimensional integrated circuit structure comprises the following steps: Obtaining the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of hardware units in the three-dimensional integrated circuit structure; the hardware units comprise a bare chip, a conversion board and a substrate, the substrate is electrically connected with the conversion board, and the bare chip is located on the side of the conversion board away from the substrate; the three-dimensional integrated circuit structure further comprises a micro bump, a rewiring layer, a through silicon via, a welding point and a wiring structure; the rewiring layer is located on the opposite surface of the conversion board; the through silicon via is located in the conversion board and penetrates the conversion board along the thickness direction and is connected with the rewiring layer located on the opposite surface of the conversion board; the micro bump is located between the bare chip and the rewiring layer to electrically connect the bare chip and the rewiring layer; the wiring structure is located on the surface of the substrate adjacent to the conversion board; the welding point is located between the substrate and the rewiring layer to electrically connect the rewiring layer and the wiring structure; the orthographic projection of the bare chip towards the substrate covers the orthographic projection of the micro bump towards the substrate, and the orthographic projection of the conversion board towards the substrate covers the orthographic projections of the rewiring layer, the through silicon via and the welding point towards the substrate respectively; Cutting and polishing the vertical section of the three-dimensional integrated circuit structure and shooting the section pattern to collect the section information of the three-dimensional integrated circuit in the z-axis direction to obtain the process and material information of each hardware unit of the layout of the three-dimensional integrated circuit structure; Establishing a coordinate system and obtaining the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit; Obtaining the layout image of each hardware unit layer by layer based on the determined effective layout image range; shooting the micro bump based on the determined effective layout image range of the bare chip to obtain the layout image of the micro bump; shooting the rewiring layer and the through silicon via based on the determined effective layout image range of the conversion board to obtain the layout image of the rewiring layer and the layout image of the through silicon via; shooting the welding point based on the determined effective layout image range of the conversion board to obtain the layout image of the welding point; obtaining the layout image of the wiring structure based on the determined effective layout image range of the substrate; Splicing the layout images of each hardware unit based on the coordinate information of each hardware unit to obtain a spliced pattern; Image alignment based on the spliced pattern and the layout images of each hardware unit to obtain the layout image of the three-dimensional integrated circuit structure.

2. The layout image acquisition method of a three-dimensional integrated circuit structure according to claim 1, characterized by, The method for obtaining the layout image of the three-dimensional integrated circuit structure comprises the following steps: Establishing a coordinate system and determining the coordinate system origin; Determine the coordinates of the opposite two points of each hardware unit in the coordinate system; Determining the effective layout image range of each hardware unit based on the coordinates of the opposite two points of each hardware unit in the coordinate system.

3. The layout image acquisition method of a three-dimensional integrated circuit structure according to claim 2, characterized by, The architecture of the hardware unit in the three-dimensional integrated circuit structure is used to obtain the three-dimensional structure information of the three-dimensional integrated circuit structure, which comprises: obtaining the architecture of the hardware unit based on 3D X-ray imaging; obtaining the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit.

4. The layout image acquisition method of a three-dimensional integrated circuit structure according to Claim 1, wherein The three-dimensional integrated circuit structure based on the stitching pattern comprises: obtaining the layout image of the three-dimensional integrated circuit structure based on the stitching pattern, the layout image of the micro-bump, the layout image of the re-wiring layer, the layout image of the through-silicon via, the layout image of the solder joint and the layout image of the wiring structure.

5. The layout image acquisition method of a three-dimensional integrated circuit structure according to claim 4, characterized by, The three-dimensional integrated circuit structure based on the stitching pattern, the layout image of the micro-bump, the layout image of the re-wiring layer, the layout image of the through-silicon via, the layout image of the solder joint and the layout image of the wiring structure comprises: image alignment of the stitching pattern, the layout image of the micro-bump, the layout image of the re-wiring layer, the layout image of the through-silicon via, the layout image of the solder joint and the layout image of the wiring structure to obtain the layout image of the three-dimensional integrated circuit structure.

6. A layout image acquisition system of a three-dimensional integrated circuit structure, characterized by comprising: The acquisition system comprises: a first acquisition module for obtaining the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit in the three-dimensional integrated circuit structure; cutting and polishing the vertical section of the three-dimensional integrated circuit structure and taking a section pattern, collecting the profile information of the three-dimensional integrated circuit in the z-axis direction to obtain the process and material information of each hardware unit of the layout of the three-dimensional integrated circuit structure; the hardware unit comprises a bare chip, a conversion board and a substrate, the substrate is electrically connected with the conversion board, and the bare chip is located on the side of the conversion board away from the substrate; the three-dimensional integrated circuit structure further comprises a micro-bump, a re-wiring layer, a through-silicon via, a solder joint and a wiring structure; the re-wiring layer is located on the opposite surface of the conversion board; the through-silicon via is located in the conversion board and penetrates the conversion board along the thickness direction and is connected with the re-wiring layer located on the opposite surface of the conversion board; the micro-bump is located between the bare chip and the re-wiring layer to electrically connect the bare chip and the re-wiring layer; the wiring structure is located on the surface of the substrate adjacent to the conversion board; the solder joint is located between the substrate and the re-wiring layer to electrically connect the re-wiring layer and the wiring structure; the orthographic projection of the bare chip towards the substrate covers the orthographic projection of the micro-bump towards the substrate, and the orthographic projection of the conversion board towards the substrate covers the orthographic projection of the re-wiring layer, the through-silicon via and the solder joint towards the substrate, respectively; a second acquisition module connected with the first acquisition module, for establishing a coordinate system and obtaining the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit. A third acquisition module, connected with the second acquisition module, is configured to acquire the layout images of the hardware units layer by layer based on the determined effective layout image range of each hardware unit, acquire the layout image of the micro-bump based on the determined effective layout image range of the die, acquire the layout images of the re-wiring layer and the through-silicon via based on the determined effective layout image range of the adapter board, acquire the layout image of the solder joint based on the determined effective layout image range of the adapter board, and acquire the layout image of the wiring structure based on the determined effective layout image range of the substrate. A splicing module, connected with the second acquisition module and the third acquisition module, is configured to splice the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced image. An integration module, connected with the splicing module, is configured to perform image alignment based on the spliced image and the layout images of the hardware units to obtain the layout image of the three-dimensional integrated circuit structure. 7.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-6 when the computer program is executed by the processor. The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 5.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 5.

9. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 5.

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