Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, a gate structure, a gate capping layer, sidewalls, source / drain doped regions, a bottom dielectric layer, a source / drain contact layer, and a source / drain capping layer; forming a top dielectric layer on the bottom dielectric layer, covering the gate capping layer, the source / drain capping layer, and the sidewalls; forming source / drain vias penetrating the top dielectric layer and the source / drain capping layer in a first region, exposing the top surface of the source / drain contact layer; forming a gate via penetrating the top dielectric layer and the gate capping layer in a second region, exposing the top surface of the gate structure; wherein, in the step of forming any one or both of the source / drain vias and the gate vias, a portion of the height of the sidewalls in the corresponding region is removed to form an etch barrier layer located on the sidewall of the corresponding via and covering the top of the sidewall; and forming a gate plug in the gate via and a source / drain plug in the source / drain via. Embodiments of this invention are beneficial for improving the performance of semiconductor structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped regions for connecting the source / drain doped regions to external circuitry.

[0004] Currently, to further reduce transistor area, the ContactOver Active Gate (COAG) process has been introduced. Compared to traditional gate contact plugs located above the gate structure in the isolation region, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving chip area.

[0005] However, devices manufactured using the COAG process still suffer from poor performance. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a first region for forming source / drain plugs and a second region for forming gate plugs; a gate structure disposed on the substrate; a gate cap layer located on top of the gate structure; sidewalls located on the sidewalls of the gate structure and the gate cap layer; source / drain doped regions located in the substrate on both sides of the gate structure; a bottom dielectric layer located on the side of the gate structure and covering the source / drain doped regions; a source / drain contact layer located in the bottom dielectric layer and in contact with the source / drain doped regions; and a source / drain cap. A cap layer is located on top of the source / drain contact layer; a top dielectric layer is located on the bottom dielectric layer and covers the gate cap layer, source / drain cap layer, and sidewalls; a source / drain plug penetrates the top dielectric layer and source / drain cap layer in the first region, and the source / drain plug contacts the top of the source / drain contact layer; a gate plug penetrates the top dielectric layer and gate cap layer in the second region, and the gate plug contacts the top of the gate structure; an etch barrier layer is located on the sidewalls of any one or both of the source / drain plugs and the gate plug, and covers the top surface of the sidewalls of the corresponding region.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a first region for forming source / drain plugs and a second region for forming gate plugs; a discrete gate structure is formed on the substrate, a gate capping layer is formed on the top of the gate structure, sidewalls are formed on the sidewalls of the gate structure and the gate capping layer, source / drain doped regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer covering the source / drain doped regions is formed on the side of the gate structure, a source / drain contact layer in contact with the source / drain doped regions is formed in the bottom dielectric layer, and a source / drain capping layer is formed on the top of the source / drain contact layer; A top dielectric layer is formed on the bottom dielectric layer, covering the gate cap layer, the source / drain cap layer, and the sidewalls; a source / drain via is formed penetrating the top dielectric layer and the source / drain cap layer of the first region, exposing the top surface of the source / drain contact layer; a gate via is formed penetrating the top dielectric layer and the gate cap layer of the second region, exposing the top surface of the gate structure; wherein, in the step of forming any one or both of the source / drain vias and the gate vias, a portion of the height of the sidewalls in the corresponding region is removed to form an etch barrier layer located on the sidewall of the corresponding via and covering the top of the sidewall; a gate plug located in the gate via and a source / drain plug located in the source / drain via are formed.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure formation method provided by this invention, in the step of forming any one or both of the source / drain vias and gate vias, a portion of the height sidewall in the corresponding region is removed to form an etch barrier layer located on the sidewall of the corresponding via and covering the top of the sidewall. By replacing the portion of the height sidewall in the corresponding region with the etch barrier layer, which has a stronger etch barrier capability, a film layer with a high etch selectivity ratio is introduced, where the materials of the source / drain capping layer, the gate capping layer, and the sidewalls are all high. With the direction parallel to the substrate and perpendicular to the extension direction of the gate structure as the lateral direction, in the step of forming the source / drain via or the gate via, the etch barrier layer can act as an etch barrier along the lateral direction and protect the sidewall. Alternatively, the etch barrier layer can occupy part of the space where the original sidewall was located, which helps prevent weak points from being generated at the corner of the top surface of the sidewall in the corresponding region. After the source / drain plugs and gate plugs are formed, the etch barrier layer can isolate the source / drain plugs from the adjacent gate structure or from the gate plugs to the adjacent source / drain contact layers, thereby reducing the probability of bridging or breakdown between the source / drain plugs and the adjacent gate structure or between the gate plugs and the adjacent source / drain contact layers, and thus improving the performance of the semiconductor structure.

[0011] Furthermore, in the semiconductor structure formation method provided in this embodiment of the invention, in the step of forming any one or both of the source / drain vias and gate vias, a portion of the height sidewalls in the corresponding region is removed to form an etch barrier layer located on the sidewall of the corresponding via and covering the top of the sidewall. This allows the etch barrier layer to be formed only in the region where the source / drain via or gate via needs to be formed. This not only facilitates the integration of the process of forming the source / drain via or gate via with the process steps of removing the portion of the height sidewalls in the corresponding region and forming the etch barrier layer, but also helps to reduce the impact on the film structure of other regions, thereby improving process compatibility and reducing process risks.

[0012] The semiconductor structure provided in this embodiment of the invention includes an etch barrier layer located on the sidewall of any one or both of the source / drain plugs and gate plugs, and covering the top surface of the sidewall in the corresponding region. The etch barrier layer acts as an etch barrier along the lateral direction, parallel to the substrate and perpendicular to the extension direction of the gate structure. During the formation of the source / drain plug or gate plug, it is usually necessary to first form a source / drain via or gate via in the corresponding region. The etch barrier layer serves to act as an etch barrier in the step of forming the source / drain via or gate via, and also protects the sidewall. Alternatively, the etch barrier layer can occupy part of the space where the original sidewall was located, which helps prevent weak points from being generated at the corners of the top surface of the sidewall in the corresponding region. Furthermore, the etch barrier layer can isolate the source / drain plug from the adjacent gate structure, or from the gate plug to the adjacent source / drain contact layer, thereby reducing the probability of bridging or breakdown between the source / drain plug and the adjacent gate structure, or between the gate plug and the adjacent source / drain contact layer, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0013] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] Figures 4 to 5 This is a schematic diagram of the structure corresponding to each step in another method of forming a semiconductor structure;

[0015] Figures 6 to 26 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] Devices fabricated using the COAG process still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0017] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] refer to Figure 1 A substrate 1 is provided, on which a gate structure 2 is formed. A gate capping layer 3 is formed on the top surface of the gate structure 2. Sidewalls 4 are formed on the sidewalls of the gate structure 2 and the gate capping layer 3. Source and drain doped regions 5 are formed in the substrate 1 on both sides of the gate structure 2 and the sidewalls 4. A bottom dielectric layer (not shown in the figure) covering the source and drain doped regions 5 is formed on the exposed substrate 1 of the gate structure 2. The bottom dielectric layer is exposed on the top surface of the gate capping layer 3. A source and drain contact layer 6 is formed in the bottom dielectric layer that contacts the source and drain doped regions 5. The sidewalls of the source and drain contact layer 6 are in contact with the sidewalls 4.

[0019] refer to Figure 2 Remove a portion of the thickness of the source / drain contact layer 6 and the sidewall 4, and form a source / drain capping layer 7 on the source / drain contact layer 6. The sidewall of the source / drain capping layer 7 is in contact with the gate capping layer 3, and the source / drain capping layer 7 covers the top of the sidewall 4 and the source / drain contact layer 6.

[0020] refer to Figure 3 A top dielectric layer 8 is formed that covers the bottom dielectric layer 6, the gate cap layer 3, and the source / drain cap layer 7; a source / drain plug 9 is formed that penetrates the source / drain cap layer 7 and the top dielectric layer 8 and is in contact with the source / drain contact layer 6.

[0021] In the above-described method of forming the source / drain plug 9, a source / drain via is first formed, penetrating the source / drain cap layer 7 and the top dielectric layer 8 and exposing the source / drain contact layer 6. Then, the source / drain plug 9 is formed within the via. To ensure that the via exposes the top surface of the source / drain contact layer 6, and to ensure a sufficiently large contact area between the source / drain plug 9 and the source / drain contact layer 6, over-etching is typically performed during the formation of the via. During over-etching, the sidewalls 4 located on the sidewalls of the source / drain contact layer 7 are easily etched, potentially creating weak points at the top corners of the sidewalls 4 (e.g.,...). Figure 3 As shown by the dotted coil in the middle, the source-drain plug 9 is prone to bridging or breakdown with the gate structure 2 at weak points, which can easily reduce the performance of the semiconductor structure and the manufacturing yield.

[0022] Another method for forming semiconductor structures has been proposed. Figures 4 to 5 This is a schematic diagram of the steps in another method for forming a semiconductor structure. The similarities between this method and the previously described method will not be repeated; the differences are as follows:

[0023] refer to Figure 4 Remove a portion of the source / drain contact layer 6a of thickness and form a source / drain cap layer 7a on the source / drain contact layer 6a. The sidewall of the source / drain cap layer 7a is in contact with the sidewall of the sidewall 4a.

[0024] refer to Figure 5 A top dielectric layer 8a is formed that covers the bottom dielectric layer (not shown), the gate cap layer 3a, and the source / drain cap layer 7a; a gate plug 9a is formed that penetrates the gate cap layer 3a and the top dielectric layer 8a and is in contact with the gate structure 2a.

[0025] In the above formation method, the gate plug 9a is in contact with the gate structure 2a of the active region. The gate plug 9a is an active gate contact hole plug (COAG). During the removal of a portion of the source / drain contact layer 6a, only a portion of the source / drain contact layer 6a is removed, without etching the sidewall 4a, thus allowing the sidewall of the source / drain capping layer 7a to contact the sidewall of the sidewall 4a. During the formation of the source / drain plug (not shown), the sidewall 4a covers the sidewall of the source / drain contact layer 6a, minimizing weak points. The sidewall 4a also serves as an isolation point between the gate structure 2a and the source / drain plug.

[0026] However, in the process of forming the gate plug 9a, the above method requires first forming a gate via (not shown) that penetrates the gate cap layer 3a and the top dielectric layer 8a and exposes the gate structure 2a. Then, the gate plug 9a is formed in the gate via. To ensure that the gate via exposes the top surface of the gate structure 2a so that the gate plug 9a has a sufficiently large contact area with the gate structure 2a, over-etching is usually performed during the formation of the gate via. During the over-etching process, the sidewalls 4a located on the sidewalls of the gate cap layer 3a and the gate structure 2a are easily etched, which can easily lead to bridging or breakdown between the gate plug 9a and the source / drain contact layer 6a (e.g., Figure 5 (As shown at the position of the dotted coil in the middle), this leads to poor performance of the semiconductor structure and reduced production yield.

[0027] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure. This method involves replacing a portion of the sidewalls in a corresponding region with an etch-blocking layer that offers stronger etch resistance. This introduces a film layer with a high etch selectivity compared to the source / drain capping layer, gate capping layer, and sidewalls. With the direction parallel to the substrate and perpendicular to the extension direction of the gate structure as the lateral direction, the etch-blocking layer acts as an etch barrier along this lateral direction during the formation of source / drain vias or gate vias, protecting the sidewalls. Alternatively, the etch-blocking layer can occupy part of the space previously occupied by the sidewalls, preventing weak points at the corners of the sidewall top surfaces in the corresponding region. After forming source / drain plugs and gate plugs, the etch-blocking layer isolates the source / drain plugs from adjacent gate structures or from adjacent source / drain contact layers, thereby reducing the probability of bridging or breakdown between the source / drain plugs and adjacent gate structures or between the gate plugs and adjacent source / drain contact layers, ultimately improving the performance of the semiconductor structure.

[0028] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figures 6 to 26 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0030] refer to Figure 6 and Figure 7 , Figure 6 This is a top view. Figure 7 for Figure 6 A cross-sectional view along the xx-sec line shows a substrate 100 including a first region 100a for forming source / drain plugs and a second region 100b for forming gate plugs. A discrete gate structure 110 is formed on the substrate 100. A gate capping layer 120 is formed on the top of the gate structure 110. Sidewalls 130 are formed on the sidewalls of the gate structure 110 and the gate capping layer 120. Source / drain doped regions 140 are formed in the substrate 100 on both sides of the gate structure 110. A bottom dielectric layer (not shown) covering the source / drain doped regions 140 is formed on the side of the gate structure 110. A source / drain contact layer 150 in contact with the source / drain doped regions 140 is formed in the bottom dielectric layer. A source / drain capping layer 160 is formed on the top of the source / drain contact layer 150.

[0031] The substrate 100 is used to provide a process platform for subsequent process fabrication. In this embodiment, the substrate 100 is used to form a fin field-effect transistor (FinFET).

[0032] In this embodiment, the substrate 100 is a three-dimensional substrate, including a substrate (not shown) and fins (not shown) protruding from the substrate. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate. In this embodiment, the substrate is a silicon substrate, and the fins are made of the same material as the substrate.

[0033] When the device is in operation, the gate structure 110 is used to control the opening or closing of the conductive channel.

[0034] In this embodiment, the gate structure 110 is located on the substrate, spanning the fin and covering part of the top surface and part of the sidewalls of the fin. In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the high-k gate dielectric layer.

[0035] The gate cap layer 120 serves to protect the top of the gate structure 110 during the formation of the source / drain contact layer 150 and the subsequent formation of the source / drain plug.

[0036] The gate cap layer 120 is made of a material that exhibits etching selectivity compared to the source / drain cap layer 160, the bottom dielectric layer, and the subsequent top dielectric layer. This helps ensure that the gate cap layer 120 effectively protects the gate structure 110. In this embodiment, the material of the gate cap layer 120 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 120 is silicon nitride.

[0037] Sidewall 130 is used to define the formation region of source / drain doped region 140, and sidewall 130 is also used to protect the sidewall of gate structure 110.

[0038] In this embodiment, the sidewall 130 is made of one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, and low-k dielectric materials. As an example, the sidewall 130 is made of a low-k dielectric material, which helps to reduce the effective capacitance between the gate structure 110 and the source / drain contact layer 150.

[0039] The source / drain doped region 140 is used to provide a carrier source. In this embodiment, the source / drain doped region 140 is also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped region 140 is located in the fins on both sides of the gate structure 110 and the sidewall 130.

[0040] When forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions.

[0041] The bottom dielectric layer is used to achieve isolation between adjacent devices, and the bottom dielectric layer is also used to achieve electrical isolation between the source and drain contact layers 150.

[0042] In this embodiment, the bottom dielectric layer is an interlayer dielectric (ILD). The material of the bottom dielectric layer is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the bottom dielectric layer is silicon oxide.

[0043] The source / drain contact layer 150 contacts the source / drain doped region 140, enabling electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures. In this embodiment, the source / drain contact layer 150 is made of copper. In other embodiments, the source / drain contact layer may also be made of conductive materials such as tungsten or cobalt.

[0044] Subsequently, a gate plug is formed that contacts the gate structure 110. The source-drain capping layer 160 is located on the top surface of the source-drain contact layer 150. During the formation of the gate plug, the source-drain capping layer 160 can protect the source-drain contact layer 150.

[0045] The source / drain capping layer 160 is made of a material with high etching selectivity to the gate capping layer 120, the bottom dielectric layer and the subsequent top dielectric layer, thereby ensuring that the source / drain capping layer 160 can protect the source / drain contact layer 150.

[0046] The source / drain capping layer 160 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. Specifically, the source / drain capping layer 160 and the gate capping layer 120 are made of different materials. As an example, the source / drain capping layer 160 is made of silicon carbide.

[0047] refer to Figure 8 and Figure 9 , Figure 8 This is a top view. Figure 9 for Figure 8 A cross-sectional view along the xx secant line shows a top dielectric layer 170 formed on the bottom dielectric layer, covering the gate cap layer 120, the source / drain cap layer 160, and the sidewall 130.

[0048] The material of the top dielectric layer 170 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric material, and ultra-low-k dielectric material.

[0049] refer to Figures 10 to 11 , Figure 10 This is a top view. Figure 11 for Figure 10 A cross-sectional view along the xx-cut line shows that the method of forming the semiconductor structure further includes: after forming the top dielectric layer 170 and before forming the source / drain vias and the gate vias, forming an interconnect trench 300 that penetrates a portion of the thickness of the top dielectric layer 170, the interconnect trench 300 being located above the first region 100a and the second region 100b.

[0050] The interconnect slot 300 is used to provide spatial location for forming interconnect lines.

[0051] In this embodiment, before forming the source / drain via and the gate via, an interconnect trench 300 is formed with the extension direction perpendicular to the interconnect trench 300 as the longitudinal direction. Correspondingly, in the subsequent steps of forming the source / drain via and the gate via, the source / drain via and the gate via are located at the bottom of the interconnect trench. The source / drain via and the gate via can be self-aligned with the interconnect trench 300 in the longitudinal direction. Moreover, the source / drain via and the gate via can communicate with the interconnect trench 300. After forming the source / drain plug, the gate plug, and the interconnect, the source / drain plug, the gate plug, and the interconnect can be an integral structure, which is beneficial to improving the contact performance between the source / drain plug and the interconnect, and between the gate plug and the interconnect.

[0052] In this embodiment, the interconnecting groove 300 is located above the first region 100a and the second region 100b.

[0053] refer to Figures 10 to 17 A source / drain via 210 is formed, penetrating the top dielectric layer 170 and the source / drain cap layer 160 of the first region 100a, exposing the top surface of the source / drain contact layer 150.

[0054] refer to Figures 18 to 24 A gate via 220 is formed through the top dielectric layer 170 and the gate cap layer 120 of the second region 100b, exposing the top surface of the gate structure 110.

[0055] In the step of forming one or both of the source / drain vias 210 and the gate vias 220, a portion of the height sidewall 130 in the corresponding region is removed to form an etch barrier layer 200 located on the sidewall of the corresponding via and covering the top of the sidewall 130.

[0056] By replacing a portion of the sidewall 130 in the corresponding region with the etch barrier layer 200, which has a stronger etch barrier capability, a film layer with a high etch selectivity ratio is introduced, where the materials of the source / drain cap layer 160, the gate cap layer 120, and the sidewall 130 are all of high quality. With the direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 110 as the lateral direction, the etch barrier layer 200 can act as an etch barrier along the lateral direction during the formation of the source / drain via 210 or the gate via 220, and also protect the sidewall 130. Alternatively, the etch barrier layer 200... The etch barrier layer 200 can occupy part of the space where the original sidewall 130 was located, which helps to prevent weak points from being generated at the corner of the top surface of the sidewall 130 in the corresponding area. After the source / drain plug and the gate plug are formed, the etch barrier layer 200 can isolate the source / drain plug and the adjacent gate structure 110, or the gate plug and the adjacent source / drain contact layer 150, thereby reducing the probability of bridging or breakdown between the source / drain plug and the adjacent gate structure 110, or between the gate plug and the adjacent source / drain contact layer 150, and thus improving the performance of the semiconductor structure.

[0057] Furthermore, in the step of forming any one or both of the source / drain vias 210 and the gate vias 220, a portion of the height sidewall 130 in the corresponding region is removed to form an etch barrier layer 200 located on the sidewall of the corresponding via and covering the top of the sidewall 130. This allows the etch barrier layer 200 to be formed only in the region where the source / drain vias 210 or the gate vias 220 are required. This not only facilitates the integration of the process of forming the source / drain vias 210 or the gate vias 220 with the process steps of removing the portion of the height sidewall 130 in the corresponding region and forming the etch barrier layer 200, but also helps to reduce the impact on the film structure of other regions, thereby improving process compatibility and reducing process risks.

[0058] As an example, in the step of forming the source-drain via 210, a portion of the height sidewall 130 of the first region 100a is removed to form a first etch barrier layer 200 (1) located on the sidewall of the source-drain via 210 and covering the top of the sidewall 130.

[0059] As an example, in the step of forming the gate via 220, a portion of the height sidewall 130 of the second region 100b is removed to form a second etch barrier layer 200 (2) located on the sidewall of the gate via 220 and covering the top of the sidewall 130.

[0060] The specific steps for forming the source / drain via 210, the gate via 220, and the etch barrier layer 200 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0061] refer to Figures 10 to 17 A source / drain via 210 is formed, penetrating the top dielectric layer 170 and the source / drain cap layer 160 of the first region 100a (e.g., Figure 17 As shown, the top surface of the source / drain contact layer 150 is exposed.

[0062] The source / drain via 210 is used to provide space for forming the source / drain plug.

[0063] In this embodiment, a source / drain via 210 is formed that penetrates the top dielectric layer 170 and the source / drain cap layer 160 at the bottom of the interconnect trench 300, and the source / drain via 210 is connected to the interconnect trench 300.

[0064] In this embodiment, in the step of forming the source-drain via 210, a portion of the height sidewall 130 of the first region 100a is removed to form a first etch barrier layer 200 (1) located on the sidewall of the source-drain via 210 and covering the top of the sidewall 130.

[0065] The material of the first etch barrier layer 200(1) has an etch selectivity ratio with any one or more of the gate cap layer 120, sidewall 130 and source / drain cap layer 160, so that in the step of forming the source / drain via 210, the first etch barrier layer 200(1) can act as an etch barrier in the lateral direction and protect the sidewall 130.

[0066] The material of the first etch barrier layer 200(1) includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, aluminum nitride, and aluminum oxide. As an example, the material of the first etch barrier layer 200(1) is aluminum oxide.

[0067] As an example, the bottom surface of the first etch barrier layer 200(1) is higher than the bottom surfaces of the source / drain capping layer 160 and the gate capping layer 120. In other embodiments, during the step of forming the first etch barrier layer, the bottom surface of the first etch barrier layer may also be lower than the bottom surfaces of the source / drain capping layer and the gate capping layer, thereby further improving the etch barrier effect of the first etch barrier layer in the lateral direction.

[0068] In this embodiment, the steps of forming the source / drain via 210 and the first etch barrier layer 200 (1) include:

[0069] like Figure 10 and Figure 11 As shown, Figure 10 This is a top view. Figure 11 for Figure 10 A cross-sectional view along the xx secant line shows an initial source / drain via 180 forming through the top dielectric layer 170 of the first region 100a.

[0070] In this embodiment, an initial source / drain via 180 is formed through the top dielectric layer 170 at the bottom of the interconnect trench 300. The initial source / drain via 180 is connected to the interconnect trench 300. In the step of forming the initial source / drain via 180, the initial source / drain via 180 can achieve self-alignment with the interconnect trench 300 in the longitudinal direction.

[0071] like Figure 12 As shown, the exposed portion of the height sidewall 130 of the initial source / drain via 180 is removed, so that the source / drain capping layer 160, the adjacent gate capping layer 120, and the top of the remaining sidewall 130 form a first gap 10.

[0072] In other embodiments, during the step of removing a portion of the height sidewall in the corresponding region, a portion of the thickness of the gate cap layer and a portion of the thickness of the source / drain cap layer located on the sidewall sidewall are etched along an extension direction parallel to the substrate surface and perpendicular to the gate structure. Specifically, during the step of removing the portion of the height sidewall exposed by the initial source / drain via, a portion of the thickness of the gate cap layer and a portion of the thickness of the source / drain cap layer located on the sidewall sidewall in the first region are etched along an extension direction parallel to the substrate surface and perpendicular to the gate structure. This results in the first gap protruding from the sidewall of the sidewall on a projection plane parallel to the substrate, along an extension direction perpendicular to the gate structure. Consequently, the width of the subsequently formed first etch barrier layer is greater than the width of the sidewall, which is beneficial for making the first etch barrier layer more effective in blocking etch in the lateral direction.

[0073] Accordingly, along the lateral direction, the cross-section of the first gap can be rectangular or inverted trapezoidal.

[0074] In this embodiment, the process of removing part of the height sidewall 130 in the corresponding area includes one or both of dry etching and wet etching.

[0075] like Figures 13 to 15 As shown, a first etch barrier layer 200 (1) is formed in the first gap 10.

[0076] The steps for forming the first etch barrier layer 200(1) include: as follows Figure 13 As shown, a deposition process is used to fill the first gap 10 with a first etch barrier film 101. The first etch barrier film 101 is also located on the bottom and sidewalls of the initial source / drain via 180 and the bottom and sidewalls of the interconnect trench 300; Figure 14 and Figure 15 As shown, Figure 14 This is a top view. Figure 15 for Figure 14 A cross-sectional view along the xx secant line shows that the first etch barrier film 101 located on the bottom and sidewalls of the initial source drain via 180 and the bottom and sidewalls of the interconnect trench 300 is removed by an etching process. The remaining first etch barrier film 101 located in the first gap 10 is used as the first etch barrier layer 200 (1).

[0077] In this embodiment, the deposition process includes atomic layer deposition, which is beneficial to improve the gap filling ability and step coverage ability of the first etch barrier film 101, and correspondingly improves the film quality of the first etch barrier layer 200(1).

[0078] In this embodiment, the etching process is an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, thus it can remove not only the first etch barrier film 101 located on the bottom of the initial source / drain via 180 and the interconnect trench 300, but also the first etch barrier film 101 located on the sidewalls of the initial source / drain via 180 and the interconnect trench 300. Since the removal of the first etch barrier film 101 in the first gap 10 is difficult, it can be retained as the first etch barrier layer 200 (1).

[0079] In this embodiment, the etching process includes one or both of dry etching and wet etching.

[0080] like Figure 16 and Figure 17 As shown, Figure 16 This is a top view. Figure 17 for Figure 16 In the cross-sectional view along the xx secant line, after forming the first etch barrier layer 200 (1), the source drain cap layer 160 below the initial source drain via 180 is removed to form the source drain via 210.

[0081] In this embodiment, the process of removing the source / drain capping layer 160 below the initial source / drain via 180 includes one or both of dry etching and wet etching.

[0082] In this embodiment, by first removing the exposed portion of the height sidewall 130 of the initial source-drain via 180 to form a first gap 10, and then forming a first etch barrier layer 200(1) in the first gap 10, and then removing the source-drain capping layer 160 below the initial source-drain via 180 to form a source-drain via 210, it is beneficial to accurately control the formation position, size and cross-sectional morphology of the first etch barrier layer 200(1).

[0083] In other embodiments, the steps of forming the source / drain via and the first etch barrier layer may further include: forming an initial source / drain via through the top dielectric layer of the first region; removing the source / drain capping layer below the initial source / drain via; removing the exposed portion of the height sidewall of the initial source / drain via; and forming the first etch barrier layer on the exposed gate capping layer sidewall of the initial source / drain via, so that the initial source / drain via forms the source / drain via.

[0084] refer to Figures 18 to 24 A gate via 220 is formed through the top dielectric layer 170 and the gate cap layer 120 of the second region 100b, exposing the top surface of the gate structure 110.

[0085] The gate via 220 is used to provide space for forming the gate plug.

[0086] In this embodiment, a gate via 220 is formed that penetrates the top dielectric layer 170 and the gate cap layer 120 at the bottom of the interconnect trench 300, and the gate via 220 is connected to the interconnect trench 300.

[0087] In this embodiment, in the step of forming the gate via 220, a portion of the height sidewall 130 of the second region 100b is removed to form a second etch barrier layer 200 (2) located on the sidewall of the gate via 220 and covering the top of the sidewall 130.

[0088] The material of the second etch barrier layer 200(2) has an etch selectivity ratio with any one or more of the gate cap layer 120, sidewall 130 and source / drain cap layer 160, so that in the step of forming the gate via 220, the second etch barrier layer 200(2) can act as an etch barrier in the lateral direction and protect the sidewall 130.

[0089] The material of the second etch barrier layer 200(2) includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, aluminum nitride, and aluminum oxide. As an example, the material of the second etch barrier layer 200(2) is aluminum oxide.

[0090] As an example, the bottom surface of the second etch barrier layer 200(2) is higher than the bottom surfaces of the source / drain capping layer 160 and the gate capping layer 120. In other embodiments, during the step of forming the second etch barrier layer, the bottom surface of the second etch barrier layer may also be lower than the bottom surfaces of the source / drain capping layer and the gate capping layer, thereby further improving the etch barrier effect of the second etch barrier layer in the lateral direction.

[0091] In this embodiment, the steps of forming the gate via 220 and the second etch barrier layer 200 (2) include:

[0092] like Figure 18 and Figure 19 As shown, Figure 18 This is a top view. Figure 19 for Figure 18 A cross-sectional view along the xx secant line shows an initial gate via 190 that penetrates the top dielectric layer 170 located in the second region 100b.

[0093] In this embodiment, an initial gate via 190 is formed through the top dielectric layer 170 at the bottom of the interconnect trench 300. The initial gate via 190 is connected to the interconnect trench 300. In the step of forming the initial gate via 190, the initial gate via 190 can achieve self-alignment with the interconnect trench 300 in the longitudinal direction.

[0094] like Figure 20 As shown, the portion of the height sidewall 130 exposed by the initial gate via 190 is removed, so that the gate cap layer 120, the adjacent source / drain cap layer 160, and the top of the remaining sidewall 130 form a second gap 20.

[0095] In other embodiments, during the step of removing a portion of the height sidewall in the corresponding region, a portion of the thickness of the gate cap layer and a portion of the thickness of the source / drain cap layer located on the sidewall sidewall are etched along an extension direction parallel to the substrate surface and perpendicular to the gate structure. Specifically, during the step of removing the portion of the height sidewall exposed by the initial gate via, a portion of the thickness of the gate cap layer and a portion of the thickness of the source / drain cap layer located on the sidewall sidewall in the second region are etched along an extension direction parallel to the substrate surface and perpendicular to the gate structure. This results in the second gap protruding from the sidewall of the sidewall on a projection plane parallel to the substrate, along an extension direction perpendicular to the gate structure. Consequently, the width of the subsequently formed second etch barrier layer is greater than that of the sidewall, which is beneficial for making the etch barrier effect of the second etch barrier layer more significant in the lateral direction.

[0096] Accordingly, along the lateral direction, the cross-section of the second gap can be rectangular or inverted trapezoidal.

[0097] like Figures 21 to 22 As shown, Figure 21 This is a top view. Figure 22 for Figure 21 A cross-sectional view along the xx secant line shows that the second etch barrier layer 200 (2) is formed in the second gap 20.

[0098] The steps of forming the second etch barrier layer 200(2) include: using a deposition process to fill the second gap 20 with a second etch barrier film (not shown), the second etch barrier film (not shown) also being located on the bottom and sidewalls of the initial gate via 190 and the bottom and sidewalls of the interconnect trench 300; using an etching process to remove the second etch barrier film located on the bottom and sidewalls of the initial gate via 190 and the bottom and sidewalls of the interconnect trench 300, the remaining second etch barrier film located in the second gap 20 being used as the second etch barrier layer 200(2).

[0099] For a detailed description of the formation of the second etch barrier film and the etching of the second barrier film to form the second etch barrier layer 200 (2), please refer to the foregoing description of the formation of the first etch barrier layer 200 (1), which will not be repeated here.

[0100] like Figures 23 to 24 As shown, Figure 23 This is a top view. Figure 24 for Figure 23In the cross-sectional view along the xx secant line, after forming the second etch barrier layer 200 (2), the gate cap layer 120 below the initial gate via 190 is removed to form the gate via 220.

[0101] In this embodiment, the process of removing the gate cap layer 120 below the initial gate via 190 includes one or both of dry etching and wet etching.

[0102] In this embodiment, by first removing the exposed portion of the height sidewall 130 of the initial gate via 190 to form a second gap 20, then forming a second etch barrier layer 200(2) in the second gap 20, and then removing the gate cap layer 120 below the initial gate via 190 to form a gate via 220, it is beneficial to accurately control the formation position, size and cross-sectional morphology of the second etch barrier layer 200(2).

[0103] In other embodiments, the step of forming the gate via and the second etch barrier layer may further include: forming an initial gate via through the top dielectric layer of the second region; removing the gate cap layer below the initial gate via; removing the exposed portion of the height sidewall of the initial gate via; and forming the second etch barrier layer on the exposed source / drain cap layer sidewall of the initial gate via, so that the initial gate via forms the gate via.

[0104] refer to Figure 25 and Figure 26 , Figure 25 This is a top view. Figure 26 for Figure 25 A cross-sectional view along the xx secant line shows a gate plug 240 located in the gate via 220 and a source plug 230 located in the source / drain via 210.

[0105] The gate plug 240 is used to realize the electrical connection between the gate structure 110 and external circuits or other interconnection structures. In this embodiment, the gate plug 240 is formed above the gate structure 110 in the active region. The gate plug 240 is an active gate contact hole plug (COAG), which helps to save chip area and thus achieve further reduction in chip size.

[0106] The source / drain plug 230 contacts the source / drain contact layer 150, thereby enabling electrical connection between the source / drain doped region 140 and external circuitry or other interconnect structures through the source / drain contact layer 150.

[0107] In this embodiment, the method for forming the semiconductor structure further includes: in the step of forming the gate plug 240 and the source / drain plug 230, forming an interconnect line 310 located in the interconnect trench 300, wherein the interconnect line 310 is in contact with the top of the gate plug 240 and the source / drain plug 230.

[0108] The interconnect 310 is used to realize the electrical connection between the gate plug 240 and the source / drain plug 230 and external circuits or other interconnect structures.

[0109] In this embodiment, the gate via 220 is connected to the interconnect trench 300, and the source / drain via 210 is connected to the interconnect trench 300. The interconnect line 310, the gate plug 240, and the source / drain plug 230 are formed by filling the gate via 220, the source / drain via 210, and the interconnect trench 300 with conductive material.

[0110] Accordingly, the interconnect 310, gate plug 240 and source / drain plug 230 are made of the same material, and the interconnect 310, gate plug 240 and source / drain plug 230 are an integral structure, which is beneficial to improving the contact performance between the interconnect 310 and the gate plug 240, and between the interconnect 310 and the source / drain plug 230.

[0111] In this embodiment, the conductive material is copper. In other embodiments, the conductive material may also be a conductive material such as tungsten or cobalt.

[0112] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figure 25 and Figure 26 , Figure 25 This is a top view. Figure 26 for Figure 25 A cross-sectional view along the xx secant line shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0113] The semiconductor structure includes: a substrate 100, including a first region 100a for forming source / drain plugs and a second region 100b for forming gate plugs; a gate structure 110, disposed on the substrate 100; a gate capping layer 120, located on top of the gate structure 110; sidewalls 130, located on the sidewalls of the gate structure 110 and the gate capping layer 120; source / drain doped regions 140, located in the substrate 100 on both sides of the gate structure 110; a bottom dielectric layer (not shown), located on the side of the gate structure 110 and covering the source / drain doped regions 140; a source / drain contact layer 150, located in the bottom dielectric layer and in contact with the source / drain doped regions 140; and a source / drain capping layer 160, located in the source / drain contact layer. The top of the contact layer 150; a top dielectric layer 170, located on the bottom dielectric layer and covering the gate cap layer 120, the source / drain cap layer 160, and the sidewall 130; a source / drain plug 230, penetrating the top dielectric layer 170 and the source / drain cap layer 160 located in the first region 100a, the source / drain plug 230 contacting the top of the source / drain contact layer 150; a gate plug 240, penetrating the top dielectric layer 170 and the gate cap layer 120 located in the second region 100b, the gate plug 240 contacting the top of the gate structure 110; an etch barrier layer 200, located on the sidewall of any one or both of the source / drain plug 230 and the gate plug 240, and covering the top surface of the sidewall 130 of the corresponding region.

[0114] By replacing a portion of the sidewall 130 in the corresponding region with the etch barrier layer 200, which has a stronger etch barrier capability, a film layer with a high etch selectivity ratio is introduced, which is the same as the source / drain cap layer 160, the gate cap layer 120, and the sidewall 130. With the direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 110 as the lateral direction, the etch barrier layer 200 can act as an etch barrier in the step of forming the source / drain plug 230 or the gate plug 240, and protect the sidewall 130. Alternatively, the etch barrier layer 200... The 0 can occupy part of the space where the original sidewall 130 was located, which helps to prevent weak points from being generated at the corner of the top surface of the sidewall 130 in the corresponding area. The etching barrier layer 200 can also isolate the source / drain plug 230 from the adjacent gate structure 110, or from the gate plug 240 to the adjacent source / drain contact layer 150, thereby reducing the probability of bridging or breakdown between the source / drain plug 230 and the adjacent gate structure 110, or between the gate plug 140 and the adjacent source / drain contact layer 150, thereby improving the performance of the semiconductor structure.

[0115] Furthermore, the etching barrier layer 200 is located only on the sidewall of any one or both of the source / drain plugs 230 and the gate plug 240, and covers the top surface of the sidewall 130 of the corresponding area. Thus, the etching barrier layer 200 is provided only in the area where the source / drain plug 230 or the gate plug 240 needs to be formed, which helps to reduce the impact on the film structure of other areas, thereby improving process compatibility and reducing process risks.

[0116] In this embodiment, the substrate 100 is used to form a fin field-effect transistor (FinFET).

[0117] In this embodiment, the substrate 100 is a three-dimensional substrate, including a substrate (not shown) and fins (not shown) protruding from the substrate. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate. In this embodiment, the substrate is a silicon substrate, and the fins are made of the same material as the substrate.

[0118] When the device is in operation, the gate structure 110 is used to control the opening or closing of the conductive channel.

[0119] In this embodiment, the gate structure 110 is located on the substrate, spanning the fin and covering part of the top surface and part of the sidewalls of the fin. In this embodiment, the gate structure 110 is a metal gate structure, including a high-k gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the high-k gate dielectric layer.

[0120] The gate cap layer 120 serves to protect the top of the gate structure 110 during the formation of the source / drain contact layer 150 and the formation of the source / drain plug 230.

[0121] The gate cap layer 120 is made of a material that has etching selectivity with the source / drain cap layer 160, the bottom dielectric layer, and the top dielectric layer 170, thereby ensuring the protective function of the gate cap layer 120 for the gate structure 110. In this embodiment, the material of the gate cap layer 120 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 120 is silicon nitride.

[0122] Sidewall 130 is used to define the formation region of source / drain doped region 140, and sidewall 130 is also used to protect the sidewall of gate structure 110.

[0123] In this embodiment, the sidewall 130 is made of one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, and low-k dielectric materials. As an example, the sidewall 130 is made of a low-k dielectric material, which helps to reduce the effective capacitance between the gate structure 110 and the source / drain contact layer 150.

[0124] The source / drain doped region 140 is used to provide a carrier source. In this embodiment, the source / drain doped region 140 is also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped region 140 is located in the fins on both sides of the gate structure 110 and the sidewall 130.

[0125] When forming an NMOS transistor, the source / drain doped region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 140 includes a stress layer doped with P-type ions.

[0126] The bottom dielectric layer is used to achieve isolation between adjacent devices, and also to achieve electrical isolation between the source and drain contact layers 150. In this embodiment, the material of the bottom dielectric layer is silicon oxide.

[0127] The source / drain contact layer 150 is in contact with the source / drain doped region 140 to enable electrical connection between the source / drain doped region 140 and external circuits or other interconnect structures.

[0128] In this embodiment, the source / drain contact layer 150 is made of copper. In other embodiments, the source / drain contact layer may also be made of conductive materials such as tungsten or cobalt.

[0129] During the formation of the gate plug 240, the source / drain cap layer 160 protects the source / drain contact layer 150. The source / drain cap layer 160 is made of a material with high etch selectivity compared to the gate cap layer 120, the bottom dielectric layer, and the top dielectric layer 170, thereby ensuring the protective effect of the source / drain cap layer 160 on the source / drain contact layer 150. The material of the source / drain cap layer 160 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. Specifically, the source / drain cap layer 160 is made of a different material than the gate cap layer 120. As an example, the material of the source / drain cap layer 160 is silicon carbide.

[0130] The material of the top dielectric layer 170 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric material, and ultra-low-k dielectric material.

[0131] The source / drain plug 230 contacts the source / drain contact layer 150, thereby enabling electrical connection between the source / drain doped region 140 and external circuitry or other interconnect structures through the source / drain contact layer 150.

[0132] The gate plug 240 is used to realize the electrical connection between the gate structure 110 and external circuits or other interconnection structures. In this embodiment, the gate plug 240 is formed above the gate structure 110 in the active region. The gate plug 240 is an active gate contact hole plug (COAG), which helps to save chip area and thus achieve further reduction in chip size.

[0133] In this embodiment, the semiconductor structure further includes an interconnect 310 located in the top dielectric layer 170 on the source / drain plug 230 and the gate plug 240. The interconnect 310 is in contact with the top of the source / drain plug 230 and the gate plug 240, and the interconnect 310 is an integral structure with the source / drain plug 230 and the gate plug 240.

[0134] The interconnect 310 is used to realize the electrical connection between the gate plug 240 and the source / drain plug 230 and external circuits or other interconnect structures.

[0135] The interconnect 310, gate plug 240 and source / drain plug 230 are integrated into a single structure, which helps to improve the contact performance between the interconnect 310 and the gate plug 240, and between the interconnect 310 and the source / drain plug 230.

[0136] In this embodiment, the interconnect 310, gate plug 240, and source / drain plug 230 are all made of copper. In other embodiments, the interconnect, gate plug, and source / drain plug may also be made of conductive materials such as tungsten or cobalt.

[0137] In this embodiment, the etching barrier layer 200 includes a first etching barrier layer 200(1), located between the sidewall of the source / drain plug 230 and the sidewall of the adjacent gate cap layer 120, and the first etching barrier layer 200(1) covers the top surface of the sidewall 130 of the first region 100a.

[0138] The first etch barrier layer 200(1) serves to act as an etch barrier in the lateral direction during the step of forming the source drain plug 230 and to protect the sidewall 130 of the first region 100a.

[0139] In this embodiment, the etching barrier layer 200 includes a second etching barrier layer 200(2), located between the sidewall of the gate plug 240 and the sidewall of the adjacent source drain cap layer 160, and the etching barrier layer 200(2) covers the top surface of the sidewall 130 of the second region 100b.

[0140] The second etch barrier layer 200(2) serves as an etch barrier in the lateral direction during the step of forming the gate plug 240 and protects the sidewall 130 of the second region 100b.

[0141] The material of the etch barrier layer 200 has an etch selectivity ratio with the materials of any one or more of the gate cap layer 120, sidewall 30, and source / drain cap layer 160. The material of the etch barrier layer 200 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, aluminum nitride, and aluminum oxide. As an example, the material of the etch barrier layer 200 is aluminum oxide.

[0142] The materials of the first etch barrier layer 200(1) and the second etch barrier layer 200(2) may be the same or different.

[0143] In this embodiment, the bottom surface of the etch barrier layer 200 is higher than the bottom surfaces of the source / drain capping layer 160 and the gate capping layer 120. In other embodiments, the bottom surface of the etch barrier layer may be lower than the bottom surfaces of the source / drain capping layer and the gate capping layer. This is beneficial for further improving the etch barrier layer's etch blocking effect in the lateral direction.

[0144] In this embodiment, the sidewall of the etching barrier layer 200 is flush with the sidewall of the lower sidewall 130. In other embodiments, on a projection plane parallel to the substrate, along an extension direction perpendicular to the gate structure, the etching barrier layer may protrude beyond the sidewall, thereby making the width of the etching barrier layer greater than the width of the sidewall. This is beneficial for making the etching barrier layer more effective in lateral etching. Laterally, the cross-section of the etching barrier layer can be rectangular or inverted trapezoidal.

[0145] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0146] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first region for forming a source / drain plug and a second region for forming a gate plug; The gate structure is discretely disposed on the substrate; A gate cap layer is located on top of the gate structure; Sidewalls are located on the sidewalls of the gate structure and the gate cap layer; The source and drain doped regions are located in the substrate on both sides of the gate structure; A bottom dielectric layer is located on the side of the gate structure and covers the source / drain doped regions; The source / drain contact layer is located in the bottom dielectric layer and is in contact with the source / drain doped region; A source / drain capping layer is located on top of the source / drain contact layer; A top dielectric layer is located on the bottom dielectric layer and covers the gate cap layer, source / drain cap layer, and sidewalls; A source / drain plug penetrates the top dielectric layer and the source / drain cap layer located in the first region, and the source / drain plug contacts the top of the source / drain contact layer; the source / drain plug is formed based on a source / drain via. A gate plug extends through the top dielectric layer and the gate cap layer located in the second region, the gate plug being in contact with the top of the gate structure; the gate plug is formed based on a gate via; An etch barrier layer is located on the sidewall of any one or both of the source / drain plugs and the gate plugs, and covers the top surface of the sidewall of the corresponding region; the etch barrier layer is formed by removing a portion of the height of the sidewall of the corresponding region during the step of forming any one or both of the source / drain vias and the gate vias. Interconnects are located in the top dielectric layer on the source / drain plugs and the gate plugs, and the interconnects are in contact with the top of the source / drain plugs and the gate plugs.

2. The semiconductor structure as described in claim 1, characterized in that, The interconnect, source / drain plug, and gate plug are an integral structure.

3. The semiconductor structure as described in claim 1, characterized in that, The etching barrier layer includes a first etching barrier layer located between the source / drain plug sidewall and the sidewall of the adjacent gate cap layer, and the first etching barrier layer covers the top surface of the sidewall of the first region.

4. The semiconductor structure as described in claim 1, characterized in that, The etching barrier layer includes a second etching barrier layer located between the gate plug sidewall and the sidewall of the adjacent source / drain cap layer, the etching barrier layer covering the top surface of the sidewall of the second region.

5. The semiconductor structure as described in claim 1, characterized in that, The bottom surface of the etch barrier layer is lower than the bottom surface of the source / drain capping layer and the gate capping layer.

6. The semiconductor structure as described in claim 1, characterized in that, On a projection plane parallel to the substrate, along an extension direction perpendicular to the gate structure, the etch barrier layer protrudes from the sidewall of the sidewall.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the etching barrier layer has an etching selectivity ratio with the material of any one or more of the gate cap layer, sidewall, and source / drain cap layers.

8. The semiconductor structure as described in claim 1, characterized in that, The etching barrier layer is made of one or more of silicon nitride, silicon carbonitride, silicon carbon oxide, silicon carbide, aluminum nitride, and aluminum oxide.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a first region for forming a source / drain plug and a second region for forming a gate plug; Discrete gate structures are formed on the substrate, a gate capping layer is formed on the top of the gate structures, sidewalls are formed on the sidewalls of the gate structures and the gate capping layer, source and drain doped regions are formed in the substrate on both sides of the gate structures, a bottom dielectric layer covering the source and drain doped regions is formed on the side of the gate structures, a source and drain contact layer in contact with the source and drain doped regions is formed in the bottom dielectric layer, and a source and drain capping layer is formed on the top of the source and drain contact layer; A top dielectric layer is formed on the bottom dielectric layer, covering the gate cap layer, source / drain cap layer, and sidewalls; A source / drain via is formed that penetrates the top dielectric layer and the source / drain cap layer of the first region, exposing the top surface of the source / drain contact layer; A gate via is formed that penetrates the top dielectric layer and the gate cap layer of the second region, exposing the top surface of the gate structure; In the step of forming one or both of the source / drain vias and the gate vias, a portion of the height sidewall in the corresponding region is removed to form an etch barrier layer located on the sidewall of the corresponding via and covering the top of the sidewall. A gate plug is formed in the gate via and a source plug is formed in the source-drain via.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the semiconductor structure further includes: after forming the top dielectric layer and before forming the source / drain vias and the gate vias, forming an interconnect trench that penetrates a portion of the thickness of the top dielectric layer, wherein the interconnect trench is located above the first region and the second region; A source / drain via is formed that penetrates the top dielectric layer and the source / drain cap layer at the bottom of the interconnect trench, and the source / drain via is connected to the interconnect trench; A gate via is formed that penetrates the top dielectric layer and the gate cap layer through the bottom of the interconnect trench, and the gate via is connected to the interconnect trench; The method for forming the semiconductor structure further includes: in the step of forming the gate plug and the source / drain plug, forming an interconnect line located in the interconnect trench, the interconnect line being in contact with the top of the gate plug and the source / drain plug.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the source-drain via, a portion of the height sidewall of the first region is removed to form a first etch barrier layer located on the sidewall of the source-drain via and covering the top of the sidewall. The steps of forming the source / drain via and the first etch barrier layer include: forming an initial source / drain via through the top dielectric layer of the first region; Remove the exposed portion of the height sidewall of the initial source / drain via, so that the source / drain capping layer, the adjacent gate capping layer, and the top of the remaining sidewalls form a first gap; form the first etch barrier layer in the first gap; after forming the first etch barrier layer, remove the source / drain capping layer below the initial source / drain via to form the source / drain via.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the source-drain via, a portion of the height sidewall of the first region is removed to form a first etch barrier layer located on the sidewall of the source-drain via and covering the top of the sidewall. The steps of forming the source / drain via and the first etch barrier layer include: forming an initial source / drain via through the top dielectric layer of the first region; removing the source / drain capping layer below the initial source / drain via; removing the exposed portion of the height sidewall of the initial source / drain via; and forming the first etch barrier layer on the exposed gate capping layer sidewall of the initial source / drain via, so that the initial source / drain via forms the source / drain via.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the gate via, a portion of the height sidewall of the second region is removed to form a second etch barrier layer located on the sidewall of the gate via and covering the top of the sidewall. The step of forming the gate via and the second etch barrier layer includes: forming an initial gate via through the top dielectric layer located in the second region; Remove the exposed portion of the sidewall of the initial gate via, so that the gate capping layer, the adjacent source / drain capping layer, and the top of the remaining sidewalls form a second gap; form the second etch barrier layer in the second gap; after forming the second etch barrier layer, remove the gate capping layer below the initial gate via to form the gate via.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the gate via, a portion of the height sidewall of the second region is removed to form a second etch barrier layer located on the sidewall of the gate via and covering the top of the sidewall; The steps of forming the gate via and the second etch barrier layer include: forming an initial gate via through the top dielectric layer of the second region; removing the gate cap layer below the initial gate via; removing the exposed portion of the height sidewall of the initial gate via; and forming the second etch barrier layer on the exposed source / drain cap layer sidewall of the initial gate via, so that the initial gate via forms the gate via.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the first etch barrier layer includes: using a deposition process to fill the first gap with a first etch barrier film, wherein the first etch barrier film is also located on the bottom and sidewall of the initial source-drain via; An etching process is used to remove the first etching barrier film located at the bottom and sidewall of the initial source-drain via. The remaining first etching barrier film located in the first gap is used as the first etching barrier layer.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the second etch barrier layer includes: using a deposition process to fill the second gap with a second etch barrier film, wherein the second etch barrier film is also located on the bottom and sidewall of the initial gate via; An etching process is used to remove the second etching barrier film located on the bottom and sidewalls of the initial gate via. The remaining second etching barrier film located in the second gap is used as the second etching barrier layer.

17. The method for forming a semiconductor structure as described in claim 15 or 16, characterized in that, The deposition process includes atomic layer deposition.

18. The method for forming a semiconductor structure as described in claim 15 or 16, characterized in that, The etching process is an isotropic etching process.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of removing a portion of the height sidewall in the corresponding region, a portion of the thickness of the gate cap layer and a portion of the thickness of the source / drain cap layer located on the sidewall sidewall are also etched along an extension direction parallel to the substrate surface and perpendicular to the gate structure.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for removing a portion of the sidewalls in the corresponding area includes one or both of the following: dry etching and wet etching.

21. The method for forming a semiconductor structure as described in claim 9, characterized in that, The bottom surface of the etch barrier layer is lower than the bottom surface of the source / drain capping layer and the gate capping layer.

22. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the etching barrier layer has an etching selectivity ratio with any one or more of the gate cap layer, sidewall, and source / drain cap layers.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The etching barrier layer is made of one or more of silicon nitride, silicon carbonitride, silicon carbon oxide, silicon carbide, aluminum nitride, and aluminum oxide.

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