A two-step bootstrap sampling switch circuit and integrated circuit

Abstract

The present application discloses a two-step bootstrap sampling switch circuit and integrated circuit, comprising an interconnected bootstrap circuit and a switch circuit. The bootstrap circuit includes an NMOS transistor Ms2, and the switch circuit includes an NMOS transistor Ms1, wherein the source terminal of Ms1 is connected to the output terminal Vout, and the source terminal of Ms2, the drain terminal of Ms1, and the input terminal Vin are connected; a first transmission gate switch T1 and a second transmission gate switch T2; one end of the first transmission gate switch T1 is connected to the source terminal of Ms2, and the other end is connected to the common-mode voltage Vcm; one end of the second transmission gate switch T2 is connected to the source terminal of Ms2, and the other end is connected to the input terminal Vin and the drain terminal of Ms1; and a timing control circuit is used to generate a first sampling signal Clks, a short pulse Clkvcm to control the first transmission gate switch T1, and a second sampling signal Clkvin to control the second transmission gate switch T2. The present invention achieves a two-step establishment by adding the first transmission gate switch T1 and the second transmission gate switch T2, ensuring that the common-mode voltage Vcm remains stable during the sampling process and that linearity is not affected.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, in particular to a sampling switch circuit, and more particularly to a two-step bootstrap sampling switch circuit and an integrated circuit. Background Art

[0002] An analog-to-digital converter (ADC) is a circuit or device that converts an analog input signal into a digital signal. The analog-to-digital conversion process begins by sampling the analog input signal using a sample-and-hold circuit. Specifically, the analog input signal is sampled during the sampling cycle of the sampling clock. After sampling, the sampled analog signal is held until the next sampling cycle.

[0003] High-precision sampling networks usually require the use of bootstrap sampling switches with high linearity to achieve high spurious-free dynamic range (SFDR) and very low total harmonic distortion (THD) performance. Common bootstrap switches include Figure 1 As shown in the figure, the operation is as follows: When not sampling, the voltages across the bootstrap capacitor Cboost are reset to VDD and VSS, respectively. When sampling is enabled (Clks is low), the Vx node is charged to Vin. Due to the principle of charge conservation, the voltage difference across the bootstrap capacitor Cboost remains constant. The voltage Vy then varies with Vx, increasing or decreasing by Vin, thus achieving Vy = VDD + Vin. For the NMOS sampling transistor Ms1, the bootstrap circuit ensures that its turn-on voltage Vg varies in tandem with the source input signal Vs, maintaining a nearly constant Vgs ≈ VDD. (Typically, parasitic capacitance of some MOS transistors at circuit nodes causes this voltage to be slightly less than VDD.) This bootstrap voltage ensures that the equivalent impedance Ron,s1 of the MOS transistor switch in the linear region does not change with changes in the input signal amplitude. The time constant of Ron,s1 * Cs is relatively constant, resulting in consistent accuracy and high linearity within the specified sampling time. This characteristic is significantly superior to that of individual NMOS or PMOS switches, as well as to that of a CMOS transmission gate.

[0004] When the bootstrap sampling switch and the front-stage differential active module are cascaded, the simplified schematic diagram is as follows: Figure 2 As shown. The pre-stage circuit here may be a differential amplifier, buffer, residual amplifier, integrator, filter, etc. The bootstrap switch can ensure good linearity, but it also introduces a problem that is often easily overlooked. Because the Vx node (see Figure 1 As shown in Figure 2), each sampling needs to be charged from VSS to Vin. The input signal needs to provide a charging current. This process will cause the voltages of Vop and Von to drop to VSS at the same time when the sampling switch MS2 is turned on. (See Figure 3(As shown in ). In some low-power applications where the front-end drive capability is limited, this process can cause a significant common-mode drop of (Vop + Von) / 2, reaching the volt level. This phenomenon significantly impacts the common-mode stability of the front-end differential circuit, and the common-mode feedback circuit takes a long time to recover from this state. Common-mode instability can reduce the linearity of the downstream sampling circuit. To accelerate the recovery process and ensure that the common mode is stable by the next sampling, greater power consumption is required in the common-mode feedback branch. Summary of the Invention

[0005] In order to solve the problems existing in the existing bootstrap switch technology, the present application provides a two-step bootstrap sampling switch circuit and integrated circuit, which are used to specifically solve the problem that the existing bootstrap switch has a significant impact on the common-mode stability of the front-stage differential circuit, the common-mode feedback circuit takes a long time to recover from this state, and the common-mode instability causes the linearity of the downstream sampling circuit to decrease.

[0006] To achieve the above objectives, the core of the technical solution adopted by the present invention is to keep the common-mode voltage Vcm stable during the reset-charging process of the bootstrap capacitor Cboost in the bootstrap circuit, thereby ensuring that the linearity of the sampling circuit is not affected. Based on this inventive concept, the specific technical solution adopted by the present invention is as follows:

[0007] A two-step bootstrap sampling switch circuit includes a bootstrap circuit and a switch circuit connected to each other. The bootstrap circuit includes an NMOS transistor Ms2, and the switch circuit includes an NMOS transistor Ms1. The source terminal of Ms1 is connected to the output terminal Vout, and the source terminal of Ms2, the drain terminal of Ms1, and the input terminal Vin are connected. The circuit also includes a first transmission gate switch T1 and a second transmission gate switch T2. One end of the first transmission gate switch T1 is connected to the source terminal of Ms2, and the other end is connected to the common mode voltage Vcm. One end of the second transmission gate switch T2 is connected to the source terminal of Ms2, and the other end is connected to the input terminal Vin and the drain terminal of Ms1. A timing control circuit is also provided for generating a first sampling signal Clks, a short pulse Clkvcm to control the first transmission gate switch T1, and a second sampling signal Clkvin to control the second transmission gate switch T2.

[0008] As one of the specific design schemes for the transmission gates T1 / T2, the present application provides one feasible preferred solution: the first transmission gate switch T1 and the second transmission gate switch T2 adopt the same structural configuration, consisting of a first NOT gate, a PMOS transistor M3, and an NMOS transistor M4; the source terminal of the NMOS transistor M4 is connected to the drain terminal of the PMOS transistor M3 to form a first connection terminal, the drain terminal of the NMOS transistor M4 is connected to the source terminal of the PMOS transistor M3 to form a second connection terminal, the gate terminal of the NMOS transistor M4 is simultaneously connected to the first NOT gate input terminal and the first sampling signal Clks, and the first NOT gate output terminal is connected to the gate terminal of the PMOS transistor.

[0009] In order to achieve precise sampling, preferably, the timing control circuit includes a clock signal unit for generating an original clock Clk0, wherein the Clk0 is connected to a second NOT gate and a third NOT gate in sequence, and the output end of the second NOT gate or the input end of the third NOT gate is used as Clks; the original clocks Clk0 and Clk0 are respectively input as two input ends of a NAND gate after a delay td, and the output end of the NAND gate is connected to a fourth NOT gate, a fifth NOT gate and a sixth NOT gate in sequence, and the output end of the sixth NOT gate is used as Clkvcm; the output end of the third NOT gate, the output end of the fourth NOT gate or the input end of the fifth NOT gate are used as two input ends of an XOR gate and are connected to a seventh NOT gate and an eighth NOT gate in sequence, and the output end of the eighth NOT gate is used as the second sampling signal Clkvin.

[0010] An integrated circuit includes all circuits combined with the above-mentioned two-step bootstrap sampling switch circuit.

[0011] Beneficial effects:

[0012] The present invention realizes a two-step establishment by adding a first transmission gate switch T1 and a second transmission gate switch T2. The voltage is established in the first step with the common-mode voltage Vcm, and then established to the input voltage Vin / Vip. This ensures that when Ms2 is turned on, the output voltage Von / Vop will not drop to VSS at the same time and pull down the output common-mode voltage Vcm, thereby ensuring that the common-mode voltage Vcm remains stable during the sampling process and ensuring that the linearity is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 The present invention relates to an existing bootstrapping sampling switch circuit.

[0015] Figure 2 It is the sampling circuit schematic diagram of the differential active module.

[0016] Figure 3 yes Figure 2 The output waveform.

[0017] Figure 4 This is a circuit diagram of the bootstrap sampling switch of the present invention.

[0018] Figure 5 yes Figure 4 timing control circuit.

[0019] Figure 6 It is a control timing diagram of the present invention.

[0020] Figure 7 yes Figure 4 Simulation waveforms of Vx and Vy nodes. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.

[0023] Preferred embodiment:

[0024] like Figure 4A two-step bootstrap sampling switch circuit is shown, comprising a bootstrap circuit and a switch circuit connected to each other. The bootstrap circuit includes an NMOS transistor Ms2, and the switch circuit includes an NMOS transistor Ms1. The source terminal of Ms1 is connected to the output terminal Vout, and the source terminal of Ms2, the drain terminal of Ms1, and the input terminal Vin are connected. The circuit also includes a first transmission gate switch T1 and a second transmission gate switch T2. One terminal of the first transmission gate switch T1 is connected to the source terminal of Ms2, and the other terminal is connected to the common-mode voltage Vcm. One terminal of the second transmission gate switch T2 is connected to the source terminal of Ms2, and the other terminal is connected to the input terminal Vin and the drain terminal of Ms1. A timing control circuit is also provided for generating a first sampling signal Clks, a short pulse Clkvcm to control the first transmission gate switch T1, and a second sampling signal Clkvin to control the second transmission gate switch T2. In this embodiment, the first transmission gate switch T1 and the second transmission gate switch T2 have the same structure, consisting of a first NOT gate, a PMOS transistor M3, and an NMOS transistor M4. The source terminal of the NMOS transistor M4 is connected to the drain terminal of the PMOS transistor M3 to form a first connection terminal, the drain terminal of the NMOS transistor M4 is connected to the source terminal of the PMOS transistor M3 to form a second connection terminal, the gate terminal of the NMOS transistor M4 is connected to the first NOT gate input terminal and the first sampling signal Clks, and the output terminal of the first NOT gate is connected to the gate terminal of the PMOS transistor.

[0025] The timing control circuit includes a clock signal unit for generating an original clock Clk0, wherein Clk0 is connected to a second NOT gate and a third NOT gate in sequence, and the output end of the second NOT gate or the input end of the third NOT gate serves as Clks; the original clocks Clk0 and Clk0 are respectively input as two input ends of a NAND gate after a delay td, and the output end of the NAND gate is connected to a fourth NOT gate, a fifth NOT gate and a sixth NOT gate in sequence, and the output end of the sixth NOT gate serves as Clkvcm; the output end of the third NOT gate, the output end of the fourth NOT gate or the input end of the fifth NOT gate serves as two input ends of an XOR gate and is connected to a seventh NOT gate and an eighth NOT gate in sequence, and the output end of the eighth NOT gate serves as a second sampling signal Clkvin.

[0026] Workflow and principle:

[0027] Unlike existing bootstrap sampling switches, the Vx node isn't directly connected to Vin from the outset. Instead, Clkvcm controls the first transmission gate switch T1, which is first connected to the common-mode voltage Vcm. This charges the Vx node from VSS to the common-mode voltage Vcm, providing the required charging current via Vcm. Therefore, charging the bootstrap capacitor Cboost does not come from Vin / Vip as with existing bootstrap sampling switches. After a delay td, charging is complete, and the second sampling signal Clkvin controls the second transmission gate switch T2, which is then connected to Vin. During this process, T1 and Ms2, as well as T2 and Ms2, are connected in series.

[0028] Compared with the existing bootstrap sampling switch circuit, another difference is that the existing bootstrap sampling switch is completed by only one clock phase, while this embodiment is established in two steps, which requires a special dedicated phase control timing, see Figure 5 and Figure 6 It is worth noting that the short pulse width td of Clkvcm is not a fixed value and can be adaptively adjusted according to the actual application and different sampling speeds. Figure 7 As shown in FIG. 1 , the waveforms of two key nodes, Vx and Vy, are shown. It can be seen that Vx first builds up from a voltage close to Vss to Vcm (in this embodiment, VDD=3V, Vcm=1.5V), and then increases to Vin. Similarly, Vy is also built up in two steps to the final waveform of VDD+Vin.

[0029] By using the bootstrap sampling circuit described in this embodiment, the jitter at the output end of the amplifier can be reduced from the common-mode jitter of about 1V in the prior art to the common-mode jitter of tens of mV, basically eliminating the common-mode problem caused by the charging and discharging of the sampling switch circuit.

[0030] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A two-step bootstrap sampling switch circuit, comprising a bootstrap circuit and a switch circuit connected to each other, wherein the bootstrap circuit includes an NMOS transistor Ms2, and the switch circuit includes an NMOS transistor Ms1, wherein the source terminal of Ms1 is connected to the output terminal Vout, and the source terminal of Ms2, the drain terminal of Ms1, and the input terminal Vin are connected, characterized in that: The device further includes a first transmission gate switch T1 and a second transmission gate switch T2; one end of the first transmission gate switch T1 is connected to the source end of Ms2, and the other end is connected to the common mode voltage Vcm; one end of the second transmission gate switch T2 is connected to the source end of Ms2, and the other end is connected to the input end Vin and the drain end of Ms1; And a timing control circuit is used to generate a first sampling signal Clks, a short pulse Clkvcm to control the first transmission gate switch T1, and a second sampling signal Clkvin to control the second transmission gate switch T2; Clkvcm controls the first transmission gate switch T1 to be connected to the common mode voltage Vcm, and after a delay td, the second sampling signal Clkvin controls the second transmission gate switch T2 to be connected to Vin.

2. The two-step bootstrap sampling switch circuit according to claim 1, characterized in that: The first transmission gate switch T1 and the second transmission gate switch T2 have the same structure, consisting of a first NOT gate, a PMOS transistor M3, and an NMOS transistor M4. The source terminal of the NMOS transistor M4 is connected to the drain terminal of the PMOS transistor M3 to form a first connection terminal, the drain terminal of the NMOS transistor M4 is connected to the source terminal of the PMOS transistor M3 to form a second connection terminal, the gate terminal of the NMOS transistor M4 is connected to the first NOT gate input terminal and the first sampling signal Clks, and the output terminal of the first NOT gate is connected to the gate terminal of the PMOS transistor M3.

3. The two-step bootstrap sampling switch circuit according to claim 1, characterized in that: The timing control circuit includes a clock signal unit for generating an original clock Clk0, wherein the Clk0 is connected to the input end of the second NOT gate, and the output end of the second NOT gate is connected to the input end of the third NOT gate; A connection node between the output terminal of the second NOT gate and the input terminal of the third NOT gate serves as Clks; The original clocks Clk0 and Clk0 are input as two inputs of a NAND gate after being delayed by td; the output of the NAND gate is connected to the input of a fourth NAND gate, the output of the fourth NAND gate is connected to the input of a fifth NAND gate, the output of the fifth NAND gate is connected to the input of a sixth NAND gate, and the output of the sixth NAND gate serves as Clkvcm; The output end of the third NOT gate serves as the first input end of the XOR gate, the connection node between the output end of the fourth NOT gate and the input end of the fifth NOT gate serves as the second input end of the XOR gate, the output end of the XOR gate is connected to the input end of the seventh NOT gate, the output end of the seventh NOT gate is connected to the input end of the eighth NOT gate, and the output end of the eighth NOT gate serves as the second sampling signal Clkvin.

4. An integrated circuit, characterized in that: A bootstrap sampling switch circuit comprising the two-step establishment according to any one of claims 1 to 3.

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