A measurement ASIC chip with multi-rate adjustable sampling rate

Abstract

The present invention discloses a multi-rate adjustable sampling rate frequency measurement ASIC chip, comprising: a cycle counting module for synchronizing the analog oscillation signal F of a silicon micro-resonant accelerometer under test to a reference clock clk provided by a crystal oscillator, counting the synchronized analog oscillation signal using the reference clock and outputting a count value N; a nonlinear compensation module for converting the count value N into a fixed-point number M proportional to the square of the frequency, aligning the count value with the input oscillation signal F, and outputting the aligned fixed-point number Dout; an arbitrary sampling rate adjustment module for adjusting the sampling rate of the output fixed-point number Dout to achieve an output of a final fixed-point value Dout3 at an arbitrary sampling rate; and a digital interface module for communicating with a host computer, including configuring registers and outputting data to the host computer. The present invention can achieve digital output of the silicon micro-resonant accelerometer, solving the problem of nonlinear output of the silicon micro-resonant accelerometer.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing and hardware programming, and in particular to an implementation of a frequency measurement algorithm on a dedicated integrated circuit, and in particular to an ASIC (Application Specific Integrated Circuit) chip for measuring a frequency with a multi-rate adjustable sampling rate. Background Art

[0002] Frequency is one of the most basic physical quantities, especially in the fields of electronic technology and digital signal processing. Due to the high anti-interference and convenient transmission advantages of frequency signals, sensors with frequency as output are constantly emerging in many fields such as aerospace, navigation, satellite positioning, and anti-missile systems. Low-power and high-precision frequency measurement methods have become a research hotspot for experts from various countries. The main frequency measurement methods for oscillation signals are phase-locked loop method, counting method and differential method. (1) In 2000, Samsung Electronics of South Korea proposed a frequency measurement circuit based on phase-locked loop, which uses the characteristic that the voltage-controlled oscillator control signal is proportional to the frequency to achieve frequency recognition (Park Hyun-soo, Shen Zai-sheng, Yuan Rong-guang. Method for detecting the frequency of a digital phase-locked loop. Publication number: CN1171386C). The advantages of the phase-locked loop frequency measurement method are high sensitivity and high precision. The disadvantage is that the phase-locked loop is a closed-loop system and may lose lock when testing a large bandwidth signal. The phase-locked loop frequency measurement does not have good stability. (2) In 2014, Nanjing University of Science and Technology proposed a method for frequency measurement based on a differential frequency measurement algorithm (Xia Guoming, Lin Chen, Shi Qin, Qiu Anping, Su Yan, Ding Henggao. A differential frequency measurement system based on a digital signal processor platform. Publication number: CN204330882U). The advantages of the differential frequency measurement method are that it does not require an additional reference clock, has strong noise resistance, and good stability. The disadvantage is that it consumes a lot of power and cannot be integrated. (3) In 2012, Zhejiang University proposed a frequency measurement circuit based on a counter (Wang Rui. A multifunctional high-precision digital frequency meter. Publication number: CN202362380U). The advantages are simple structure and low power consumption. The disadvantages are that it is not well matched with the resonant accelerometer, the output is nonlinear, and the accuracy does not meet the requirements. In summary, the above frequency measurement methods all have their own advantages and disadvantages, and are difficult to adapt to the frequency reading requirements of silicon micro-resonant accelerometers with low power consumption, high precision and large bandwidth. Summary of the Invention

[0003] The purpose of the present invention is to provide a measurement ASIC chip with a multi-rate adjustable sampling rate frequency, so as to realize a sigma-delta noise modulation effect on the digital output of a silicon micro-resonant accelerometer, arbitrarily adjust the output sampling rate, and have no error in the mean value of the acceleration signal characterized by frequency.

[0004] The technical solutions for achieving the purpose of the present invention are:

[0005] A multi-rate adjustable sampling rate frequency measurement ASIC chip, comprising:

[0006] A cycle counting module is used to synchronize the analog oscillation signal F of the silicon micro-resonant accelerometer under test to the reference clock clk provided by the crystal oscillator, output a synchronized square wave signal F1, count the synchronized square wave signal F1 using the reference clock, and output a count value N;

[0007] The nonlinear compensation module is used to convert the count value N into a fixed-point number M that is proportional to the square of the frequency, and then align it with the synchronized square wave signal F1, and then output the aligned fixed-point number Dout;

[0008] An arbitrary sampling rate adjustment module is used to adjust the sampling rate of the output Dout to achieve the final fixed-point value Dout3 of the output at any sampling rate;

[0009] Digital interface module, used to communicate with the host computer, including configuring registers and outputting data to the host computer.

[0010] Compared with the prior art, the present invention has the following significant advantages:

[0011] (1) This frequency measurement method has a first-order sigma-delta noise modulation principle, which greatly suppresses the low-frequency quantization noise in the output frequency and achieves a noise level of 0.1mHz / rtHz in the 0.1Hz to 1Hz bandwidth;

[0012] (2) Through the nonlinear compensation module, the output data is proportional to the square of the frequency, ensuring that the mean value of the acceleration signal represented by frequency is error-free;

[0013] (3) Through the sampling rate adjustable module, multi-sampling rate output is achieved to meet different usage scenarios;

[0014] (4) For the silicon micro-resonant accelerometer, the ASIC chip was specially optimized and redesigned, and the squarer, divider, and CIC filter in the circuit were redesigned to reduce the area and power consumption of the ASIC, achieving high-precision output in an area of ​​1.1mm*2.6mm and a power consumption of 10mW. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural diagram of the multi-rate adjustable sampling rate frequency measurement ASIC chip of the present invention.

[0016] Figure 2 This is a schematic diagram of the error in counting using the period counting method.

[0017] Figure 3 It is the quantization noise model diagram.

[0018] Figure 4(ab) are the amplitude-frequency characteristic curves of the noise shaping power spectral density.

[0019] Figure 5 The figure is a schematic diagram of the layout of the multi-rate adjustable sampling rate frequency measurement ASIC chip of the present invention.

[0020] Figure 6 The output frequency noise level of the multi-rate adjustable sampling rate frequency measurement ASIC chip of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] The present embodiment is a multi-rate adjustable sampling rate frequency measurement ASIC chip, the overall structure of which is as follows Figure 1 As shown, it includes a cycle counting module, a nonlinear compensation module, an arbitrary sampling rate adjustment module, and a digital interface module which are arranged in sequence starting from the input end.

[0023] The cycle counting module includes a synchronizer unit, a counter unit, a rising edge detector unit, a comparator unit, and a subtractor unit;

[0024] Combine Figure 2 , the analog oscillation signal F of the silicon micro-resonant accelerometer is input to the cycle counting module,

[0025] First, the synchronizer is used to set up two-stage registers to beat two times to synchronize the analog oscillation signal F to the reference clock clk, and the synchronized square wave signal F1 is output. The counter continuously counts the reference clock clk, and the count value is cnt. The bit width is set to 12 bits. The rising edge of the synchronized square wave signal F1 is detected by the two registers in the rising edge detector, and the output values ​​are fa and fb.

[0026] fa<=F1,fb<=fa

[0027] When fa is equal to 1 and fb is equal to 0, it means that a rising edge is detected, and the value of the counter at the rising edge is saved by two 12-bit wide registers in the subtractor, that is,

[0028] reg1<=cnt, reg2<=reg1

[0029] The output count value N is output through the subtractor

[0030] N=reg2-reg1

[0031] When a rising edge is detected, the indication signal N rd =1, otherwise, N rd =0.

[0032] When the synchronizer synchronizes the analog oscillation signal F to the reference clock clk, quantization error will be introduced. The solution of this embodiment is to use oversampling technology to average multiple times to compensate for the quantization error. Figure 2 The principle is as follows: Assume that the true value of the analog oscillation signal F is R, the quantized input is y, and the quantized value is N. At time t = n, their relationship is y[n] = R[n] - N[n-1] + y[n-1]

[0033] The quantization error accumulation model of cycle counting is as follows: Figure 3 Assume that the error of the quantizer is e, that is

[0034] e[n]=N[n]-y[n]

[0035] Then the transfer formula of quantization error can be expressed as

[0036] N[n]=R[n]+e[n]-e[n-1]

[0037] The error between the quantized output N and the true value R is expressed as Q. The relationship between Q and the quantizer error e at time t is Q[n] = N[n] - R[n] = e[n] - e[n-1]

[0038] The z-transform can be expressed as

[0039] Q(z)=e(z)(1-z -1 )

[0040] In the frequency domain, use e jω Instead of z, the power spectrum of the modulated quantization noise can be expressed as

[0041]

[0042] S e (w) is the unilateral power spectrum density of the quantizer, which can be approximated as white noise. Assuming its peak-to-peak value is a, the power spectrum density is approximately

[0043]

[0044] Noise transfer function 1-z -1 The amplitude-frequency characteristic curve is as follows Figure 4 As shown in the figure, this frequency measurement method clearly demonstrates its ability to suppress noise at low bandwidths. Assuming a 20kHz input signal frequency and a 10MHz standard clock, the noise level at an output sampling rate of 0.1Hz is 0.1mHz / rtHz. Therefore, by designing a cycle counting module based on the sigma-delta noise modulation principle, multiple quantization averaging processes can effectively suppress low-frequency quantization noise, achieving low-noise output.

[0045] The nonlinear compensation module includes a reciprocal unit, a square unit, and a delay aligner unit;

[0046] According to the relationship between the input acceleration and output frequency of the silicon micro-resonant accelerometer

[0047]

[0048] Among them, f is the output frequency, w is the output angular frequency, f n is the natural frequency of the resonant beam, l is the length of the mass block, h is the thickness of the mass block, and w th is the width of the mass block, E is the elastic modulus of the mass block, m is the mass of the mass block, and a is the input acceleration.

[0049] The above equation shows that the relationship between output frequency and input acceleration is nonlinear. In shock and vibration environments, this nonlinearity can cause output acceleration offset. Since the input acceleration and the square of the output frequency are linear, a nonlinear compensation module is implemented after periodic frequency measurement.

[0050] The nonlinear compensation module converts the count difference N into a frequency square fixed-point number q and aligns the square fixed-point number q with the input analog oscillation signal F. This module includes three sub-units: reciprocal calculation, square calculation, and delay alignment.

[0051] First, input the count difference N into the inverse module, that is,

[0052]

[0053] Wherein, M1 represents the reciprocal magnification coefficient. In this embodiment, M1=2 29 , the specific steps are as follows:

[0054] 1) The comparator outputs the indication signal N in the cycle counting module rd When it is high, the highest non-zero bit of the count difference N is determined and amplified to the original bit width. For example, if N[10∶8]=001, then regN=2, and the count difference N is shifted 2 bits to the left.

[0055] 2) Define the 12-bit-wide dividend B = 0x7FF (0x indicates hexadecimal representation), the 22-bit-wide reciprocal c and the counter 2 with the reference clock clk as the counting cycle, its count value cont2, and expand the count difference N bit width to 12 bits, compare the constant value B and the count difference N

[0056] BN>0

[0057] If true, the dividend B is equal to the difference between B and N shifted left by one and increased by one, the quotient c is equal to c shifted left by one and increased by one, and the count value cont2 itself is increased by one. Otherwise, the dividend B is equal to B shifted left by one and increased by one, the reciprocal c is equal to c shifted left by one, and the count value cont2 itself is increased by one.

[0058] Then judge

[0059] cont2==regN+20

[0060] If they are not equal, continue to loop step 2); if they are equal, the output inverse value c is valid. Define counter 3 with reference clock clk as the counting cycle, its count value is cont3, according to the comparator indication signal N rd When cont3 is high, cont3=cont3+1. When cont3=23+regN, the countdown indication signal crd is set to a high level to ensure the synchronization between the countdown indication signal crd and the countdown value c.

[0061] Secondly, the reciprocal value c and the reciprocal indication signal crd are input to the square module, that is,

[0062]

[0063] Among them, M q is the scaling factor, in this embodiment, M q =2 22 , the specific steps are as follows:

[0064] 1) In the countdown indication signal c rd When the level is high, the exponentiation in the square module is defined as 44 bits wide Q3

[0065] Q3={22′b0,c}

[0066] Define the multiplier Q2, Q2=c, and define the count value N;

[0067] 2) Then start judging

[0068] Q2[N]=1

[0069] If it is true, the multiplier Q2 is shifted left by one, the power Q3 is equal to Q3 plus Q2, and the count value N is equal to N plus one. Otherwise, the multiplier Q2 is shifted left by one, the power Q3 remains unchanged, the count value N is equal to N plus one, and then judge

[0070] N==22

[0071] If they are not equal, continue to loop step 2), if they are equal, output the square value fixed point number Define counter 4 with reference clock clk as counting period, whose count value is cont4. When the countdown indication signal crd is high, cont4=cont4+1. When the count value cont4=22, the square indication signal qrd is set to a high level, ensuring the synchronization of the square indication signal qrd and the square fixed-point number q.

[0072] Finally, the square indication signal qrd and the square fixed-point number q are input into the delay alignment module. This module records the high level of the square indication signal qrd through a set of register arrays 1, whose data is in[0∶3], and saves the corresponding square fixed-point number q into another set of registers 2, whose data is [21∶0]R[0∶3], that is,

[0073] if(q rd =1)in[N]=q rd , R[N]=q

[0074] Where N is in[N] and R[N] is the position in its register array.

[0075] Then define a counter 5 with the reference clock clk as the counting period. Its count value is C. When in[N]=1, C starts counting. When the count value reaches the maximum value COUNT (COUNT can be 1k~2k), the output is

[0076] Dout=R[N+1],in[N]=0

[0077] This conversion establishes a one-to-one correspondence between the output signal Dout and the input oscillating signal F. Four registers are used to store data to match the maximum value COUNT of the count value C. Since the frequency of the input oscillating signal F is between 10kHz and 25kHz, each input square wave cycle corresponds to 400 to 1000 clk cycles, allowing the program to run continuously without errors.

[0078] The arbitrary sampling rate adjustment module includes an integrator, a decimator, and a comb. Dout is input into the integrator. The basic principle of the integrator is to perform a simple accumulation of the input data, that is, first beat it through the register, then expand the bit width (until the subsequent addition does not overflow the data), and finally add the input and output of the integrator.

[0079] Dout1=Dout1+Dout

[0080] Dout1 is input into the decimator, which counts the integrator's output data Dout1 and then decimates it every M data interval (M is the sampling rate, input from the host computer via the SPI interface). First, a counter 6 with a modulus M and a reference clock clk as its counting period is defined. Its value is cnt. Then, an indicator signal phase is defined. When cnt = M-1, the output is high, and otherwise, it outputs a low level. When the indicator signal phase is high, the decimated data Dout2 is output.

[0081] Dout1 is input into the comb filter, which processes the data Dout2, performs subtraction to implement low-pass filtering, and outputs the final fixed-point value Dout3.

[0082] The integrator, decimator, and comb filter connected in series form the CIC filter structure. The comb filter filters and suppresses high-frequency noise; the integrator performs a sliding average to reduce quantization error; and the decimator performs a sliding average of count values ​​synchronized to the reference clock to achieve a suitable output rate. By filtering out high-frequency noise, sampling is achieved from the reference clock clk to the specified output rate. Selecting different sampling rates, M, yields data dout3 at different output rates.

[0083] The function of the digital interface module is to communicate with the host computer (such as MCU) through the SPI interface, and it has a complete SPI interface and configuration register. It has an SPI standard four-wire interface SS, SCK, DIN, and DOUT. The host computer configures the sampling value M through DOUT. After the configuration is completed, the address is input through DOUT again to digitally output dout3 from DIN. In this module, a two-level RAM structure is used. When SS is pulled high, the first-level RAM writes data to the second-level RAM. When SS is pulled low, the first-level RAM suspends writing and the second-level RAM starts to transmit its data to the host computer to protect the data and prevent new data from being written before a frame of data is transmitted.

[0084] The layout of the frequency measurement ASIC design is as follows Figure 5 As shown in Figure 2, the frequency measurement ASIC chip was tested experimentally. The analog oscillation signal F output by the silicon micro-resonant accelerometer was collected under normal temperature and static conditions for 20 minutes. The data noise power spectrum density was output by the frequency measurement ASIC, as shown in Figure 2. Figure 6 As shown, it can be seen that the noise presents a slope of 20dB / dec at high frequencies, which meets the first-order Sigma-delta noise modulation principle. The frequency decreases by 10 times, and the noise suppression capability increases by 20dB. The noise spectral density in the 0.1-1Hz bandwidth reaches 0.8mHz / rtHz, which meets the application requirements of silicon micro-resonant accelerometers.

Claims

1. A multi-rate adjustable sampling rate frequency measurement ASIC chip, characterized in that: include: A cycle counting module is used to synchronize the analog oscillation signal F of the silicon micro-resonant accelerometer under test to the reference clock clk provided by the crystal oscillator, output a synchronized square wave signal F1, count the synchronized square wave signal F1 using the reference clock, and output a count value N; The nonlinear compensation module is used to convert the count value N into a fixed-point number q that is proportional to the square of the frequency, and then align the fixed-point number q with the synchronized square wave signal F1 to output the aligned fixed-point number Dout; An arbitrary sampling rate adjustment module is used to adjust the sampling rate of the aligned fixed-point number Dout to achieve the output of an arbitrary sampling rate and finally output the fixed-point number Dout3; Digital interface module, used for communicating with the host computer, including configuring registers and outputting data to the host computer; The nonlinear compensation module includes: The reciprocal unit is used to output the indication signal N in the comparator of the cycle counting module. rd =1, output reciprocal And countdown indication signal c rd ; When the countdown indicator signal c rd =1, indicating that the countdown c has been updated and is available. rd =0, it means the countdown c is not updated and continues the previous countdown; The square unit, in the inverse indication signal c rd When it is 1, the reciprocal unit outputs the reciprocal c and then outputs it after square, that is, outputs the square fixed point number and square indicator signal q rd ; When the square indicator signal q rd =1, indicating that the square fixed point number q has been updated and is available. rd =0, it means that the square fixed point number q is not updated and continues the previous fixed point number; A delay aligner unit, configured to align the square fixed-point number q with the synchronized square wave signal F1, and then output an aligned fixed-point number signal Dout; Where M1 represents the reciprocal magnification coefficient, and M2 represents the reduction coefficient of the reciprocal square of the fixed-point number; The delay aligner unit comprises: Comparator, used to compare the square indication signal q rd Is it a high level? Multiple groups of registers, used to record multiple groups of square indication signals q rd , and the square indication signal q rd The corresponding fixed point number q is based on the two adjacent square indication signals q rd The high level of determines the duration of the output fixed-point number q, which is the duration corresponding to the synchronized square wave signal F1; counter, used when the square indicator signal q rd When the level is high, the counting starts. When the set value is reached, the register outputs the aligned fixed-point number signal Dout. The arbitrary sampling rate adjustment module includes: The integrator is used to add the aligned fixed-point number signal Dout to the fixed-point number output by the integrator itself, and output the sliding average value Dout1 after one beat; A decimator is used to extract a fixed-point value Dout2 from the sliding average value Dout1 according to a set decimation rate; The comb filter is used to perform low-pass filtering on the extracted fixed-point value Dout2 and output a final fixed-point value Dout3.

2. The multi-rate adjustable sampling rate frequency measurement ASIC chip according to claim 1, characterized in that: The cycle counting module includes: A synchronizer unit, configured to synchronize the analog oscillation signal F to the reference clock clk and output a synchronized square wave signal F1; The counter unit is used to continuously count the synchronized square wave signal F1 according to the period of the reference clock clk; The rising edge detector unit uses two sets of registers to detect the rising edge of the synchronized square wave signal F1; The comparator unit is used to compare whether the data stored in one group of registers fa is equal to 1 and whether the data stored in another group of registers fb is equal to 0; when fa = 1 and fb = 0 are satisfied at the same time, the comparator outputs an indication signal N rd =1, otherwise the comparator outputs the indication signal N rd =0; The subtractor is used to calculate the difference between the count values ​​at two adjacent rising edges of the synchronized square wave signal F1 and output the count value N; when the comparator outputs the indication signal N rd =1, indicating that the count value N has been updated and is available. rd =0, indicating that the count value N is not updated and continues to be the previous difference value.

3. The multi-rate adjustable sampling rate frequency measurement ASIC chip according to claim 1, characterized in that: The digital interface module includes: A configuration register is provided for defining a configuration word to control the decimation rate of the decimator; A two-level RAM structure is provided to split the final output fixed-point value Dout3 and output it to the host computer in sequence.

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