Display module and manufacturing method thereof, and display device

Abstract

The embodiments of the present disclosure disclose a display module and a preparation method thereof, and a display device, which relate to the field of display technology and can avoid the problem of reduced transmittance caused by blocking of light by a driving circuit. The display module includes a display panel and a dimming panel superimposed on the display panel. The display panel has multiple pixel areas. The dimming panel has multiple dimming areas, and one dimming area covers at least one pixel area in a direction perpendicular to the display panel. Among them, the dimming panel includes multiple dimming electrodes and multiple signal lines. A dimming electrode is located in a dimming area, and there is a gap between any two adjacent dimming electrodes. Each dimming electrode is directly electrically connected to at least one signal line; the signal line is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area where the dimming electrode is located to the dimming electrode electrically connected thereto. The above-mentioned display module is applied to a display device so that the display device displays a picture.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display module and a preparation method thereof, and a display device. Background Art

[0002] Currently, High Dynamic Range (HDR) technology is widely used in large-size display devices such as televisions (TVs) to enable the display devices to have a high contrast ratio (CR).

[0003] In the related technologies, high dynamic range technology includes two implementation methods, one is backlight unit (English abbreviation: Mini LED BLU) technology, and the other is double-layer panel (Panel BD Cell) technology. Among them, the backlight unit technology can realize multi-zone dimming of the display device, but the number of LED lamps set in the backlight unit is large and the yield is low, resulting in a large thickness and high manufacturing cost of the display device. Compared with the backlight unit technology, the double-layer panel technology can realize multi-zone dimming of the display device while reducing the thickness and manufacturing cost of the display device, becoming one of the development directions in the field of display technology.

[0004] Public Content

[0005] An object of some embodiments of the present disclosure is to provide a display module and a method for manufacturing the same, and a display device, so as to increase the light transmittance of a dimming panel in the display module and improve the display effect of the display module.

[0006] To achieve the above objectives, some embodiments of the present disclosure provide the following technical solutions:

[0007] In a first aspect, a display module is provided, comprising a display panel, and a dimming panel superimposed on the display panel. The display panel has a plurality of pixel areas. The dimming panel has a plurality of dimming areas, and one dimming area covers at least one pixel area in a direction perpendicular to the display panel. The dimming panel comprises a plurality of dimming electrodes and a plurality of signal lines. A dimming electrode is located in one of the dimming areas, and there is a gap between any two adjacent dimming electrodes. Each of the dimming electrodes is directly electrically connected to at least one signal line; the signal line is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area where the dimming electrode is located to the dimming electrode electrically connected thereto.

[0008] In the above-mentioned embodiment of the present disclosure, each dimming electrode in the dimming panel is directly electrically connected to at least one signal line, and a control voltage signal for controlling the light transmittance of the dimming area where the dimming electrode is located is transmitted to the dimming electrode electrically connected thereto through the signal line. That is, the dimming panel adopts a passive driving method, and a driving circuit does not need to be set in the dimming panel, thereby avoiding the problem of blocking the light by the driving circuit and causing its transmittance to be reduced, thereby improving the light transmittance of the dimming panel and improving the display effect of the display module.

[0009] In some embodiments, the plurality of dimming electrodes are arranged in an array, the row direction of the plurality of dimming electrodes is a first direction, and the column direction of the plurality of dimming electrodes is a second direction.

[0010] Each signal line extends in its entirety along the second direction, and the plurality of signal lines are arranged in parallel along the first direction. The orthographic projection of each signal line on the display panel at least partially overlaps with the orthographic projection of a column of dimming electrodes to which it is electrically connected on the display panel.

[0011] In some embodiments, the signal line includes a plurality of bending portions connected in sequence, and the signal line is in a folded line shape. Every two adjacent bending portions form a bending unit. Along a direction perpendicular to the display panel, one dimming electrode covers the plurality of bending units of the signal line.

[0012] In some embodiments, along the first direction, one bending unit passes through 1 to 6 pixel areas. Along the second direction, one bending unit passes through 1 to 6 pixel areas.

[0013] In some embodiments, the dimming panel further includes a first shading pattern, the orthographic projection of the first shading pattern on the display panel is located between the orthographic projections of two adjacent columns of the dimming electrodes on the display panel. The first shading pattern extends along the second direction as a whole. The first shading pattern is made of the same material as the signal line and is disposed on the same layer.

[0014] In some embodiments, when the signal line is in a zigzag shape, the edge contour of the dimming electrode extending along the second direction is in a zigzag shape that is the same as the shape of the signal line, and the edge contour is parallel to the signal line. Along the first direction, the shapes of the edge contours of two adjacent dimming electrodes that are close to each other are complementary.

[0015] The first light shielding pattern is in a fold line shape which is the same as the edge contour shape of the light-adjusting electrode extending along the second direction, and the first light shielding pattern and the edge contour are parallel to each other.

[0016] In some embodiments, the dimming panel further includes a second shading pattern, the orthographic projection of the second shading pattern on the display panel is located between the orthographic projections of two adjacent rows of the dimming electrodes on the display panel. The second shading pattern extends along the first direction as a whole, and the second shading pattern is disconnected at a position where it intersects with the signal line. The second shading pattern is made of the same material as the signal line and is disposed on the same layer.

[0017] In some embodiments, the dimming panel further comprises a driver chip disposed on one side of the dimming panel, the driver chip being directly electrically connected to the plurality of signal lines. The driver chip is configured to provide the control voltage signals to the plurality of signal lines respectively, so as to control the light transmittance of the dimming area where the dimming electrodes electrically connected to the respective signal lines are located.

[0018] In some embodiments, the dimming panel further includes a first passivation layer disposed between the plurality of dimming electrodes and the plurality of signal lines, the first passivation layer having a plurality of first via holes, and each of the dimming electrodes is electrically connected to a corresponding signal line through at least one first via hole.

[0019] In some embodiments, when the signal line includes a plurality of bends connected in sequence and the signal line is in a zigzag shape, the orthographic projection of the first via on the display panel is located at the intersection of the orthographic projections of two adjacent bends on the display panel.

[0020] In some embodiments, the signal line has a line width ranging from 2.2 μm to 3.0 μm.

[0021] In some embodiments, the display panel includes a first substrate and a second substrate arranged relatively to each other, a plurality of pixel driving circuits arranged on the side of the first substrate facing the second substrate, and a color filter layer and a black matrix pattern arranged on the side of the second substrate facing the first substrate.

[0022] The dimming panel further includes a third substrate located on a side of the second substrate away from the first substrate and arranged opposite to the second substrate. The plurality of dimming electrodes and the plurality of signal lines are arranged on a side of the third substrate facing the second substrate, or on a side of the second substrate facing the third substrate.

[0023] The dimming panel and the display panel share the second substrate; and the orthographic projection of the black matrix pattern on the second substrate covers the orthographic projection of the gap between any two adjacent dimming electrodes on the second substrate.

[0024] In some embodiments, the dimming panel further comprises a reference electrode disposed on one of the second substrate and the third substrate. The orthographic projection of the reference electrode on the second substrate overlaps with the orthographic projection of each of the dimming electrodes on the second substrate. The reference electrode is configured to transmit a reference voltage signal and generate an electric field between the reference electrode and each of the dimming electrodes.

[0025] In some embodiments, the reference electrode and the plurality of dimming electrodes are respectively disposed on different substrates.

[0026] Alternatively, the reference electrode and the plurality of dimming electrodes are disposed on the same substrate. The reference electrode is relatively far from the substrate where the reference electrode and the plurality of dimming electrodes are located, and a portion of the reference electrode facing each of the dimming electrodes has a plurality of slits.

[0027] Alternatively, the reference electrode and the plurality of dimming electrodes are disposed on the same substrate. The reference electrode is relative to the plurality of dimming electrodes and is close to the substrate where the reference electrode and the plurality of dimming electrodes are located, and each of the dimming electrodes has a plurality of slits.

[0028] In some embodiments, the width of the gaps between the plurality of dimming electrodes ranges from 3.0 μm to 3.5 μm.

[0029] In some embodiments, the width of the black matrix pattern ranges from 4 μm to 6 μm.

[0030] In some embodiments, the display module further includes a first polarizer disposed on a side of the first substrate away from the second substrate, a metal wire grid polarization layer disposed on a side of the second substrate away from the first substrate, and a second polarizer disposed on a side of the third substrate away from the first substrate. The directions of the absorption axes of the first polarizer and the second polarizer are respectively perpendicular to the direction of the absorption axis of the metal wire grid polarization layer.

[0031] In some embodiments, when the plurality of dimming electrodes are disposed on the second substrate and the reference electrode is disposed on the third substrate, the metal wire grid polarization layer is located between the second substrate and the plurality of dimming electrodes. When the reference electrode is disposed on the second substrate and the plurality of dimming electrodes is disposed on the third substrate, the metal wire grid polarization layer is located between the second substrate and the reference electrode.

[0032] When the plurality of dimming electrodes and the reference electrode are both disposed on the second substrate and the plurality of dimming electrodes are closer to the second substrate relative to the reference electrode, the metal wire grid polarization layer is located between the second substrate and the plurality of dimming electrodes.

[0033] When the plurality of dimming electrodes and the reference electrode are both disposed on the second substrate, and the reference electrode is closer to the second substrate than the plurality of dimming electrodes, the metal wire grid polarization layer is located between the second substrate and the reference electrode.

[0034] In a second aspect, a display device is provided, comprising the display module described in any one of the above embodiments, and a backlight module disposed on a side of the dimming panel away from the display panel. The backlight module is configured to provide light for the display module.

[0035] The beneficial effects that can be achieved by the display device provided in the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display module described in any of the above embodiments, and will not be elaborated here.

[0036] In a third aspect, a method for preparing a display module is provided, comprising: forming a plurality of pixel driving circuits on the first substrate.

[0037] A color filter layer and a black matrix pattern are formed on the second substrate.

[0038] The first substrate formed with the plurality of pixel driving circuits is assembled with the second substrate formed with the color filter layer and the black matrix pattern to form a display panel, wherein the display panel has a plurality of pixel regions.

[0039] A plurality of dimming electrodes and a plurality of signal lines are formed on the third substrate or on a side of the second substrate away from the first substrate.

[0040] The third substrate is assembled with the display panel to form a dimming panel. The third substrate is located on the side of the second substrate away from the first substrate. The dimming panel and the display panel share the second substrate. The dimming panel has multiple dimming areas, and one dimming area covers at least one pixel area along a direction perpendicular to the display panel. A dimming electrode is located in one of the dimming areas, and there is a gap between any two adjacent dimming electrodes. Each of the dimming electrodes is directly electrically connected to at least one signal line, and the signal line is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area where the dimming electrode is located to the dimming electrode electrically connected thereto.

[0041] The beneficial effects that can be achieved by the method for preparing the display module provided in the embodiment of the present disclosure are the same as the beneficial effects that can be achieved by the display module described in any of the above embodiments, and will not be elaborated here.

[0042] In some embodiments, when the plurality of dimming electrodes and the plurality of signal lines are formed on the third substrate, the preparation method further includes: before aligning the third substrate with the display panel, forming a reference electrode on a side of the second substrate away from the first substrate; forming a plurality of dimming electrodes on a side of the third substrate close to the first substrate, one dimming electrode being located in one of the dimming regions, and a gap being present between any two adjacent dimming electrodes.

[0043] During the process of assembling the third substrate and the display panel, the orthographic projection of the black matrix pattern on the second substrate covers the orthographic projection of the gap between any two adjacent dimming electrodes on the second substrate.

[0044] In some embodiments, when the plurality of dimming electrodes and the plurality of signal lines are formed on a side of the second substrate away from the first substrate, the preparation method further includes: before aligning the third substrate with the display panel, forming a plurality of dimming electrodes on a side of the second substrate away from the first substrate, one dimming electrode being located in one dimming area, and a gap being provided between any two adjacent dimming electrodes; and forming a reference electrode on a side of the third substrate close to the first substrate.

[0045] In the process of forming a plurality of dimming electrodes on a side of the second substrate away from the first substrate, the orthographic projection of the black matrix pattern on the second substrate covers the orthographic projection of the gap between any two adjacent dimming electrodes on the second substrate.

[0046] In some embodiments, the preparation method also includes: before aligning the third substrate with the display panel, using a composition process to form a metal wire grid polarization layer on a side of the second substrate away from the first substrate; and forming an insulating layer on a side of the metal wire grid polarization layer away from the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0048] Figure 1 is a structural schematic diagram of a display module according to the related art;

[0049] Figure 2 is a top view of a display module according to some embodiments of the present disclosure;

[0050] Figure 3 for Figure 2 A partial cross-sectional view along the section line OO';

[0051] Figure 4 is a top view of a display panel according to some embodiments of the present disclosure;

[0052] Figure 5 is a pixel architecture diagram of a display panel according to some embodiments of the present disclosure;

[0053] Fig. 6A is a top view of a dimming panel according to some embodiments of the present disclosure;

[0054] Figure 6B is a top view of another dimming panel according to some embodiments of the present disclosure;

[0055] Figure 7 is a partial cross-sectional view of a display module according to some embodiments of the present disclosure;

[0056] Figure 8 is a partial cross-sectional view of another display module according to some embodiments of the present disclosure;

[0057] Fig. 9 is a partial cross-sectional view of another display module according to some embodiments of the present disclosure;

[0058] Fig.10 is a partial cross-sectional view of another display module according to some embodiments of the present disclosure;

[0059] Fig.11 is a partial cross-sectional view of another display module according to some embodiments of the present disclosure;

[0060] Fig.12 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0061] Fig.13A is a basic flow chart of a method for preparing a display module according to some embodiments of the present disclosure;

[0062] Fig. 13B is a specific flow chart of a method for preparing a display module according to some embodiments of the present disclosure;

[0063] Figure 14A to Figure 14K Schematic diagram of each step of a method for preparing a display module according to some embodiments of the present disclosure;

[0064] Fig.15Ais a basic flow chart of another method for preparing a display module according to some embodiments of the present disclosure;

[0065] Fig. 15B is a specific flow chart of another method for preparing a display module according to some embodiments of the present disclosure;

[0066] Figures 16A to 16K Schematic diagram of each step of another method for preparing a display module according to some embodiments of the present disclosure;

[0067] Fig.17A and Fig. 17B 3 is a distribution diagram of brightness values ​​at various positions in the gap region between dimming electrodes according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0068] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0069] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0070] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0071] When describing some embodiments, the term "electrically connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0072] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0073] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0074] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0075] In related technologies, such as Figure 1 As shown, the display module 100 includes a display panel 1 and a dimming panel 2 which are stacked. The dimming panel 2 is aligned with the display panel 1 and attached together to realize the assembly of the dimming panel 2 and the display panel 1. The backlight module can be set on the side of the dimming panel 2 in the display module 100 away from the display panel 1, and the light emitted by the backlight module passes through the dimming panel 2 and the display panel 1 in sequence. The dimming panel 2 is configured to perform partition modulation on the light passing through itself and incident on the display panel 1, and the display panel 1 is configured to display the picture.

[0076] In order to realize the partition modulation of the backlight brightness by the dimming panel 2, a dimming electrode and a driving circuit electrically connected to the dimming electrode are set in the dimming panel 2 corresponding to each dimming area, and the driving circuit is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area where the dimming electrode is located to the dimming electrode electrically connected thereto. In other words, the dimming panel 2 adopts an active drive mode, but because the driving circuit includes opaque structures such as thin film transistors and metal signal lines, the light transmittance of the dimming panel 2 is reduced, which affects the display effect of the display module 100.

[0077] To solve the above problems, some embodiments of the present disclosure provide a display module, such as Figure 2 and Figure 3 As shown, the display module 200 includes a display panel 3 and a dimming panel 4 superimposed on the display panel 3 .

[0078] The display panel 3 is configured to display images. Figure 4 and Figure 5 As shown, the display panel 3 has a display area AA (Active Area, referred to as AA area; also referred to as an effective display area) and a peripheral area BB located at least on one side of the display area AA. The display area AA of the display panel 3 includes a plurality of sub-pixel areas P, each of which has a sub-pixel disposed therein. The display area AA is also provided with a plurality of gate scanning signal lines GL (Gate Line) extending along the row direction X in which the plurality of sub-pixel areas P are arranged, and a plurality of data signal lines DL (Data Line) extending along the column direction Y in which the plurality of sub-pixel areas P are arranged.

[0079] For the convenience of explanation, the above-mentioned multiple sub-pixel regions P and the multiple sub-pixels located in the multiple sub-pixel regions P are described in the present disclosure by taking the matrix arrangement as an example. At this time, the sub-pixels arranged in a row along the row direction X are called a row of sub-pixels, and the sub-pixels arranged in a row along the column direction Y are called a column of sub-pixels. A row of sub-pixels can be connected to a gate scanning signal line GL, and a column of sub-pixels can be connected to a data signal line DL. A pixel driving circuit T' is provided in a sub-pixel region P for controlling the sub-pixels to display.

[0080] The pixel driving circuit T' in the sub-pixel region P is described below by way of example.

[0081] like Figure 5 As shown, the pixel driving circuit T' comprises a thin film transistor M and a liquid crystal capacitor C. The two plates of the liquid crystal capacitor C are respectively formed by a pixel electrode and a common electrode. The gate of the thin film transistor M is connected to the gate line GL, the first electrode is connected to the data line DL, and the second electrode is connected to the liquid crystal capacitor C. The thin film transistor M is used to transmit the data signal on the data line DL to the liquid crystal capacitor C.

[0082] At least two sub-pixels form one pixel, and the sub-pixel regions P where the at least two pixels included in one pixel are located form one pixel region P'. Figure 2 and Figure 4 As shown, along the row direction X where multiple sub-pixel regions P are arranged, every three sub-pixels form a pixel. The three sub-pixels included in a pixel may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Accordingly, the sub-pixel regions P where the three sub-pixels included in a pixel are located form a pixel region P'.

[0083] like Figure 2 , Figure 3 and Fig. 6A As shown, the dimming panel 4 has a plurality of dimming areas D. Along a direction C perpendicular to the display panel 3, one dimming area D covers at least one pixel area P'. Figure 2 The case where one dimming area D covers one pixel area P' is shown. The dimming panel 4 is configured to adjust the transmittance of light passing through each dimming area D to the display panel 3, that is, the dimming panel 4 has a local dimming (English full name: Local Dimming) function, so that the display image of the display module 200 has a higher contrast.

[0084] Exemplarily, along the direction C perpendicular to the display panel 3, one dimming area D covers one pixel area P' or at least two pixel areas P'. For example, when the resolution of the display panel 3 is 3840×2160 and the size of one pixel area P' is 90μm×90μm, "resolution is 3840×2160", which means that there are 3840 pixels along the row direction of the multiple pixel areas P' (i.e., the row direction X of the multiple sub-pixel areas P), and 2160 pixels along the column direction of the multiple pixel areas P' (i.e., the row direction Y of the multiple sub-pixel areas P). One dimming area D can be set to cover 80×80 pixel areas P', so the number of dimming areas D is In this way, the local dimming requirement of the dimming panel 4 can be met, thereby improving the contrast of the displayed image of the display module 200 .

[0085] It should be noted that, in the above expression, “the size of the pixel area P′ is 90 μm×90 μm” means that along the row direction where multiple pixel areas P′ are arranged, the size of the pixel area P′ is 90 μm, and along the column direction where multiple pixel areas P′ are arranged, the size of the pixel area P′ is 90 μm.

[0086] like Figure 3 and Figure 7 As shown, the dimming panel 4 includes a plurality of dimming electrodes 43 and a plurality of signal lines 41A.

[0087] One dimming electrode 43 is located in one dimming area D, and there is a gap S between any two adjacent dimming electrodes 43 .

[0088] Each dimming electrode 43 is directly electrically connected to at least one signal line 41A, that is, the dimming panel 4 adopts a passive driving mode. The signal line 41A is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area D where the dimming electrode 43 is located to the dimming electrode 43 electrically connected thereto.

[0089] Compared with the conventional dimming panel adopting active driving mode, in the above-mentioned embodiment of the present disclosure, a control voltage signal for controlling the light transmittance of the dimming area D where the dimming electrode 43 is located is transmitted to the dimming electrode 43 electrically connected thereto through the signal line 41A, that is, the dimming panel 4 adopts passive driving mode, and there is no need to set up a driving circuit in the dimming panel 4, thereby avoiding the problem of blocking the light by the driving circuit and causing its transmittance to be reduced, thereby improving the light transmittance of the dimming panel 2 and improving the display effect of the display module 100.

[0090] like Fig. 6A As shown, the plurality of dimming electrodes 43 are arranged in an array, and the row direction of the plurality of dimming electrodes 43 is the first direction V, and the column direction of the plurality of dimming electrodes 43 is the second direction U.

[0091] Each signal line 41A extends in the second direction U as a whole, and a plurality of signal lines 41A are arranged in parallel in the first direction V.

[0092] The orthographic projection of each signal line 41A on the display panel 3 at least partially overlaps with the orthographic projection of a column of dimming electrodes 43 to which it is electrically connected, so that the dimming electrodes 43 and the signal line 41A are electrically connected through the vias.

[0093] It should be noted that the first direction V and the second direction U may be perpendicular to each other. In this case, the first direction V may be in the same direction as the row direction X in which the plurality of pixel regions P' are arranged, and the second direction U may be in the same direction as the column direction Y in which the plurality of pixel regions P' are arranged.

[0094] It should be noted that “each signal line 41A extends along the second direction U as a whole” means that the signal line 41A as a whole has a tendency to extend along the second direction U. The signal line 41A may be a straight line, so that each part of the signal line 41A extends along the second direction U; the signal line may also be a non-straight line, such as a wavy line, a folded line, a sawtooth line, etc., so that each part of the signal line 41A may deviate from the second direction U, but the signal line 41A as a whole has a tendency to extend along the second direction U.

[0095] In some embodiments, Fig. 6A and Figure 6B As shown, the signal line 41A includes a plurality of bending portions 410 connected in sequence, and the signal line 41A is in a folded line shape as a whole. Moreover, in the signal line 41A, every two adjacent bending portions 410 form a bending unit 411. Along the direction C perpendicular to the display panel 3, a dimming electrode 43 covers the plurality of bending units 411 of the signal line 41A. Through the design of the signal line 41A, the problem of moiré on the display screen can be improved.

[0096] In some embodiments, in each bending unit 411, the length and the inclination angle of the bending portion 410 can be set according to the size of the dimming electrode 43 and the number of bending units 411 covered by each dimming electrode 43 along the second direction U. Here, "the inclination angle of the bending portion 410" refers to the angle between the bending portion and the first direction V. The inclination angle of the bending portion 410 is less than 90°, for example, within the range of 0 to 45°, for example, 26° or 30°, etc.

[0097] In some embodiments, Figure 6B As shown, one bending unit 411 passes through 1 to 6 pixel regions P' along the first direction V. For example, one bending unit 411 may pass through 1, 2, 3, 4, 5 or 6 pixel regions P'.

[0098] Along the second direction U, one bending unit 411 passes through 1 to 6 pixel regions P'. For example, one bending unit 411 may pass through 1, 2, 3, 4, 5 or 6 pixel regions P'. It can be seen that the signal line 41A may be designed in a variety of ways.

[0099] Moire simulation experiments were conducted on signal lines 41A with different designs, and the experimental results are shown in Table 1 below:

[0100] Table 1

[0101]

[0102] Here, “split” refers to an example of a different design of the signal line 41A.

[0103] “Line width” refers to the line width of the signal line 41A.

[0104] The “ratio (column direction Y) main:sub” refers to the ratio of the number of pixel regions P′ passed by each bending unit 411 of the signal line 41A along the column direction Y (i.e., the second direction U) in which the plurality of pixel regions P′ are arranged. For example, the ratio (column direction Y) main:sub is 1:2, indicating that each bending unit 411 passes through two pixel regions P′ along the column direction Y (i.e., the second direction U).

[0105] The “ratio (row direction X) main:sub” refers to the ratio of the number of pixel regions P′ passed by each bend 410 of the signal line 41A along the row direction X (i.e., the first direction V) in which the plurality of pixel regions P′ are arranged. For example, the ratio (row direction X) main:sub is 1:3, indicating that each bend 410 passes through three pixel regions P′ along the row direction X (i.e., the first direction V).

[0106] The “moiré result” refers to the severity of the moiré produced on the display screen under different designs of the signal line 41A.

[0107] It can be seen from Table 1 above that the signal line 41A has the lightest moiré pattern on the display screen under the split4 design, that is, the signal line 41A has a line width of 2.2 μm, a ratio (column direction Y) main:sub of 1:4, and a ratio (row direction X) main:sub of 1:3.

[0108] Furthermore, by comparing split3 and split4, it can be seen that when the ratio (column direction Y) main:sub and the ratio (row direction X) main:sub of the signal line 41A are the same, the smaller the line width of the signal line 41A, the lighter the moiré produced on the display screen.

[0109] Therefore, combined with the routing design of split4 in Table 1, in order to further improve the moiré problem generated by the display screen, in some embodiments of the present disclosure, the line width range of the signal line 41A can be 2.2μm to 3.0μm, for example, 2.2μm, 2.4μm, 2.6μm, 2.8μm or 3.0μm, etc.

[0110] For example, Figure 6B As shown, along the second direction U, the ratio of each bending unit 411 of the signal line 41A to the number of pixel areas P' it passes through is 1:4, that is, each bending unit 411 passes through 4 pixel areas P'; along the first direction V, the ratio of each bending unit 411 of the signal line 41A to the number of pixel areas P' it passes through is 1:3, that is, each bending unit 411 passes through 3 pixel areas P'.

[0111] In some embodiments, Figure 3 , Fig. 6A , Figure 6B and Figure 7 As shown, the dimming panel 4 further includes a first passivation layer 42A disposed between the plurality of dimming electrodes 43 and the plurality of signal lines 41A. The first passivation layer 42A has a plurality of first via holes H1 . Each dimming electrode 43 is electrically connected to a corresponding signal line 41A through at least one first via hole H1 .

[0112] Exemplarily, each dimming electrode 43 is electrically connected to a corresponding signal line 41A through a first via hole H1 .

[0113] Exemplarily, each dimming electrode 43 is electrically connected to a corresponding signal line 41A through at least two first via holes H1 , such as two, three or four first via holes H1 , which can reduce the resistivity of the electrical connection between the dimming electrode 43 and the signal line 41A.

[0114] Exemplarily, the material of the first passivation layer 42a includes silicon nitride (chemical formula: SiN x ).

[0115] In some embodiments, Figure 6B As shown, when the signal line 41A includes a plurality of bends 410 connected in sequence and the signal line 41A is in a zigzag shape, the orthographic projection of the first via H1 on the display panel 3 is located at the intersection of the orthographic projections of two adjacent bends 410 on the display panel 3, that is, the first via H1 is located at the corner of the bend unit 411. Compared with setting the first via H1 at non-end positions of the bend 410 (for example, the middle position of the bend 410), the above-mentioned setting of the first via H1 at the intersection of two adjacent bends 410 can reduce the resistivity of the electrical connection between the dimming electrode 43 and the signal line 41A.

[0116] In some embodiments, Fig. 6A and Figure 6B As shown, the dimming panel 4 further includes a driving chip 48 disposed on one side of the dimming panel 4 , and the driving chip 48 is electrically connected to the plurality of signal lines 41A.

[0117] The driving chip 48 is configured to provide a control voltage signal to each signal line 41A respectively, so as to control the voltage of the dimming electrode 43 electrically connected to each signal line 41A, thereby achieving individual control of the dimming electrode 43 .

[0118] In related technologies, such as Figure 1 As shown, when the display module 100 is displaying images, there is a problem that the edges of the dimming electrodes are bright, which affects the display quality; especially when displaying low grayscale images, this problem is more obvious.

[0119] The inventors of the present disclosure have found through research that one of the reasons for the above-mentioned problem is that since there are gaps (Space) between the plurality of dimming electrodes, the liquid crystal in the area facing the gaps cannot be effectively regulated, thus causing light leakage in the gaps.

[0120] To solve the above problem, in some embodiments, a light leakage simulation experiment is performed for the gap S between the plurality of dimming electrodes 43 at different gap widths. The experimental results are shown in Table 2 below:

[0121] Table 2

[0122]

[0123] The “affected width” refers to the width of the light leakage area affected by the gap S. It should be noted that, affected by the deflection of the liquid crystal molecules, the light leakage area caused by the gap S between two adjacent dimming electrodes 43 includes not only the gap area, but also the areas on both sides of the gap S in the extending direction perpendicular to the gap S. Therefore, in the extending direction perpendicular to the gap S, the width of the light leakage area will be greater than the width of the gap area.

[0124] “Gap Brightness Max” refers to the maximum brightness value in the light leakage area.

[0125] “Block brightness” refers to the average brightness value of the dimming area D where the dimming electrode 43 is located.

[0126] It can be obtained from Table 2 above that, when the block brightness is the same, it can be considered that when the control voltage on the dimming electrode 43 is the same, the smaller the width of the gap S, the smaller the affected width, and the smaller the gap brightness Max, that is, the smaller the width of the gap S between two adjacent dimming electrodes 43, the smaller the width of the light leakage area affected by the gap S, and the smaller the maximum brightness value in the gap, so that the visual effect of the light leakage is milder.

[0127] Therefore, in combination with the above experimental results, the width of the gap S between two adjacent dimming electrodes 43 can be set as small as possible to reduce light leakage from the gap S. For example, the width of the gap S can be set to the minimum value that the device can achieve. For example, the width of the gap S can be set to 2.8 μm.

[0128] Considering that if the width of the gap S is set too small, the preparation difficulty may increase, and there may be too much etching residue, which may lead to the problem of inability to effectively insulate adjacent dimming electrodes 43, the width of the gap S between multiple dimming electrodes 43 can be set to a range of 3.0μm to 3.5μm, for example, 3.0μm, 3.1μm, 3.3μm, 3.4μm or 3.5μm, etc., so as to reduce the light leakage of the gap S without significantly increasing the process difficulty and ensuring effective insulation between adjacent dimming electrodes 43.

[0129] In order to verify the experimental results of the above light leakage simulation experiment, the following experiment was conducted:

[0130] refer to Fig.17A and Fig. 17B , Fig.17A The figure shows the distribution of the brightness values ​​at various positions in the gap in the extending direction perpendicular to the gap S when the width of the gap S is 3.5 μm; Fig. 17B The figure shows the distribution of the brightness values ​​of various regions in the gap S in a direction perpendicular to the extension direction of the gap S when the gap width is 10 μm.

[0131] It can be seen that when the control voltage on the dimming electrode 43 is the same, that is, when the block brightness is the same, the smaller the width of the gap S is, the smaller the gap brightness Max is, that is, the smaller the maximum brightness value in the light leakage area is, and thus the visual effect of the light leakage is milder.

[0132] In addition, the problem of light leakage in the gap S between the dimming electrodes 43 can be solved by the following embodiments.

[0133] In some embodiments, Figure 6B As shown, the dimming panel 4 further includes a first light shielding pattern 41B which is made of the same material and arranged in the same layer as the signal line 41A, and the first light shielding pattern 41B extends along the second direction U as a whole.

[0134] It should be noted that the description of “the first shading pattern 41B extends along the second direction U as a whole” is similar to the description of “each signal line 41A extends along the second direction U as a whole” mentioned above, that is, the first shading pattern 41B has a tendency to extend along the second direction U as a whole.

[0135] The orthographic projection of the first shading pattern 41B on the display panel 3 is located between the orthographic projections of two adjacent columns of dimming electrodes 43 on the display panel 3. The first shading pattern 41B is utilized to shield the gap between two adjacent columns of dimming electrodes 43, thereby reducing light leakage in the gap between the dimming electrodes and alleviating the phenomenon of brightening at the edges of the dimming electrodes 43.

[0136] For example, Figure 6B As shown, when the signal line 41A is in a zigzag shape, the edge profile of the dimming electrode 43 extending along the second direction U is in the same zigzag shape as the signal line 41A, and the edge profile is parallel to the signal line 41A. And along the first direction V, the shapes of the edge profiles of the two adjacent dimming electrodes 43 close to each other are complementary. On this basis, the first light shielding pattern 41B is in the same zigzag shape as the edge profile of the dimming electrode 43 extending along the second direction U, and the first light shielding pattern 41B is parallel to the edge profile.

[0137] Through the above-mentioned setting method, the edge contour of the dimming electrode 43 extending along the second direction U and the first shading pattern 41B are the same as the shape of the signal line 41A, that is, they are both in the shape of a broken line, so that the orthographic projection of the first shading pattern 41B on the display panel 3 is located between the orthographic projections of two adjacent columns of dimming electrodes 43 on the display panel 3, thereby shielding the gap between the two adjacent dimming electrodes 43.

[0138] Furthermore, compared with the signal line 41A being in a zigzag shape, the first shading pattern 41B is in a straight line shape. In the above embodiment, the first shading pattern 41B and the signal line 41A have the same shape, which can ensure the uniformity of the display effect.

[0139] In addition, the first shading pattern 41B and the signal line 41A are made of the same material and are disposed in the same layer, so that the two can be formed under the same process flow, without the need for additional process steps for forming the first shading pattern 41B, which is conducive to simplifying the preparation process of the display module.

[0140] It should be noted that, in the embodiment of the present disclosure, the shape of the dimming electrode 43 can be a rectangle, for example, a square. The shape of the dimming electrode 43 can also be other shapes, which are not limited in the embodiment of the present disclosure. When the overall shape of the dimming electrode 43 is determined, the edge contour of the dimming electrode 43 can be a straight line or a non-straight line, for example, Figure 6B As shown, although the edge contour of the dimming electrode 43 extending along the second direction U is in a broken line shape, the overall shape of the dimming electrode 43 can still be regarded as being approximately rectangular, for example, approximately square.

[0141] In some embodiments, Figure 6B As shown, the dimming panel 43 further includes a second light shielding pattern 41C made of the same material and disposed in the same layer as the signal line 41A. The second light shielding pattern 41C extends along the first direction V as a whole, and is disconnected at a position where it intersects with the signal line 41A.

[0142] Based on this, the orthographic projection of the second shading pattern 41C on the display panel 3 is located between the orthographic projections of two adjacent rows of dimming electrodes 43 on the display panel 3. The second shading pattern 41C can block the gap between two adjacent rows of dimming electrodes 43, further reducing light leakage in the gap between the dimming electrodes 43 and improving the phenomenon of the edges of the dimming electrodes 43 appearing bright.

[0143] Furthermore, the second light shielding pattern 41C and the signal line 41A are made of the same material and are disposed in the same layer, so that the two can be formed in the same process flow without additional process steps for forming the second light shielding pattern 41C, which is beneficial to simplifying the preparation process of the display module.

[0144] In addition, the second shading pattern 41C extends as a whole along the first direction V, and is disconnected at the intersection with the signal line 41A, thereby avoiding electrical connection between the second shading pattern 41C and the signal line 41A, which would cause crosstalk in the control voltage signal transmitted on the signal line 41A.

[0145] In addition to the above embodiments, in the related art, during the process of bonding and assembling the dimming panel 2 and the display panel 1, the black matrix pattern in the display panel 1 will be made to correspond to the gap between two adjacent dimming electrodes as much as possible, so that the black matrix pattern can be used to block the gap between two adjacent dimming electrodes, thereby reducing light leakage in the gap.

[0146] However, since each dimming electrode in the dimming panel 2 corresponds to multiple sub-pixels in the display panel 1, the size of the dimming electrode is relatively large compared to the size of the sub-pixel, and the gap width between two adjacent dimming electrodes is also large; in addition, the alignment between the dimming panel 2 and the display panel 1 is performed between the two panels, so the alignment accuracy is not high. Therefore, the black matrix pattern cannot effectively block the gap between two adjacent dimming electrodes, which causes the edge of the dimming electrode to be shiny, affecting the picture quality of the display module 100; especially when displaying low grayscale pictures, the phenomenon of the edge of the dimming electrode being shiny will be more obvious.

[0147] To solve the above problems, in some embodiments, Figure 3 As shown, the display panel 3 includes a first substrate 30 and a second substrate 31 arranged opposite to each other, a driving circuit layer T arranged on the side of the first substrate 30 facing the second substrate 31 , and a color filter layer 32 and a black matrix pattern 33 arranged on the side of the second substrate 31 facing the first substrate 30 .

[0148] A driving circuit layer T is set on the first substrate 30 to form an array substrate 3A, and a color filter layer 32 and a black matrix pattern 33 are set on the second substrate 31 to form a color filter substrate 3B. The array substrate 3A and the color filter substrate 3B are assembled to form the above-mentioned display panel 3.

[0149] like Figure 2 and Figure 3 As shown, the orthographic projection of the black matrix pattern 33 on the second substrate 31 covers the orthographic projection of the gap S between any two adjacent dimming electrodes 43 on the second substrate 31 .

[0150] Through the above-mentioned setting method, the orthographic projection of the black matrix pattern 33 on the second substrate 31 covers the orthographic projection of the gap S between any two adjacent dimming electrodes 43 on the second substrate 31, so that the black matrix pattern 33 blocks the gap S between any two adjacent dimming electrodes 43, preventing light from directly passing through the gap S and emitting to the display panel 1, further improving the problem of bright edges of the dimming electrode 43.

[0151] The display panel 3 may be a liquid crystal display panel. In this case, the display panel 3 includes, in addition to the array substrate 3A and the color filter substrate 3B, a first liquid crystal layer 34 located between the array substrate 3A and the color filter substrate 3B. By applying an electric field to the first liquid crystal layer 34, the liquid crystal molecules located in each sub-pixel region P in the first liquid crystal layer 34 are controlled to deflect to different degrees, thereby achieving control of the grayscale of each sub-pixel.

[0152] like Figure 2 and Figure 3As shown, the color filter layer 32 includes a plurality of filter parts, and the plurality of filter parts are respectively opposite to the plurality of sub-pixel regions P. The plurality of filter parts include, for example, a plurality of red filter parts, a plurality of green filter parts, and a plurality of blue filter parts. The black matrix pattern 33 separates the plurality of filter parts to prevent cross-color between sub-pixels of different colors.

[0153] like Figure 2 and Figure 3 As shown, the dimming panel 4 includes a third substrate 40 located on a side of the second substrate 31 away from the first substrate 30 and arranged opposite to the second substrate 31. The dimming panel 4 and the display panel 3 share the second substrate 31. The dimming panel 4 can be formed by assembling the third substrate 40 and the display panel 3.

[0154] It should be noted that “the dimming panel 4 and the display panel 3 share the second substrate 31 ” means that the second substrate 31 serves as both a substrate of the display panel 3 and a substrate of the dimming panel 4 .

[0155] like Figure 3 As shown, the dimming panel 4 further includes a second liquid crystal layer 45 disposed between the second substrate 31 and the third substrate 40. By applying an electric field to the second liquid crystal layer 45, the liquid crystal molecules in different dimming areas D in the second liquid crystal layer 45 are controlled to deflect to different degrees, and the transmittance of the light in the second liquid crystal layer 45 can be modulated in different areas.

[0156] Compared with the arrangement of the color film substrate in the conventional display panel relative to the array substrate close to the display side (ie, the light emitting side) of the display panel, in the above embodiments of the present disclosure, see Figure 2 and Figure 3 By making the array substrate 3A of the display panel 3 close to the display side E (i.e., the light emitting side) of the display module 200, and the color film substrate 3B is arranged on the side of the array substrate 3A close to the dimming panel 4, the distance between the black matrix pattern 33 in the color film substrate 3B and the dimming electrode in the dimming panel 4 is reduced, and the difficulty of aligning the black matrix pattern 33 with the gap S between two adjacent dimming electrodes is reduced, which is beneficial to improve the alignment accuracy of the black matrix pattern 33 with the gap S between two adjacent dimming electrodes, so that the black matrix pattern 33 can effectively block the light leakage in the gap area between two adjacent dimming electrodes, avoid the bright phenomenon of the edge of the dimming electrode, and thus improve the picture quality of the display module 200.

[0157] Furthermore, in conventional technology, the two panels that need to be aligned are the dimming panel 4 and the display panel 3, while in the above-mentioned embodiment of the present disclosure, by making the dimming panel 4 and the display panel 3 share the second substrate 31, in the process of forming the dimming panel 4, the third substrate 40 of the dimming panel 4 and the display panel 3 are aligned, and the alignment accuracy between the substrate and the panel is higher than the alignment accuracy of the two panels, that is, the alignment accuracy between the third substrate 40 of the dimming panel 4 and the display panel 3 is higher, which is beneficial for the black matrix pattern 33 to more effectively block the light leakage in the gap area between two adjacent dimming electrodes.

[0158] In addition, since the dimming panel 4 and the display panel 3 share the second substrate 31 , the display module 200 reduces one substrate, thereby reducing the thickness of the display module 200 , which is beneficial to making the display module 200 lighter and thinner.

[0159] In some embodiments, when the alignment accuracy between the dimming panel 4 and the display panel 3 is improved and the black matrix pattern 33 can be guaranteed to block the gap S between any two adjacent dimming electrodes 43, the width of the black matrix pattern 33 can be appropriately reduced, which is beneficial to increasing the aperture ratio of the sub-pixel area P, thereby helping to improve the display brightness of the display module 200.

[0160] Exemplarily, the width of the black matrix pattern 33 may be set to a range of 5.0 μm±1.0 μm, such as 5 μm, 5.2 μm, 5.4 μm, 5.6 μm, 5.8 μm or 6.0 μm, etc.

[0161] In some embodiments, Figure 3 and Figure 7 As shown, the display panel 3 further includes first alignment films 35 respectively disposed on both sides of the first liquid crystal layer 34. That is, the first alignment films 35 are disposed on one side of the array substrate 3A facing the color filter substrate 3B and the other side of the color filter substrate 3B facing the array substrate 3A.

[0162] In some embodiments, Figure 3 and Figure 7 As shown, a plurality of dimming electrodes 43 are disposed on one of the second substrate 31 or the third substrate 40 .

[0163] For example, Figure 3 As shown, in the case where a plurality of dimming electrodes 43 are disposed on the third substrate 40 , a plurality of signal lines 41A are disposed on the third substrate 40 .

[0164] In the case where the plurality of signal lines 41A are disposed on the third substrate 40 , the plurality of signal lines 41A are located on a side of the plurality of dimming electrodes 43 close to the third substrate 40 . Figure 3Alternatively, the plurality of signal lines 41A are located on a side of the plurality of dimming electrodes 43 that is away from the third substrate 40 .

[0165] For example, Figure 7 As shown, in the case where a plurality of dimming electrodes 43 are disposed on the second substrate 31 , a plurality of signal lines 41A are disposed on the second substrate 31 .

[0166] When the plurality of signal lines 41A are disposed on the second substrate 31 , the plurality of signal lines 41A are located on a side of the plurality of dimming electrodes 43 close to the second substrate 31 . Figure 7 Alternatively, the plurality of signal lines 41A are located on a side of the plurality of dimming electrodes 43 that is away from the second substrate 31 .

[0167] In some embodiments, Figure 3 and Figure 7 As shown, the dimming panel 4 further includes a reference electrode 46 disposed on one of the second substrate 31 and the third substrate 40. The orthographic projection of the reference electrode 46 on the second substrate 31 overlaps with the orthographic projection of each dimming electrode 43 on the second substrate 31.

[0168] When the dimming panel 4 is working, the reference electrode 46 is configured to transmit a reference voltage signal, and each dimming electrode 43 transmits a control voltage signal respectively, thereby generating an electric field between each dimming electrode 43 and the reference electrode 46. The electric field can drive the liquid crystal molecules of the second liquid crystal layer 45 located in the corresponding dimming area D to deflect, thereby adjusting the transmittance of light passing through each dimming area D and emitted to the display panel 3.

[0169] For example, the reference electrode 46 may cover the entire display area of ​​the dimming panel 4. Figure 3 and Figure 7 As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are respectively disposed on different substrates. The liquid crystal modulation type of the dimming panel 4 can be a TN (Twisted Nematic) type.

[0170] For example, Figure 3 and Figure 7 As shown, the dimming electrode 43 is a block electrode, and a plurality of dimming electrodes 43 are independently arranged; the reference electrode 46 is a planar electrode covering the entire display area of ​​the dimming panel 4 .

[0171] For example, Figure 3 As shown, a plurality of dimming electrodes 43 are disposed on a side of the third substrate 40 close to the first substrate 30 , and a reference electrode 46 is disposed on a side of the second substrate 31 away from the first substrate 30 .

[0172] In the above embodiment, since the dimming electrode 43 is a block electrode, a photolithography process is required to prepare the dimming electrode 43. Therefore, the dimming electrode 43 is set on a third substrate 40 with a simple structure (the third substrate 40 has a simpler structure than the display panel 3). This can reduce the difficulty of the preparation process of the dimming electrode 43 and avoid the impact of the preparation of the dimming electrode 43 on the structure in the display panel 3.

[0173] For example, Figure 7 As shown, a plurality of dimming electrodes 43 are disposed on a side of the second substrate 31 away from the first substrate 30, and a reference electrode 46 is disposed on a side of the third substrate 40 close to the first substrate 30. The black matrix pattern 33 and the dimming electrode 43 are both disposed on the second substrate 31 and are respectively located on both sides of the second substrate 31, which can further reduce the distance between the black matrix pattern 33 and the dimming electrode 43, thereby further reducing the difficulty of aligning the gap S between the black matrix pattern 33 and two adjacent dimming electrodes.

[0174] Furthermore, if the black matrix pattern 33 and the dimming electrode 43 are respectively made on two substrates, the substrates on which the two are located need to be aligned later, and the problem of alignment deviation will inevitably exist. In the above embodiment, the black matrix pattern 33 and the dimming electrode 43 are both arranged on the second substrate 31, and are respectively located on both sides of the second substrate 31. When the black matrix pattern 33 and the dimming electrode 43 are aligned, it is only necessary to set an alignment mark on the corresponding film layer to achieve accurate alignment of the two, thereby eliminating the alignment deviation caused by the alignment of the two substrates, so that the black matrix pattern 33 can more effectively block the gap S between the two adjacent dimming electrodes 43.

[0175] In other embodiments, Figure 8 and Fig. 9 As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are disposed on the same substrate. The liquid crystal modulation type of the dimming panel 4 can adopt the Advanced Super Dimension Switch (ADS) type.

[0176] The reference electrode 46 is relative to the plurality of dimming electrodes 43 and is far away from the substrate where the reference electrode 46 and the plurality of dimming electrodes 43 are located. The dimming electrodes 43 are block electrodes, and the plurality of dimming electrodes 43 are independently arranged; the reference electrode 46 is a planar electrode covering the entire display area of ​​the dimming panel 4, and a portion of the reference electrode 46 directly facing each dimming electrode 43 has a plurality of slits 461.

[0177] For example, Figure 8As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are both disposed on a side of the third substrate 40 close to the first substrate 30. Disposing the reference electrode 46 and the plurality of dimming electrodes 43 on the third substrate 40 with a simple structure can reduce the difficulty of the preparation process of the reference electrode 46 and the dimming electrode 43, and avoid the influence of the preparation of the reference electrode 46 and the dimming electrode 43 on the structure of the display panel 3.

[0178] For example, Fig. 9 As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are disposed on the side of the second substrate 31 away from the first substrate 30. The reference electrode 46 and the plurality of dimming electrodes 43 are disposed on the second substrate 31, which can reduce the difficulty of aligning the black matrix pattern 33 and the gap S between two adjacent dimming electrodes.

[0179] In other embodiments, Fig.10 and Fig.11 As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are disposed on the same substrate, and the reference electrode 46 is relative to the plurality of dimming electrodes 43 and close to the substrate where the reference electrode 46 and the plurality of dimming electrodes 43 are located.

[0180] Exemplarily, the reference electrode 46 is a planar electrode covering the entire display area of ​​the dimming panel 4 ; the dimming electrode 43 is a block electrode, a plurality of dimming electrodes 43 are independently arranged, and each dimming electrode 43 has a plurality of slits 431 .

[0181] A plurality of third via holes H3 are formed on the reference electrode 46 , so that the plurality of dimming electrodes 43 can pass through the third via holes H3 to be electrically connected to the signal line 41A on the substrate, so as to transmit the control voltage signal to the plurality of dimming electrodes 43 .

[0182] For example, Fig.10 As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are both disposed on a side of the third substrate 40 close to the first substrate 30 .

[0183] For example, Fig.11 As shown, the reference electrode 46 and the plurality of dimming electrodes 43 are both disposed on a side of the second substrate 31 away from the first substrate 30 .

[0184] In some embodiments, Figure 8 to Figure 11 As shown, when the reference electrode 46 and the plurality of dimming electrodes 43 are disposed on the same substrate, the dimming panel 4 further includes a second passivation layer 42B disposed between the plurality of dimming electrodes 43 and the reference electrode 46 to insulate the plurality of dimming electrodes 43 from the reference electrode 46 .

[0185] For example, Figure 8 and Fig. 9As shown, when the reference electrode 46 is relative to the multiple dimming electrodes 43 and far away from the reference electrode 46 and the substrate where the multiple dimming electrodes 43 are located, the second passivation layer 42B covers the multiple dimming electrodes 43, separates the multiple dimming electrodes 43 from the reference electrode 46, and realizes insulation between the dimming electrode 43 and the reference electrode 46.

[0186] For example, Fig.10 and Fig.11 As shown, when the reference electrode 46 is relative to the plurality of dimming electrodes 43, close to the substrate where the reference electrode 46 and the plurality of dimming electrodes 43 are located, and the reference electrode 46 is located between the film layer where the plurality of signal lines 41A are located and the plurality of dimming electrodes 43, part of the second passivation layer 42B is sunken into the third via hole H3 in the reference electrode 46 and contacts the first passivation layer 42A. A through second via hole H2 is provided in the second passivation layer 42B, and the second via hole H2 is connected to the first via hole H1 to expose at least a portion of the signal line 41A. Each dimming electrode 43 is electrically connected to a signal line 41A through the second via hole H2 and the first via hole H1.

[0187] The second passivation layer 42B is partially sunken into the third via hole H3 in the reference electrode 46 , separating each dimming electrode 43 from the inner wall of the third via hole H3 of the reference electrode 46 , thereby achieving insulation between the dimming electrode 43 and the reference electrode 46 .

[0188] In some embodiments, Figure 3 and Figure 7 As shown, the dimming panel 4 further includes second alignment films 44 disposed on both sides of the second liquid crystal layer 45. That is, the second alignment films 44 are disposed on one side of the color filter substrate 3B facing the third substrate 40 and the other side of the third substrate 40 facing the color filter substrate 3B.

[0189] In some embodiments, Figure 3 and Figure 7 As shown, the display module 200 also includes a first polarizer 50 arranged on the side of the first substrate 30 away from the second substrate 31, a metal wire grid polarizer layer (Wire Grid Polarizer, abbreviated as WGP) 6 arranged on the side of the second substrate 31 away from the first substrate 30, and a second polarizer 51 arranged on the side of the third substrate 40 away from the first substrate 30.

[0190] The directions of the absorption axes of the first polarizer 50 and the second polarizer 51 are respectively perpendicular to the direction of the absorption axis of the metal wire grid polarization layer 6 .

[0191] In the case where the display module 200 is a display module in a normally white mode, when the dimming panel 4 is turned off, the light from the backlight module whose polarization direction is perpendicular to the absorption axis of the second polarizer 51 enters the dimming panel 4 of the display module 200 through the second polarizer 51. Then, the polarization direction of the polarized light is deflected 90° by the second liquid crystal layer 45 and is perpendicular to the absorption axis of the metal wire grid polarization layer 6, so that the polarized light can all pass through the metal wire grid polarization layer 6 and enter the display panel 3. Then, the polarization direction of the polarized light is deflected 90° by the first liquid crystal layer 34 and is perpendicular to the absorption axis of the first polarizer 50, and finally the polarized light can all pass through the first polarizer 50, so that the display module 200 is in a normally white mode.

[0192] It should be noted that the directional relationship between the absorption axes of the first polarizer 50, the second polarizer 51 and the metal wire grid polarization layer 6 is not limited to the above-mentioned relationship. The directional relationship between the absorption axes of the three can be set accordingly according to factors such as the liquid crystal modulation modes of the display panel 3 and the dimming panel 4 and the normally white or normally black mode of the display module 200.

[0193] Exemplarily, the metal wire grid polarization layer 6 includes a plurality of parallel metal wires, and the material of the metal wires may include aluminum, silver, molybdenum, etc.

[0194] In the above-mentioned embodiments of the present disclosure, a photolithography process can be used to set the metal wire grid polarization layer 6 on the surface of the second substrate 31 away from the first substrate 30, instead of the polarizer pasted on the second substrate 31, so that in the subsequent steps, a film layer can be further prepared on the second substrate 31, such as a dimming electrode 43 or a reference electrode 46, so that the purpose of the dimming panel 4 and the display panel 3 sharing the second substrate 31 can be achieved; and, corresponding to the use of the polarizer, the use of the metal wire grid polarization layer 6 is beneficial to reducing the thickness of the display module 200.

[0195] In some embodiments, Figure 3 As shown, when the reference electrode 46 is disposed on the second substrate 31 and the plurality of dimming electrodes 43 are disposed on the third substrate 40 , the metal wire grid polarization layer 6 is located between the second substrate 31 and the reference electrode 46 .

[0196] On this basis, the display module 200 also includes an insulating layer 7 arranged between the metal wire grid polarization layer 6 and the reference electrode 46 , and the metal wire grid polarization layer 6 is separated from the reference electrode 46 by the insulating layer 7 to achieve insulation between the metal wire grid polarization layer 6 and the multiple dimming electrodes 43 .

[0197] Exemplarily, the material of the insulating layer 7 includes silicon nitride.

[0198] In other embodiments, Figure 7As shown, when a plurality of dimming electrodes 43 are disposed on the second substrate 31 and a reference electrode 46 is disposed on the third substrate 40 , the metal wire grid polarization layer 6 is located between the second substrate 31 and the plurality of dimming electrodes 43 .

[0199] On this basis, the display module 200 also includes an insulating layer 7 arranged between the metal wire grid polarization layer 6 and the multiple signal lines 41A, and the metal wire grid polarization layer 6 is separated from the multiple signal lines 41A by the insulating layer 7 to achieve insulation between the metal wire grid polarization layer 6 and the multiple signal lines 41A.

[0200] In the above embodiment, the material of the insulating layer 7 may include silicon nitride.

[0201] In other embodiments, Figure 8 and Fig.10 As shown, when the plurality of dimming electrodes 43 and the reference electrode 46 are disposed on the third substrate 40 , the metal wire grid polarizing layer 6 is located between the second substrate 31 and the second alignment film 44 .

[0202] In other embodiments, Fig. 9 As shown, when multiple dimming electrodes 43 and reference electrodes 46 are both arranged on the second substrate 31 and the multiple dimming electrodes 43 are close to the second substrate 31 relative to the reference electrode 46 , the metal wire grid polarization layer 6 is located between the second substrate 31 and the multiple dimming electrodes 43 .

[0203] In other embodiments, Fig.11 As shown, when multiple dimming electrodes 43 and reference electrode 46 are both arranged on the second substrate 31 and the reference electrode 46 is close to the second substrate 31 relative to the multiple dimming electrodes 43, the metal wire grid polarization layer 6 is located between the second substrate 31 and the reference electrode 46.

[0204] On this basis, if Fig. 9 and Fig.11 As shown, the display module 200 also includes an insulating layer 7 disposed between the metal wire grid polarization layer 6 and the plurality of signal lines 41A. The insulating layer 7 separates the metal wire grid polarization layer 6 from the plurality of signal lines 41A, thereby achieving insulation between the metal wire grid polarization layer 6 and the plurality of signal lines 41A.

[0205] In some embodiments, the first substrate 30 and the second substrate 31 of the display panel 3, and the third substrate 40 of the dimming panel 4 are flexible and stretchable substrates, which is conducive to the display module 200 adopting the COP (full name: ChipOn Pi) packaging process, thereby realizing the narrow frame of the display module 200 and improving the screen-to-body ratio of the display module 200.

[0206] For example, the material of the first substrate 30 , the second substrate 31 , and the third substrate 40 may include colorless polyimide (CPI for short).

[0207] Some embodiments of the present disclosure also provide a display device, such as Fig.12 As shown, the display device 400 includes the display module 200 in the above embodiment, and a backlight module 300 disposed on a side of the dimming panel 4 away from the display panel 3. The backlight module 300 is used to provide the display module 200 with light required for displaying images.

[0208] In the display device 400 provided in the embodiment of the present disclosure, the dimming panel 4 adopts a passive driving method, so that there is no need to set a driving circuit in the dimming panel 4, thereby avoiding the blocking of light by the driving circuit and causing a reduction in its transmittance, thereby improving the light transmittance of the dimming panel 2 and improving the picture quality of the display device 400.

[0209] The display panel 3 in the display device 400 described above can be a high transmittance advanced super dimensional field switching (High Transmission rate Advanced Super Dimension Switch, abbreviated as HADS) type liquid crystal display device, and can also be an advanced super dimensional field switching type, IPS (In-Plane Switching) type, FFS (Fringe Field Switching) type, TN type, MVA (Multi-domain Vertical Alignment) type, or PVA (Patterned Vertical Alignment) type liquid crystal display device.

[0210] The display device 400 described above may be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether textual or . More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0211] Some embodiments of the present disclosure also provide a method for preparing a display module 200, such as Fig.13A As shown, it includes the following S10 to S50:

[0212] S10 : forming a plurality of pixel driving circuits T′ on the first substrate 30 .

[0213] For example, Fig.14A As shown, a driving circuit layer T is formed on a first substrate 30, and the driving circuit layer T includes a plurality of pixel driving circuits T', thereby obtaining an array substrate 3A. One pixel driving circuit T' is located in one sub-pixel region P, and is used to control the gray scale of the sub-pixel.

[0214] S20 : ​​forming a color filter layer 32 and a black matrix pattern 33 on the second substrate 31 .

[0215] For example, Fig. 14B As shown, a color filter layer 32 and a black matrix pattern 33 are formed on the second substrate 31 to obtain a color filter substrate 3B. The color filter layer 32 includes a red light blocking unit, a green light blocking unit and a blue light blocking unit. The black matrix pattern 33 separates the red light blocking unit, the green light blocking unit and the blue light blocking unit to prevent cross-color between sub-pixels of different colors.

[0216] For example, a black matrix pattern 33 having a plurality of via holes may be formed first; and then the color filter layer 32 may be formed in the via holes of the black matrix pattern 33 .

[0217] S30: Fig. 14C As shown, a first substrate 30 formed with a driving circuit layer T is assembled with a second substrate 31 formed with a color filter layer 32 and a black matrix pattern 33 to form a display panel 3.

[0218] The display panel 3 has a plurality of sub-pixel regions P, and the display panel 3 is configured to display images.

[0219] In the above steps, liquid crystal molecules are injected into the liquid crystal cell formed by the first substrate 30 and the second substrate 31 during the cell assembly process to form the first liquid crystal layer 34 of the display panel 3 .

[0220] In some embodiments, Fig. 13B As shown, after S30 and before S40, the method for preparing the display module 200 further includes the following S31 to S33:

[0221] S31: Fig.14D As shown, before S33 , a metal wire grid polarization layer 6 is formed on a side of the second substrate 31 away from the first substrate 30 by using a patterning process.

[0222] Exemplarily, a thin film deposition process is used to form a metal wire grid polarization film on a side of the second substrate 31 away from the first substrate 30; and a photolithography process is used to pattern the metal wire grid polarization film to form a metal wire grid polarization layer 6. For example, the thin film deposition process may include chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) or magnetron sputtering.

[0223] S32: Fig.14E As shown, after S31 , a thin film deposition process is used to form an insulating layer 7 on a side of the metal wire grid polarization layer 6 away from the first substrate 30 .

[0224] The metal wire grid polarization layer 6 is separated from the reference electrode 46 to be formed subsequently by the insulating layer 7 , so as to achieve insulation between the metal wire grid polarization layer 6 and the reference electrode 46 .

[0225] S33: Fig.14F As shown, a reference electrode 46 is formed on a side of the second substrate 31 away from the first substrate 30 .

[0226] Exemplarily, a magnetron sputtering process is used to form the reference electrode 46 on a side of the insulating layer 7 away from the first substrate 30 .

[0227] S40 : forming a plurality of dimming electrodes 43 and a plurality of signal lines 41A on the third substrate 40 .

[0228] Exemplarily, S40 may include the following S41 to S43:

[0229] S41: Figure 14G As shown, a plurality of signal lines 41A are formed on one side of the third substrate 40 .

[0230] Exemplarily, a signal line metal layer is formed on one side of the third substrate 40 by using chemical vapor deposition; and a photolithography process is used to pattern the signal line metal layer to form a plurality of signal lines 41A.

[0231] S42: Fig.14H As shown, a first passivation layer 42A is formed on a side of the plurality of signal lines 41A away from the third substrate 40 .

[0232] Illustratively, a first passivation layer 42A covering the multiple signal lines 41A is formed on a side of the multiple signal lines 41A away from the third substrate 40 by chemical vapor deposition; a plurality of first vias H1 are formed on the first passivation layer 42A by dry etching, and each first via H1 exposes at least a portion of a signal line 41A.

[0233] S43: Fig.14I As shown, a plurality of dimming electrodes 43 are formed on a side of the first passivation layer 42A away from the third substrate 40 .

[0234] Each dimming electrode 43 is electrically connected to a corresponding signal line 41A through a first via hole H1. One dimming electrode 43 is located in one dimming area D, and there is a gap S between any two adjacent dimming electrodes 43.

[0235] Exemplarily, a magnetron sputtering process is used to form an electrode film on a side of the first passivation layer 42A close to the first substrate 30 ; a wet etching process is used to pattern the electrode film to form a plurality of dimming electrodes 43 .

[0236] S50: Fig.14J As shown, the third substrate 40 is assembled with the display panel 3 to form a dimming panel 4 .

[0237] Among them, the third substrate 40 is located on the side of the second substrate 31 away from the first substrate 30, and the dimming panel 4 and the display panel 3 share the second substrate 31. The dimming panel 4 has multiple dimming areas D, and along the direction perpendicular to the display panel, one dimming area D covers at least one pixel area P'. A dimming electrode 43 is located in a dimming area D, and there is a gap S between any two adjacent dimming electrodes 43. Each dimming electrode 43 is directly electrically connected to at least one signal line 41A, and the signal line 41A is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area D where the dimming electrode 43 is located to the dimming electrode 43 electrically connected thereto. The dimming panel 4 is configured to separately adjust the transmittance of light passing through each dimming area D and projected toward the display panel 3.

[0238] During the process of assembling the third substrate 40 and the display panel 3 , the orthographic projection of the black matrix pattern 33 on the second substrate 31 covers the orthographic projection of the gap S between any two adjacent dimming electrodes 43 on the second substrate 31 .

[0239] Exemplarily, the PI Coat process is first used to coat the second alignment film 44 on the third substrate 40 and the display panel 3; then the One Drop Filling (ODF) process is used to align the third substrate 40 and the display panel 3 to form the dimming panel 4.

[0240] In some embodiments, after S50, the method for preparing the display module 200 further includes:

[0241] S51: Figure 14K As shown, a first polarizing plate 50 is attached to the first substrate 30 ; and a second polarizing plate 51 is attached to the third substrate 40 .

[0242] In the preparation method in the above-mentioned embodiment of the present disclosure, the array substrate 3A of the display panel 3 is located on the display side (i.e., the light emitting side) of the display module 200, and the color film substrate 3B is arranged on the side of the array substrate 3A close to the dimming panel 4, thereby reducing the distance between the black matrix pattern 33 in the color film substrate 3B and the dimming electrode 43 in the dimming panel 4, and reducing the difficulty of aligning the black matrix pattern 33 with the gap between two adjacent dimming electrodes, which is beneficial to improving the alignment accuracy of the black matrix pattern 33 with the gap between two adjacent dimming electrodes, so that the black matrix pattern 33 can effectively block the light leakage in the gap area between two adjacent dimming electrodes, and avoid the phenomenon of brightening at the edge of the dimming electrode, thereby ensuring the picture quality of the display module 200.

[0243] Furthermore, compared to aligning the dimming panel 4 and the display panel 3, in the disclosed embodiment, the dimming panel 4 and the display panel 3 share the second substrate 31, and the alignment of the third substrate 40 of the dimming panel 4 and the display panel 3 is the alignment of the substrate and the panel, which can improve the alignment accuracy, thereby improving the alignment accuracy of the gap S area between the black matrix pattern 33 and the two adjacent dimming electrodes 43.

[0244] Some embodiments of the present disclosure also provide another method for preparing the display module 200, such as Fig.15A As shown, it includes the following S60 to S100:

[0245] S60: Fig.16A As shown, similar to the above S10 , a plurality of pixel driving circuits T′ are formed on the first substrate 30 .

[0246] S70: Fig. 16B As shown, similar to the above S20 , a color filter layer 32 and a black matrix pattern 33 are formed on the second substrate 31 .

[0247] S80: Fig. 16C As shown, similar to the above S30 , the first substrate 30 formed with the driving circuit layer T is assembled with the second substrate 31 formed with the color filter layer 32 and the black matrix pattern 33 to form the display panel 3 .

[0248] In some embodiments, Fig. 15B As shown, after S80 and before S90, the method for preparing the display module 200 further includes the following S81-S82:

[0249] S81: Fig.16D As shown, similar to the above S31 , a metal wire grid polarization layer 6 is formed on a side of the second substrate 31 away from the first substrate 30 by adopting a patterning process.

[0250] S82: Fig.16E As shown, similar to the above S31 , a thin film deposition process is used to form an insulating layer 7 on a side of the metal wire grid polarization layer 6 away from the first substrate 30 .

[0251] S90 : forming a plurality of dimming electrodes 43 and a plurality of signal lines 41A on a side of the second substrate 31 away from the first substrate 30 .

[0252] Exemplarily, S90 may include the following S91 to S94:

[0253] S91: Fig.16F As shown, a plurality of signal lines 41A are formed on a side of the second substrate 31 away from the first substrate 30 .

[0254] Exemplarily, a signal line metal layer is formed on a side of the insulating layer 7 away from the first substrate 30 by chemical vapor deposition; and a photolithography process is used to pattern the signal line metal layer to form a plurality of signal lines 41A.

[0255] S92: Figure 16G As shown, a first passivation layer 42A is formed on a side of the plurality of signal lines 41A away from the first substrate 30 .

[0256] Illustratively, a first passivation layer 42A covering multiple signal lines 41A is formed on a side of the second substrate 31 away from the first substrate 30 by chemical vapor deposition; a plurality of first vias H1 are formed on the first passivation layer 42A by dry etching, and each first via H1 exposes at least a portion of a signal line 41A.

[0257] S93: Fig.16H As shown, a plurality of dimming electrodes 43 are formed on a side of the first passivation layer 42A away from the first substrate 30 .

[0258] Each dimming electrode 43 is electrically connected to a corresponding signal line 41A through a first via hole H1. One dimming electrode 43 is located in one dimming area D, and there is a gap S between any two adjacent dimming electrodes 43.

[0259] When forming a plurality of dimming electrodes 43 on a side of the second substrate 31 away from the first substrate 30 , the orthographic projection of the black matrix pattern 33 on the second substrate 31 covers the orthographic projection of the gap S between any two adjacent dimming electrodes 43 on the second substrate 31 .

[0260] Exemplarily, a magnetron sputtering process is used to form an electrode film on a side of the first passivation layer 42A away from the first substrate 30 ; a wet etching process is used to pattern the electrode film to form a plurality of dimming electrodes 43 .

[0261] In the preparation method in the above-mentioned embodiment of the present disclosure, both the black matrix pattern 33 and the dimming electrode 43 are manufactured on the second substrate 31, which further reduces the distance between the black matrix pattern 33 and the dimming electrode 43, and reduces the difficulty of aligning the black matrix pattern 33 with the gap between two adjacent dimming electrodes. It can avoid the problem of respectively manufacturing the black matrix pattern 33 and the dimming electrode 43 on two substrates, and subsequently needing to align the substrates where the two are located, resulting in the alignment deviation problem of the gap S between the black matrix pattern 33 and the two adjacent dimming electrodes 43.

[0262] S94: Fig.16I As shown, a reference electrode 46 is formed on one side of the third substrate 40 by using a magnetron sputtering process.

[0263] S100: Fig.16J As shown, similar to the above S50 , the third substrate 40 and the display panel 3 are assembled to form a dimming panel 4 .

[0264] In some embodiments, after S100, the method for preparing the display module 200 further includes:

[0265] S110: Figure 16K As shown, similar to the above S41 , a first polarizing plate 50 is attached to the first substrate 30 ; and a second polarizing plate 51 is attached to the third substrate 40 .

[0266] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display module, characterized in that: include: A display panel, the display panel having a plurality of pixel regions; the display panel having a display area and a peripheral area located at least on one side of the display area; the display area including a plurality of sub-pixel regions; the display area is further provided with a plurality of gate scanning lines extending along a row direction in which the plurality of sub-pixel regions are arranged, and a plurality of data lines extending along a column direction in which the plurality of sub-pixel regions are arranged; a sub-pixel is arranged in each sub-pixel region; at least two sub-pixels constitute one pixel, and the sub-pixel regions in which the at least two pixels included in one pixel are located constitute one pixel region; A dimming panel superimposed on the display panel, the dimming panel having a plurality of dimming areas, and one dimming area covers at least one pixel area along a direction perpendicular to the display panel; Wherein, the dimming panel includes: A plurality of dimming electrodes, one dimming electrode is located in one dimming area, and there is a gap between any two adjacent dimming electrodes; the plurality of dimming electrodes are arranged in an array; the row direction of the plurality of dimming electrodes is a first direction, and the column direction of the plurality of dimming electrodes is a second direction; A plurality of signal lines, each of the dimming electrodes is directly electrically connected to at least one signal line; the signal line is configured to transmit a control voltage signal for controlling the light transmittance of a dimming area where the dimming electrode is located to the dimming electrode electrically connected thereto; each of the signal lines extends along the second direction as a whole, and the plurality of signal lines are arranged in parallel along the first direction; the orthographic projection of each of the signal lines on the display panel at least partially overlaps with the orthographic projection of a column of dimming electrodes where the dimming electrode electrically connected thereto is located on the display panel; the signal line comprises a plurality of bending portions connected in sequence, and the signal line is in the shape of a zigzag line; each two adjacent bending portions form a bending unit; along a direction perpendicular to the display panel, one of the dimming electrodes covers a plurality of bending units of the signal line; the edge contour of the dimming electrode extending along the second direction is in the shape of a zigzag line having the same shape as that of the signal line, and the edge contour is parallel to the signal line; along the first direction, the shapes of the edge contours of two adjacent dimming electrodes close to each other are complementary; A first shading pattern; an orthographic projection of the first shading pattern on the display panel is located between the orthographic projections of two adjacent columns of the dimming electrodes on the display panel; the first shading pattern as a whole extends along the second direction; the first shading pattern is made of the same material as the signal line and is arranged in the same layer; the first shading pattern is in the shape of a broken line that is the same as the shape of an edge contour of the dimming electrode extending along the second direction, and the first shading pattern and the edge contour are parallel to each other.

2. The display module according to claim 1, characterized in that: Along the first direction, one of the bending units passes through 1 to 6 pixel areas; Along the second direction, one bending unit passes through 1 to 6 pixel areas.

3. The display module according to any one of claims 1 to 2, characterized in that: The dimming panel also includes: a second shading pattern; the orthographic projection of the second shading pattern on the display panel is located between the orthographic projections of two adjacent rows of dimming electrodes on the display panel; The second light shielding pattern extends in its entirety along the first direction, and is disconnected at a position where the second light shielding pattern intersects with the signal line; the second light shielding pattern is made of the same material as the signal line and is disposed in the same layer.

4. The display module according to claim 1, characterized in that: The dimming panel also includes: A driving chip disposed on one side of the dimming panel, the driving chip being directly electrically connected to the plurality of signal lines; The driving chip is configured to provide the control voltage signals to the plurality of signal lines respectively, so as to control the light transmittance of the dimming area where the dimming electrodes electrically connected to the signal lines are located.

5. The display module according to claim 1, characterized in that: The dimming panel also includes: A first passivation layer is disposed between the plurality of dimming electrodes and the plurality of signal lines, wherein the first passivation layer has a plurality of first via holes, and each of the dimming electrodes is electrically connected to a corresponding signal line through at least one first via hole.

6. The display module according to claim 5, characterized in that: When the signal line includes a plurality of bends connected in sequence and the signal line is in a zigzag shape, The orthographic projection of the first via hole on the display panel is located at the intersection of the orthographic projections of two adjacent bending portions on the display panel.

7. The display module according to claim 1, characterized in that: The signal line has a line width ranging from 2.2 μm to 3.0 μm.

8. The display module according to claim 1, characterized in that: The display panel comprises: A first substrate and a second substrate arranged opposite to each other; A plurality of pixel driving circuits are disposed on a side of the first substrate facing the second substrate; and A color filter layer and a black matrix pattern are disposed on a side of the second substrate facing the first substrate; The dimming panel also includes: a third substrate located on a side of the second substrate away from the first substrate and arranged opposite to the second substrate; the plurality of dimming electrodes and the plurality of signal lines are arranged on a side of the third substrate facing the second substrate, or on a side of the second substrate facing the third substrate; The dimming panel and the display panel share the second substrate; and the orthographic projection of the black matrix pattern on the second substrate covers the orthographic projection of the gap between any two adjacent dimming electrodes on the second substrate.

9. The display module according to claim 8, characterized in that: The dimming panel also includes: A reference electrode disposed on one of the second substrate and the third substrate; the orthographic projection of the reference electrode on the second substrate overlaps with the orthographic projection of each of the dimming electrodes on the second substrate; The reference electrode is configured to transmit a reference voltage signal and generate an electric field between the reference electrode and each of the dimming electrodes.

10. The display module according to claim 9, characterized in that: The reference electrode and the plurality of dimming electrodes are respectively disposed on different substrates; or, The reference electrode and the plurality of dimming electrodes are disposed on the same substrate; the reference electrode is relatively far from the substrate where the reference electrode and the plurality of dimming electrodes are located, and a portion of the reference electrode directly facing each of the dimming electrodes has a plurality of slits; or, The reference electrode and the plurality of dimming electrodes are arranged on the same substrate; the reference electrode is relative to the plurality of dimming electrodes and is close to the substrate where the reference electrode and the plurality of dimming electrodes are located, and each of the dimming electrodes has a plurality of slits.

11. The display module according to claim 9, characterized in that: The width of the gaps between the plurality of dimming electrodes ranges from 3.0 μm to 3.5 μm.

12. The display module according to claim 11, characterized in that: The width of the black matrix pattern ranges from 4 μm to 6 μm.

13. The display module according to any one of claims 9 to 12, characterized in that: Also includes: A first polarizer disposed on a side of the first substrate away from the second substrate; A metal wire grid polarization layer disposed on a side of the second substrate away from the first substrate; A second polarizer disposed on a side of the third substrate away from the first substrate; Wherein, the directions of the absorption axes of the first polarizer and the second polarizer are respectively perpendicular to the directions of the absorption axes of the metal wire grid polarization layer.

14. The display module according to claim 13, characterized in that: In the case where the plurality of dimming electrodes are disposed on the second substrate and the reference electrode is disposed on the third substrate, the metal wire grid polarization layer is located between the second substrate and the plurality of dimming electrodes; In the case where the reference electrode is disposed on the second substrate and the plurality of dimming electrodes are disposed on the third substrate, the metal wire grid polarization layer is located between the second substrate and the reference electrode; In the case where the plurality of dimming electrodes and the reference electrode are both disposed on the second substrate, and the plurality of dimming electrodes are closer to the second substrate than the reference electrode, the metal wire grid polarization layer is located between the second substrate and the plurality of dimming electrodes; When the plurality of dimming electrodes and the reference electrode are both disposed on the second substrate, and the reference electrode is closer to the second substrate than the plurality of dimming electrodes, the metal wire grid polarization layer is located between the second substrate and the reference electrode.

15. A display device, characterized in that: include: The display module according to any one of claims 1 to 14; A backlight module disposed on a side of the dimming panel away from the display panel; The backlight module is configured to provide light for the display module.

16. A method for preparing a display module according to claim 1, characterized in that: include: forming a plurality of pixel driving circuits on the first substrate; forming a color filter layer and a black matrix pattern on the second substrate; Aligning a first substrate having the plurality of pixel driving circuits with a second substrate having the color filter layer and the black matrix pattern to form a display panel; wherein the display panel has a plurality of pixel regions; forming a plurality of dimming electrodes and a plurality of signal lines on a third substrate or on a side of the second substrate away from the first substrate; The third substrate is assembled with the display panel to form a dimming panel; the third substrate is located on a side of the second substrate away from the first substrate; the dimming panel and the display panel share the second substrate; wherein the dimming panel has a plurality of dimming areas, and a dimming area covers at least one pixel area along a direction perpendicular to the display panel; a dimming electrode is located in one of the dimming areas, and there is a gap between any two adjacent dimming electrodes; each of the dimming electrodes is directly electrically connected to at least one signal line, and the signal line is configured to transmit a control voltage signal for controlling the light transmittance of the dimming area where the dimming electrode is located to the dimming electrode electrically connected thereto.

17. The preparation method according to claim 16, characterized in that: In the case where the plurality of dimming electrodes and the plurality of signal lines are formed on the third substrate, the preparation method further includes: Before assembling the third substrate with the display panel, forming a reference electrode on a side of the second substrate away from the first substrate; During the process of assembling the third substrate and the display panel, the orthographic projection of the black matrix pattern on the second substrate covers the orthographic projection of the gap between any two adjacent dimming electrodes on the second substrate.

18. The preparation method according to claim 16, characterized in that: In the case where the plurality of dimming electrodes and the plurality of signal lines are formed on a side of the second substrate away from the first substrate, the preparation method further includes: Before aligning the third substrate with the display panel, forming a reference electrode on a side of the third substrate close to the first substrate; In the process of forming a plurality of dimming electrodes on a side of the second substrate away from the first substrate, the orthographic projection of the black matrix pattern on the second substrate covers the orthographic projection of the gap between any two adjacent dimming electrodes on the second substrate.

19. The preparation method according to any one of claims 16 to 18, characterized in that: Also includes: Before assembling the third substrate and the display panel, Using a patterning process, forming a metal wire grid polarization layer on a side of the second substrate away from the first substrate; An insulating layer is formed on a side of the metal wire grid polarization layer away from the first substrate.

Images