Storage device

Abstract

The present disclosure relates to a storage device. The present disclosure provides a storage device comprising a first isolation unit extending along a first direction, a first storage array of a first storage segment, and a second storage array of a second storage segment. The first storage array of the first storage segment adjoins a first boundary of the first isolation unit along a second direction different from the first direction. The second storage array of the second storage segment adjoins a second boundary of the first isolation unit along a second direction different from the first boundary. The storage device further comprises a first decoder unit of the first storage segment and a second decoder unit of the second storage segment, which are arranged on opposite sides of the first isolation unit.

Description

Technical Field

[0001] The present disclosure relates to a storage device, and more particularly to a storage device including a densely configured storage array. Background Art

[0002] In the semiconductor industry, wordline segment designs for read / write memory have been widely adopted in products requiring low operating voltage (VCCmin) and low power consumption. In some advanced process nodes, the layout of multiple wordline segments (floor plan) consumes significant area due to the required white space between the memory array and logic circuits. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a storage device is provided, comprising a first isolation unit extending along a first direction, a first storage array of a first storage segment, and a second storage array of a second storage segment. The first storage array of the first storage segment is adjacent to a first boundary of the first isolation unit along a second direction different from the first direction. The second storage array of the second storage segment is adjacent to a second boundary of the first isolation unit along a second direction different from the first boundary. The storage device further comprises a first decoder unit of the first storage segment and a second decoder unit of the second storage segment, which are arranged on opposite sides of the first isolation unit.

[0004] According to an embodiment of the present disclosure, a storage device is provided, comprising a first storage memory. The first storage memory comprises a plurality of first edge cells, a plurality of first storage cells, a plurality of second edge cells and a plurality of second storage cells, a plurality of third edge cells and a plurality of first word lines and a plurality of second word lines. The first edge cells are arranged in at least a first edge row of a plurality of storage rows. The first storage cells are arranged in a first group of storage rows, wherein the edge rows in the first group of storage rows are directly adjacent to at least the first edge row of storage rows. The second edge cells are arranged in a second group of a plurality of storage rows, and the second storage cells are arranged in a third group of a plurality of storage rows, wherein the second edge cells are sandwiched between the first storage cells and the second storage cells. The third edge cell is arranged in at least a second edge row of storage rows, wherein the edge rows in the third group of storage rows are directly adjacent to at least the second edge row of storage rows. The first word line is coupled to the first storage cell, and the second word line is coupled to the second storage cell, wherein the first word line and the second word line terminate in the second group of storage rows.

[0005] According to an embodiment of the present disclosure, a memory device is provided, comprising a plurality of memory segments and an isolation unit. The memory segments are adjacent to a word line decoder configuration, wherein one of the memory segments is configured to be activated in response to a word line signal transmitted from the word line decoder. The isolation unit is configured to be sandwiched between two adjacent segments of the memory segment, wherein each of the two adjacent segments includes a first decoder and a memory array coupled to the first decoder via a plurality of word lines. The first decoders in the two adjacent segments are configured on opposite sides of the isolation unit, and the word line is configured between the first decoders in the two adjacent segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 FIG. 4 is a schematic diagram of a layout of a storage device according to an embodiment.

[0008] Figure 2A FIG. 4 is a circuit diagram of a storage device according to an embodiment.

[0009] Figure 2B For example, according to the embodiment Figure 2A Schematic diagram of a circuit of a storage device in FIG.

[0010] Figure 3A For example, according to the embodiment Figure 1 Layout diagram of the storage device in.

[0011] Figure 3B For example, according to the embodiment Figure 1 Layout diagram of the storage device in.

[0012] Figure 4 FIG. 4 is a schematic diagram of a layout of a storage device according to an embodiment.

[0013] Figure 5 For example, according to the embodiment Figure 4 Schematic diagram of a circuit of a storage device in FIG.

[0014] Figure 6 For example, according to the embodiment Figure 4 Layout diagram of the storage device in.

[0015] Figure 7 FIG. 4 is a schematic diagram of a layout of a storage device according to an embodiment.

[0016] Figure 8 FIG. 4 is a schematic diagram of a layout of a storage device according to an embodiment.

[0017] Figure 9 FIG. 4 is a schematic diagram of a layout of a storage device according to an embodiment.

[0018] Figure 10 FIG. 1 is a flow chart of a method for manufacturing a memory device according to an embodiment.

[0019] Figure 11 is a block diagram of a system for designing an integrated circuit layout according to an embodiment.

[0020] Figure 12 FIG. 1 is a block diagram of an integrated circuit manufacturing system and an associated integrated circuit manufacturing process according to an embodiment. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the provided objectives. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, in various examples, the embodiments of the present disclosure may be repeated with reference to numbers and / or letters. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate the relationship between the various embodiments and / or configurations discussed.

[0022] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which they are used. The use of examples in this specification (including examples of any term discussed herein) is illustrative only and in no way limits the scope and meaning of the embodiments of the present disclosure or any of the exemplified terms. Similarly, the embodiments of the present disclosure are not limited to the various embodiments given in this specification.

[0023] As used herein, the terms "comprising," "including," "having," "containing," "involving," and the like should be construed as open-ended, ie, meaning including, but not limited to, including.

[0024] Reference throughout this specification to "one embodiment," "an embodiment," or "some embodiments" means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment of the disclosed embodiments. Thus, the use of the phrase "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout this specification is not necessarily referring to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, implementations, or characteristics may be combined in any suitable manner.

[0025] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (additional) component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of components in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and likewise, the spatially relative descriptors used herein may be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] As used herein, "approximately," "about," "roughly," or "substantially" shall generally refer to any approximation of a given value or range, wherein it varies depending on the various technologies to which it pertains, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numerical quantities given herein are approximate, meaning that if the term "approximately," "about," "roughly," or "substantially" is not explicitly stated, it can be inferred or means another approximate value.

[0027] Please refer to Figure 1 . Figure 1 FIG. 1 is a schematic diagram of the layout of the storage device 10 according to an embodiment. Figure 1 As shown, the memory device 10 includes a word line decoder 110, memory segments 210-220, and an isolation unit 310. In some embodiments, the word line decoder 110 is also considered to be configured in the word line decoder unit 110 in the floor plan. For illustration, the memory segments 210-220 are adjacent to the word line decoder unit 110 along the direction 410. The isolation unit 310 extends along the direction 420 and is configured to be sandwiched between two adjacent memory segments (memory segments 210-220). In other words, the memory segments 210-220 are mirror-configured relative to the isolation unit 310. In some embodiments, one of the memory segments 210-220 is configured to be activated in response to a word line signal transmitted from the word line decoder 110. The detailed operation of the memory device 10 will be discussed in conjunction with Figure 2A as well as Figure 2B This will be explained in the following sections.

[0028] In some embodiments, memory section 210 includes a decoder 211, a memory array 212, and an edge cell array 213. Similarly, memory section 220 includes a decoder 221, a memory array 222, and an edge cell array 223. In some embodiments, decoder 211 is also considered to be configured in decoder unit 211 in the layout diagram.

[0029] In some embodiments, the memory arrays 212, 222, the edge cell arrays 213, 223, and the isolation cell 310 include static random access memory (SRAM) cells, for example, SRAM cells composed of six transistors (6T). However, the embodiments can be easily applied to other SRAM cells having different numbers of transistors, such as 8T SRAM cells and 10T SRAM cells. In some embodiments, the memory cells in the memory arrays 212, 222, the edge cell arrays 213, 223, and the isolation cell 310 have the same structural configuration and are manufactured using the same mask. The difference is that the memory cells in the edge cell arrays 213, 223 and the isolation cell 310 are considered "dummy" and do not operate or have any function during the electrical operation of the memory device 10.

[0030] like Figure 1 As shown, memory array 212 is adjacent to boundary B1 of isolation cell 310 along direction 410, while memory array 222 is adjacent to boundary B2 of isolation cell 310, which is different from boundary B1, along direction 410. Furthermore, edge cell array 213 is adjacent to boundary B3 of memory array 212 opposite isolation cell 310, and edge cell array 223 is adjacent to boundary B4 of memory array 222 opposite isolation cell 310.

[0031] The isolation cell 310 has a width W1 in the layout diagram. The edge cell arrays 213 and 223 have a width W2. In some embodiments, the isolation cell 310 includes the same edge cells as those in the edge cell arrays 213 and 223. In some embodiments, the isolation cell 310 includes a number N of edge cell arrays, where N is a positive integer. For example, when the isolation cell 310 includes one row of edge cell arrays, the width W1 is equal to the width W2. In different embodiments, when the isolation cell 310 includes more than one row of edge cell arrays, the width W1 is greater than the width W2. Detailed layout diagrams will be provided in the following sections. Figure 3A Instructions.

[0032] In some embodiments, the storage arrays 212, 222 and the edge cell arrays 213, 223 are included in the storage bank 201, such as Figure 1 Meanwhile, in the arrangement diagram, the decoder units 211 and 221 are arranged outside the memory bank 201. In other words, the decoder units 211 and 221 are arranged on opposite sides of the isolation unit 310.

[0033] like Figure 1 As shown, the memory bank 201 is separated from the decoder units (logic circuits) 211 and 221 by blank spaces 214 and 224, respectively. In some embodiments, the blank spaces 214 and 224 have a width SP of approximately 0.2 microns.

[0034] In some approaches, edge cell arrays must be configured on both sides of the memory array in a memory device. Furthermore, blank space is required between the edge cell arrays on both sides and other adjacent logic circuits to separate them. In other words, each memory array must have at least two rows of edge cell arrays and two blank space sections between it and the surrounding logic circuits. Thus, at least four rows of edge cell arrays and four blank space sections exist between the two memory arrays and the surrounding logic circuits. As a result, a significant amount of area is lost in the memory device, which in turn increases the size and manufacturing cost of the finished product.

[0035] Compared to the aforementioned method, the configuration disclosed herein uses isolation cells to separate two adjacent memory arrays, and additional edge cell arrays are placed on both sides of the two memory arrays, facing the isolation cells. This reduces the number of edge cell arrays between the two memory arrays and the surrounding logic circuits to two rows, and the empty space is also reduced to two sections. This improves the area utilization of the memory device, thereby reducing the size and manufacturing cost of the finished product.

[0036] Figure 1 The configuration is given for illustrative purposes. Figure 1 For example, in some embodiments, the memory device 10 also includes a plurality of edge cells adjacent to the memory arrays 212 and 222 along the direction 420 .

[0037] Please refer to Figure 2A . Figure 2A FIG. 1 is a circuit diagram of a storage device 10 according to an embodiment. Figure 1 For ease of understanding, Figure 2A Similar components in the drawings are designated by the same reference numerals.

[0038] like Figure 2AAs shown, the word line decoder 110 is used to receive the address ADR and decode the word line signal GWLB in response to the address ADR. In some embodiments, the address ADR includes multiple bits and indicates that the word line coupled to a column of memory cells in the memory bank 201 needs to be activated accordingly. The word line signal GWLB is transmitted to the decoders 211 and 221. Then, the decoder 211 selects the word line according to the word line signal GWLB and the word line segment select signal WSEG. <0> Generates word line signal WL_1 to memory array 212. Similarly, decoder 221 generates word line signal WL_1 according to word line signal GWLB and word line segment select signal WSEG. <1> A word line signal WL_2 is generated to the memory array 222 .

[0039] Please refer to Figure 2B . Figure 2B For example, according to the embodiment Figure 2A Schematic diagram of the circuit of the storage device 10. Figures 1 to 2A For ease of understanding, Figure 2B Similar components in the drawings are designated by the same reference numerals.

[0040] Specifically, word line decoder 110 transmits word line signal GWLB to decoders 211 and 221 via (n+1) word lines GWLB_0-GWLB_n, ​​where n represents the number of memory cells in memory device 10 arranged in the (n+1) column. For example, word line signal GWLB includes (n+1) word line signals corresponding to the memory cells in the (n+1) column. For simplicity, these word line signals are also labeled GWLB_0-GWLB_n.

[0041] Next, in some embodiments, the memory device 10 further includes a word line select decoder 120. The word line select decoder 120 is used to receive the address ADR to decode and generate a word line segment select signal WSEG. <0> , WSEG <1> For example, when the word line select decoder 120 decodes the address ADR indicating that the memory cell to be activated is in the memory array 212, the word line segment select signal WSEG <0> The word line segment select signal WSEG has a logic 0. <1> On the contrary, when the word line select decoder 120 decodes the address ADR indicating that the memory cell to be activated is in the memory array 222, the word line segment select signal WSEG is <0> The word line segment select signal WSEG has a logic 1. <1> Has logic 0.

[0042] like Figure 2BAs shown, the decoder 211 includes logic gates 211a-211n. In some embodiments, the logic gates 211a-211n are NOR gates. The first terminal of the logic gate 211a receives the word line signal GWLB_0 and the second terminal receives the word line segment select signal WSEG. <0> , and generates a word line signal (also regarded as a word line signal transmitted on word line WL_1_0) WL_1_0 at the output terminal to the memory cell MC_1_0 in the memory array 212. Thus, when the word line signal GWLB_0 has a logic 0 and the word line segment select signal WSEG <0> When the memory cell MC_1_0 has a logic 0, the memory cell MC_1_0 is activated. For simplicity, the memory device 10 is shown as having memory cells arranged in a row. In different embodiments of the present disclosure, the memory device 10 has memory cells arranged in multiple rows and coupled to multiple data lines (bit lines / bit line bars, etc., not shown), wherein a column decoder (not shown) is also used to select the memory cells to be stored / read in the same column. The configuration relationship between the decoder 221 and the memory array 222 is similar to the relationship between the decoder 211 and the memory array 212. Therefore, repeated description is omitted here.

[0043] Figures 2A to 2B The configuration is given for illustrative purposes. Figures 2A to 2B Various implementations are within the contemplated scope of the embodiments of the present disclosure. For example, in some embodiments, the word line select decoder 120 is integrated into the main control circuit ( Figure 8 , 720) or in the word line decoder 110.

[0044] Please refer to Figure 3A . Figure 3A For example, according to the embodiment Figure 1 The layout diagram of the storage device 10 in FIG. Figure 3A In the illustrated embodiment, the memory bank 201 includes memory cells MC and edge cells EC arranged in memory rows COLUMN1 -COLUMNk and n columns.

[0045] Specifically, the edge cells EC included in the edge cell array 213 are arranged in the memory column COLUMN1 , wherein the memory column COLUMN1 is regarded as an edge column among the memory columns COLUMN1 -COLUMNk.

[0046] Next, the memory cells MC included in the memory array 212 are arranged in memory rows COLUMN2-COLUMNb, where memory rows COLUMN2-COLUMNb are considered to be a first group of memory rows among memory rows COLUMN1-COLUMNk. In other words, memory row COLUMN2, considered to be an edge row of the first group of memory rows, is adjacent to memory row COLUMN1, considered to be an edge row of memory rows COLUMN1-COLUMNk.

[0047] The edge cells EC included in the isolation unit 310 are arranged in the memory rows COLUMN(b+1)-COLUMN(m-1). The memory rows COLUMN(b+1)-COLUMN(m-1) are considered to be a second group of memory rows among the memory rows COLUMN1-COLUMNk. In other words, the memory row COLUMN(b+1), which is considered to be an edge row in the second group of memory rows, is adjacent to the memory row COLUMNb, which is considered to be another edge row in the first group of memory rows.

[0048] The memory cells MC included in the memory array 222 are arranged in the memory rows COLUMNm-COLUMN(k-1). The memory rows COLUMNm-COLUMN(k-1) are considered to be the third group of memory rows among the memory rows COLUMN1-COLUMNk. In other words, the memory row COLUMNm, which is considered to be an edge row in the third group of memory rows, is adjacent to the memory row COLUMN(m-1), which is considered to be another edge row in the second group of memory rows.

[0049] The edge cells EC included in the edge cell array 223 are arranged in a memory row COLUMNk. The memory row COLUMNk is considered to be another edge row among the memory rows COLUMN1-COLUMNk. In other words, the memory row COLUMN(k-1), which is considered to be another edge row in the third group of memory rows, is adjacent to the memory row COLUMNk, which is considered to be another edge row among the memory rows COLUMN1-COLUMNk.

[0050] As mentioned above, in Figure 3A In the embodiment, relative to the edge cell EC in the isolation unit 310, the edge cells included in the edge cell array 213 and the memory cells MC included in the memory array 212 are mirror images of the edge cells included in the edge cell array 223 and the memory cells MC included in the memory array 222.

[0051] In some embodiments, the memory array 212 corresponds to (b-1) bits, and the memory array 222 corresponds to (k-m+1) bits.

[0052] Please continue to refer to Figure 3AThe word lines WL_1_0-WL_1_n coupled to the decoder 211 and coupled to the memory cells MC in the memory array 212 extend along the direction 410 and terminate at the isolation unit 310. Similarly, the word lines WL_2_0-WL_2_n coupled to the decoder 221 and coupled to the memory cells MC in the memory array 222 extend along the direction 410 and terminate at the isolation unit 310. In other words, the word lines WL_1_0-WL_1_n and WL_2_0-WL_2_n terminate at the second group of memory rows COLUMN(b+1)-COLUMN(m-1). At the same time, as Figure 3A As shown, word lines WL_1_0 - WL_1_n and WL_2_0 - WL_2_n included in two adjacent memory segments 210 are disposed between decoders 211 - 221. For simplicity, only word lines WL_1_0, WL_1_n, WL_2_0, and WL_2_n are shown.

[0053] In some embodiments, during operation, decoder 211 is configured to transmit word line signals WL_1_0-WL_1_n on a first side of memory bank 201 to activate one of memory cells MC in memory array 212. Similarly, decoder 221 is configured to transmit word line signals WL_2_0-WL_2_n on a second side of memory bank 201 opposite to the first side to activate one of memory cells MC in memory array 222.

[0054] Please refer to Figure 3B . Figure 3B For example, according to the embodiment Figure 1 Layout diagram of the memory device in FIG. For simplicity, only word lines WL_1_0 and WL_2_0 are shown.

[0055] Figures 3A to 3B The configuration is given for illustrative purposes. Figures 3A to 3B Various implementations are within the contemplated scope of the embodiments of the present disclosure. For example, in some embodiments, the edge cells EC included in the edge cell arrays 213 and 223 are arranged in more than one memory row.

[0056] Please refer to Figure 4 . Figure 4 FIG. 4 is a schematic diagram of the layout of the storage device 40 according to an embodiment. Figures 1 to 3B For ease of understanding, Figure 4 Similar components in the drawings are designated by the same reference numerals.

[0057] and Figure 1In contrast, the storage device 40 further includes storage segments 230-240 and an isolation unit 320. In some embodiments, the storage segment 230 is configured to correspond to, for example, the storage segment 210. The storage segment 240 is configured to correspond to, for example, the storage segment 220. The isolation unit 320 is configured to correspond to, for example, the isolation unit 310. Figure 4 As shown, storage segment 230 includes a decoder (also considered to be arranged in decoder unit 231) 231, a storage array 232, an edge cell array 233, and an empty space 234 between the decoder 231 and the edge cell array 233. Similarly, storage segment 240 includes a decoder (also considered to be arranged in decoder unit 241) 241, a storage array 242, an edge cell array 243, and an empty space 244 between the decoder 241 and the edge cell array 243. In some embodiments, the storage arrays 232, 242 and the edge cell arrays 233, 243 are included in the memory bank 202.

[0058] The isolation cell 320 is sandwiched between the memory sections 230 and 240. Specifically, the isolation cell 320 is disposed between and adjacent to the memory arrays 232 and 242. In other words, the memory array 232 is adjacent to the boundary B5 of the isolation cell 320, and the memory array 242 is adjacent to the boundary B6 of the isolation cell 320.

[0059] In addition, the decoder units 231 and 241 are arranged on opposite sides of the isolation unit 320. Figure 4 As shown, decoder cell 231 is adjacent to decoder cell 221 along direction 410. In other words, in addition to the two adjacent memory segments 210-220 sandwiching isolation cell 310, the decoder cell 231 included in memory segment 230 adjacent to memory segment 220 is adjacent to the decoder cell 221 included in memory segment 220. Explained another way, decoder cells 231 and 241 are also arranged between edge cell arrays 223 and 233.

[0060] Figure 4 The configuration is given for illustrative purposes. Figure 4 Various implementations are within the contemplated scope of the embodiments of the present disclosure. For example, in some embodiments, the storage device 40 includes Figure 4 The configuration shown in FIG. 1 is a plurality of storage repositories 201 - 202 .

[0061] Please refer to Figure 5 . Figure 5 For example, according to the embodiment Figure 4 Schematic diagram of a circuit of the storage device 40. Figure 2BIn contrast, the word line select decoder 120 is further configured to decode and generate a word line segment select signal WSEG in response to the address ADR, which is transmitted to the decoders 231 and 241 respectively. <2> , WSEG <3> For example, when the word line select decoder 120 decodes the address ADR indicating that the memory cell to be activated is in the memory array 232, the word line segment select signal WSEG <2> The word line segment select signal WSEG has a logic 0. <0> , WSEG <1> , WSEG <3> It has logic 1. And so on, repeated description is omitted here.

[0062] Please refer to Figure 6 . Figure 6 For example, according to the embodiment Figure 4 Layout diagram of the storage device 40 in FIG.

[0063] Please refer to Figure 7 . Figure 7 FIG. 7 is a schematic diagram of the layout of the storage device 70 according to an embodiment. Figures 1 to 6 For ease of understanding, Figure 7 Similar components in the drawings are designated by the same reference numerals.

[0064] and Figure 4 In contrast, instead of arranging the word line decoder unit 110 on the same side of the memory segments 210-240, the word line decoder unit 110 in the memory device 70 is arranged between the memory segments 210 and 230. In other words, the memory banks 201-202 are symmetrical with respect to the word line decoder unit 110. In detail, Figure 7 As shown, decoder unit 211 is adjacent to boundary B7 of word line decoder unit 110, and decoder unit 231 is adjacent to boundary B8 of word line decoder unit 110. In other words, decoder units 211 and 231 are adjacent to two opposite boundaries B7-B8 of word line decoder unit 110.

[0065] In addition, the storage device 70 further includes a storage segment 250 adjacent to the storage segment 240. The storage segment 250 includes a decoder 251, a storage array 252, edge cell arrays 253 and 254 disposed on both sides of the storage array 252, and a blank space 255. Figure 7 As shown, decoder units 241 , 251 are adjacent to each other and positioned between memory arrays 242 , 252 .

[0066] In some embodiments, the memory segments 210-220 are considered as a first group G1, and the memory segments 230-250 are considered as a second group G2. The first group G1 is configured on one side of the word line decoder unit 110, and the second group G2 is configured on the other side of the word line decoder unit 110. Figure 7As shown, the number of memory segments included in the first group G1 is different from the number of memory segments included in the second group G2. Specifically, the number of memory segments included in the first group G1 is an even number, and the number of memory segments included in the second group G2 is an odd number.

[0067] In some embodiments, the storage device 70 further includes another storage segment and the storage segment 250 forms the same configuration as the storage segments 210 - 220 .

[0068] In various embodiments, both sides of the word line decoder unit 110 include multiple groups of memory segments with the same configuration (eg, memory segments 210 - 220 ).

[0069] As previously mentioned, in some approaches, each memory segment must include at least two edge cell arrays and blank space. Therefore, when a memory device includes a large number of memory segments, the non-memory area consumed increases significantly. In contrast, using the configuration of the present disclosure, when a memory device includes a large number of memory segments, the non-memory area consumed decreases. For example, in some approaches, a memory device includes eight memory segments with 64 columns and 64 rows, occupying a total area of ​​approximately 855 square microns, but using the configuration of the present disclosure, the area occupied is only 817 square microns, a reduction of approximately 5%. For another example, in some approaches, a memory device includes twelve memory segments with 512 columns and 48 rows, occupying a total area of ​​approximately 5211.8 square microns, but using the configuration of the present disclosure, the area occupied is only 4887.6 square microns, a reduction of approximately 7%.

[0070] Furthermore, in some approaches, for example, in a memory device comprising 12 memory banks with 512 columns and 48 rows, including four memory rows in one bank would violate IC layout design rules. In contrast, with the configuration disclosed herein, since the overall memory bank area is reduced, four memory rows can be included in one bank without violating IC layout design rules. This significantly enhances the flexibility of memory device layout.

[0071] Figure 7 The configuration is given for illustrative purposes. Figure 7 Various implementations are contemplated within the scope of the present disclosure. For example, in some embodiments, the number of memory segments included in the first group G1 and the number of memory segments included in the second group G2 are both even numbers or both odd numbers. In various embodiments, the number of memory segments included in the first group G1 and the number of memory segments included in the second group G2 are the same.

[0072] Please refer to Figure 8 . Figure 8 FIG. 8 is a schematic diagram of the layout of the storage device 80 according to an embodiment. Figures 1 to 7 For ease of understanding, Figure 8 For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted in this article unless there is a need to introduce the specific operations of similar components. Figure 8 The collaborative relationship of the components shown in.

[0073] and Figure 7 In contrast, memory device 80 further includes a main control circuit 720 and an input / output circuit 730. In some embodiments, word line decoder 110, main control circuit 720, and input / output circuit 730 cooperate to perform memory operations such as reading or writing memory cells in memory device 80.

[0074] Figure 8 The configuration is given for illustrative purposes. Figure 8 Various implementations are within the contemplated scope of the embodiments of the present disclosure. For example, in some embodiments, the memory device includes a plurality of memory segments located on the other side of the master control circuit 720 relative to the word line decoder 110, wherein the memory segments are connected to the memory segments. Figure 7 The memory segments shown in have the same or similar configurations.

[0075] Please refer to Figure 9 . Figure 9 FIG. 1 is a schematic diagram of the layout of a storage device 90 according to an embodiment. Figures 1 to 8 For ease of understanding, Figure 9 Similar components in the drawings are designated by the same reference numerals.

[0076] and Figure 4 In contrast, the replacement isolation cell 310 has a width W1, while the storage device 90 includes two rows of edge cell arrays (e.g., edge cell array 213) and has a width W3. Similarly, the replacement isolation cell 320 has a width W1, while the storage device 90 includes two rows of edge cell arrays (e.g., edge cell array 233) and has a width W4. In some embodiments, widths W3 and W4 are equal. In some embodiments, widths W3 and W4 are unequal.

[0077] Figure 9 The configuration is given for illustrative purposes. Figure 9 Various implementations of are within the contemplated scope of the embodiments of the present disclosure. For example, in some embodiments, 310 in memory device 90 includes more than two rows of edge cell arrays.

[0078] Please refer to Figure 10 . Figure 10FIG. 1 is a flow chart of a method 1000 for manufacturing a memory device according to an embodiment. Figure 10 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable. Like reference numbers are used throughout the various views and illustrative embodiments to designate like components. The method 1000 includes the following references: Figure 7 The integrated circuit 70 is described with respect to steps 1010 to 1020 .

[0079] In step 1010, if Figure 7 As shown, the memory segments 210 - 250 are arranged adjacent to the word line decoder 110 , wherein one of the memory segments 210 - 250 is activated in response to the word line signal GWLB transmitted from the word line decoder.

[0080] In some embodiments, as Figure 7 In the embodiment, the memory segments belonging to the first group G1 and the second group G2 are arranged on opposite sides of the word line decoder unit 110 and include different numbers of memory segments. For example, the first group G1 includes 2 memory segments, and the second group G2 includes 3 memory segments.

[0081] In step 1020, an isolation cell is sandwiched between two adjacent memory segments in a memory segment. For example, the isolation cell 310 is sandwiched between two adjacent memory segments 210-220 in the memory segments 210-250. Each of the two adjacent memory segments 210-220 includes a decoder 211, 221 and a memory array 212, 222 connected thereto via a plurality of word lines. The decoders 211, 221 in the two adjacent memory segments 210-220 are disposed on opposite sides of the isolation cell 310, and the word lines WL_1_0-WL_1_n, WL_2_0-WL_2_n are disposed between the decoders 211, 221, as shown in FIG. Figure 3A shown.

[0082] In some embodiments, as Figure 7 As shown, the memory segment 210-250 is adjacent to the other memory segment 250 of one (240) of the two adjacent segments 230-240 and includes a decoder (unit) 251. The decoder unit 241 and the decoder unit 251 are adjacent to each other.

[0083] Now Figure 11 For reference. Figure 11 FIG. 1 is a block diagram of an electronic design automation (EDA) system 1100 for designing an integrated circuit layout according to some embodiments of the present disclosure. The EDA system 1100 is used to implement Figure 10 One or more steps of the method 1000 disclosed in Figures 1 to 9 Explanation: In some embodiments, the EDA system 1100 includes an APR system.

[0084] In some embodiments, EDA system 1100 is a general-purpose computing component that includes a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. Storage medium 1104 is encoded with (i.e., stores) computer program code (instructions) 1106, i.e., a set of executable instructions. Execution of instructions 1106 by hardware processor 1102 represents (at least in part) an EDA tool that implements, for example, a portion or all of method 1100.

[0085] The processor 1102 is electrically coupled to the computer-readable storage medium 1104 via a bus 1108. The processor 1102 is also electrically coupled to an I / O interface 1110 and a manufacturing tool 1116 via the bus 1108. A network interface 1112 is also electrically coupled to the processor 1102 via the bus 1108. The network interface 1112 is connected to a network 1114, enabling the processor 1102 and the computer-readable storage medium 1104 to connect to external components via the network 1114. The processor 1102 is configured to execute computer program code 1106 encoded in the computer-readable storage medium 1104 to enable the system 1100 to perform part or all of the indicated processes and / or methods. In one or more embodiments, the processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0086] In one or more embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1104 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0087] In one or more embodiments, the storage medium 1104 stores computer program code 1106 for enabling the EDA system 1100 (wherein such execution represents (at least in part) an EDA tool) to perform some or all of the indicated processes and / or methods. In one or more embodiments, the storage medium 1104 also stores some or all of the information that facilitates the execution of the indicated processes and / or methods. In one or more embodiments, the storage medium 1104 stores information including those standard cells as disclosed herein (e.g., as described above with respect to Figures 1 to 9 An IC layout diagram 1120 of a standard cell (a cell included in the memory devices 10, 40, 70, 80, and / or 90 discussed).

[0088] EDA system 1100 includes an I / O interface 1110. I / O interface 1110 is coupled to external circuitry. In one or more embodiments, I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for communicating information and commands to processor 1102.

[0089] EDA system 1100 also includes a network interface 1112 coupled to processor 1102. Network interface 1112 allows EDA system 1100 to communicate with a network 1114 to which one or more other computer systems are connected. Network interface 1112 includes a wireless network interface such as BLUE TOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface such as ETHERNET, USB, or IEEE-1164. In one or more embodiments, some or all of the processes and / or methods described are implemented in two or more systems 1100.

[0090] The EDA system 1100 also includes a fabrication tool 1116 coupled to the processor 1102. The fabrication tool 1116 is configured to fabricate integrated circuits based on the design files processed by the processor 1102, for example, Figures 1 to 9 Storage devices 10, 40, 70-90 of the icons.

[0091] The EDA system 1100 is configured to receive information via an I / O interface 1110. The information received via the I / O interface 1110 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for processing by the processor 1102. The information is transmitted to the processor 1102 via a bus 1108. The EDA system 1100 is configured to receive information related to the UI via the I / O interface 1110. This information is stored in a computer-readable medium 1104 as a design specification 1122.

[0092] In some embodiments, a part or all of the process and / or method pointed out is implemented as a separate software application for execution by a processor. In some embodiments, a part or all of the process and / or method pointed out is implemented as a software application that is a part of an additional software application. In some embodiments, a part or all of the process and / or method pointed out is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method pointed out is implemented as a software application that is a part of an EDA tool. In some embodiments, a part or all of the process and / or method pointed out is implemented as a software application used by an EDA system 1100. In some embodiments, a layout diagram comprising standard cells is generated using a suitable layout generation tool.

[0093] In some embodiments, these processes are implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, for example, one or more of an optical disc (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM, RAM), a memory card, and the like.

[0094] Figure 12 FIG1 is a block diagram of an IC manufacturing system 1200 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor shields or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the IC manufacturing system 1200.

[0095] exist Figure 12 In the embodiment of the present invention, IC manufacturing system 1200 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing IC components 1260, such as design room 1220, shielded room 1230, and IC manufacturer / fab ("fab") 1250. These entities in IC manufacturing system 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an enterprise intranet or the Internet. These communication networks include wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of design room 1220, shielded room 1230, and IC fab 1250 are owned by a single entity. In some embodiments, two or more of design room 1220, shielded room 1230, and IC fab 1250 coexist in a common facility and utilize common resources.

[0096] The design office (or design team) 1220 generates an IC design layout 1222. The IC design layout 1222 includes a plurality of IC components 1260 (e.g., Figures 1 to 9 Various geometric patterns designed by the storage device 10, 40, 70-90) of the icon, for example, Figure 1 、 Figures 3A to 3B 、 Figure 4 as well as Figures 6 to 9 12. The IC layout design depicted in FIG. 12. These geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers that make up the various components of the IC component 1260 to be manufactured. The various layers combine to form various IC features. For example, a portion of the IC design layout 1222 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) and various metal layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, conductive segments, or vias for interconnecting layers. The design studio 1220 implements an appropriate design program to form the IC design layout 1222. The design program includes one or more of a logical design, a physical design, or a location and route. The IC design layout 1222 is presented in one or more data files having information about the geometric patterns. For example, the IC design layout 1222 can be expressed in a GDSII file format or a DFII file format.

[0097] The shield chamber 1230 includes data preparation 1232 and shield fabrication 1244. The shield chamber 1230 uses the IC design layout 1222 to fabricate one or more shields 1245 to be used to fabricate various layers of the IC component 1260 according to the IC design layout 1222. The shield chamber 1230 performs shield data preparation 1232, wherein the IC design layout 1222 is translated into a representative data file (RDF). The shield data preparation 1232 provides the RDF to the shield fabrication 1244. The shield fabrication 1244 includes a shield writer. The shield writer converts the RDF into an image on a substrate such as a shield (mask) 1245 or a semiconductor wafer 1253. The design layout 1222 is fabricated by the shield data preparation 1232 to comply with the specific characteristics of the shield writer and / or the requirements of the IC wafer fab 1250. In Figure 12 , data preparation 1232 and shield manufacturing 1244 are illustrated as separate components. In some embodiments, data preparation 1232 and shield manufacturing 1244 may be collectively referred to as shield data preparation.

[0098] In some embodiments, data preparation 1232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by self-diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 1222. In some embodiments, data preparation 1232 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masking, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0099] In some embodiments, data preparation 1232 includes a mask rule checker (MRC) that checks the IC design layout 1222, which has undergone processing in OPC, against a set of mask establishment rules that contain certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for the constraints during mask fabrication 1244, which may cancel portions of the modifications performed by OPC to comply with the mask establishment rules.

[0100] In some embodiments, data preparation 1232 includes lithography process checking (LPC), which simulates the process to be performed by IC fab 1250 to manufacture IC component 1260. LPC simulates this process based on IC design layout 1222 to create a simulated manufactured component, such as IC component 1260. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated manufactured component has been created by LPC, if the simulated component is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 1222.

[0101] It should be understood that the above description of mask data preparation 1232 has been simplified for clarity. In some embodiments, data preparation 1232 includes additional features, such as logic operations (LOPs), to modify IC design layout 1222 according to manufacturing rules. Additionally, the processes applied to IC design layout 1222 during data preparation 1232 can be performed in a variety of different orders.

[0102] After data preparation 1232 and during mask fabrication 1244, a mask 1245 or a group of masks 1245 are fabricated based on the modified IC design layout 1222. In some embodiments, mask fabrication 1244 includes performing one or more lithographic exposures based on the IC design layout 1222. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on a mask (photomask or reticle) 1245 based on the modified IC design layout 1222. Shield 1245 can be formed using various techniques. In some embodiments, shield 1245 is formed using binary techniques. In some embodiments, the mask pattern includes opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask pattern of shield 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1245 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1245, various features in the pattern formed on the phase shift mask are designed to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1244 is used in a variety of processes. For example, the mask(s) are used in an ion implantation process to form various doped regions in semiconductor wafer 1253, in an etching process to form various etched regions in semiconductor wafer 1253, and / or in other suitable processes.

[0103] IC fab 1250 includes wafer fabrication 1252. IC fab 1250 is an IC manufacturing enterprise that includes one or more fabrication facilities used to manufacture a variety of different IC products. In some embodiments, IC fab 1250 is a semiconductor foundry. For example, one fabrication facility may be used for front-end fabrication of multiple IC products (front-end-of-line (FEOL) fabrication), while a second fabrication facility may provide back-end fabrication (back-end-of-line (BEOL) fabrication) for interconnection and packaging of the IC products. A third fabrication facility may provide other services for the foundry enterprise.

[0104] IC fab 1250 uses shield 1245 fabricated by shield chamber 1230 to fabricate IC components 1260. Thus, IC fab 1250 at least indirectly uses IC design layout 1222 to fabricate IC components 1260. In some embodiments, semiconductor wafer 1253 is fabricated by IC fab 1250 using shield 1245 to form IC components 1260. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1253 further includes one or more of various doped regions, dielectric features, multiple levels of interconnects, and the like (formed in subsequent fabrication steps).

[0105] As described above, the memory device in the disclosed embodiments arranges memory arrays back-to-back and sandwiches isolation cells between adjacent memory segments. This reduces the area used for edge cells and the required empty space, further improving the area efficiency of the memory device and reducing manufacturing costs.

[0106] According to an embodiment of the present disclosure, a storage device is provided, comprising a first isolation unit extending along a first direction, a first storage array of a first storage segment, and a second storage array of a second storage segment. The first storage array of the first storage segment is adjacent to a first boundary of the first isolation unit along a second direction different from the first direction. The second storage array of the second storage segment is adjacent to a second boundary of the first isolation unit along a second direction different from the first boundary. The storage device further comprises a first decoder unit of the first storage segment and a second decoder unit of the second storage segment, which are arranged on opposite sides of the first isolation unit.

[0107] In some embodiments, the memory device further includes a first edge cell array of a first memory segment and a second edge cell array of a second memory segment. The first edge cell array of the first memory segment is adjacent to a boundary of the first memory array of the first memory segment opposite the first isolation cell. The second edge cell array of the second memory segment is adjacent to a boundary of the second memory array of the second memory segment opposite the first isolation cell.

[0108] In some embodiments, the memory device further comprises a plurality of edge cell arrays. The edge cell arrays are adjacent to the first memory array of the first memory segment and the second memory array of the second memory segment. The first isolation unit comprises N edge cell arrays, where N is a positive integer.

[0109] In some embodiments, the number N is equal to 2.

[0110] In some embodiments, the memory device further includes a third memory array of the third memory segment, a fourth memory array of the fourth memory segment, a second isolation unit, and a third decoder unit of the third memory segment and a fourth decoder unit of the fourth memory segment. The second isolation unit is disposed between and adjacent to the third memory array of the third memory segment and the fourth memory array of the fourth memory segment. The third decoder unit of the third memory segment and the fourth decoder unit of the fourth memory segment are disposed on opposite sides of the second isolation unit, wherein the third decoder unit of the third memory segment is adjacent to the second decoder unit of the second memory segment along the second direction.

[0111] In some embodiments, the memory device further includes a first edge cell array and a second edge cell array. The first edge cell array is adjacent to the second memory array of the second memory segment, and the second edge cell array is adjacent to the third memory array of the third memory segment. The third decoder unit of the third memory segment and the second decoder unit of the second memory segment are disposed between the first edge cell array and the second edge cell array.

[0112] In some embodiments, the memory device further includes a third memory array of a third memory segment, a third decoder unit of the third memory segment, and a word line decoder unit, wherein the second decoder unit of the second memory segment and the third decoder unit of the third memory segment are adjacent to two opposite boundaries of the word line decoder unit.

[0113] In some embodiments, the memory device further includes a second isolation unit, a fourth memory array of a fourth memory segment, a fourth decoder unit of the fourth memory segment, a fifth decoder unit of the fifth memory segment, and a fifth memory array of the fifth memory segment. The third memory array of the third memory segment is adjacent to a first boundary of the second isolation unit. The fourth memory array of the fourth memory segment is adjacent to a second boundary of the second isolation unit that is different from the first boundary. The third decoder unit of the third memory segment and the fourth decoder unit of the fourth memory segment are arranged on opposite sides of the second isolation unit. The fourth decoder unit of the fourth memory segment and the fifth decoder unit of the fifth memory segment are adjacent to each other and arranged between the fourth memory array of the fourth memory segment and the fifth memory array of the fifth memory segment.

[0114] In some embodiments, the memory device further includes a plurality of first word lines and a plurality of second word lines. The first word lines extend from a first decoder unit of a first memory segment to a first memory array of the first memory segment. The second word lines extend from a second decoder unit of a second memory segment to a second memory array of the second memory segment, wherein the first word lines and the second word lines terminate at a first isolation unit.

[0115] In some embodiments, the first memory array of the first memory segment includes a plurality of memory cells arranged in a plurality of columns and a plurality of rows, and the first isolation unit includes a plurality of edge cells. The memory cells and the edge cells have the same structural configuration.

[0116] According to an embodiment of the present disclosure, a storage device is provided that includes a first storage memory. The first storage memory includes a plurality of first edge cells, a plurality of first storage cells, a plurality of second edge cells, a plurality of second storage cells, a plurality of third edge cells, and a plurality of first word lines and a plurality of second word lines. The first edge cells are configured in at least a first edge row of a plurality of storage rows. The first storage cells are configured in a first group of storage rows, wherein the edge rows in the first group of storage rows are directly adjacent to at least a first edge row of storage rows. The second edge cells are configured in a second group of a plurality of storage rows, and the second storage cells are configured in a third group of a plurality of storage rows, wherein the second edge cells are sandwiched between the first storage cells and the second storage cells. The third edge cell is configured in at least a second edge row of storage rows, wherein the edge rows in the third group of storage rows are directly adjacent to at least a second edge row of storage rows. The first word line is coupled to the first storage cell, and the second word line is coupled to the second storage cell, wherein the first word line and the second word line terminate in the second group of storage rows.

[0117] In some embodiments, the memory device further includes a first decoder and a second decoder, wherein the first decoder is coupled to the first word line and the second decoder is coupled to the second word line, wherein the first decoder and the second decoder are disposed on opposite sides of the first memory bank.

[0118] In some embodiments, the memory device further includes a first decoder and a second decoder. The first decoder is configured to transmit a plurality of first wordline signals to a first wordline on a first side of the first memory bank to activate one of the first memory cells. The second decoder is configured to transmit a plurality of second wordline signals to a second wordline on a second side of the first memory bank that is different from the first side to activate one of the second memory cells.

[0119] In some embodiments, the first edge unit and the first storage unit are a mirror image arrangement of the third edge unit and the second storage unit relative to the second edge unit.

[0120] In some embodiments, the memory device further includes a second memory bank. The first memory bank and the second memory bank have the same configuration, and the first memory bank and the second memory bank are symmetrical with respect to word line decoders disposed in the first memory bank and the second memory bank.

[0121] In some embodiments, the memory device further includes a plurality of first memory banks and a word line decoder. The word line decoder is coupled to the first memory banks. The number of first groups of first memory banks is equal to the number of second groups of first memory banks. The first group of first memory banks is disposed on a first side of the word line decoder, and the second group of first memory banks is disposed on a second side of the word line decoder that is different from the first side.

[0122] According to an embodiment of the present disclosure, a memory device is provided that includes a plurality of memory segments and an isolation unit. The memory segments are adjacent to a word line decoder configuration, wherein one of the memory segments is configured to be activated in response to a word line signal transmitted from the word line decoder. The isolation unit is configured to be sandwiched between two adjacent segments of the memory segment, wherein each of the two adjacent segments includes a first decoder and a memory array coupled to the first decoder via a plurality of word lines. The first decoders in the two adjacent segments are configured on opposite sides of the isolation unit, and the word line is configured between the first decoders in the two adjacent segments.

[0123] In some embodiments, a first group of memory segments is arranged on a first side of a word line decoder, and a second group of memory segments is arranged on a second side of the word line decoder that is different from the first side. A first number of memory segments in the first group and a second number of memory segments in the second group are different from each other.

[0124] In some embodiments, the first number is an odd number and the second number is an even number.

[0125] In some embodiments, a first decoder of one of the two adjacent segments is configured in a first decoder unit, and another segment of the storage segment adjacent to the one of the two adjacent segments includes a second decoder configured in a second decoder unit, wherein the first decoder unit and the second decoder unit are adjacent to each other.

[0126] The foregoing summarizes the features of multiple embodiments so that those skilled in the art can better understand the aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can readily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that various changes, substitutions, and modifications may be made thereto without departing from the spirit and scope of the embodiments of the present disclosure.

[0127] Example 1. A storage device comprises: a first isolation unit extending along a first direction; a first storage array of a first storage segment, adjacent to a first boundary of the first isolation unit along a second direction different from the first direction; a second storage array of a second storage segment, adjacent to a second boundary of the first isolation unit different from the first boundary along the second direction; and a first decoder unit of the first storage segment and a second decoder unit of the second storage segment, arranged on opposite sides of the first isolation unit.

[0128] Example 2. The storage device as described in Example 1 further includes: a first edge cell array of the first storage segment, adjacent to the boundary of the first storage array of the first storage segment opposite to the first isolation unit; and a second edge cell array of the second storage segment, adjacent to the boundary of the second storage array of the second storage segment opposite to the first isolation unit.

[0129] Example 3. The storage device as described in Example 1 further includes: a plurality of edge cell arrays, wherein the plurality of edge cell arrays are adjacent to the first storage array of the first storage segment and the second storage array of the second storage segment; wherein the first isolation unit includes a number N of the plurality of edge cell arrays, where N is a positive integer.

[0130] Example 4. The memory device of Example 3, wherein the number N is equal to 2.

[0131] Example 5. The storage device as described in Example 1 further includes: a third storage array of a third storage segment and a fourth storage array of a fourth storage segment; a second isolation unit, configured and adjacent to the middle of the third storage array of the third storage segment and the fourth storage array of the fourth storage segment; and a third decoder unit of the third storage segment and the fourth decoder unit of the fourth storage segment, configured on opposite sides of the second isolation unit, wherein the third decoder unit of the third storage segment is adjacent to the second decoder unit of the second storage segment along the second direction.

[0132] Example 6. The storage device as described in Example 5 further includes: a first edge cell array and a second edge cell array, wherein the first edge cell array is adjacent to the second storage array of the second storage segment, and the second edge cell array is adjacent to the third storage array of the third storage segment; wherein the third decoder unit of the third storage segment and the second decoder unit of the second storage segment are configured between the first edge cell array and the second edge cell array.

[0133] Example 7. The storage device as described in Example 1 further includes: a third storage array of a third storage segment and a third decoder unit of the third storage segment; and a word line decoder unit, wherein the second decoder unit of the second storage segment and the third decoder unit of the third storage segment are adjacent to two opposite boundaries of the word line decoder unit.

[0134] Example 8. The storage device as described in Example 7 further includes: a second isolation unit, wherein the third storage array of the third storage segment is adjacent to a first boundary of the second isolation unit; a fourth storage array of the fourth storage segment is adjacent to a second boundary of the second isolation unit that is different from the first boundary; a fourth decoder unit of the fourth storage segment, wherein the third decoder unit of the third storage segment and the fourth decoder unit of the fourth storage segment are configured on opposite sides of the second isolation unit; and a fifth decoder unit of the fifth storage segment and a fifth storage array of the fifth storage segment, wherein the fourth decoder unit of the fourth storage segment and the fifth decoder unit of the fifth storage segment are adjacent to each other and configured between the fourth storage array of the fourth storage segment and the fifth storage array of the fifth storage segment.

[0135] Example 9. The storage device as described in Example 1 further includes: a plurality of first word lines, the plurality of first word lines extending from the first decoder unit of the first storage segment to the first storage array of the first storage segment; and a plurality of second word lines, the plurality of second word lines extending from the second decoder unit of the second storage segment to the second storage array of the second storage segment, wherein the plurality of first word lines and the plurality of second word lines terminate at the first isolation unit.

[0136] Example 10. The memory device of Example 1, wherein the first memory array of the first memory segment includes a plurality of memory cells arranged in a plurality of columns and a plurality of rows, and the first isolation unit includes a plurality of edge cells, wherein the plurality of memory cells and the plurality of edge cells have the same structural configuration.

[0137] Example 11. A storage device, comprising: a first storage memory, comprising: a plurality of first edge cells, arranged in at least a first edge row of a plurality of storage rows; a plurality of first storage cells, arranged in a first group of the plurality of storage rows, wherein the edge rows in the first group of the plurality of storage rows are directly adjacent to the at least first edge row of the plurality of storage rows; a plurality of second edge cells and a plurality of second storage cells, the plurality of second edge cells being arranged in a second group of the plurality of storage rows, and the plurality of second storage cells being arranged in a third group of the plurality of storage rows, wherein the plurality of second edge cells are sandwiched between the plurality of first storage cells and the plurality of second storage cells; a plurality of third edge cells being arranged in at least a second edge row of the plurality of storage rows, wherein the edge rows in the third group of the plurality of storage rows are directly adjacent to the at least second edge row of the plurality of storage rows; and a plurality of first word lines and a plurality of second word lines, the plurality of first word lines coupling the plurality of first storage cells, the plurality of second word lines coupling the plurality of second storage cells, wherein the plurality of first word lines and the plurality of second word lines terminate in the second group of the plurality of storage rows.

[0138] Example 12. The storage device as described in Example 11 further includes: a first decoder and a second decoder, the first decoder is coupled to the multiple first word lines, and the second decoder is coupled to the multiple second word lines, wherein the first decoder and the second decoder are configured on opposite sides of the first memory bank.

[0139] Example 13. The storage device as described in Example 11 further includes: a first decoder for transmitting a plurality of first word line signals to the plurality of first word lines at a first side of the first storage memory to activate one of the plurality of first storage cells; a second decoder for transmitting a plurality of second word line signals to the plurality of second word lines at a second side of the first storage memory that is different from the first side to activate one of the plurality of second storage cells.

[0140] Example 14. The storage device of Example 11, wherein, relative to the second edge cells, the first edge cells and the first storage cells are a mirror image arrangement of the third edge cells and the second storage cells.

[0141] Example 15. The storage device of Example 11 further includes: a second memory bank, wherein the first memory bank and the second memory bank include the same configuration, and the first memory bank and the second memory bank are symmetrical to each other with respect to word line decoders disposed in the first memory bank and the second memory bank.

[0142] Example 16. The storage device as described in Example 11 further includes: a plurality of first storage banks; and a word line decoder, coupled to the plurality of first storage banks, wherein the number of first groups of the plurality of first storage banks is the same as the number of second groups of the plurality of first storage banks, the first groups of the plurality of first storage banks are configured on a first side of the word line decoder, and the second groups of the plurality of first storage banks are configured on a second side of the word line decoder that is different from the first side.

[0143] Example 17. A storage device comprising: a plurality of storage segments adjacent to a word line decoder configuration, wherein one of the plurality of storage segments is configured to be activated in response to a word line signal transmitted from the word line decoder; and an isolation unit configured to be sandwiched between two adjacent segments of the plurality of storage segments, wherein each of the two adjacent segments includes a first decoder and a storage array coupled to the first decoder via a plurality of word lines, wherein the first decoders in the two adjacent segments are configured on opposite sides of the isolation unit, and the plurality of word lines are configured between the first decoders in the two adjacent segments.

[0144] Example 18. A storage device as described in Example 17, wherein a first group of the multiple storage segments is configured on a first side of the word line decoder, and a second group of the multiple storage segments is configured on a second side of the word line decoder that is different from the first side; wherein a first number of the multiple storage segments in the first group and a second number of the multiple storage segments in the second group are different from each other.

[0145] Example 19. The memory device of Example 18, wherein the first number is an odd number and the second number is an even number.

[0146] Example 20. A storage device as described in Example 17, wherein the first decoder of one of the two adjacent segments is configured in a first decoder unit; wherein another segment of the multiple storage segments adjacent to the one of the two adjacent segments includes a second decoder configured in a second decoder unit, wherein the first decoder unit and the second decoder unit are adjacent to each other.

Claims

1. A storage device comprising: A first isolation unit extending along a first direction; A first memory array of a first memory section is adjacent to a first boundary of the first isolation unit along a second direction different from the first direction; A second storage array of a second storage section adjoins a second boundary of the first isolation unit different from the first boundary along the second direction; The first decoder unit of the first storage segment and the second decoder unit of the second storage segment are arranged on opposite sides of the first isolation unit; a plurality of first word lines extending from the first decoder unit of the first memory segment to the first memory array of the first memory segment; as well as A plurality of second word lines extend from the second decoder unit of the second storage segment to the second storage array of the second storage segment, wherein the plurality of first word lines and the plurality of second word lines terminate at the first isolation unit.

2. The storage device according to claim 1, further comprising: a first edge cell array of the first storage segment, adjacent to a boundary of the first storage array of the first storage segment opposite to the first isolation unit; as well as The second edge cell array of the second storage segment is adjacent to a boundary of the second storage array of the second storage segment opposite to the first isolation unit.

3. The storage device according to claim 1 , further comprising: a plurality of edge cell arrays, the plurality of edge cell arrays being adjacent to the first storage array of the first storage section and the second storage array of the second storage section; The first isolation unit includes a plurality of edge unit arrays of number N, where N is a positive integer. The storage device of claim 3 , wherein the number N is equal to 2.

5. The storage device according to claim 1 , further comprising: a third memory array of the third memory section and a fourth memory array of the fourth memory section; a second isolation unit, configured and adjacent to the third storage array of the third storage section and the fourth storage array of the fourth storage section; as well as The third decoder unit of the third storage segment and the fourth decoder unit of the fourth storage segment are arranged on opposite sides of the second isolation unit, wherein the third decoder unit of the third storage segment is adjacent to the second decoder unit of the second storage segment along the second direction.

6. The storage device according to claim 5, further comprising: a first edge cell array and a second edge cell array, wherein the first edge cell array is adjacent to the second storage array of the second storage segment, and the second edge cell array is adjacent to the third storage array of the third storage segment; The third decoder unit of the third storage segment and the second decoder unit of the second storage segment are disposed between the first edge cell array and the second edge cell array.

7. The storage device according to claim 1, further comprising: a third memory array of a third memory segment and a third decoder unit of the third memory segment; as well as A word line decoder unit, wherein the second decoder unit of the second storage segment and the third decoder unit of the third storage segment are adjacent to two opposite boundaries of the word line decoder unit.

8. The storage device according to claim 7, further comprising: a second isolation unit, wherein the third memory array of the third memory section abuts a first boundary of the second isolation unit; a fourth memory array of a fourth memory section adjacent to a second boundary of the second isolation unit that is different from the first boundary; a fourth decoder unit of the fourth storage segment, wherein the third decoder unit of the third storage segment and the fourth decoder unit of the fourth storage segment are arranged on opposite sides of the second isolation unit; as well as a fifth decoder unit of a fifth storage segment and a fifth storage array of the fifth storage segment, wherein the fourth decoder unit of the fourth storage segment and the fifth decoder unit of the fifth storage segment are adjacent to each other and are arranged between the fourth storage array of the fourth storage segment and the fifth storage array of the fifth storage segment.

9. The memory device of claim 1 , wherein the first memory array of the first memory segment comprises a plurality of memory cells arranged in a plurality of columns and a plurality of rows, and the first isolation unit comprises a plurality of edge cells, The plurality of storage units and the plurality of edge units have the same structural configuration.

10. A storage device comprising: The first repository includes: a plurality of first edge cells arranged in at least a first edge row of the plurality of storage rows; a first plurality of storage cells arranged in a first group of the plurality of storage rows, wherein an edge row of the first group of the plurality of storage rows is directly adjacent to the at least first edge row of the plurality of storage rows; a plurality of second edge cells and a plurality of second storage cells, the plurality of second edge cells being arranged in a second group of the plurality of storage rows, and the plurality of second storage cells being arranged in a third group of the plurality of storage rows, wherein the plurality of second edge cells are sandwiched between the plurality of first storage cells and the plurality of second storage cells; a plurality of third edge cells arranged in at least a second edge row of the plurality of storage rows, wherein an edge row in the third group of the plurality of storage rows is directly adjacent to the at least second edge row of the plurality of storage rows; and A plurality of first word lines and a plurality of second word lines, the plurality of first word lines are coupled to the plurality of first memory cells, the plurality of second word lines are coupled to the plurality of second memory cells, wherein the plurality of first word lines and the plurality of second word lines terminate at the second group of the plurality of memory rows.

11. The storage device according to claim 10, further comprising: A first decoder and a second decoder are provided, wherein the first decoder is coupled to the first word lines and the second decoder is coupled to the second word lines, wherein the first decoder and the second decoder are disposed at opposite sides of the first memory bank.

12. The storage device according to claim 10, further comprising: a first decoder for transmitting a plurality of first word line signals to the plurality of first word lines at a first side of the first memory bank to activate one of the plurality of first memory cells; The second decoder is configured to transmit a plurality of second word line signals to the plurality of second word lines at a second side of the first memory bank different from the first side to activate one of the plurality of second memory cells.

13. The storage device according to claim 10, wherein: With respect to the second edge units, the first edge units and the first storage units are a mirror image arrangement of the third edge units and the second storage units.

14. The storage device according to claim 10, further comprising: a second repository, wherein the first repository and the second repository comprise the same configuration, and The first memory bank and the second memory bank are symmetrical to each other with respect to word line decoders disposed in the first memory bank and the second memory bank.

15. The storage device according to claim 10, further comprising: a plurality of said first storage repositories; as well as A word line decoder is coupled to the plurality of first memory banks, wherein the number of a first group of the plurality of first memory banks is the same as the number of a second group of the plurality of first memory banks, the first group of the plurality of first memory banks is configured on a first side of the word line decoder, and the second group of the plurality of first memory banks is configured on a second side of the word line decoder that is different from the first side.

16. A storage device comprising: a plurality of memory segments adjacent to a word line decoder configuration, wherein one of the plurality of memory segments is configured to be activated in response to a word line signal transmitted from the word line decoder; as well as an isolation unit configured to be sandwiched between two adjacent segments of the plurality of storage segments, wherein each of the two adjacent segments includes a first decoder and a storage array coupled to the first decoder through a plurality of word lines; The first decoders in the two adjacent sections are arranged at opposite sides of the isolation unit, and the plurality of word lines are arranged between the first decoders in the two adjacent sections.

17. The memory device of claim 16, wherein a first group of the plurality of memory segments is arranged on a first side of the word line decoder, and A second group of the plurality of memory banks is arranged on a second side of the word line decoder different from the first side; A first number of the plurality of storage segments in the first group and a second number of the plurality of storage segments in the second group are different from each other.

18. The memory device of claim 17, wherein the first number is an odd number and the second number is an even number.

19. The storage device of claim 16, wherein the first decoder of one of the two adjacent segments is configured in a first decoder unit; wherein another segment of the plurality of storage segments adjacent to said one of the two adjacent segments includes a second decoder configured in a second decoder unit, The first decoder unit and the second decoder unit are adjacent to each other.

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