Memory devices and their operation methods

Abstract

This application relates to a memory device and a method of operating the same. A memory device and a method of operating the memory device are provided that improve performance by reducing the peak current flowing through the bit lines while simultaneously reducing the time required to complete a programming operation.

Description

Technical Field

[0001] One or more embodiments described herein relate to a memory device and a method of operating the memory device. Background Technology

[0002] The storage device stores data in the memory device under the control of the host. In some cases, the storage device may include a storage controller that controls the memory device.

[0003] Memory devices are classified as volatile memory devices or non-volatile memory devices. Volatile memory devices can only store data when powered by a power source. When power is interrupted, the data stored in the volatile memory device is lost. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0004] Non-volatile memory devices retain data even when power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), and flash memory. Summary of the Invention

[0005] The embodiments provide a memory device and a method of operating the memory device that improve performance by reducing the peak current flowing through the bit lines while reducing the time to complete the programming operation.

[0006] According to one aspect of this disclosure, a memory device is provided, comprising: a plurality of memory cells; a plurality of page buffers, each page buffer being connected to a corresponding memory cell via a plurality of bit lines and configured to temporarily store data to be stored in the plurality of memory cells respectively; and a page buffer controller configured to control one or more voltages to be applied to the plurality of bit lines during a programming operation that stores data in the plurality of memory cells, wherein the programming operation includes a plurality of programming cycles, each programming cycle including a programming voltage application operation and a verification operation, the programming voltage application operation including a pre-charge period, a programming voltage application period, and a discharge period, the plurality of... Each page buffer is configured to provide bit line voltages to the plurality of bit lines in response to a page buffer sensing signal output from a page buffer controller, and the page buffer controller includes: a first signal provider configured to provide a first pulse signal as a page buffer sensing signal during a first period in a precharge period, the first pulse signal having a first voltage level greater than ground voltage; and a second signal provider configured to provide a second pulse signal as a page buffer sensing signal after the first period, the second pulse signal increasing from the first voltage level to a second voltage level with a slope determined according to a cycle count of the plurality of programming cycles, the slope corresponding to one of a plurality of predetermined slopes.

[0007] According to another aspect of this disclosure, a memory device is provided, comprising: a plurality of memory cells; a plurality of page buffers, each page buffer being connected to a corresponding memory cell via a plurality of bit lines and configured to temporarily store data in the corresponding memory cell among the plurality of memory cells; and a page buffer controller configured to control one or more voltages to be applied to the plurality of bit lines during a programming operation that stores data in the plurality of memory cells, wherein the programming operation includes a plurality of programming cycles, each programming cycle including a programming voltage application operation and a verification operation, the programming voltage application operation including a pre-charge period, a programming voltage application period, and a discharge period. The plurality of page buffers are configured to provide bit line voltages to the plurality of bit lines in response to a page buffer sensing signal output from a page buffer controller, and the page buffer controller includes: a first signal provider configured to provide a first pulse signal as a page buffer sensing signal during a first period in a precharge period, the first pulse signal having a first voltage level higher than ground voltage; and a second signal provider configured to provide a step signal as a page buffer sensing signal after the first period, the step signal increasing from the first voltage level to a second voltage level based on a step voltage, the step voltage corresponding to a cycle count of the plurality of programming cycles among a plurality of predetermined step voltages.

[0008] According to another aspect of this disclosure, a method of operating a memory device is provided, the method comprising the steps of: providing a first pulse signal to a page buffer during a first time period, the pulse signal serving as a page buffer sensing signal and having a first voltage level higher than ground voltage; after the first time period, providing a ramp signal to the page buffer, the ramp signal serving as a page buffer sensing signal and increasing from the first voltage level to a second voltage level with a slope determined based on a cycle count of a plurality of programming cycles, the slope corresponding to one of a plurality of predetermined slopes; after the ramp signal reaches the second voltage level, providing a second pulse signal to the page buffer, the second pulse signal serving as a page buffer sensing signal and having a third voltage level higher than or equal to the second voltage level; and applying a programming voltage to word lines commonly connected to a plurality of memory cells.

[0009] According to another aspect of this disclosure, a memory device is provided, comprising: a plurality of memory cells; a voltage generator configured to generate an operating voltage for a programming operation to store data in the plurality of memory cells; a plurality of page buffers connected to the plurality of memory cells via a plurality of bit lines, the plurality of page buffers providing bit line voltages to the plurality of bit lines in response to a page buffer sensing signal; and a page buffer controller configured to provide the page buffer sensing signal to the plurality of page buffers during a programming operation, wherein the page buffer controller includes: a first signal provider configured to provide a pulse signal as the page buffer sensing signal during a first time period, the pulse signal being generated by the voltage generator; and a second signal provider configured to... To provide a ramp signal as a page buffer sensing signal during a second time period following the first time period, the ramp signal has a slope determined based on a cycle count of a programming cycle representing the extent of programming operation execution, and the second signal provider includes: a plurality of switches provided with a page buffer pump voltage; a plurality of transistors grouped and connected in series to the plurality of switches, the plurality of transistors being configured to output a bias current from the plurality of switches in response to a voltage control signal provided based on a cycle count of the programming cycle; a capacitor commonly connected to the plurality of transistors and configured to charge the capacitor voltage with respect to the bias current; and a voltage output circuit commonly connected to the plurality of transistors and configured to transmit the capacitor voltage corresponding to the page buffer sensing signal.

[0010] According to another aspect of this disclosure, a page buffer controller is provided, comprising: a controller configured to control sensing signals for one or more page buffers during a programming operation, the one or more page buffers providing bit line voltages to at least one bit line, wherein the sensing signals include: a first signal provided by the controller during a first period of a precharge phase, the first signal having a first voltage level greater than ground voltage; and a second signal provided by the controller during a second period of the precharge phase occurring after the first period, the second signal increasing from the first voltage level to the second voltage level at one of a plurality of predetermined slopes corresponding to a cycle count of a programming cycle for the programming operation, wherein the second signal is configured to increase at the first slope during the second period when the cycle count is equal to or less than a first reference count or when the cycle count is greater than a second reference count greater than the first reference count; and when the cycle count is greater than the first reference count and equal to or less than the second reference count, the second signal is configured to increase at a second slope less than the first slope during a third period of the precharge phase longer than the second period. Attached Figure Description

[0011] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0013] Figure 1 An implementation of the storage system is shown.

[0014] Figure 2 An embodiment of the memory device is shown.

[0015] Figure 3 An implementation of the storage block is shown.

[0016] Figure 4 This illustrates how programming operations can be implemented.

[0017] Figure 5 This illustrates how programming operations can be implemented.

[0018] Figure 6 Implementation methods for programming voltage and verification voltage are shown.

[0019] Figure 7 This illustrates an implementation of the erase state and multiple programming states.

[0020] Figure 8 An implementation of the peak current flowing through the bit line is shown.

[0021] Figure 9 An implementation of a page buffer and a page buffer controller is shown.

[0022] Figure 10 An implementation of a page buffer and a page buffer controller is shown.

[0023] Figure 11 An implementation of a page buffer and a page buffer controller is shown.

[0024] Figure 12 This illustrates an implementation of the page buffer sensing signal.

[0025] Figure 13 This illustrates an implementation of the page buffer sensing signal.

[0026] Figure 14 An implementation of a page buffer sensing signal provided during the intermediate programming period is shown.

[0027] Figure 15 An embodiment of a method for operating a memory device is shown.

[0028] Figure 16 An implementation of the storage controller is shown.

[0029] Figure 17 This illustrates an implementation of a memory card system.

[0030] Figure 18 An implementation of a solid-state drive (SSD) system is shown.

[0031] Figure 19 This illustrates an implementation method for the user system. Detailed Implementation

[0032] The specific structural or functional descriptions disclosed herein are merely illustrative in order to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0033] Figure 1 This is a diagram illustrating a storage system according to an embodiment. (Refer to...) Figure 1Storage systems can be implemented as data processing systems, including, for example, personal computers (PCs), data center and enterprise data storage systems, direct-attached storage (DAS), data processing systems including storage area networks (SANs), data processing systems including network-attached storage (NAS), etc.

[0034] The storage system may include a storage device 1000 and a host 400. The storage device 1000 may be a device that stores data upon request from the host 400. Examples of the host 400 include mobile phones, smartphones, MP3 players, laptops, desktop computers, game consoles, TVs, tablet PCs, or in-vehicle infotainment systems.

[0035] For example, depending on the host interface corresponding to the communication scheme with host 400, storage device 1000 can be one of various types of storage devices. Examples of storage device 1000 include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro-MMCs (micro-MMCs), secure digital cards (SDs), mini SD cards, micro SD cards, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media cards (SMCs), and memory sticks.

[0036] The storage device 1000 can be manufactured in various package types. Examples include, for instance, stacked package (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0037] Storage device 1000 may include memory device 100 and memory controller 200. Memory device 100 may operate under the control of memory controller 200. Specifically, memory device 100 may receive commands and addresses from memory controller 200 and access memory cells selected by address within the memory cells. Memory device 100 may perform operations indicated by commands on the memory cells selected by address.

[0038] Commands can be, for example, programming commands, read commands, or erase commands. The operation indicated by a command can be, for example, a programming operation (or a write operation), a read operation, or an erase operation.

[0039] A programming operation can be an operation in which the memory device 100 stores write data provided from the host 400 under the control of the memory controller 200. For example, the memory device 100 may receive programming commands, addresses, and data and program the data into a memory cell selected by address. The data to be programmed into the selected memory cell can be considered as write data.

[0040] A read operation can be an operation in which the memory device 100 reads data stored in the memory device 100 under the control of the memory controller 200. For example, the memory device 100 may receive a read command and an address, and read data from a region selected by the address in the memory cell array. The data to be read from the selected region among the data stored in the memory device 100 can be defined as read data.

[0041] An erase operation can be an operation in which the memory device 100 erases data stored in the memory device 100 under the control of the memory controller 200. For example, the memory device 100 may receive an erase command and an address, and erase data stored in a region selected by the address.

[0042] The memory device 100 can be implemented as a volatile memory device or a non-volatile memory device. Examples of volatile memory devices include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Torque-Shifted Random Access Memory (STT-RAM), etc.

[0043] Examples of non-volatile memory devices may include flash memory. Flash memory may include NAND flash memory, vertical NAND flash memory, NOR flash memory, etc. In some embodiments, for ease of description, it is assumed that memory device 100 is NAND flash memory.

[0044] The memory device 100 can store write data under the control of the memory controller 200, or it can read stored read data and provide the read data to the memory controller 200.

[0045] The memory device 100 may include a plurality of dies. Each die may include at least one plane. A plane may include a memory cell array, which includes memory cells for storing write data. The memory cell array may include a plurality of memory blocks. A memory block may be a cell for performing an erase operation to erase data. A memory block may include a plurality of pages. A page may be a cell for performing a programming operation to store write data or a read operation to retrieve stored read data.

[0046] A memory block may include multiple memory cells. Depending on whether a programming operation is to be performed, each memory cell may have an erase state as its target state, or it may have one of multiple programming states as its target state. Each memory cell may have a target state for each plurality of memory cells.

[0047] Programming operations can be operations that store data in multiple memory cells. For example, a programming operation can be an operation that increases the threshold voltage of a selected memory cell among multiple memory cells, such that each threshold voltage of the selected memory cell is included in a respective target state. Implementations of these features will be referred to... Figures 4 to 7 describe.

[0048] The number of programming states can be determined based on the number of bits of data stored in the memory cell. For example, in the case of a memory cell storing 3 bits of data, the number of programming states can be 7. In other embodiments, the number of data bits stored and / or the number of programming states can be different. Implementations of these features will be referred to... Figure 7 describe.

[0049] The target state to which a memory cell in multiple programming and erasing states is to be programmed can be determined based on the data to be stored in the memory cell.

[0050] Memory device 100 may include page buffer controller 101 and page buffer 102. During programming operations, page buffer controller 101 may control the voltages to be applied to multiple bit lines. The voltages to be applied to the multiple bit lines may be bit line voltages. For example, bit line voltages may be programming enable voltages or programming disable voltages.

[0051] In one implementation, the page buffer controller 101 may provide a page buffer sensing signal to the page buffer 102 to supply bit line voltages to multiple bit lines. The implementation will be described with reference to... Figures 2 to 14 describe.

[0052] In implementations, for example, the page buffer control signal may be implemented as a pulse signal with a constant voltage level, a ramp signal with a positive slope, a step signal that increases according to a step voltage, or another type of signal. Some implementations will be referred to Figures 12 to 14 describe.

[0053] Page buffer 102 can be connected to multiple memory cells via bit lines. Page buffer 102 can temporarily store data to be stored in multiple memory cells. In one embodiment, multiple page buffers 102 may be provided. One or more page buffers 102 may be connected to multiple memory cells respectively via multiple bit lines. Multiple page buffers 102 can temporarily store data to be stored in multiple memory cells respectively.

[0054] In an implementation, page buffer 102 may provide bit line voltage to bit lines in response to a page buffer sensing signal. For example, multiple page buffers 102 may provide bit line voltage to multiple bit lines in response to a page buffer sensing signal from page buffer controller 101.

[0055] The storage controller 200 controls the overall operation of the storage device 1000. When power is applied to the storage device 1000, the storage controller 200 can execute instructions (e.g., firmware).

[0056] When the memory device 100 is a flash memory device, the instructions may correspond to firmware including a host interface layer, a flash translation layer, and a flash interface layer. The host interface layer controls the operation between the host 400 and the memory controller 200. The flash translation layer translates logical addresses provided by the host 400 into physical addresses. The flash interface layer controls communication between the memory controller 200 and the memory device 100.

[0057] The storage controller 200 can control the storage device 100 to perform programming, reading, and erasing operations in response to write requests, read requests, and erase requests from the host 400, respectively. During a programming operation, the storage controller 200 can provide the storage device 100 with programming commands, a physical address, and write data. During a read operation, the storage controller 200 can provide the storage device 100 with read commands and a physical address. During an erase operation, the storage controller 200 can provide the storage device 100 with erase commands and a physical address.

[0058] Regardless of any request from host 400, storage controller 200 can autonomously generate commands, addresses, and data. Storage controller 200 can then send these autonomously generated commands, addresses, and data to storage device 100.

[0059] For example, the storage controller 200 may generate commands, addresses, and data for performing background operations. Additionally, the storage controller 200 may provide commands, addresses, and data to the storage device 100. The background operation may be at least one of wear leveling, read reclamation, and garbage collection.

[0060] For example, wear leveling can correspond to static wear leveling, dynamic wear leveling, etc. Static wear leveling may include the operation of storing the number of times a storage block is erased and moving cold data that rarely undergoes erase or write operations to the storage block that has been erased the most times. Dynamic wear leveling may include the operation of storing the number of times a storage block is erased and programming data into the storage block that has been erased the least times.

[0061] Read recycling can include the operation of moving data stored in one storage block to another storage block before an uncorrectable error occurs in the data stored in the storage block.

[0062] Garbage collection may include operations such as copying valid data from bad blocks in a storage block to free blocks and erasing invalid data from bad blocks. Copying valid data from bad blocks to free blocks indicates that valid data from bad blocks is moved to free blocks.

[0063] The storage device 1000 may also include a buffer memory. In some embodiments, the buffer memory may be located in the storage controller 200. Examples of buffer memories include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), and Spin Torque-Shifted Random Access Memory (STT-RAM).

[0064] The memory controller 200 can control two or more memory devices 100. The memory controller 200 can control the memory devices 100, for example, according to an interleaving technique, to improve operational performance. The interleaving technique controls the overlap of operations on two or more memory devices 100. In another embodiment, the memory controller 200 may use different techniques to control the memory devices 100.

[0065] The host 400 can communicate with the storage device 1000 via an interface. Examples of interfaces include a Serial Advanced Technology Attachment (SATA) interface, a High-Speed ​​SATA (SATAe) interface, a Serial Attached Small Computer System Interface (SAS) interface, a High-Speed ​​Peripheral Component Interconnect (PCIe) interface, a High-Speed ​​Non-Volatile Memory (NVMe) interface, an Advanced Host Controller Interface (AHCI) interface, or a multimedia card interface. In other embodiments, the interface may be of another type.

[0066] The host 400 may store write data in the storage device 1000 or communicate with the storage device 1000 to retrieve read data stored in the storage device 1000. In one embodiment, the host 400 may provide the storage device 1000 with a write request, requesting the storage device 1000 to store write data. Additionally, the host 400 may provide the storage device 1000 with a write request, write data, and a logical address for identifying the write data.

[0067] In response to a write request from host 400, storage device 1000 may store the write data provided by host 400 in storage device 100 and may provide host 400 with a response that the storage of write data has been completed.

[0068] In one implementation, the host 400 may provide the storage device 1000 with a read request, requesting the storage device 1000 to provide the host 400 with data stored in the storage device 1000. Additionally, the host 400 may provide the storage device 1000 with a read request and a read address.

[0069] In response to a read request provided by host 400, storage device 1000 may read read data corresponding to the read address provided by host 400 from storage device 100 and may provide the read data to host 400 as a response to the read request.

[0070] Figure 2 An embodiment of a memory device 100 is shown, which includes a memory cell array 110, peripheral circuitry 120, and control logic 130. The memory cell array 110 may include a plurality of memory blocks MB1 to MBk (k is a positive integer). In another embodiment, the number of memory blocks MB1 to MBk shown may be different.

[0071] Each of the memory blocks MB1 to MBk can be connected to local lines LL and bit lines BL1 to BLn (n is a positive integer). Local lines LL can be connected to the line decoder 122 and to each of the memory blocks MB1 to MBk. Local lines LL may include a first select line, a second select line, and multiple word lines arranged between the first and second select lines. Local lines LL may also include dummy lines between the first select line and word lines, dummy lines between the second select line and word lines, and pipelines.

[0072] Bit lines BL1 to BLn can be connected together to memory blocks MB1 to MBk.

[0073] The memory blocks MB1 to MBk can be implemented in a two-dimensional or three-dimensional structure. For example, the memory cells in the memory blocks MB1 to MBk with a two-dimensional structure can be arranged in a direction parallel to the substrate. In one embodiment, the memory cells in the memory blocks MB1 to MBk with a three-dimensional structure can be stacked in a direction perpendicular to the substrate.

[0074] Peripheral circuitry 120 may include a voltage generator 121, a row decoder 122, a page buffer group 123, a column decoder 124, input / output circuitry 125, and sensing circuitry 126. The voltage generator 121 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation command OP_CMD. Additionally, the voltage generator 121 can selectively discharge local lines LL in response to the operation command OP_CMD. For example, under the control of control logic 130, the voltage generator 121 can generate programming voltage, verification voltage, through voltage, turn-on voltage, read voltage, erase voltage, source line voltage, precharge voltage, page buffer pump voltage, core voltage or supply voltage, mirror voltage, reference voltage, and / or other voltages.

[0075] In one embodiment, voltage generator 121 can generate an internal power supply voltage by adjusting an external power supply voltage. For example, the internal power supply voltage can be used as the operating voltage of the memory device 100. In another embodiment, voltage generator 121 can generate multiple voltages using either an external power supply voltage or an internal power supply voltage. Voltage generator 121 may include multiple pump capacitors for receiving the internal power supply voltage, and multiple voltages can be generated by selectively activating the multiple pump capacitors under the control of control logic 130. The multiple generated voltages can be supplied to the memory cell array 110 via row decoder 122.

[0076] The row decoder 122 can transmit an operating voltage Vop to a local line LL in response to a row address RADD. The operating voltage Vop can be transmitted via the local line LL to a selected memory block among memory blocks MB1 to MBk. For example, in a programming operation, the row decoder 122 can apply a programming voltage to the selected word line and can apply a programming pass voltage (e.g., a level different from (e.g., lower than) the programming voltage) to the unselected word line. In a programming verification operation, the row decoder 122 can apply a verification voltage to the selected line and can apply a verification pass voltage (e.g., different from (e.g., higher than) the verification voltage) to the unselected word line.

[0077] During a read operation, the line decoder 122 can apply a read voltage to the selected word line and can apply a read pass voltage (e.g., different from (e.g., higher than) the read voltage) to the unselected word line.

[0078] During an erase operation, the line decoder 122 can select a memory block based on the decoded address. During the erase operation, the line decoder 122 can apply a ground voltage to the word line connected to the selected memory block.

[0079] Page buffer group 123 may include first page buffers PB1 to n page buffers PBn connected to memory cell array 110 via corresponding first bit lines BL1 to n bit lines BLn. The first page buffers PB1 to n page buffers PBn may operate under the control of control logic 130. For example, the first page buffers PB1 to n page buffers PBn may operate in response to the page buffer control signal PBSIGNALS. In one embodiment, the first page buffers PB1 to n page buffers PBn may temporarily store data received via the first bit lines BL1 to n bit lines BLn, or the voltage or current of the bit lines BL1 to BLn may be sensed during read or verification operations.

[0080] During programming operations, page buffers PB1 through PBn can provide bit line voltages to first bit line BL1 through BLn in response to the page buffer control signal PBSIGNALS. For example, the bit line voltages can be programming enable or programming disable voltages. When a programming voltage is applied to the selected word line, page buffers PB1 through PBn can receive data DATA via column decoder 124 and input / output circuitry 125. Page buffers PB1 through PBn can temporarily store the received data DATA and can transfer the temporarily stored data DATA to the selected memory cell via first bit line BL1 through BLn. The memory cell of the selected page is programmed based on the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained.

[0081] During the verification operation, the first page buffer PB1 to the nth page buffer PBn can sense the data stored in the selected memory cell through the first bit line BL1 to the nth bit line BLn.

[0082] During a read operation, the first page buffer PB1 to the nth page buffer PBn can sense the data DATA stored in the selected memory cell through the first bit line BL1 to the nth bit line BLn, and can output the sensed data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0083] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can float the first bit line BL1 to the nth bit line BLn.

[0084] The column decoder 124 can transfer data between the input / output circuitry 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 can exchange data with the page buffers PB1 to PBn via the data lines DL, or with the input / output circuitry 125 via the column lines CL.

[0085] The input / output circuit 125 can transmit commands CMD and addresses ADD (transmitted from the storage controller 200) to the control logic 130, or exchange data DATA with the column decoder 124.

[0086] During a read or verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit VRY_BIT<#> and may output a pass signal PASS or a failure signal FAIL by comparing the transmit voltage VPB from the page buffer group 123 with a reference sensing voltage generated by the reference voltage.

[0087] Control logic 130 can control peripheral circuitry 120 in response to command CMD and address ADD output operation command OP_CMD, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRY_BIT<#>. In an implementation, page buffer sensing signals, current sensing signals, sense amplifier precharge signals, sense node precharge signals, sense amplifier sensing signals, sense amplifier discharge signals, and / or other signals may be included in the page buffer control signal PBSIGNALS. An example will be provided. Figures 9 to 11 describe.

[0088] In one embodiment, control logic 130 may include page buffer controller 101. In another embodiment, during programming operations, page buffer controller 101 may provide a pulse signal having a first voltage level as a page buffer sensing signal. After providing the pulse signal having the first voltage level as the page buffer sensing signal, page buffer controller 101 may provide a ramp signal as the page buffer sensing signal. The ramp signal may increase from the first voltage level to a second voltage level, as shown in reference... Figures 12 to 14 Described.

[0089] In one embodiment, during programming operations, the page buffer controller 101 can provide a pulse signal having a first voltage level as a page buffer sensing signal. After providing the pulse signal having the first voltage level as the page buffer sensing signal, the page buffer controller 101 can provide a step signal that increases from the first voltage level to a second voltage level based on one or more steps according to a constant step voltage as the page buffer sensing signal. The embodiment will be referred to... Figures 12 to 14 describe.

[0090] Figure 3It shows what can be represented Figure 2 The diagram shows an implementation of storage block MBi for storage blocks MB1 to MBk.

[0091] Reference Figure 3 The memory block MBi may include a first select line, a second select line, multiple word lines WL1 to WL16, a source line SL, multiple bit lines BL1 to BLn, and multiple strings ST. For example, the first select line may be the source select line SSL. Hereinafter, it is assumed that the first select line is the source select line SSL. For example, the second select line may be the drain select line DSL. Hereinafter, it is assumed that the second select line is the drain select line DSL. The multiple word lines WL1 to WL16 may be arranged parallel to each other between the source select line SSL and the drain select line DSL. Figure 3 The number of word lines WL1 to WL16 shown is merely illustrative and may be different in another embodiment.

[0092] The source line SL can be connected to multiple string STs. Multiple bit lines BL1 to BLn can be connected to string STs individually. Additionally, multiple string STs can be connected to bit lines BL1 to BLn and the source line SL. String STs can be configured identically to each other; therefore, a string ST connected to the first bit line BL1 will be described as an example.

[0093] A string ST may include multiple memory cells MC1 to MC16, at least one first selection transistor, and at least one second selection transistor. The multiple memory cells MC1 to MC16 may be connected in series between the source selection transistor SST and the drain selection transistor DST. The gate electrodes of the memory cells MC1 to MC16 may be connected to multiple word lines WL1 to WL16, respectively. Therefore, the number of memory cells MC1 to MC16 included in a string ST may be equal to the number of word lines WL1 to WL16.

[0094] For example, one or more of the memory cells MC1 to MC16 may be configured as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, and a four-level cell (QLC) storing 4 bits of data. However, this disclosure is not limited thereto, and the memory cells may store 5 bits or more of data.

[0095] A group of memory cells connected to the same word line, including memory cells in different string STs, can be referred to as a physical page PG. Therefore, a memory block MBi may include a number of physical pages PG corresponding to the number of word lines WL1 to WL16. Hereinafter, it is assumed that the memory cell (e.g., MC3) in the physical page PG is the selected memory cell.

[0096] For example, the first selection transistor can be a source selection transistor (SST). Hereinafter, we assume the first selection transistor is a source selection transistor (SST).

[0097] The source select transistor SST may have a first electrode connected to the source line SL and a second electrode connected to a first memory cell MC1 among a plurality of memory cells MC1 to MC16. The gate electrode of the source select transistor SST may be connected to the source select line SSL.

[0098] For example, the second selection transistor can be a drain-select transistor (DST). Hereinafter, we assume the second selection transistor is a drain-select transistor (DST).

[0099] The drain-select transistor (DST) may have a first electrode connected to the sixteenth memory cell MC16 (among a plurality of memory cells MC1 to MC16) and a second electrode connected to the first bit line BL1. The gate electrode of the drain-select transistor (DST) may be connected to the drain-select line DSL.

[0100] Programming allows voltage to be applied to some of the multiple bit lines BL1 to BLn. Programming disables voltage from being applied to the other bit lines BL1 to BLn. Parasitic capacitors can be generated between the bit lines. As the voltage difference between the multiple bit lines BL1 to BLn increases, the voltage charged into the parasitic capacitors can increase. As the voltage charged into the parasitic capacitors increases, the peak current flowing through the bit lines can increase.

[0101] For example, a programming enable voltage can be applied to the first bit line BL1 and a programming disable voltage can be applied to the second bit line BL2. A first parasitic capacitor can be generated between the first bit line BL1 and the second bit line BL2, which are respectively subjected to voltages (e.g., programming enable voltages and programming disable voltages with different voltage levels).

[0102] In one example, a programming enable voltage or a programming disable voltage may be applied to each of the first bit line BL1 and the second bit line BL2. A second parasitic capacitor may be generated between the first bit line BL1 and the second bit line BL2 to which voltages (e.g., programming enable voltages or programming disable voltages of the same voltage level) are applied. In one embodiment, the voltage level of the voltage charged into the first parasitic capacitor may be different from (e.g., higher than) the voltage level of the voltage charged into the second parasitic capacitor.

[0103] Figure 4 This is a diagram that conceptually illustrates an implementation of the programming operation of the memory device 100.

[0104] Reference Figure 1 , Figure 2 and Figure 4The memory device 100 is capable of performing programming operations. The programming operations may include multiple programming cycles PL1 to PLm. Each programming cycle may include a programming voltage application step PGM Step and a verification step VFY Step. Whenever a programming operation is performed, the programming voltage application step PGM Step and the verification step VFY Step (included in each programming cycle) may be executed. The degree to which the programming operation is performed can be checked by the extent to which the programming cycle is repeated.

[0105] A Programming Voltage Application Step (PGM Step) can be a step of applying a programming voltage to a selected word line that is commonly connected to the selected memory cell. The PGM Step included in various programming cycles may include a Precharge period, a Program period, and a Discharge period. In this specification, "Programming Voltage Application Step" and "Programming Voltage Application Operation" may have the same meaning.

[0106] During the precharge phase, operations can be performed to set the bit line voltages to the voltages applied to multiple bit lines. This operation of setting the bit line voltages may be referred to as a "bit line setting operation." In implementations, the bit line voltages can be either programmable enable voltages or programmable disable voltages. For example, a programmable enable voltage can be a ground voltage. A programmable disable voltage can be a power supply voltage.

[0107] The programming period can be a time period during which selected memory cells are programmed to have a threshold voltage corresponding to the programming state. For example, control logic 130 can control voltage generator 121 and row decoder 122 to apply a programming voltage to the selected word line. Alternatively, control logic 130 can control voltage generator 121 and row decoder 122 to apply a programming voltage (e.g., a level having a level lower than the programming voltage) to unselected word lines.

[0108] When a programming pulse is applied to a selected word line during the programming phase, the threshold voltage of the memory cell connected to the bit line to which a programming enable voltage is applied can be increased. Conversely, the threshold voltage of the memory cell connected to the bit line to which a programming disable voltage is applied can be maintained during the programming phase.

[0109] The discharge period can be the time during which the voltage applied to the word line and select line is discharged. Control logic 130 controls voltage generator 121 and line decoder 122 to apply a ground voltage corresponding to 0V to the word line and select line. The voltage applied to the word line and select line can be discharged.

[0110] The verification step VFY Step can be an operation to determine whether the threshold voltage of a memory cell has reached the threshold voltage corresponding to the target state. Alternatively, the verification step VFY Step can be an operation to determine whether a selected memory cell has been programmed by applying a verification voltage. In one implementation, "verification step" and "verification operation" can have the same meaning.

[0111] In the verification step VFY Step, a verification voltage for verifying the target state can be applied to the selected word line. Verification step VFY Step can pass when the threshold voltage of a predetermined number of memory cells (within the memory cells with the same target state) is higher than the verification voltage. Verification step VFY Step may fail when the individual threshold voltages of a predetermined number of memory cells (within the memory cells with the same target state) are equal to or lower than the verification voltage.

[0112] The programming operation is considered successful when all target states pass verification. It is considered a failure if the programming operation fails within the predetermined baseline time. It is also considered a failure if the programming operation fails to complete even after executing the programming loop corresponding to the predetermined maximum loop count.

[0113] Figure 5 It is a waveform diagram showing the programming operation of the memory device according to the embodiment.

[0114] Reference Figure 1 , Figure 2 , Figure 4 and Figure 5 The programming voltage application step (PGM Step) can be performed from T0 to T8, and the verification step (VFY Step) can be performed from T8 to T11. In one embodiment, the verification step (VFY Step) can be performed before T0.

[0115] The Programming Voltage Application Step (PGM Step) may include a Precharge period, a Program period, and a Discharge period. For example, the Precharge period may be from T0 to T3, the Program period may be from T3 to T7, and the Discharge period may be from T7 to T8.

[0116] At time T0, control logic 130 controls voltage generator 121 and line decoder 122 to apply precharge voltage Vpre to the selected word line Selected WL. Therefore, the voltage level of the selected word line Selected WL can be increased.

[0117] Additionally, at time T0, control logic 130 can control voltage generator 121 and line decoder 122 to apply pre-charge voltage Vpre to the unselected word line Unselected WL. Therefore, the voltage level of the unselected word line Unselected WL can be increased.

[0118] Additionally, at time T0, the page buffer controller 101 can provide the page buffer 102 with a pulse signal having a voltage level of the reference voltage VREF as a page buffer sensing signal PBSENSE. When the pulse signal with a voltage level of the reference voltage VREF is provided to the page buffer 102, it prevents the peak current flowing through the bit lines from increasing or decreasing rapidly, thereby reducing the time required to complete the programming operation. An example will be provided below. Figure 9 describe.

[0119] The reference voltage VREF can correspond to the threshold voltage of the page buffer sensing transistor based on the internal temperature, skew, or other parameter of the memory device 100.

[0120] In one implementation, the reference voltage VREF can be the sum of the bit line voltage and the threshold voltage of the page buffer sensing transistor. For example, when the bit line voltage is 0.35V and the threshold voltage of the page buffer sensing transistor is 0.8V, the reference voltage VREF can be 1.15V. In other implementations, these voltages may be different.

[0121] The length of the time period from time T0 to time T1 (e.g., the length of the time period for providing a pulse signal with a voltage level of reference voltage VREF) can be varied according to the characteristics of the page buffer sensing transistor in page buffer 102.

[0122] At time T1, control logic 130 controls voltage generator 121 and line decoder 122 to provide ground voltage GND to the selected word line (Selected WL) and the unselected word line (Unselected WL). The voltage levels of the selected word line (Selected WL) and the unselected word line (Unselected WL) can be reduced.

[0123] At time T1, the page buffer controller 101 may output a ramp signal as the page buffer sensing signal PBSENSE. The slope of the ramp signal may have various values. As the slope of the ramp signal becomes steeper (e.g., as the slope of the ramp signal increases), the time for the bit line to be precharged (or the time for the bit line to be set) may be reduced.

[0124] In the implementation, when the slope of the ramp signal is relatively small, the page buffer sensing signal PBSENSE (as the ramp signal) may not reach the voltage level of the turn-on voltage Vpbs, which is the target voltage, at time T2. Figure 5 As shown, the page buffer controller 101 can provide a pulse signal with a voltage level of the on-state voltage Vpbs to the page buffer 102 as a page buffer sensing signal PBSENSE, so that the page buffer sensing signal PBSENSE reaches the voltage level of the on-state voltage Vpbs. When a pulse signal is provided so that the page buffer sensing signal PBSENSE reaches the voltage level of the on-state voltage Vpbs, this can be considered a fully charged state.

[0125] In this implementation, when the slope of the ramp signal is relatively large (e.g., higher than a predetermined value), the page buffer sensing signal PBSENSE, which is the ramp signal, can reach the voltage level of the on-state voltage Vpbs at time T2. The page buffer controller 101 can provide the page buffer 102 with the page buffer sensing signal PBSENSE that maintains the voltage level of the on-state voltage Vpbs.

[0126] The turn-on voltage Vpbs is a high voltage, and can be high enough to turn on the page buffer sensing transistor in page buffer 102. Based on the turn-on voltage Vpbs, insufficient pre-charge of the bit lines is prevented, thereby improving programming reliability and increasing the speed of programming operations.

[0127] At time T3, page buffer 102 may provide a programming enable voltage or programming disable voltage to the bit line in response to a page buffer sensing signal PBSENSE with a voltage level having an on-state voltage Vpbs.

[0128] During the periods providing the ramp signal and the pulse signal providing a voltage level with a conduction voltage of Vpbs, ground voltage can be provided to the Selected word line (WL) and the Unselected word line (WL). An example will be provided. Figure 5 Description. The time period for providing the ramp signal can be from time T1 to time T2, and the time period for providing the pulse signal with a voltage level of conduction voltage Vpbs can be from time T2 to time T3. From time T1 to time T3, the ground voltage can be provided to the selected word line (Selected WL) and the unselected word line (Unselected WL).

[0129] At time T3, the precharge period can end, and the page buffer sensing signal PBSENSE (with a voltage level of ground voltage GND) can be provided to the page buffer 102.

[0130] At time T4, control logic 130 controls voltage generator 121 and line decoder 122 to supply voltage Vpass to word lines Selected WL and Unselected WL.

[0131] At time T5, control logic 130 controls voltage generator 121 and line decoder 122 to provide programming voltage Vpgm to the selected word line Selected WL. The voltage level of the selected word line Selected WL can be increased.

[0132] At time T6, the voltage level of the selected word line Selected WL can be increased from the voltage level of the pass voltage Vpass to the voltage level of the programming voltage Vpgm.

[0133] During the time period from time T4 to time T7, the voltage of the Unselected WL line can be maintained at the pass voltage Vpass.

[0134] At time T7, the programming period can end, and control logic 130 can control voltage generator 121 to discharge word lines Selected WL and Unselected WL. For example, control logic 130 can control voltage generator 121 to apply ground voltage GND to word lines Selected WL and Unselected WL.

[0135] At time T8, the discharge period can end.

[0136] At time T9, control logic 130 can control voltage generator 121 and line decoder 122 to apply verification voltage Vvfy to the selected word line (WL). Additionally, control logic 130 can control voltage generator 121 and line decoder 122 to apply verification pass voltage Vpass to the unselected word line (WL).

[0137] The verification voltage Vvfy can be a voltage used to determine the programming state of each selected memory cell. The verification pass voltage Vpass can be a voltage that allows a memory cell connected to the Unselected word line (Unselected WL) to become a conducting cell, so that the bit line voltage is not affected by the memory cells connected to the Unselected word line (Unselected WL).

[0138] At time T10, control logic 130 can control voltage generator 121 to discharge word lines Selected WL and Unselected WL.

[0139] At time T11, the verification step VFY can be completed.

[0140] Figure 6 This is a diagram illustrating the programming voltage and verification voltage according to an implementation method. Figure 6 In the implementation shown, it is assumed that the selected memory cell is a TLC.

[0141] Reference Figure 5 and Figure 6 Programming operations can include multiple programming loops. The value of each programming loop can be a loop counter. For example, the value of the first programming loop can be 1, the value of the second programming loop can be 2, and the value of the third programming loop can be 3.

[0142] Each programming cycle may include a programming voltage application step (PGM Step) and a verification step (VFY Step). For example, a first programming cycle may include a first programming voltage application step applying a first programming voltage Vpgm1 and a first verification step sequentially applying a first verification voltage Vvfy1 to a third verification voltage Vvfy3. For example, a second programming cycle may include a second programming voltage application step applying a second programming voltage Vpgm2 and a second verification step sequentially applying a first verification voltage Vvfy1 to a third verification voltage Vvfy3. In one embodiment, a (Max-1)th programming cycle may include a (L-1)th programming voltage application step applying a (L-1)th programming voltage VpgmL-1 and a (L-1)th verification step sequentially applying a fifth verification voltage Vvfy5 to a seventh verification voltage Vvfy7, where L is a natural number.

[0143] The programming voltage Vpgm can be provided using the Incremental Step Pulse Programming (ISPP) method. Each time a programming cycle is repeated, the programming voltage Vpgm can be increased by a predetermined step programming voltage ΔV. For example, the programming voltage Vpgm can be increased sequentially from the first programming voltage Vpgm1 to the Lth programming voltage VpgmL.

[0144] For example, the number of verification voltages can be determined based on the number of multiple programming states. An example will be provided below. Figure 6 Description. When the memory cell is TLC, the number of programming states can be 7, and the number of verification voltages Vvfy1 to Vvfy7 can be 7. However, in another embodiment, the number of verification voltages and the number of programming states can be different.

[0145] Programming voltages Vpgm1 to VpgmL and verification voltages Vvfy1 to Vvfy7 can be repeated until the maximum programming cycle MAX is executed. For example, which programming states to verify in the verification step of a particular programming cycle (e.g., which verification voltages to apply) can be predetermined before product release based on experiments, designs, etc., considering the number of erase and programming operations to be performed.

[0146] As the number of erase and program operations increases, the speed at which the selected memory cell is programmed can increase. Therefore, the verification voltage to be applied in a particular programming cycle can be determined based on the characteristics of the memory cell, taking into account the increase in the number of erase and program operations.

[0147] The example will refer to Figure 6 Description. From the first programming cycle to the third programming cycle, verification of the first to third programming states can be performed for each programming cycle. For example, from the first programming cycle to the third programming cycle, a first verification voltage Vvfy1 to a third verification voltage Vvfy3 can be applied to the selected word line for each programming cycle.

[0148] Figure 7 This diagram illustrates the erase state and multiple programming states according to an embodiment. The target state (among multiple programming and erase states) to which the memory cell is programmed can be determined based on the data stored in the memory cell. When the memory cell is an SLC, the target state can be erase state E or the first programming state PV1. When the memory cell is an MLC, the target state can be erase state E or one of the first programming states PV1 to the third programming states PV3. When the memory cell is a TLC, the target state can be erase state E or one of the first programming states PV1 to the seventh programming states PV7. In other embodiments, these target states may be different.

[0149] In one implementation, the number of programming states can be determined based on the number of bits of data stored in the memory cell. When the memory cell is an SLC, the memory cell can be in an erase state E or a first programming state PV1. Therefore, the number of programming states can be 1. When the memory cell is an MLC, the memory cell can be in an erase state E or any of the first programming states PV1 to the third programming states PV3. Therefore, the number of programming states can be 3. When the memory cell is a TLC, the number of programming states can be 7. For example, when the number of bits is a (a is a natural number), the number of multiple programming states can be p, where p = 2. a -1.

[0150] Reference Figure 7 The memory cell may have a threshold voltage belonging to a threshold voltage distribution corresponding to any of the erase state E or programming states PV1 to PV7. For example, the memory cell may be in erase state E before performing a programming operation. In an embodiment, the first programming state PV1 may be the state of the memory cell after performing an erase operation.

[0151] Each time a programming cycle repeats, the programming voltage Vpgm can be increased by a predetermined step programming voltage ΔV. The threshold voltage of the memory cell can be increased according to the programming voltage Vpgm, and the threshold voltage distribution of the memory cell can change each time a programming operation is performed. For example, after performing an erase operation, the threshold voltage distribution of the memory cell can change (or shift) in the direction of threshold voltage increase.

[0152] Whenever a programming operation is performed (or whenever the programming loop repeats), the verification steps for the corresponding first programming state PV1 to seventh programming state PV7 can be executed sequentially from the first programming state PV1 to the seventh programming state PV7.

[0153] Verification of the first programming state PV1 may include determining whether the threshold voltage of the selected memory cell has reached the threshold voltage corresponding to the first programming state PV1 (e.g., the first verification voltage Vvfy1). Memory cells among those to be programmed into the first programming state PV1 that have a threshold voltage higher than the first verification voltage Vvfy1 may be in a cutoff state (or cutoff cells). Memory cells among those to be programmed into the first programming state PV1 that have a threshold voltage lower than or equal to the first verification voltage Vvfy1 may be in a conducting state (or conducting cells).

[0154] Verification of each of the second programming states PV2 to the seventh programming states PV7 may include determining whether the threshold voltage of the selected memory cell has reached the threshold voltage corresponding to each of the second programming states PV2 to the seventh programming states PV7 (e.g., each of the second verification voltage Vvfy2 to the seventh verification voltage Vvfy7).

[0155] Figure 8 This is a graph showing an example of the peak current flowing through the bit line according to the degree of execution of the programmed operation.

[0156] Reference Figure 3 and Figure 8 As shown above Figure 3 As described, when bit line voltages are applied to multiple bit lines BL1 to BLn during programming operations, parasitic capacitances can be generated between the multiple bit lines BL1 to BLn. Peak current can be generated in each of the multiple bit lines BL1 to BLn through these parasitic capacitances.

[0157] The magnitude of the peak current can vary depending on the extent to which the programming operation is performed. For example, the extent to which the programming operation is performed can be divided into an initial programming period (PGM Initial Period), a middle programming period (PGM Middle Period), and a final programming period (PGM Last Period). In another embodiment, the programming operation can be divided into different (or different numbers) periods. For example, the extent to which the programming operation is performed can be divided into more detailed periods than just the initial programming period (PGM Initial Period), the middle programming period (PGM Middle Period), and the final programming period (PGM Last Period).

[0158] For example, the peak current can be increased from the initial programming period (PGM Initial Period) to the middle programming period (PGM Middle Period). The peak current can be decreased from the middle programming period (PGM Middle Period) to the last programming period (PGM Last Period).

[0159] In this implementation, the degree of execution of the programming operation can be the degree to which the loop count of the programming loop is repeated. For example, the programming initial period (PGM Initial Period) can be the period corresponding to when the loop count of the programming loop is less than a first reference count; the programming middle period (PGM Middle Period) can be the period corresponding to when the loop count of the programming loop is greater than or equal to the first reference count and less than a second reference count; and the programming last period (PGM Last Period) can be the period corresponding to when the loop count of the programming loop is greater than or equal to the second reference count. The second reference count can be greater than the first reference count.

[0160] The reason why the peak current changes depending on the degree of execution of the programming operation is that the number of bit lines (of the multiple bit lines BL1 to BLn) with the programming enable voltage applied is different from the number of bit lines (of the multiple bit lines BL1 to BLn) with the programming disable voltage applied.

[0161] For example, assuming the selected memory cell is TLC, the number of target states is 8 (e.g., erase state E and first programming states PV1 through seventh programming states PV7). During the PGM Initial Period, the probability that a programming enable voltage will be applied to multiple bit lines BL1 through BLn is higher than the probability that a programming disable voltage will be applied to multiple bit lines BL1 through BLn. For example, when the programming operation begins, the selected memory cell can be programmed with a 7 / 8 probability. Therefore, the programming enable voltage can be applied to multiple bit lines BL1 through BLn with a 7 / 8 probability, and the programming disable voltage can be applied to multiple bit lines BL1 through BLn with a 1 / 8 probability.

[0162] The number of bit lines BL1 to BLn to which a programmable allowable voltage is applied can be relatively large (e.g., higher than a predetermined value). The voltage difference between the multiple bit lines BL1 to BLn can be the difference between the programmable allowable voltages applied between most (e.g., a predetermined number) of the multiple bit lines BL1 to BLn, and the difference between the programmable allowable voltages can be close to a predetermined number (e.g., 0). Therefore, the parasitic capacitance generated between the multiple bit lines BL1 to BLn can be eliminated or very low (e.g., within a predetermined tolerance), and the peak current can be relatively low (e.g., below a predetermined level).

[0163] During the PGM Middle Period, there may be a greater number of memory cells programmed to the target state compared to the memory cells in the PGM Initial Period. Since a programming disable voltage is applied to the bit lines connected to the programmed memory cells, the difference between the probability that a programming enable voltage will be applied to multiple bit lines BL1 to BLn and the probability that a programming disable voltage will be applied to multiple bit lines BL1 to BLn can be reduced by one or more steps. The number of bit lines BL1 to BLn with programming enable voltages applied can be almost equal to the number of bit lines BL1 to BLn with programming disable voltages applied (e.g., within a predetermined tolerance). Therefore, parasitic capacitors can be generated based on the difference between the programming enable voltage and the programming disable voltage applied between multiple bit lines BL1 to BLn, and the peak current can be relatively high (e.g., higher than a predetermined value).

[0164] During the PGM Last Period, there may be a greater number of memory cells programmed to the target state compared to the memory cells during the PGM Middle Period. The probability that a programming enable voltage will be applied to multiple bit lines BL1 to BLn is lower than the probability that a programming disable voltage will be applied to multiple bit lines BL1 to BLn. The number of bit lines BL1 to BLn with programming enable voltages applied is less than the number of bit lines BL1 to BLn with programming disable voltages applied. The voltage difference between multiple bit lines BL1 to BLn can be the difference between programming disable voltages applied to most (e.g., a predetermined number) of the multiple bit lines BL1 to BLn, and the difference between programming disable voltages can be close to a predetermined value (e.g., 0) within a given tolerance. Therefore, the parasitic capacitance between multiple bit lines BL1 to BLn can be limited to a predetermined tolerance, and the peak current (PeakCurrent) can be relatively low (e.g., below a predetermined value).

[0165] In one implementation, the peak current can be a current that prevents the selected memory cell from being programmed to a target voltage. Additionally, since the peak current flowing through a bit line is a current whose introduced charge increases rapidly over time (e.g., at a rate higher than a predetermined rate), the peak current can be a current that damages the bit line.

[0166] When the peak current decreases, the pre-charge time of the bit lines increases, which can degrade the performance of the memory device as the programming operation completion time increases. An implementation of a page buffer controller for reducing peak current while preventing or reducing the increase in programming operation completion time is described below.

[0167] Figure 9 This is a circuit diagram illustrating a page buffer controller and a page buffer according to an embodiment. For example, Figure 9 The page buffer 910 shown can be Figure 1 The page buffer 102 is shown. In one embodiment, Figure 9 The page buffer 910 shown can be Figure 2 The example shown represents one of the page buffers from the first page buffer PB1 to the nth page buffer PBn. For ease of description, assume... Figure 9 The page buffer 910 shown is Figure 2 The first page buffer PB1 is shown, but refer to... Figure 9 The described implementation can be applied to the second page buffer PB2 to the nth page buffer PBn.

[0168] Reference Figure 2 , Figure 5 and Figure 9 Page buffer 910 can operate in response to page buffer control signals PBSIGNALS from control logic 130. For example, page buffer control signals PBSIGNALS may include a page buffer sensing signal PB_SENSE, a current sensing signal SA_CSOC, a sense amplifier precharge signal SA_PRECH_N, a sense node precharge signal PRECHSO_N, a sense amplifier sensing signal SA_SENSE, and a sense amplifier discharge signal SA_DISCH. In an embodiment, the page buffer sensing signal PB_SENSE and the current sensing signal SA_CSOC may be signals provided by page buffer controller 920.

[0169] In this implementation, the page buffer 910 may provide a bit line voltage to the first bit line BL1 in response to the page buffer sensing signal PB_SENSE. The bit line voltage may be a ground voltage corresponding to the programming enable voltage or a power supply voltage VCORE corresponding to the programming disable voltage.

[0170] Page buffer 910 can be connected to the memory cell via the first bit line BL1, and performs a bit line precharge operation by charging the first bit line BL1 with charge supplied from the power supply voltage VCORE through the first NMOS transistors N1 to N5 and the first PMOS transistors P1 to P3. Additionally, page buffer 910 can discharge the charge charged into the first bit line BL1 to ground voltage through the first NMOS transistor N1, the fourth NMOS transistor N4, and the fifth NMOS transistor N5.

[0171] The first NMOS transistor N1 can be connected between the first bit line BL1 and the common node CSO. The first NMOS transistor N1 can be controlled by the page buffer sensing signal PB_SENSE. The page buffer sensing signal PB_SENSE can be applied to the gate electrode of the first NMOS transistor N1. The first NMOS transistor N1 can be a page buffer sensing transistor.

[0172] The second NMOS transistor N2 can be connected between the common node CSO and the sense amplifier node SAN. The second NMOS transistor N2 can be controlled by the current sensing signal SA_CSOC. The current sensing signal SA_CSOC can be applied to the gate electrode of the second NMOS transistor N2.

[0173] The third NMOS transistor N3 can be connected between the sensing node SO and the common node CSO. The third NMOS transistor N3 can be controlled by the sensing signal SA_SENSE from the sensing amplifier. The sensing signal SA_SENSE from the sensing amplifier can be applied to the gate electrode of the third NMOS transistor N3.

[0174] The fourth NMOS transistor N4 can be controlled by the sense amplifier discharge signal SA_DISCH. The sense amplifier discharge signal SA_DISCH can be applied to the gate electrode of the fourth NMOS transistor N4.

[0175] The fifth NMOS transistor N5 can be controlled by the node QS voltage of the sense latch circuit LATS. The node QS voltage of the sense latch circuit LATS can be applied to the gate electrode of the fifth NMOS transistor N5. The fourth NMOS transistor N4 and the fifth NMOS transistor N5 can be connected in series between the common node CSO and the ground voltage.

[0176] The first PMOS transistor P1 can be connected between the power supply voltage VCORE and the sense amplifier node SAN. The first PMOS transistor P1 can be controlled by the node QS voltage of the sense latch circuit LATS. The node QS voltage of the sense latch circuit LATS can be applied to the gate electrode of the first PMOS transistor P1.

[0177] The second PMOS transistor P2 can be connected between the sense amplifier node SAN and the sense node SO. The second PMOS transistor P2 can be controlled by the sense amplifier precharge signal SA_PRECH_N. The sense amplifier precharge signal SA_PRECH_N can be applied to the gate electrode of the second PMOS transistor P2.

[0178] The third PMOS transistor P3 can be connected between the power supply voltage VCORE and the sensing node SO. The third PMOS transistor P3 can be controlled by the sensing node precharge signal PRECHSO_N. The sensing node precharge signal PRECHSO_N can be applied to the gate electrode of the third PMOS transistor P3.

[0179] The sense latch circuit LATS may include a latch configured with two inverters (connected to node QS) and a reset transistor and a set transistor for controlling the voltage of node QS.

[0180] For example, Figure 9 The page buffer controller 920 shown can be Figure 1 and Figure 2 The page buffer controller 920 is shown. According to one embodiment, the page buffer controller 920 may include a first signal provider 921, a second signal provider 922, and a third signal provider 923.

[0181] The first signal provider 921 can provide a pulse signal as a page buffer sensing signal PB_SENSE. This pulse signal can be generated by the voltage generator 121 during a first period in the pre-charge period and can be used as a reference voltage VREF. The voltage level of the reference voltage VREF can be greater than the voltage level of ground (e.g., 0V). In one embodiment, the reference voltage VREF can correspond to or be based on the sum of the bit line voltage and the threshold voltage of the first NMOS transistor N1. However, in another embodiment, the reference voltage VREF can have different values.

[0182] In one embodiment, the first signal provider 921 may include a first voltage output circuit AMP1 through a fifth voltage output circuit AMP5 and a current mirror circuit. The first voltage output circuit AMP1 outputs a reference voltage VREF generated by the voltage generator 121 to the current mirror circuit. The reference voltage VREF may be applied to a first input terminal (e.g., an inverting terminal) of the first voltage output circuit AMP1. A second input terminal (e.g., a non-inverting terminal) of the first voltage output circuit AMP1 may be connected to the current mirror circuit. For example, the first voltage output circuit AMP1 may be a buffer amplifier.

[0183] The current mirror circuit can generate a current sensing signal SA_CSOC based on the reference voltage VREF and the mirror voltage VMV, and can provide the current sensing signal SA_CSOC to the second voltage output circuit AMP2. In addition, the current mirror circuit can generate a page buffer sensing signal PB_SENSE based on the reference voltage VREF and the mirror voltage VMV, and can provide the page buffer sensing signal PB_SENSE to the fourth voltage output circuit AMP4.

[0184] In one embodiment, the current mirror circuit may include fourth PMOS transistors P4 through P7, sixth NMOS transistor N6 and seventh NMOS transistor N7, and first resistors R1 through fourth resistors R4. Fourth PMOS transistor P4 and fifth PMOS transistor P5 may be connected in series between the mirror voltage VMV and the first resistor R1. The gate electrode of fourth PMOS transistor P4 may be connected to one end of the first resistor R1. The gate electrode of fifth PMOS transistor P5 may be connected to the other end of the first resistor R1. The first resistor R1 may be connected between fifth PMOS transistor P5 and sixth NMOS transistor N6.

[0185] The sixth NMOS transistor N6 can be connected between the first resistor R1 and the second resistor R2. The output terminal of the first voltage output circuit AMP1 can be connected to the gate electrode of the sixth NMOS transistor N6. One electrode of the sixth NMOS transistor N6 can be connected to one end of the second resistor R2 and the second input terminal of the first voltage output circuit AMP1. The second resistor R2 can be connected between the sixth NMOS transistor N6 and ground voltage.

[0186] The sixth PMOS transistor P6 and the seventh PMOS transistor P7 can be connected in series between the mirror voltage VMV and the third resistor R3. The gate electrode of the sixth PMOS transistor P6 can be connected to one end of the first resistor R1. The gate electrode of the seventh PMOS transistor P7 can be connected to the other end of the first resistor R1. The third resistor R3 can be connected between the seventh PMOS transistor P7 and the seventh NMOS transistor N7.

[0187] A current sensing signal SA_CSOC can be generated at the node where one electrode of the seventh PMOS transistor P7 and one end of the third resistor R3 are connected.

[0188] The seventh NMOS transistor N7 can be connected between the third resistor R3 and the fourth resistor R4. The gate electrode of the seventh NMOS transistor N7 can be connected to the other end of the third resistor R3.

[0189] A page buffer sensing signal PB_SENSE can be generated at the node where one electrode of the seventh NMOS transistor N7 and the other end of the third resistor R3 are connected. A fourth resistor R4 can be connected between the seventh NMOS transistor N7 and ground. For example, each of the second voltage output circuits AMP2 to the fifth voltage output circuits AMP5 can be a buffer amplifier.

[0190] The second voltage output circuit AMP2 can output the current sensing signal SA_CSOC generated by the current mirror circuit.

[0191] The third voltage output circuit AMP3 can output the current sensing signal SA_CSOC output by the second voltage output circuit AMP2 to the gate electrode of the second NMOS transistor N2 of the page buffer 910.

[0192] exist Figure 9 In the illustrated embodiment, the first signal provider 921 may include, for example, a second voltage output circuit AMP2 and a third voltage output circuit AMP3, but this disclosure is not limited thereto. For example, Figure 9 The second voltage output circuit AMP2 and the third voltage output circuit AMP3 shown can be implemented as a buffer amplifier. In this case, the first signal provider 921 may include only one of the second voltage output circuit AMP2 and the third voltage output circuit AMP3. In another example, the first signal provider 921 may include three or more buffer amplifiers that output the current sensing signal SA_CSOC.

[0193] The fourth voltage output circuit AMP4 can output the page buffer sensing signal PB_SENSE generated by the current mirror circuit.

[0194] The fifth voltage output circuit AMP5 can output the page buffer sensing signal PB_SENSE output by the fourth voltage output circuit AMP4 to the gate electrode of the first NMOS transistor N1 included in the page buffer 910.

[0195] exist Figure 9 In the illustrated embodiment, the first signal provider 921 may include a fourth voltage output circuit AMP4 and a fifth voltage output circuit AMP5, but this disclosure is not limited thereto. For example, Figure 9 The fourth voltage output circuit AMP4 and the fifth voltage output circuit AMP5 shown can be implemented as a buffer amplifier. For example, the first signal provider 921 may include only one of the fourth voltage output circuit AMP4 and the fifth voltage output circuit AMP5. In another example, the first signal provider 921 may include three or more buffer amplifiers that output the page buffer sensing signal PB_SENSE.

[0196] The second signal provider 922 can output a page buffer sensing signal PB_SENSE that increases based on an increment determined according to the degree of execution of the programming operation after the first time period. For example, the second signal provider 922 can provide a ramp signal as the page buffer sensing signal PB_SENSE, wherein the ramp signal increases from a first voltage level to a second voltage level. For example, the slope of the ramp signal can be determined based on the cycle count of multiple programming cycles (among multiple predetermined slopes) after the first time period.

[0197] In one example, the second signal provider 922 can provide a step signal as a page buffer sensing signal PB_SENSE, wherein the step signal increases from a first voltage level to a second voltage level based on one or more steps. For example, the step signal can be increased based on a step voltage determined based on a cycle count of multiple programming cycles among a plurality of predetermined step voltages.

[0198] The first voltage level can be the voltage level of a reference voltage VREF. The voltage level of the reference voltage VREF can be greater than the voltage level of ground (e.g., 0V). For example, the reference voltage VREF can correspond to or be based on the sum of the bit line voltage and the threshold voltage of the first NMOS transistor N1. In another embodiment, the reference voltage VREF can have different values.

[0199] In an implementation, the second signal provider 922 may include multiple switches SW1 to SW3, an eighth PMOS transistor P8 to a thirteenth PMOS transistor P13, a capacitor CAP, an eighth NMOS transistor M8, and a sixth voltage output circuit AMP6.

[0200] A page buffer pump voltage PBPMP can be provided to multiple switches SW1 to SW3. The page buffer pump voltage PBPMP can be generated by voltage generator 121. The multiple switches SW1 to SW3 can be connected between the page buffer pump voltage PBPMP and the eighth PMOS transistor P8 to the thirteenth PMOS transistor P13. When the multiple switches SW1 to SW3 are turned on, the page buffer pump voltage PBPMP can be provided to the eighth PMOS transistor P8 to the thirteenth PMOS transistor P13.

[0201] In this implementation, the magnitude of the bias current Ibias can be varied according to the number of active switches among the multiple switches SW1 to SW3. For example, the magnitude of the bias current Ibias can be varied according to the number of active switches among the multiple switches SW1 to SW3, and the slope of the ramp signal can also be varied. For example, as the number of active switches among the multiple switches SW1 to SW3 increases, the slope of the ramp signal can increase.

[0202] like Figure 9 As shown, the number of switches SW1 to SW3 can be 3, but in another embodiment, the number can be different (e.g., the number of switches SW1 to SW3 can be less than or greater than 3). The slope of the ramp signal or the step voltage of the step signal can be adjusted more finely.

[0203] Eighth PMOS transistors P8 through thirteenth PMOS transistors P13 can be connected between multiple switches SW1 through SW3 and a reference voltage VREF. Eighth PMOS transistors P8 through thirteenth PMOS transistors P13 can be grouped and connected to multiple switches SW1 through SW3. Each of the eighth PMOS transistors P8 through thirteenth PMOS transistors P13 can be controlled by voltage control signals Vb1 and Vb2. Voltage control signals Vb1 and Vb2 can be provided by control logic 130, which provides voltage control signals Vb1 and Vb2 based on the cycle count of the programming loop.

[0204] When any one of the eighth PMOS transistors P8 to the thirteenth PMOS transistor P13 is turned on, the bias current Ibias can flow from the page buffer pump voltage PBPMP towards the reference voltage VREF. In an embodiment, the bias current Ibias can be more finely adjusted by the eighth PMOS transistors P8 to the thirteenth PMOS transistor P13.

[0205] The capacitor CAP can be connected between the reference voltage VREF and the ground voltage. The capacitor CAP can be charged according to the bias current Ibias.

[0206] The eighth transistor N8 can be connected between the reference voltage VREF and the ground voltage. The eighth transistor N8 can be controlled by the transistor's on-state voltage TrON.

[0207] The sixth voltage output circuit AMP6 can receive the capacitor voltage charged through capacitor CAP and provide the capacitor voltage as the page buffer sensing signal PB_SENSE. For example, the sixth voltage output circuit AMP6 can be a buffer amplifier.

[0208] The third signal provider 923 can provide a pulse signal with a voltage level of turn-on voltage Vpbs as the page buffer sensing signal PB_SENSE. In an embodiment, the third signal provider 923 may include a fourteenth PMOS transistor P14. The fourteenth PMOS transistor P14 can be controlled by a high-voltage control signal Fully_ON. The high-voltage control signal Fully_ON can be provided by control logic 130. The fourteenth PMOS transistor P14 can be turned on by the high-voltage control signal Fully_ON to provide the page buffer pump voltage PBPMP as the page buffer sensing signal PB_SENSE.

[0209] Page buffer 910 and page buffer controller 920 can be implemented as follows: Figure 9 The circuit shown is different in another embodiment. Page buffer 910 and page buffer controller 920 can be implemented in various ways (e.g., according to design methods).

[0210] Figure 10 This is a circuit diagram illustrating a page buffer controller and a page buffer according to an embodiment. Figure 10 middle, Figure 10 The page buffer 910 shown is the same as described above. Additionally, Figure 10 The page buffer controller 1020 shown can perform operations with Figure 9 The page buffer controller 920 shown has the same function.

[0211] Reference Figure 10 The page buffer controller 1020 may include a first signal provider 1021, a second signal provider 1022, and a third signal provider 1023. The first signal provider 1021 and... Figure 9 The first signal provider 921 shown is the same. Similar to... Figure 9 The second signal provider 922 shown may include multiple switches SW1 to SW3, an eighth PMOS transistor P8 to a thirteenth PMOS transistor P13, a capacitor CAP, and a sixth voltage output circuit AMP6.

[0212] The second signal provider 1022 may include a first variable resistor VR1 and a second variable resistor VR2, replacing... Figure 9 The eighth NMOS transistor N8 is included in the second signal provider 922 shown.

[0213] The first variable resistor VR1 and the second variable resistor VR2 can be connected in series. One end of the first variable resistor VR1 can be connected to the ninth PMOS transistor P9, the eleventh PMOS transistor P11, and the thirteenth PMOS transistor P13. The other end of the first variable resistor VR1 can be connected to one end of the second variable resistor VR2.

[0214] One end of the second variable resistor VR2 can be connected to the other end of the first variable resistor VR1. The voltage generated at the node where one end of the second variable resistor VR2 and the other end of the first variable resistor VR1 are connected can be provided to the sixth voltage output circuit AMP6.

[0215] The third signal provider 1023 can correspond to Figure 9 The third signal provider 923 is shown.

[0216] The page buffer controller 1020 can be implemented as follows: Figure 10 The circuit shown may be implemented in a different manner in another embodiment. The page buffer controller 1020 may be implemented in various ways (e.g., depending on the design method).

[0217] Figure 11 This is a circuit diagram showing a page buffer controller and a page buffer according to an embodiment. (Refer to...) Figure 11 , Figure 11 The page buffer 910 shown is the same as that described above. Figure 11 The page buffer controller 1120 shown can perform operations with Figure 9 The page buffer controller 920 shown is or Figure 10 The page buffer controller 1020 shown has the same function.

[0218] The page buffer controller 1120 may include a first signal provider 1121, a second signal provider 1122, and a third signal provider 1123. The first signal provider 1121 and... Figure 9 The first signal provider 921 shown or Figure 10 The first signal provider 1021 shown is the same.

[0219] The second signal provider 1122 may include a fifteenth PMOS transistor P15 and a sixteenth PMOS transistor P16, as well as a current source CS. The fifteenth PMOS transistor P15 may be connected between the page buffer pump voltage PBPMP and the current source CS. The gate electrode of the fifteenth PMOS transistor P15 may be connected to the first electrode of the fifteenth PMOS transistor P15 and the current source CS. The current source CS provides current flowing from the page buffer pump voltage PBPMP toward ground.

[0220] The sixteenth PMOS transistor P16 can be connected between the page buffer pump voltage PBPMP and the first NMOS transistor N1. The gate electrode of the sixteenth PMOS transistor P16 can be connected to the current source CS. The sixteenth PMOS transistor P16 can supply the current generated by the current source CS to the gate electrode of the first NMOS transistor N1.

[0221] The third signal provider 1123 can be connected with Figure 9 The third signal provider 923 shown Figure 10 The third signal provider 1023 shown is the same.

[0222] Page buffer controller 1120 can be implemented as follows: Figure 11 The circuit shown can be implemented in a different manner in another embodiment. The page buffer controller 1120 can be implemented in various ways (e.g., depending on the design method).

[0223] Figure 12 This is a diagram illustrating an implementation of a page buffer sensing signal provided during the initial or final programming period.

[0224] Reference Figure 12 , Figure 12 The precharge period shown can be a period in which the precharge operation is performed during either the PGM Initial Period or the PGM Last Period. In an embodiment, the PGM Initial Period can be a period corresponding to the case where the cycle count of the current programming operation is equal to or less than a first reference count. The PGM Last Period can be a period corresponding to the case where the cycle count of the current programming operation is greater than a second reference count. The second reference count can be greater than the first reference count.

[0225] During the First Period, a pulse signal with a voltage level of the reference voltage VREF can be provided to the page buffer sensing transistor as the page buffer sensing signal PB_SENSE (e.g., Figures 9 to 11 The gate electrode of the first NMOS transistor N1 shown.

[0226] The first period can be a time interval from time T0 to time T1. A pulse signal with a voltage level of a reference voltage VREF can be generated, for example, by a first signal provider 921. The voltage level of the reference voltage VREF can be greater than the voltage level of ground (e.g., 0V). For example, the reference voltage VREF can be the sum of the bit line voltage and the threshold voltage of the first NMOS transistor N1. In another embodiment, the reference voltage VREF can have different values.

[0227] During the second period following the first period, in one embodiment, a first ramp signal Line1 may be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. The first ramp signal Line1 may be increased with a first slope (e.g., based on a first step voltage ΔV1 relative to a unit time Δt).

[0228] In one implementation, during the second period following the first period, the first step signal Line1' may be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. The first step signal Line1' may be a signal that increases by one or more steps per unit time Δt based on the first step voltage ΔV1.

[0229] During the Second Period, the page buffer sensing signal PB_SENSE can increase from a first voltage level to a second voltage level. The first voltage level can be the voltage level of the reference voltage VREF. The second voltage level can be the voltage level of the turn-on voltage Vpbs. The turn-on voltage Vpbs can be the voltage at which the page buffer sensing transistor is turned on.

[0230] The second period can be the time period from time T1 to time T2. The first ramp signal Line1 or the first step signal Line1' can be sensed, for example, by the second signal provider 922.

[0231] Following the second period, a pulse signal with a second voltage level can be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. The period for providing the pulse signal with the second voltage level can be the period from time T2 to time T3. The pulse signal with the second voltage level can be generated, for example, by the second signal provider 922.

[0232] At time T3, the page buffer sensing signal PB_SENSE applied to the gate electrode of the page buffer sensing transistor can be discharged to ground voltage.

[0233] According to the above implementation, the peak current generated in each of the initial and final programming periods is prevented from increasing, or if an increase occurs, the degree of increase is reduced. Furthermore, the time required to complete the programming operation is prevented from increasing, or if an increase occurs, the degree of increase is reduced. As a result, the performance of the programming operation can be improved.

[0234] Figure 13 This is a diagram illustrating an implementation of a page buffer sensing signal provided during the intermediate programming period. Figure 13 In this context, the precharge period can be a time period within a precharge operation performed during the programming middle period (PGM Middle Period). In an implementation, the PGM Middle Period can be a time period corresponding to a situation where the cycle count of the current programming operation is greater than a first reference count and equal to or less than a second reference count.

[0235] Reference Figure 13 During the first period from time T0 to time T1, a pulse signal with a voltage level of the reference voltage VREF can be provided to the page buffer sensing transistor (e.g., Figures 9 to 11 The gate electrode of the first NMOS transistor N1 shown.

[0236] In this implementation, during the third period following the first period, the second ramp signal Line2 can be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. The second ramp signal Line2 can be a signal that increases with a second slope. The second slope can correspond to a second step voltage ΔV2 relative to a unit time Δt. The second slope can be less than the first slope.

[0237] In one implementation, during the third period following the first period, the second step signal Line2' can be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. The second step signal Line2' can be a signal that increases based on the second step voltage ΔV2 per unit time Δt based on one or more steps.

[0238] During the Third Period, the page buffer sensing signal PB_SENSE may increase from a first voltage level to a second voltage level. The first voltage level may be the voltage level of the reference voltage VREF. The second voltage level may be the voltage level of the turn-on voltage Vbps. The Third Period may occur after the First Period. In one embodiment, a Third Period may occur instead of a Second Period. In one embodiment, the Third Period may be longer than the Second Period. For example, when time T2 is a time before time T2', the Third Period may be the period from time T1 to time T2'. For example, the second ramp signal or the second step signal Line2' may be generated by the second signal provider 922.

[0239] Following the Third Period, a pulse signal with a second voltage level can be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. For example, the period for providing the pulse signal with the second voltage level can be the period from time T2' to time T3'. The period from time T2' to time T3' can be equal to the period from time T2 to time T3. For example, the pulse signal with the second voltage level can be generated by the second signal provider 922.

[0240] At time T3', the page buffer sensing signal applied to the gate electrode of the page buffer sensing transistor can be discharged to ground voltage.

[0241] As described above, the peak current generated during the intermediate programming period can be prevented from increasing or its increase can be reduced, and the time for programming operation to complete can be prevented from increasing excessively or its increase can be reduced. As a result, the performance of the programming operation can be improved.

[0242] Figure 14 This is a diagram illustrating an implementation of a page buffer sensing signal provided during the intermediate programming period. Similar to... Figure 13 In Figure 14 In this context, the Precharge period can be the period during which the precharge operation is performed in the Programming Middle Period (PGM Middle Period).

[0243] During the first period from time T0 to time T1, a pulse signal with a voltage level of the reference voltage VREF can be provided to the page buffer sensing transistor (e.g., Figures 9 to 11 The gate electrode of the first NMOS transistor N1 shown.

[0244] During the third period following the first period, in this embodiment, the third ramp signal Line3 can be provided to the gate electrode of the page buffer sensing transistor as the page buffer sensing signal PB_SENSE. The third ramp signal Line3 can be a signal that increases with a third slope. The third slope can be a third step voltage ΔV3 relative to a unit time Δt and can be less than the second slope.

[0245] In one implementation, during the third period following the first period, the third step signal Line3' can be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor. The third step signal Line3' can be a signal that increases by one or more steps per unit time Δt based on the third step voltage ΔV3. For example, the third ramp signal Line3 or the third step signal Line3' can be generated by the second signal provider 922.

[0246] During the Third Period, the page buffer sensing signal PB_SENSE may increase from a first voltage level to a second voltage level. The first voltage level may be the voltage level of the reference voltage VREF, and the second voltage level may be lower than the voltage level of the turn-on voltage Vpbs. When the second voltage level is lower than the voltage level of the turn-on voltage Vbps, the bit line voltage (e.g., the supply voltage VCORE) may not be adequately charged into the bit line.

[0247] Following the Third Period, a pulse signal with a voltage level of on-state voltage Vbps can be provided as a page buffer sensing signal PB_SENSE to the gate electrode of the page buffer sensing transistor to fully charge the bit line voltage (e.g., the power supply voltage VCORE) into the bit line. The period for providing the pulse signal with a voltage level of on-state voltage Vbps can be, for example, from time T2' to time T3', and in one embodiment, it can be equal to the period from time T2 to time T3. For example, the pulse signal with a voltage level of on-state voltage Vbps can be generated by the third signal provider 923.

[0248] At time T3', the page buffer sensing signal PB_SENSE applied to the gate electrode of the page buffer sensing transistor can be discharged to ground voltage.

[0249] As described above, this prevents or reduces the increase in peak current generated during the programming intermediate period, and also prevents excessive increases in the programming operation completion time. Furthermore, it ensures that the bit line voltage is adequately supplied to the bit lines. Therefore, the performance of the programming operation can be improved.

[0250] Figure 15 The diagram illustrates an embodiment of a method of operating a memory device, which may be any embodiment of the memory device described herein (e.g., memory device 100).

[0251] Reference Figure 15 The method may include a precharge operation S110, a programming voltage application operation S120, and a verification operation S130. The precharge operation S110 may include controlling the page buffer 102 to set the bit line voltage applied to multiple bit lines. An example of the precharge operation S110 will be described in detail.

[0252] During a first time period, the memory device 100 may provide a pulse signal having a first voltage level higher than the ground voltage to the page buffer 102. For example, during the first time period in a precharge operation, the page buffer controller 101 may provide the pulse signal as a page buffer sensing signal to the gate electrode (S111) of the page buffer sensing transistor (e.g., the first NMOS transistor N1) in the page buffer 102. The pulse signal may have a first voltage level higher than the ground voltage.

[0253] After the first time period, the memory device 100 may provide a ramp signal to the page buffer 102, increasing from a first voltage level to a second voltage level. The ramp signal slope can be determined based on the cycle count of multiple programming cycles among multiple predetermined slopes.

[0254] For example, the page buffer controller 101 may check whether the execution level of the programming operation is the initial programming period based on the cycle count of multiple programming cycles (S112). When the execution level of the programming operation is the initial programming period (e.g., S112 is yes), during a second period after the first period, the page buffer controller 101 provides a first ramp signal as a page buffer sensing signal to the gate electrode of the page buffer sensing transistor (S113). The first ramp signal may be increased with a first slope.

[0255] In one implementation, during a second time period following the first time period, in a programming cycle having a cycle count equal to or less than the first reference count among a plurality of programming cycles, the page buffer controller 101 may provide the first ramp signal as a page buffer sensing signal to the gate electrode of the page buffer sensing transistor.

[0256] When the execution level of the programming operation is not at the initial programming period (e.g., S112 is not), the page buffer controller 101 can check whether the execution level of the programming operation is in the middle of the programming period (S114) based on the cycle count of multiple programming cycles. When the execution level of the programming operation is at the final programming period (e.g., S114 is not), operation S113 can be executed.

[0257] In one embodiment, during the second time period, in a programming cycle with a cycle count greater than the second reference count among multiple programming cycles, the page buffer controller 101 may provide the first ramp signal as a page buffer sensing signal to the gate electrode of the page buffer sensing transistor.

[0258] When the execution level of the programming operation is in the middle of the programming period (e.g., S114 is yes), instead of the second period, during the third period, the page buffer controller 101 can provide the second ramp signal as a page buffer sensing signal to the gate electrode of the page buffer sensing transistor (S115). The second ramp signal can be increased by a second ramp that is less than the first ramp.

[0259] In one implementation, during the third time period, in a programming cycle among multiple programming cycles that has a cycle count greater than the first reference count and equal to or less than the second reference count, the page buffer controller 101 may provide the second ramp signal as a page buffer sensing signal to the gate electrode of the page buffer sensing transistor.

[0260] After the ramp signal reaches the second voltage level, the memory device 100 may provide a pulse signal to the page buffer 102 as a page buffer sensing signal having a third voltage level greater than or equal to the second voltage level. The third voltage level may correspond to the on-state voltage.

[0261] For example, after the second or third time period, the page buffer controller 101 may check whether the second voltage level of the second ramp signal has reached the voltage level of the turn-on voltage (S116). When the second voltage level of the second ramp signal is not the voltage level of the turn-on voltage (e.g., S116 is not), after the third time period, the page buffer controller 101 may provide a pulse signal as a page buffer sensing signal to the gate electrode of the page buffer sensing transistor (S117). This pulse signal may have a third voltage level greater than the second voltage level.

[0262] When the second voltage level of the second ramp signal is the voltage level of the turn-on voltage (e.g., S116 is yes), after the second time period, a pulse signal with a third voltage level (e.g., equal to the second voltage level) can be provided to the gate electrode of the page buffer sensing transistor, and operation S120 can be performed.

[0263] The programming voltage application operation S120 is performed after the precharge operation S110 and may include the operation of the memory device 100 applying a programming voltage to word lines that are commonly connected to a plurality of memory cells.

[0264] The verification operation S130 is performed after the programming voltage application operation S120, and may include the operation by which the memory device 100 determines whether a selected memory cell has been programmed by applying a verification voltage.

[0265] Figure 16 This is a diagram showing a storage controller 200 according to an embodiment.

[0266] Reference Figure 16 The storage controller 200 may include a processor 210, RAM 220, error correction code (ECC) circuitry 230, host interface 240, ROM 250, and flash memory interface 260. The processor 210 controls the overall operation of the storage controller 200.

[0267] RAM 220 can be used as a buffer memory, cache memory, working memory, etc. of the storage controller 200. In one example, RAM 220 can be a buffer memory.

[0268] ECC circuit 230 can generate ECC for correcting failure bits or error bits in data received from memory device 100. ECC circuit 230 can generate data with added parity bits by performing ECC encoding on data provided to memory device 100. The parity bits can be stored in memory device 100. ECC circuit 230 can perform ECC decoding on data output from memory device 100 and can use the parity bits to correct errors. For example, ECC circuit 230 can use various coding modulations to correct errors. Examples include LDPC codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, RSC, TCM, and BCM.

[0269] ECC circuit 230 can calculate the ECC value of the data to be programmed into memory device 100 during a programming operation. ECC circuit 230 can perform error correction operations on data read from memory device 100 during a read operation based on the ECC value. ECC circuit 230 can perform error correction operations on data recovered from memory device 100 during a failed data recovery operation.

[0270] The storage controller 200 can communicate with external devices (e.g., host 400, application processor, etc.) via the host interface 240. The ROM 250 can store various information for the operation of the storage controller 200 in the form of firmware or other instructions. The storage controller 200 can communicate with the memory device 100 via the flash interface 260. The storage controller 200 can send commands (CMD), addresses (ADDR), control signals (CTRL), etc., to the memory device 100 via the flash interface 260, and receive data (DATA). For example, the flash interface 260 may include a NAND interface.

[0271] Figure 17 This is a block diagram illustrating a memory card system 2000 applicable to a storage device as described herein, according to an embodiment.

[0272] Reference Figure 17 The memory card system 2000 includes a memory device 2100, a memory controller 2200, and a connector 2300. For example, the memory device 2100 may be a non-volatile memory device. Examples include electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0273] Storage controller 2200 is connected to and has access to storage device 2100. For example, storage controller 2200 can control read operations, write operations, erase operations, and background operations of storage device 2100. Storage controller 2200 can serve as an interface between storage device 2100 and host computer. Storage controller 2200 drives firmware (or other instructions) for controlling storage device 2100. For example, storage controller 2200 can be configured according to reference... Figure 1 The storage controller 200 described is implemented in a similar or identical manner.

[0274] The storage controller 2200 may include components such as random access memory (RAM), processing unit, host interface, memory interface, error corrector and / or other components.

[0275] Storage controller 2200 can communicate with external devices via connector 2300. Storage controller 2200 can communicate with external devices (e.g., host 400) according to at least one specific communication protocol, standard, or interface. Examples include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. Connector 2300 can be a connector compatible with at least one of the aforementioned communication protocols, standards, or interfaces.

[0276] The memory device 2100 and the memory controller 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2200 and the memory device 2100 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro and eMMC), SD cards (SD, miniSD, microSD and SDHC) and universal flash memory (UFS).

[0277] Figure 18 This is a block diagram illustrating a solid-state drive (SSD) system applicable to storage devices as described herein, according to an embodiment.

[0278] Reference Figure 18 The SSD 3000 exchanges signals SIG with the host 400 through signal connector 3001 and receives power PWR through power connector 3002. The SSD 3200 includes an SSD controller 3200, multiple flash memory modules 3100_1, 3100_2 and 3100_n, an auxiliary power supply 3300, and a buffer memory 3400.

[0279] For example, the SSD controller 3200 can execute and reference Figure 1 The storage controller 200 described has the same function. The SSD controller 3200 can control multiple flash memory modules 3100_1, 3100_2, and 3100_n in response to a signal SIG received from the host 400. In one embodiment, the signal SIG can be a signal based on the interface between the host 400 and the SSD 3000. For example, the signal SIG can be a signal defined by at least one interface such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0280] Auxiliary power supply 3300 is connected to host 400 via power connector 3002. Auxiliary power supply 3300 can receive power PWR from host 400 and can be charged using power PWR. When the power supply from host 400 is unstable (e.g., does not conform to a predetermined level or pattern), auxiliary power supply 3300 can provide power to SSD 3000. For example, auxiliary power supply 3300 may be located inside or outside SSD 3000. For example, auxiliary power supply 3300 may be on the motherboard to provide auxiliary power to SSD 3000.

[0281] Buffer memory 3400 may temporarily store data. For example, buffer memory 3400 may temporarily store data received from host 400 or data received from multiple flash memory modules 3100_1, 3100_2, and 3100_n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3100_1, 3100_2, and 3100_n. Buffer memory 3400 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0282] Figure 19 This is a block diagram of a user system applicable to the storage device as described herein, according to an implementation method.

[0283] Reference Figure 19 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500. The application processor 4100 can drive components, operating systems (OS), user programs, etc., included in the user system 4000. In one embodiment, the application processor 4100 may include one or more controllers for controlling components, interfaces, graphics engines, etc., in the user system 4000. The application processor 4100 may be provided as a system-on-a-chip (SoC).

[0284] The memory module 4200 can operate as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. The application processor 4100 and the memory module 4200 may be housed in a single semiconductor package (e.g., a stacked package (PoP)).

[0285] Network module 4300 may communicate with external devices, for example, using wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Exemplarily, network module 4300 may be included in application processor 4100.

[0286] Storage module 4400 may store, for example, data received from application processor 4100. In one embodiment, storage module 4400 may send the data stored therein to application processor 4100. For example, storage module 4400 may be implemented as a non-volatile semiconductor memory device including phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. For example, storage module 4400 may be provided as a removable drive (e.g., a memory card or external drive of user system 4000).

[0287] For example, storage module 4400 can be configured according to reference. Figure 1 The described storage device 1000 operates in a similar or identical manner. Storage module 4400 may include one or more non-volatile memory devices that can operate in accordance with the referenced... Figure 1 The memory device 100 described operates in a similar or identical manner. User interface 4500 may include one or more interfaces for inputting data and / or commands to application processor 4100 and / or for outputting data to external devices. User interface 4500 may include one or more user input interfaces (e.g., keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element) and / or one or more user output interfaces (e.g., liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor).

[0288] According to one or more of the above embodiments, the memory device achieves improved performance by reducing the completion time of programming operations and / or reducing the peak current flowing through the bit lines. A method of operating such a memory device is also provided.

[0289] The methods, processes, and / or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or other than the elements described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods may transform the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0290] When implemented at least partially in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or other elements besides those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods described herein.

[0291] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0292] In the above embodiments, all steps may be performed selectively, or some steps may be omitted. In various embodiments, the steps may not be performed in the described order, but may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0293] Furthermore, exemplary embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for illustrative purposes only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. Two or more embodiments may be combined to form additional embodiments.

[0294] Cross-reference to related applications

[0295] This application claims priority to Korean Patent Application No. 10-2020-0136192, filed on October 20, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory units; Multiple page buffers, each page buffer is connected to a corresponding memory cell via multiple bit lines, and temporarily stores the data to be stored in the multiple memory cells respectively; as well as A page buffer controller controls one or more voltages to be applied to the plurality of bit lines during programming operations that store the data in the plurality of memory cells, wherein... The programming operation includes multiple programming loops, each programming loop including a programming voltage application operation and a verification operation. The programming voltage application operation includes a pre-charge period, a programming voltage application period, and a discharge period. The plurality of page buffers provide bit line voltages to the plurality of bit lines in response to a page buffer sensing signal output from the page buffer controller, and The page buffer controller includes: A first signal provider provides a first pulse signal as a page buffer sensing signal during a first time period in the pre-charge period, the first pulse signal having a first voltage level greater than the ground voltage; and A second signal provider provides a second pulse signal as a page buffer sensing signal after the first time period. The second pulse signal increases from the first voltage level to a second voltage level with a slope determined according to the cycle count of the plurality of programming cycles, the slope corresponding to one of a plurality of predetermined slopes.

2. The memory device according to claim 1, wherein, When the cycle count is equal to or less than the first reference count, or when the cycle count is greater than a second reference count that is greater than the first reference count, the second signal provider provides the second pulse signal during the second time period to include a first ramp signal, the first ramp signal increasing at a first slope greater than a second slope, the second time period occurring after the first time period in the pre-charge period.

3. The memory device according to claim 2, wherein, The second voltage level corresponds to the on-state voltage of the page buffer sensing transistor in the page buffer. The page buffer sensing transistor connects the bit line and the common sensing node in response to the page buffer sensing signal, and The second signal provider provides a third pulse signal as a sensing signal for the page buffer after the second time period, the third pulse signal having the second voltage level.

4. The memory device according to claim 3, wherein, When the first ramp signal and the third pulse signal having the second voltage level are supplied, the ground voltage is applied to the word lines that are commonly connected to the plurality of memory cells.

5. The memory device according to claim 2, wherein, When the cycle count is greater than the first reference count and equal to or less than the second reference count, the second signal provider provides a second ramp signal as the page buffer sensing signal during the third time period, and the second ramp signal increases with the second slope during the third time period, which is longer than the second time period.

6. The memory device according to claim 5, wherein, The second voltage level corresponds to the on-state voltage of the page buffer sensing transistor in the page buffer. The page buffer sensing transistor connects the bit line and the common sensing node in response to the page buffer sensing signal, and The second signal provider provides a third pulse signal with the second voltage level as a page buffer sensing signal after the third time period.

7. The memory device according to claim 5, wherein, The second voltage level is lower than the on-state voltage of the page buffer sensing transistor in the page buffer. The page buffer sensing transistor connects the bit line and the common sensing node in response to the page buffer sensing signal, and The page buffer controller further includes a third signal provider that provides a third pulse signal with the on-state voltage as a page buffer sensing signal after the third time period.

8. The memory device according to claim 7, wherein, When the second ramp signal and the third pulse signal having the on-voltage are supplied, the ground voltage is applied to the word lines that are commonly connected to the plurality of memory cells.

9. A memory device comprising: Multiple memory units; Multiple page buffers, each page buffer is connected to a corresponding memory cell via multiple bit lines, and temporarily stores the data in the corresponding memory cell among the multiple memory cells; as well as A page buffer controller controls one or more voltages to be applied to the plurality of bit lines during programming operations that store the data in the plurality of memory cells, wherein... The programming operation includes multiple programming loops, each programming loop including a programming voltage application operation and a verification operation. The programming voltage application operation includes a pre-charge period, a programming voltage application period, and a discharge period. The plurality of page buffers provide bit line voltages to the plurality of bit lines in response to a page buffer sensing signal output from the page buffer controller, and The page buffer controller includes: A first signal provider provides a first pulse signal as a page buffer sensing signal during a first time period in the pre-charge period, the first pulse signal having a first voltage level higher than the ground voltage; and A second signal provider provides a step signal as a page buffer sensing signal after the first time period. The step signal increases from the first voltage level to the second voltage level based on a step voltage, which corresponds to the cycle count of the plurality of programming cycles among a plurality of predetermined step voltages.

10. The memory device according to claim 9, wherein, When the cycle count is equal to or less than the first reference count, or when the cycle count is greater than a second reference count that is greater than the first reference count, the second signal provider provides a first step signal as a page buffer sensing signal during a second time period, the second time period occurring after the first time period in the precharge period, the first step signal increasing based on a first step voltage that is greater than a second step voltage.

11. The memory device according to claim 10, wherein, When the cycle count is greater than the first reference count and equal to or less than the second reference count, the second signal provider provides a second step signal as the page buffer sensing signal during a third period that is longer than the second period, the second step signal increasing based on the second step voltage.

12. The memory device according to claim 11, wherein, The second voltage level is lower than the on-state voltage of the page buffer sensing transistor in the page buffer. The page buffer sensing transistor connects the bit line and the common sensing node in response to the page buffer sensing signal, and The page buffer controller further includes a third signal provider that provides a second pulse signal after the third time period. The second pulse signal provided after the third time period serves as a page buffer sensing signal and has the on-state voltage.

13. A method of operating a memory device, the method comprising the steps of: During the first time period, a first pulse signal is provided to the page buffer, the first pulse signal being used as a page buffer sensing signal and having a first voltage level higher than the ground voltage; After the first time period, a ramp signal is provided to the page buffer, which is used as a sensing signal for the page buffer and increases from the first voltage level to the second voltage level with a slope determined based on the cycle count of multiple programming cycles, the slope corresponding to one of a plurality of predetermined slopes; After the ramp signal reaches the second voltage level, a second pulse signal is provided to the page buffer. This second pulse signal is used as a sensing signal for the page buffer and has a third voltage level that is higher than or equal to the second voltage level. as well as The programming voltage is applied to the word line that is connected to multiple memory cells.

14. The method according to claim 13, wherein, The step of providing the ramp signal to the page buffer as a page buffer sensing signal includes: In a programming loop having a loop count that is equal to or less than a first reference count or greater than a second reference count that is greater than the first reference count, a first ramp signal is provided during a second time period, the first ramp signal increasing at a first ramp rate greater than a second ramp rate, and the second time period occurs after the first time period.

15. The method according to claim 14, wherein, The step of providing the second pulse signal to the page buffer includes: providing the second pulse signal after the second time period, and The third voltage level is equal to the second voltage level.

16. The method of claim 15, further comprising the step of: When the first ramp signal and the second pulse signal are provided, the ground voltage is applied to the word line that is commonly connected to the plurality of memory cells.

17. The method of claim 14, wherein, The step of providing the ramp signal to the page buffer as a page buffer sensing signal includes: In a programming loop having a loop count greater than the first reference count and equal to or less than the second reference count, a second ramp signal is provided during a third period longer than the second period, the second ramp signal increasing with the second slope, and the third period occurring after the first period.

18. The method according to claim 17, wherein, The step of providing the second pulse signal having a third voltage level higher than the second voltage level is performed after the third time period.

19. The method of claim 18, further comprising the step of: When the second ramp signal and the second pulse signal are supplied, the ground voltage is applied to the word line that is commonly connected to the plurality of memory cells.

20. A memory device comprising: Multiple memory units; A voltage generator that generates operating voltages for programming operations that store data in the plurality of memory cells; Multiple page buffers are connected to the multiple memory cells via multiple bit lines, and the multiple page buffers provide bit line voltages to the multiple bit lines in response to a page buffer sensing signal; as well as A page buffer controller, which provides page buffer sensing signals to the plurality of page buffers during the programming operation, wherein the page buffer controller includes: A first signal provider provides a pulse signal as a sensing signal for the page buffer during a first time period, the pulse signal being generated by the voltage generator; and A second signal provider provides a ramp signal as a page buffer sensing signal during a second time period following the first time period. The ramp signal has a slope determined based on a loop count of a programming loop representing the extent to which the programming operation is performed. The second signal provider includes: Multiple switches, wherein the multiple switches are provided with page buffer pump voltage; Multiple transistors are grouped and connected in series to the multiple switches, and the multiple transistors output bias current from the multiple switches in response to a voltage control signal, the voltage control signal being provided based on the cycle count of the programming cycle; A capacitor, which is commonly connected to the plurality of transistors and is charged with respect to the bias current; and A voltage output circuit, which is connected to the plurality of transistors, transmits the capacitor voltage corresponding to the page buffer sensing signal.

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