Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a display region. The display region includes a plurality of sub-pixels disposed on a base, a plurality of first signal lines extending along a first direction, and a plurality of data lines extending along a second direction. At least one sub-pixel includes a drive circuit including a plurality of transistors and at least one storage capacitor. The transistors include at least a first conductive layer and a second conductive layer; the first direction is perpendicular to the second direction. The plurality of first signal lines are located at a third conductive layer. The third conductive layer is located at a side of the control electrode of the transistors of the drive circuit away from the base.

Description

[0001] This application is a divisional application of the application with the application date of October 19, 2020, the application number of 202011118923.9, and the invention name of "Display substrate, preparation method thereof, and display device". TECHNICAL FIELD

[0002] The present document relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof, and a display device. BACKGROUND

[0003] An organic light-emitting diode (OLED) display substrate is a display substrate different from a traditional liquid crystal display (LCD), and has the advantages of active light-emitting, good temperature characteristics, small power consumption, fast response, bendability, ultra-thinness, and low cost. Therefore, the OLED display substrate has become one of the important development directions of a new generation of display devices, and has attracted more and more attention. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a display substrate and a display device.

[0006] In one aspect, the present disclosure provides a display substrate, comprising: a display area, the display area comprising a plurality of sub-pixels disposed on a substrate, a plurality of first signal lines extending along a first direction, and a plurality of data lines extending along a second direction. At least one sub-pixel comprises a drive circuit, the drive circuit comprising a plurality of transistors and at least one storage capacitor; the transistor at least comprises a first conductive layer and a second conductive layer; the first direction is perpendicular to the second direction. The plurality of first signal lines is located in a third conductive layer, and the third conductive layer is located on a side of the control electrode of the transistor of the drive circuit away from the substrate.

[0007] In some example embodiments, the third conductive layer comprises a first electrode or a second electrode of at least one transistor of the drive circuit.

[0008] In some example embodiments, the first conductive layer is located between the substrate and the third conductive layer; the first signal line located in the third conductive layer transmits a signal to at least one sub-pixel through the first conductive layer.

[0009] In some example embodiments, the first conductive layer comprises a control electrode of at least one transistor of the drive circuit; the first signal line is connected to the control electrode of at least one transistor of the drive circuit.

[0010] In some example embodiments, the display region further comprises a plurality of first power lines extending along the second direction, the data lines and the first power lines are located on the side of the storage capacitor closest to the electrode of the substrate away from the substrate.

[0011] In some example embodiments, the display region further comprises at least one power connection part electrically connected with the first power lines. The first power lines at least partially overlap with the power connection part at the projection of the substrate.

[0012] In some example embodiments, the display region further comprises a fourth conductive layer disposed on the substrate, and at least one conductive layer between the fourth conductive layer and the first conductive layer.

[0013] In some example embodiments, the power connection part is located between the at least one conductive layer between the first conductive layer and the fourth conductive layer.

[0014] In some example embodiments, the power connection part is located in the second conductive layer.

[0015] In some example embodiments, a third insulating layer is disposed between the second conductive layer and the third conductive layer, and the first power lines are electrically connected with the power connection part through the via holes of the third insulating layer.

[0016] In some example embodiments, the power connection part is electrically connected with the first electrode of the third switching transistor of the driving circuit.

[0017] In some example embodiments, the power connection part and the second electrode of the storage capacitor are an integral structure.

[0018] In some example embodiments, the plurality of first signal lines comprises a plurality of scan lines and a reset signal line.

[0019] In some example embodiments, in the second direction, the projection of the power connection part on the substrate is located between the projection of at least one of the scan lines and the reset signal line on the substrate connected with the same row of sub-pixels.

[0020] In some example embodiments, the at least one power connection part is connected with a plurality of sub-pixels.

[0021] In some example embodiments, the at least one power connection part is electrically connected with at least two of the three sub-pixels at the same time.

[0022] In some exemplary embodiments, the plurality of sub-pixels includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel. The at least one power connection portion is electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.

[0023] In some exemplary embodiments, the first sub-pixel is red, the second sub-pixel is green, and the third sub-pixel is blue.

[0024] In some exemplary embodiments, the first power line forms a double-layer trace with an adjacent conductive layer in the region where the sub-pixel is located.

[0025] In some exemplary embodiments, the double-layered trace portion of the first power line at least partially overlaps with the orthographic projection of the storage capacitor in the first direction.

[0026] On the other hand, this disclosure provides a display device including a display substrate as described above.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0029] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 2 This is a schematic diagram of the structure of a scanning drive circuit according to at least one embodiment of the present disclosure;

[0031] Figure 3 This is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0032] Figure 4 for Figure 3 The provided timing diagram for the shift register unit;

[0033] Figure 5 This is an equivalent circuit diagram of the driving circuit for a sub-pixel according to at least one embodiment of the present disclosure;

[0034] Figure 6 for Figure 5 The provided timing diagram of the driver circuit is shown.

[0035] Figure 7 This is a top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 8 for Figure 7 A cross-sectional view along the QQ direction;

[0037] Figure 9 This is a top view of a display substrate after the semiconductor layer has been formed in at least one embodiment of this disclosure;

[0038] Figure 10 This is a top view of a display substrate after the first conductive layer has been formed in at least one embodiment of this disclosure;

[0039] Figure 11 This is a top view of a display substrate after the second conductive layer has been formed in at least one embodiment of this disclosure;

[0040] Figure 12 This is a top view of a display substrate after the third conductive layer has been formed in at least one embodiment of the present disclosure;

[0041] Figure 13 This is a top view of a display substrate after the fourth conductive layer has been formed in at least one embodiment of this disclosure;

[0042] Figure 14 This is a top view of a plurality of sub-pixels of a display substrate according to at least one embodiment of the present disclosure;

[0043] Figure 15 This is a simulation schematic diagram of the gate driving of a display substrate according to at least one embodiment of the present disclosure;

[0044] Figure 16 include Figure 16 (a) and Figure 16 (b) shows a schematic diagram of the gate drive delay;

[0045] Figure 17 This is a schematic flowchart of a method for preparing a display substrate according to at least one embodiment of the present disclosure;

[0046] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0047] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0048] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional feature or element to form a unique technology within the scope of the claims. Any feature or element of any embodiment can also be combined with features or elements from other technology solutions to form another unique technology solution within the scope of the claims. Therefore, it should be understood that any of the features shown or discussed in the present disclosure can be realized alone or in any appropriate combination. Accordingly, the embodiments are not to be restricted, except as by the appended claims and their equivalents. Furthermore, one or more modifications and changes can be made within the protection scope of the appended claims.

[0049] Furthermore, in describing representative embodiments, the specification can have presented the method or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps can be possible, and are within the scope of the present disclosure. Therefore, the particular order in which the steps are presented is not limiting. Furthermore, for purposes of the claims, the steps of the claims are not limited to the order in which they are presented herein. It is possible that the steps can be executed in a different order than that presented herein, and still be within the scope of the present disclosure.

[0050] Embodiments will be described below with reference to the accompanying drawings. The embodiments can be implemented in numerous different forms, and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art.

[0051] In the drawings, the size, the layer thickness, or the region of each constituent is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure should not be interpreted only by the illustrated shapes of the components. The embodiment of the present disclosure can be implemented with another shape, and so forth.

[0052] In the present disclosure, ordinal numbers such as "first", "second", and "third" are used in order to avoid confusion among components, and are not used to describe the numbers themselves. In the present disclosure, "a plurality of" can mean two or more.

[0053] In the present disclosure, words of orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation, and are only for the convenience of describing the present specification and simplifying the description, and thus are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or an intervening element can be present. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0054] In the present disclosure, the words "connected", "coupled", or "linked" and the like similar words do not necessarily mean a physical or mechanical connection, but can include an electrical connection, whether direct or indirect. The "electrical connection" includes a case where the components are connected together through an element having a certain electrical action. The "element having a certain electrical action" is not particularly limited as long as it can perform the transmission and reception of an electrical signal between the components to be connected. Examples of the "element having a certain electrical action" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0055] In the present disclosure, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less, or can include a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state in which the angle formed by two straight lines is 80° or more and 100° or less, or can include a state in which the angle is 85° or more and 95° or less.

[0056] In the present disclosure, "film" and "layer" can be interchanged. For example, "conductive layer" can be sometimes changed to "conductive film". Similarly, "insulating film" can be sometimes changed to "insulating layer".

[0057] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain) and the source electrode (a source electrode terminal, a source region, or a source), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which a current mainly flows. In the case of using a transistor with opposite polarity or in the case of a change in the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0058] A person skilled in the art can understand that the transistor used in all embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Exemplarily, the thin film transistor used in the embodiments of the present disclosure can be an oxide semiconductor transistor. Since the source electrode and the drain electrode of the switching transistor used herein are symmetrical, the source electrode and the drain electrode thereof can be interchanged. In the embodiments of the present disclosure, the control electrode can be a gate electrode, in order to distinguish the two electrodes of the transistor other than the gate electrode, one of the electrodes is referred to as a first electrode, and the other electrode is referred to as a second electrode, the first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode.

[0059] With the wide application and development of display technology, the market demand for medium and large-sized OLED display substrates gradually emerges. With the increase of the resolution of the OLED display substrate, the scanning time length of each row of sub-pixels in the OLED display substrate becomes shorter and shorter, and the data signal writing time length is continuously reduced. With the increase of the size of the OLED display substrate, the length of the gate line horizontally arranged in the OLED display substrate gradually increases, which is easy to cause serious gate driving delay (Gate Delay), resulting in insufficient charging of the sub-pixels; and moreover, with the increase of the refresh rate, the trend of insufficient charging becomes more and more obvious.

[0060] The embodiments of the present disclosure provide a display substrate and a preparation method thereof and a display device, which can improve the resolution and refresh rate of the display substrate.

[0061] The display substrate provided by the embodiment of the present disclosure comprises a display area and a peripheral area located at the periphery of the display area. The peripheral area is provided with a scan driving circuit. The display area is provided with a plurality of sub-pixels, a plurality of first signal lines connected with the scan driving circuit and extending along a first direction. At least one of the plurality of sub-pixels comprises a light emitting element and a driving circuit for driving the light emitting element to emit light, and the driving circuit comprises a plurality of transistors and a storage capacitor. The display area comprises a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer which are sequentially arranged on the substrate. The semiconductor layer comprises an active layer of the plurality of transistors. The first conductive layer comprises control electrodes of the plurality of transistors and a first electrode of the storage capacitor. The second conductive layer comprises a second electrode of the storage capacitor. The third conductive layer comprises the plurality of first signal lines and first electrodes and second electrodes of the plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with a first via, and the first signal line contacts the control electrode of the transistor exposed by the first conductive layer through the first via.

[0062] The display substrate provided by the embodiment of the present disclosure comprises a display area and a peripheral area located at the periphery of the display area. The peripheral area is provided with a scan driving circuit. The display area is provided with a plurality of sub-pixels, a plurality of first signal lines connected with the scan driving circuit and extending along a first direction. At least one of the plurality of sub-pixels comprises a light emitting element and a driving circuit for driving the light emitting element to emit light, and the driving circuit comprises a plurality of transistors and a storage capacitor. The display area comprises a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer which are sequentially arranged on the substrate. The semiconductor layer comprises an active layer of the plurality of transistors. The first conductive layer comprises control electrodes of the plurality of transistors and a first electrode of the storage capacitor. The second conductive layer comprises a second electrode of the storage capacitor. The third conductive layer comprises the plurality of first signal lines and first electrodes and second electrodes of the plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with a first via, and the first signal line contacts the control electrode of the transistor exposed by the first conductive layer through the first via.

[0063] In some example embodiments, the display area further comprises a fourth conductive layer arranged on a side of the third conductive layer away from the substrate. The fourth conductive layer comprises a plurality of second signal lines extending along a second direction perpendicular to the first direction. An insulating layer between the fourth conductive layer and the third conductive layer is provided with a second via, and the second signal line contacts the first electrode or the second electrode of the transistor exposed by the third conductive layer through the second via. In the example embodiment, the second signal lines perpendicular to the extension direction of the first signal lines are arranged on the fourth conductive layer, so as to avoid the direct intersection of the second signal lines and the first signal lines.

[0064] In some example embodiments, the third conductive layer can comprise a three-layer stacked structure of titanium (Ti), aluminum (Al) and titanium. That is, the third conductive layer can comprise a titanium layer, an aluminum layer and a titanium layer which are sequentially stacked. However, the present embodiment is not limited thereto. In some examples, the third conductive layer can be a single-layer metal structure. In the example embodiment, the third conductive layer is prepared by using a metal material with low resistivity, so as to reduce the resistance of the first signal line.

[0065] In some example embodiments, the orthogonal projection of the first signal line on the substrate can at least partially overlap with the orthogonal projection of the control electrode of the transistor connected with the first signal line on the substrate. In some examples, the orthogonal projection of the first signal line on the substrate can cover the orthogonal projection of the control electrode of the transistor connected with the first signal line on the substrate. However, the present embodiments are not limited thereto.

[0066] In some example embodiments, a plurality of first vias can be arranged along the extension direction of the first signal line, and the orthogonal projection of the first signal line on the substrate can cover the orthogonal projection of the first via on the substrate.

[0067] In some example embodiments, the first signal line can include a scan line. The scan driving circuit can include a plurality of cascaded shift register units, and the i-th shift register unit can provide a scan signal to the i-th row of sub-pixels through the scan line, where i is an integer greater than 0.

[0068] In some example embodiments, the first signal line can include a scan line and a reset signal line. The scan driving circuit can include a plurality of cascaded shift register units. The i-th shift register unit can provide a scan signal to the i-th row of sub-pixels through the scan line, and the i-th shift register unit can provide a reset signal to the i+1-th row of sub-pixels through the reset signal line, where i is an integer greater than 0.

[0069] In some example embodiments, the shift register unit can include a first transistor to an eighth transistor, a first capacitor and a second capacitor. The control electrode of the first transistor is connected with the first clock signal terminal, the first electrode of the first transistor is connected with the first voltage terminal, and the second electrode of the first transistor is connected with the first control node. The control electrode of the second transistor is connected with the second control node, the first electrode of the second transistor is connected with the first clock signal, and the second electrode of the second transistor is connected with the first control node. The control electrode of the third transistor is connected with the first clock signal terminal, the first electrode of the third transistor is connected with the input signal terminal, and the second electrode of the third transistor is connected with the second control node. The control electrode of the fourth transistor is connected with the first control node, the first electrode of the fourth transistor is connected with the second voltage terminal, and the second electrode of the fourth transistor is connected with the first electrode of the fifth transistor. The control electrode of the fifth transistor is connected with the second clock signal terminal, and the second electrode of the fifth transistor is connected with the second control node. The control electrode of the sixth transistor is connected with the first voltage terminal, the first electrode of the sixth transistor is connected with the second control node, and the second electrode of the sixth transistor is connected with the third control node. The control electrode of the seventh transistor is connected with the third control node, the first electrode of the seventh transistor is connected with the output terminal, and the second electrode of the seventh transistor is connected with the second clock signal terminal. The control electrode of the eighth transistor is connected with the first control node, the first electrode of the eighth transistor is connected with the second voltage terminal, and the second electrode of the eighth transistor is connected with the output terminal. The first electrode of the first capacitor is connected with the output terminal, and the second electrode of the first capacitor is connected with the third control node. The first electrode of the second capacitor is connected with the second voltage terminal, and the second electrode of the second capacitor is connected with the first control node. However, the present embodiments are not limited thereto.

[0070] In some example embodiments, the peripheral region can further be provided with a light-emitting driving circuit. The display region can be further provided with a plurality of light-emitting control lines connected with the light-emitting driving circuit and extending along the first direction, and the light-emitting driving circuit can provide a light-emitting control signal to the sub-pixels through the light-emitting control lines. The first conductive layer can further include the plurality of light-emitting control lines. The control electrode of at least one transistor in the driving circuit of a row of sub-pixels and the light-emitting control line can be in one structure. However, the present embodiments are not limited thereto.

[0071] In some example embodiments, the second signal lines can include data lines, first power supply lines and initial signal lines. In some examples, each column of sub-pixels can be connected with the same data line and the same first power supply line. In some examples, each row of sub-pixels can be connected with the same initial signal line. However, the present embodiments are not limited thereto.

[0072] In some example embodiments, the display area can further include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer can be disposed between the semiconductor layer and the first conductive layer, the second insulating layer can be disposed between the first conductive layer and the second conductive layer, the third insulating layer can be disposed between the second conductive layer and the third conductive layer, and the fourth insulating layer can be disposed between the third conductive layer and the fourth conductive layer.

[0073] In some example embodiments, for at least one sub-pixel, the plurality of transistors of the drive circuit can include a first to a sixth switch transistor and a drive transistor. The control electrode of the first switch transistor can be connected to a scan line, the first electrode of the first switch transistor can be connected to a data line, and the second electrode of the first switch transistor can be connected to the first electrode of the drive transistor. The control electrode of the second switch transistor can be connected to the scan line, the first electrode of the second switch transistor can be connected to the control electrode of the drive transistor, and the second electrode of the second switch transistor can be connected to the second electrode of the drive transistor. The control electrode of the third switch transistor can be connected to an emission control line, the first electrode of the third switch transistor can be connected to a first power supply line, and the second electrode of the third switch transistor can be connected to the first electrode of the drive transistor. The control electrode of the fourth switch transistor can be connected to the emission control line, the first electrode of the fourth switch transistor can be connected to the second electrode of the drive transistor, and the second electrode of the fourth switch transistor can be connected to the first electrode of the light emitting element. The control electrode of the fifth switch transistor can be connected to a reset signal line, the first electrode of the fifth switch transistor can be connected to an initial signal line, and the second electrode of the fifth switch transistor can be connected to the first electrode of the second switch transistor. The control electrode of the sixth switch transistor can be connected to the reset signal line, the first electrode of the sixth switch transistor can be connected to the initial signal line, and the second electrode of the sixth switch transistor can be connected to the first electrode of the light emitting element. The first electrode of the storage capacitor can be connected to the control electrode of the drive transistor, and the second electrode of the storage capacitor can be connected to the first power supply line. In this example embodiment, the drive circuit of the sub-pixel can be a 7T1C structure (including 7 transistors and 1 capacitor). However, the present embodiment is not limited thereto. In some examples, the drive circuit of the sub-pixel can be a 2T1C structure, or a 3T1C structure, etc.

[0074] In some example embodiments, the reset signal line to which the control electrode of the fifth switch transistor is connected and the reset signal line to which the control electrode of the sixth switch transistor is connected can be respectively located on both sides of the scan line to which the control electrodes of the first and second switch transistors are connected. In some examples, the distance between the reset signal line to which the control electrode of the sixth switch transistor is connected and the scan line can be greater than the distance between the reset signal line to which the control electrode of the fifth switch transistor is connected and the scan line. However, the present embodiment is not limited thereto.

[0075] In some exemplary embodiments, the second electrodes of storage capacitors in adjacent sub-pixels located in the same row can be in direct contact. In some examples, the second electrodes of storage capacitors in adjacent sub-pixels located in the same row can be a single, integrated structure. However, this embodiment is not limited to this.

[0076] In some exemplary embodiments, the first electrode of the storage capacitor and the control electrode of the driving transistor can be an integral structure. The second electrode of the storage capacitor can have a hollowed-out region, and the orthographic projection of the control electrode of the driving transistor on the substrate can cover the orthographic projection of the hollowed-out region on the substrate. The first electrode of the second switching transistor can be connected to the control electrode of the driving transistor through the hollowed-out region.

[0077] In some exemplary embodiments, the display area may further include: a fifth conductive layer, a fifth insulating layer disposed between the fourth conductive layer and the fifth conductive layer, an organic light-emitting layer of a light-emitting element disposed on the side of the fifth conductive layer away from the substrate, and a second electrode. The fifth conductive layer may include a first electrode of the light-emitting element. The second electrode of the light-emitting element may be disposed on the side of the organic light-emitting layer away from the substrate. In some examples, the first electrode of the light-emitting element may be the anode of the light-emitting element, and the second electrode of the light-emitting element may be the cathode of the light-emitting element.

[0078] The following examples illustrate the display substrate provided in the embodiments of this disclosure.

[0079] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, the display substrate of this exemplary embodiment may include: a display area AA and a peripheral area located around the display area AA. The display area AA may be provided with a plurality of sub-pixels P arranged in a regular manner along a first direction (e.g., Figure 1 Multiple first signal lines (including scan lines and reset signal lines) extending in the X direction and multiple light emission control lines along the second direction (such as...) Figure 1 Multiple second signal lines (including data lines, first power lines, and initial signal lines) extending in the Y direction. The first and second directions can be located in the same plane, and the first direction can be perpendicular to the second direction. In this example, each first signal line can extend in the X direction, and the multiple first signal lines can be arranged sequentially in the Y direction; each second signal line can extend in the Y direction, and the multiple second signal lines can be arranged sequentially in the X direction.

[0080] like Figure 1As shown, M rows of scanning lines G1 to GM are arranged along the Y direction, and N columns of data lines D1 to DN are arranged along the X direction and insulated from each other. M and N are both integers greater than 0. The sub-pixels P can be distributed at the intersection positions of the M rows of scanning lines and the N columns of data lines, and the plurality of sub-pixels P are regularly arranged in a matrix. In some examples, three sub-pixels emitting different color lights (for example, red, green, and blue) or four sub-pixels emitting different color lights (for example, red, green, blue, and white) can constitute a pixel unit. However, the present embodiment is not limited thereto.

[0081] For the convenience of distinguishing the scanning lines and the rows of sub-pixels, in some examples, the rows are sequentially referred to as the 1st row, the 2nd row, …, and the Mth row from top to bottom. Figure 1 Similarly, for the convenience of distinguishing the data lines and the columns of sub-pixels, in some examples, the columns are sequentially referred to as the 1st column, the 2nd column, …, and the Nth column from left to right. Figure 1

[0082] In the present example embodiment, the peripheral region can be provided with a timing controller 10, a data driving circuit 11, a scanning driving circuit 12, and a light-emitting driving circuit 13. The scanning driving circuit 12 and the light-emitting driving circuit 13 can be respectively arranged on opposite sides (for example, left and right sides) of the display region AA, and the timing controller 10 and the data driving circuit 11 can be arranged on one side of the display region AA. However, the present embodiment is not limited thereto.

[0083] In the present example embodiment, the data driving circuit 11 can provide a data signal to the sub-pixels through the data lines. The scanning driving circuit 12 can provide a scanning signal to the sub-pixels through the scanning lines, and provide a reset signal to the sub-pixels through a reset signal line. The light-emitting driving circuit 13 can provide a light-emitting control signal to the sub-pixels through a light-emitting control line. The timing controller 10 can provide driving signals to the data driving circuit 11, the scanning driving circuit 12, and the light-emitting driving circuit 13. The actions of the scanning driving circuit 12, the data driving circuit 11, and the light-emitting driving circuit 13 can be controlled by the timing controller 10. The timing controller 10 can provide gray scale data specifying the gray scale at which the sub-pixels should display to the data driving circuit 11. The data driving circuit 11 can provide a data signal with a potential corresponding to the gray scale data of the sub-pixels to the sub-pixels of the row selected by the scanning driving circuit 12 through the data lines.

[0084] Figure 2 A structural schematic diagram of the scanning driving circuit of at least one embodiment of the present disclosure is shown. As shown in FIG. 2, the scanning driving circuit 12 can include a shift register 21, a reset signal line 22, a scanning line 23, and a light-emitting control line 24. Figure 2 ​As shown, the scan driving circuit of the present exemplary embodiment can include a plurality of cascaded shift register units. Wherein, a signal input end INPUT(1) of a first stage shift register unit is connected with an initial signal end STV, and an output end GP(i) of an i-th stage shift register unit is connected with a signal input end INPUT(i+1) of an (i+1)-th stage shift register unit. The output end GP(i) of the i-th stage shift register unit can provide a scanning signal to the sub-pixels of the i-th row through a scanning line, and provide a reset signal to the sub-pixels of the (i+1)-th row through a reset signal line. Wherein, i is an integer greater than 0.

[0085] Figure 3 An equivalent circuit diagram of any stage shift register unit of the scan driving circuit of at least one embodiment of the present disclosure is shown in FIG. 3. As shown, Figure 3 As shown, the shift register unit of the present exemplary embodiment can include a first transistor M1 to an eighth transistor M8, a first capacitor C1 and a second capacitor C2.

[0086] In this exemplary embodiment, the control electrode of the first transistor M1 is connected to the first clock signal terminal CLK1, the first terminal of the first transistor M1 is connected to the first voltage terminal VGL, and the second terminal of the first transistor M1 is connected to the first control node P1. The control electrode of the second transistor M2 is connected to the second control node P2, the first terminal of the second transistor M2 is connected to the first clock signal terminal CLK1, and the second terminal of the second transistor M2 is connected to the first control node P1. The control electrode of the third transistor M3 is connected to the first clock signal terminal CLK1, the first terminal of the third transistor M3 is connected to the signal input terminal INPUT, and the second terminal of the third transistor M3 is connected to the second control node P2. The control electrode of the fourth transistor M4 is connected to the first control node P1, the first terminal of the fourth transistor M4 is connected to the second voltage terminal VGH, and the second terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5. The control electrode of the fifth transistor M5 is connected to the second clock signal terminal CLK2, and the second terminal of the fifth transistor M5 is connected to the second control node P2. The control electrode of the sixth transistor M6 is connected to the first voltage terminal VGL, the first electrode of the sixth transistor M6 is connected to the second control node P2, and the second electrode of the sixth transistor M6 is connected to the third control node P3. The control electrode of the seventh transistor M7 is connected to the third control node P3, the first electrode of the seventh transistor M7 is connected to the second clock signal terminal CLK2, and the second electrode of the seventh transistor M7 is connected to the output terminal GP. The control electrode of the eighth transistor M8 is connected to the first control node P1, the first electrode of the eighth transistor M8 is connected to the second voltage terminal VGH, and the second electrode of the eighth transistor M8 is connected to the output terminal GP. The first electrode of the first capacitor C1 is connected to the output terminal GP, and the second electrode of the first capacitor C1 is connected to the third control node P3. The first electrode of the second capacitor C2 is connected to the second voltage terminal VGH, and the second electrode of the second capacitor C2 is connected to the first control node P1.

[0087] The following example uses P-type thin-film transistors, from M1 to M8. Figure 3 The operation of the shift register unit shown is illustrated by way of example. The operation of the first-stage shift register unit is used as an example for explanation. Figure 4 for Figure 3 The provided timing diagram for the shift register unit is shown. Figure 3 and Figure 4 As shown, the shift register unit of this exemplary embodiment may include eight transistor units (M1 to M8), two capacitor units (C1 and C2), three input terminals (INPUT, CLK1, CLK2), one output terminal (GP), and two voltage terminals (VGL, VGH). The first voltage terminal VGL can continuously provide a low-level signal, and the second voltage terminal VGH can continuously provide a high-level signal.

[0088] In the input stage S11, the input signal of the first clock signal terminal CLK1 is low, the first transistor M1 is turned on and the third transistor M3 is turned on. The first transistor M1 is turned on, and the input signal of the first voltage terminal VGL is low, so that the potential of the first control node P1 is pulled low; the third transistor M3 is turned on, and the input signal of the signal input terminal INPUT is low, so that the potential of the second control node P2 is pulled low, so that the second transistor M2 is turned on, which can further ensure that the potential of the first control node P1 is pulled low. Since the potential of the first control node P1 is pulled low, the fourth transistor M4 and the eighth transistor M8 are turned on. The eighth transistor M8 is turned on, and the input signal of the second voltage terminal VGH is high, so that the potential of the output terminal GP is pulled high. The input signal of the second clock signal terminal CLK2 is high, so that the fifth transistor M5 is turned off. The input signal of the first voltage terminal VGL is low, so that the sixth transistor M6 is turned on, and the potential of the third control node P3 is pulled low by the potential of the second control node P2, so that the seventh transistor M7 is turned on, which can further ensure that the potential of the output terminal GP is pulled high.

[0089] In the output stage S12, the input signal of the first clock signal terminal CLK1 is high, the first transistor M1 and the third transistor M3 are turned off, the potential of the second control node P2 remains low, the second transistor M2 is turned on, and the potential of the first control node P1 remains high. Moreover, under the action of the second capacitor C2, the first control node P2 can be further ensured to remain at a high level. Since the potential of the first control node P2 remains at a high level, the fourth transistor M4 and the eighth transistor M8 are turned off. The input signal of the second clock signal terminal CLK2 is low, and the fifth transistor M5 is turned on. The input signal of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, the potential of the third control node P3 is further pulled low by the second control node P2, so that the seventh transistor M7 is turned on, and the potential of the output terminal GP is pulled low by the input signal of the second clock signal terminal CLK2.

[0090] In the reset stage S13, the input signal of the first clock signal terminal CLK1 is low, the first transistor M1 and the third transistor M3 are turned on, and the potential of the first control node P1 is pulled low by the input signal of the first voltage terminal VGL; the input signal of the signal input terminal INPUT is high, the potential of the second control node P2 is pulled high, and the second transistor M2 is turned off. Since the potential of the first control node P1 is pulled low, the fourth transistor M4 and the eighth transistor M8 are turned on. The eighth transistor M8 is turned on, and the potential of the output terminal GP can be kept at high level because the input signal of the second voltage terminal VGH is high. The input signal of the second clock signal terminal CLK2 is high, and the fifth transistor M5 is turned off. The input signal of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, the potential of the third control node P3 is pulled high by the second control node P2, and the seventh transistor M7 is turned off.

[0091] In the first holding stage S14, the input signal of the first clock signal terminal CLK1 is high, the first switch transistor M4 and the third switch transistor M3 are turned off, the input signal of the signal input terminal INPUT is high, the potential of the second control node P2 is kept high, the second transistor M2 is turned off, and the potential of the first control node P1 is kept low. Since the potential of the first control node P1 is kept low, the fourth transistor M4 and the eighth transistor M8 are turned on, and the potential of the output terminal GP is kept high. The input signal of the second clock signal terminal CLK2 is low, and the fifth transistor M5 is turned on. The potential of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, the potential of the third control node P3 is kept high, and the seventh transistor M7 is turned off.

[0092] In the second holding stage S15, the input signal of the first clock signal terminal CLK1 is low, the first transistor M1 and the third transistor M3 are turned on, the input signal of the signal input terminal INPUT is high, the potential of the second control node P2 is kept high, the second transistor M2 is turned off, and the potential of the first control node P1 is kept low. Since the potential of the first control node P1 is kept low, the fourth transistor M4 and the eighth transistor M7 are turned on, and the potential of the output terminal GP is kept high. The input signal of the second clock signal terminal CLK2 is high, and the fifth transistor M5 is turned off. The potential of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, the potential of the third control node P3 is kept high, and the seventh transistor M7 is turned off.

[0093] After the second holding stage, the first holding stage and the second holding stage can be repeated until the input signal of the signal input terminal INPUT is low, and then the input stage is restarted.

[0094] In the present exemplary embodiment, at least one sub-pixel can include a light emitting element and a driving circuit for driving the light emitting element to emit light. The driving circuit can include a plurality of transistors and a storage capacitor. In the present example, the driving circuit of the sub-pixel can be a 7T1C structure (i.e., including seven transistors and one capacitor). However, the present embodiment is not limited thereto. In some examples, the driving circuit of the sub-pixel can be a 2T1C, or a 3T1C, etc. structure.

[0095] Figure 5 An equivalent circuit diagram of the driving circuit of at least one embodiment of the present disclosure is shown in FIG. 3. As shown in FIG. 3, the driving circuit of the present exemplary embodiment can include first to sixth switching transistors T1 to T6, a driving transistor DTFT, and a storage capacitor Cst. Figure 5

[0096] In the present exemplary embodiment, the control electrode of the driving transistor DTFT is connected with the first node N1, the first electrode of the driving transistor T3 is connected with the second node N2, and the second electrode of the driving transistor T3 is connected with the third node N3. The control electrode of the first switching transistor T1 is connected with the scan line G, the first electrode of the first switching transistor T1 is connected with the data line D, and the second electrode of the first switching transistor T1 is connected with the second node N2. The control electrode of the second switching transistor T2 is connected with the scan line G, the first electrode of the second switching transistor T2 is connected with the first node N1, and the second electrode of the second switching transistor T2 is connected with the third node N3. The control electrode of the third switching transistor T3 is connected with the light emitting control line EM, the first electrode of the third switching transistor T3 is connected with the first power supply line VDD, and the second electrode of the third switching transistor T3 is connected with the second node N2. The control electrode of the fourth switching transistor T4 is connected with the light emitting control line EM, the first electrode of the fourth switching transistor T4 is connected with the third node N3, and the second electrode of the fourth switching transistor T4 is connected with the anode of the light emitting element EL. The control electrode of the fifth switching transistor T5 is connected with the reset signal line RST, the first electrode of the fifth switching transistor T5 is connected with the initial signal line Vint, and the second electrode of the fifth switching transistor T5 is connected with the first node N1. The control electrode of the sixth switching transistor T6 is connected with the reset signal line RST, the first electrode of the sixth switching transistor T6 is connected with the initial signal line Vint, and the second electrode of the sixth switching transistor T6 is connected with the anode of the light emitting element EL. The first electrode of the storage capacitor Cst is connected with the first node N1, and the second electrode of the storage capacitor Cst is connected with the first power supply line VDD. The cathode of the light emitting element EL is connected with the second power supply line VSS.

[0097] The working process of the driving circuit provided in the present disclosure will be exemplarily described below, taking the first to sixth switching transistors T1 to T6 and the driving transistor DTFT all being P-type thin film transistors as an example. Figure 5 Figure 6 The working process of the driving circuit provided in the present disclosure will be exemplarily described below, taking the first to sixth switching transistors T1 to T6 and the driving transistor DTFT all being P-type thin film transistors as an example.​​Figure 5 A working timing diagram of the driving circuit is provided. As shown in the figure, the driving circuit involved in the present exemplary embodiment can include 6 switching transistors (T1-T6), 1 driving transistor (DTFT), 1 capacitor unit (Cst), 5 signal input terminals (D, G, EM, RST and Vint), 2 power supply terminals (VDD and VSS). Exemplarily, the first power supply line VDD can continuously provide a high-level signal, and the second power supply line VSS can continuously provide a low-level signal. Figure 5

[0098] In the reset stage S21, the scan line G inputs a high-level signal, and the first switching transistor T1 and the second switching transistor T2 are turned off. The light-emitting control line EM inputs a high-level signal, and the third switching transistor T3 and the fourth switching transistor T4 are turned off. The reset signal line RST inputs a low-level signal, and the fifth switching transistor T5 and the sixth switching transistor T6 are turned on, so as to provide the signal input by the initial signal line Vint to the first node N1 and the fourth node N4, so as to reset the first node N1 and the fourth node N4, thereby eliminating the influence of the previous frame signal.

[0099] In the write stage S22, the reset signal line RST inputs a high-level signal, and the fifth switching transistor T5 and the sixth switching transistor T6 are turned off. The light-emitting control line EM inputs a high-level signal, and the third switching transistor T3 and the fourth switching transistor T4 are turned off. The scan line G inputs a low-level signal, and the first switching transistor T1 and the second switching transistor T2 are turned on. The first switching transistor M1 is turned on, and the data signal input by the data line DATA is provided to the second node N2, at this time, the potential Vn2 of the second node N2 = Vdata, and Vdata is the voltage value of the data signal. The second switching transistor M2 is turned on, so as to connect the first node N1 and the third node N3, i.e. to connect the control electrode and the second electrode of the driving transistor DTFT, so as to write the data signal transmitted to the second node N2 and the threshold voltage Vth (i.e. the compensation signal) of the driving transistor DTFT into the first node N1, and charge the storage capacitor Cst at the same time, at this time, the potential Vn1 of the first node N1 = Vdata-Vth. Through the write stage S21, the data signal can be written into the control electrode of the driving transistor DTFT, and the threshold voltage of the driving transistor DTFT can be compensated, so as to eliminate the influence of the threshold voltage of the driving transistor DTFT on the driving current in the light-emitting stage.

[0100] ​In the light emitting stage S23, the reset signal line RST inputs a high level signal, the fifth switch transistor T5 and the sixth switch transistor T6 are cut off. The scan line G inputs a high level signal, the first switch transistor T1 and the second switch transistor T2 are cut off. The light emitting control line EM inputs a low level signal, the third switch transistor T3 and the fourth switch transistor T4 are turned on. The third switch transistor T3 is turned on, and the signal input by the first power supply line VDD is provided to the second node N2, at this time, Vn2=Vvdd. The driving transistor DTFT is turned on under the action of the signal (i.e. the data signal and the compensation signal) at the first node N1, and outputs a driving current under the action of the signal provided by the first power supply line VDD, to drive the light emitting element EL to emit light. Wherein, the potential of the first node N1 remains unchanged at Vdata-Vth under the action of the storage capacitor Cst, and the source-gate voltage of the driving transistor DTFT can be:

[0101] Vsg=Vn2-Vn1=Vvdd-Vdata+Vth.

[0102] According to the following transistor I-V curve equation:

[0103] I=K(Vsg-Vth) 2 =K(Vvdd-Vdata) 2 ;

[0104] Wherein, K is a fixed constant related to the process parameters and geometric size of the driving transistor DTFT.

[0105] Therefore, the driving current is irrelevant to the threshold voltage of the driving transistor DTFT, and the influence of the threshold voltage on the light emitting element EL is eliminated, so that the display uniformity and light emitting efficiency can be improved.

[0106] Figure 7 A top view of a sub-pixel of a display substrate of at least one embodiment of the present disclosure. Figure 8 A cross-sectional view in the Q-Q direction. Figure 7 A cross-sectional view in the Q-Q direction. Figure 7 A cross-sectional view in the Q-Q direction. Figure 8As shown, the display area of the display substrate provided by the present example embodiment can include a substrate 30, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially arranged on the substrate 30. The first insulating layer 32 can be arranged between the semiconductor layer and the first conductive layer, the second insulating layer 34 can be arranged between the first conductive layer and the second conductive layer, the third insulating layer 36 can be arranged between the second conductive layer and the third conductive layer, the fourth insulating layer 38 can be arranged between the third conductive layer and the fourth conductive layer, and the fifth insulating layer 40 can be arranged between the fourth conductive layer and the fifth conductive layer. The fifth conductive layer can include an anode 41 of a light-emitting element, and the fifth conductive layer can further include an organic light-emitting layer 43 and a cathode 44 of the light-emitting element.

[0107] Figure 9 FIG. 6 is a top view of a display substrate after forming a semiconductor layer in at least one embodiment of the present disclosure. As shown, the display area of the display substrate provided by the present example embodiment can include a substrate 30, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially arranged on the substrate 30. The first insulating layer 32 can be arranged between the semiconductor layer and the first conductive layer, the second insulating layer 34 can be arranged between the first conductive layer and the second conductive layer, the third insulating layer 36 can be arranged between the second conductive layer and the third conductive layer, the fourth insulating layer 38 can be arranged between the third conductive layer and the fourth conductive layer, and the fifth insulating layer 40 can be arranged between the fourth conductive layer and the fifth conductive layer. The fifth conductive layer can include an anode 41 of a light-emitting element, and the fifth conductive layer can further include an organic light-emitting layer 43 and a cathode 44 of the light-emitting element. Figure 7 to Figure 9 As shown, the fifth switch transistor T5, the second switch transistor T2, the first switch transistor T1, the drive transistor DTFT, the third switch transistor T3, the fourth switch transistor T4, and the sixth switch transistor T6 can be formed along the semiconductor layer as shown in FIG. 6. As shown, the semiconductor layer can have a curved or bent shape. The semiconductor layer can include an active layer 210 of the first switch transistor T1, an active layer 220 of the second switch transistor T2, an active layer 230 of the third switch transistor T3, an active layer 240 of the fourth switch transistor T4, an active layer 250 of the fifth switch transistor T5, an active layer 260 of the sixth switch transistor T6, and an active layer 270 of the drive transistor DTFT. Figure 9 As shown, the semiconductor layer can have a curved or bent shape. The semiconductor layer can include an active layer 210 of the first switch transistor T1, an active layer 220 of the second switch transistor T2, an active layer 230 of the third switch transistor T3, an active layer 240 of the fourth switch transistor T4, an active layer 250 of the fifth switch transistor T5, an active layer 260 of the sixth switch transistor T6, and an active layer 270 of the drive transistor DTFT. Figure 9 In the present example embodiment, the material of the active layer can include, for example, polysilicon or metal oxide. In some examples, the active layer can include a channel region, a first doped region, and a second doped region. The channel region can not be doped with impurities and have semiconductor properties. The first doped region and the second doped region can be on both sides of the channel region and doped with impurities and thus have electrical conductivity. The impurities can vary depending on the type of transistor.

[0108] In the present example embodiment, the first doped region or the second doped region of the active layer can be interpreted as the source electrode or the drain electrode of the transistor. For example, the source electrode of the drive transistor can correspond to the periphery of the channel region of the active layer, the first doped region doped with impurities; the drain electrode of the drive transistor can correspond to the periphery of the channel region of the active layer, the second doped region doped with impurities. In addition, the part of the active layer between the transistors can be interpreted as a wiring doped with impurities and can be used to electrically connect the transistors.

[0109]

[0110] Figure 10 ​FIG. 6 is a top view of a display substrate after forming a first conductive layer in at least one embodiment of the present disclosure. As shown in FIG. 6, the first conductive layer can include an emission control line EM, a control electrode 211 of a first switching transistor T1, control electrodes 221a and 221b of a second switching transistor T2, a control electrode 231 of a third switching transistor T3, a control electrode 241 of a fourth switching transistor T4, control electrodes 251a and 251b of a fifth switching transistor T5, a control electrode 261 of a sixth switching transistor T6, a control electrode 271 of a driving transistor DTFT, and a first electrode 281 of a storage capacitor Cst. Figure 7 to Figure 10

[0111] In the present exemplary embodiment, the control electrode 271 of the driving transistor DTFT and the first electrode 281 of the storage capacitor Cst can be an integral structure. The emission control line EM, the control electrode 231 of the third switching transistor T3, and the control electrode 241 of the fourth switching transistor T4 can be an integral structure. The control electrodes 221a and 221b of the second switching transistor T2 can be an integral structure. The control electrodes 251a and 251b of the fifth switching transistor T5 can be an integral structure.

[0112] Figure 11 FIG. 7 is a top view of a display substrate after forming a second conductive layer in at least one embodiment of the present disclosure. As shown in FIG. 7, the second conductive layer can include a second electrode 282 of the storage capacitor Cst. In the present exemplary embodiment, the second electrode 282 of the storage capacitor Cst can have a hollow region H. The orthogonal projection of the control electrode 271 of the driving transistor DTFT on the base 30 can cover the orthogonal projection of the hollow region H on the base 30. In some examples, the orthogonal projection of the hollow region H on the base 30 can be circular or polygonal. However, the present embodiment is not limited thereto. Figure 7 to Figure 11

[0113] FIG. 8 is a top view of a display substrate after forming a third conductive layer in at least one embodiment of the present disclosure. As shown in FIG. 8, the third conductive layer can include a scan line G, reset signal lines RSTa and RSTb, a first electrode 212 of the first switching transistor T1, a first electrode 222 of the second switching transistor T2, a first electrode 232 of the third switching transistor T3, a second electrode 243 of the fourth switching transistor T4, a first electrode 252 of the fifth switching transistor T5, and a first electrode 262 of the sixth switching transistor T6. Figure 12 Figure 7 to Figure 12 In the present exemplary embodiment, the scan line G can be parallel to the reset signal lines RSTa and RSTb, and the distance between the scan line G and the reset signal line RSTa can be less than the distance between the scan line G and the reset signal line RSTb.

[0114]

[0115] ​​​In the present exemplary embodiment, the scan line G can be connected with the control electrode 211 of the first switching transistor Tl through the first via hole K2 in the third insulating layer 36 and the second insulating layer 34. The scan line G can be connected with the control electrodes 221a and 221b of the second switching transistor Tl through the first via hole K3 in the third insulating layer 36 and the second insulating layer 34. The reset signal line RSTa can be connected with the control electrodes 251a and 251b of the fifth switching transistor T5 through the first via hole K10 in the third insulating layer 36 and the second insulating layer 34. The reset signal line RSTb can be connected with the control electrode 261 of the sixth switching transistor T6 through the first via hole K11 in the third insulating layer 36 and the second insulating layer 34.

[0116] In the present exemplary embodiment, the orthogonal projection of the scan line G on the substrate 30 can cover the orthogonal projection of the control electrode 211 of the first switching transistor Tl on the substrate 30, and can partially overlap with the orthogonal projections of the control electrodes 221a and 221b of the second switching transistor T2 on the substrate 30. The orthogonal projection of the reset signal line RSTa on the substrate 30 can partially overlap with the orthogonal projections of the control electrodes 251a and 251b of the fifth switching transistor T5 on the substrate 30. The orthogonal projection of the reset signal line RSTb on the substrate 30 can cover the orthogonal projection of the control electrode 261 of the sixth switching transistor T6 on the substrate 30.

[0117] In the present exemplary embodiment, the orthogonal projection of the scan line G on the substrate 30 can cover the orthogonal projections of the first via holes K2 and K3 on the substrate 30. The orthogonal projection of the reset signal line RSTa on the substrate 30 can cover the orthogonal projection of the first via hole K10 on the substrate 30. The orthogonal projection of the reset signal line RSTb on the substrate 30 can cover the orthogonal projection of the first via hole K11 on the substrate 30.

[0118] In this exemplary embodiment, the first electrode 212 of the first switching transistor T1 can be connected to the first doped region 210b of the active layer 210 of the first switching transistor T1 through a third via K1 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32. The first electrode 222 of the second switching transistor T2 can be connected to the first doped region 220b of the active layer 220 of the second switching transistor T2 through a third via K4 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32, and can also be connected to the control electrode 271 of the driving transistor DTFT through a first via K5 in the third insulating layer 36 and the second insulating layer 34. The first electrode 232 of the third switching transistor T3 can be connected to the first doped region 230b of the active layer 230 of the third switching transistor T3 through a third via K7 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32, and can also be connected to the second electrode 282 of the storage capacitor Cst through a fourth via K6 in the third insulating layer 36. The second terminal 243 of the fourth switching transistor T4 can be connected to the second doped region 240c of the active layer 240 of the fourth switching transistor T4 through the third via K8 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32. The first terminal 252 of the fifth switching transistor T5 can be connected to the first doped region 250b of the active layer 250 of the fifth switching transistor T5 through the third via K9 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32. The first terminal 262 of the sixth switching transistor T6 can be connected to the first doped region 260b of the active layer 260 of the sixth switching transistor T6 through the third via K12 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32.

[0119] Figure 13 This is a top view showing the formation of a fourth conductive layer in at least one embodiment of this disclosure. Figure 7 to Figure 13 As shown, the fourth conductive layer may include: a connecting electrode 291, a data line D, a first power line VDD, and an initial signal line Vint. The data line D, the first power line VDD, and the initial signal line Vint extend in parallel directions, all parallel to the second direction. The width of the first power line VDD along the first direction may be greater than the width of the initial signal line Vint along the first direction, and the width of the initial signal line Vint along the first direction may be greater than the width of the first power line VDD along the first direction.

[0120] In the present exemplary embodiment, the data line D can be connected to the first electrode 212 of the first switching transistor Tl through a second via hole K14 in the fourth insulating layer 38. The first power line VDD can be connected to the first electrode 232 of the third switching transistor T3 through second via holes K17, K18 and K19 in the fourth insulating layer 38. In the present exemplary embodiment, by providing a plurality of second via holes in the fourth insulating layer 38 to connect the first electrode 232 of the third switching transistor T3 and the first power line VDD, it is possible to ensure that a stable power signal is provided. The initial signal line Vint can be connected to the first electrode 252 of the fifth switching transistor T5 through a second via hole K15 in the fourth insulating layer 38, and can be connected to the first electrode 262 of the sixth switching transistor T6 through a second via hole K16 in the fourth insulating layer 38.

[0121] In the present exemplary embodiment, the connection electrode 291 can be connected to the second electrode 243 of the fourth switching transistor T4 through a second via hole K20 in the fourth insulating layer 38. The connection electrode 291 can also be connected to the anode 41 of the light emitting element through a fifth via hole K21 in the fifth insulating layer 40.

[0122] In the present exemplary embodiment, the storage capacitor Cst can include a first electrode 281 and a second electrode 282 with the second insulating layer 34 therebetween. The first electrode 281 of the storage capacitor Cst can also serve as the control electrode of the drive transistor DTFT. In the present exemplary embodiment, the control electrode 271 of the drive transistor DTFT and the first electrode 281 of the storage capacitor Cst can be in an integral structure.

[0123] In the present exemplary embodiment, the drive transistor DTFT can include an active layer 270 and a control electrode 271. The active layer 270 of the drive transistor DTFT can include a first doped region 270b, a second doped region 270c and a channel region 270a connecting the first doped region 270b and the second doped region 270c. The control electrode 271 can also serve as the first electrode 281 of the storage capacitor Cst. The channel region 270a of the active layer 270 of the drive transistor DTFT can overlap the control electrode 271 in a normal projection on the substrate 30. The first doped region 270b and the second doped region 270c extend in two directions with respect to the channel region 270a. The first doped region 270b of the drive transistor DTFT is connected to the second doped region 210c of the active layer 210 of the first switching transistor Tl. The second doped region 270c of the drive transistor DTFT is connected to the second doped region 220c of the active layer 220 of the second switching transistor T2 and the first doped region 240b of the active layer 240 of the fourth switching transistor T4.

[0124] In the present exemplary embodiment, the first switch transistor T1 can include an active layer 210, a control electrode 211, and a first electrode 212. The active layer 210 of the first switch transistor T1 can include a first doped region 210b, a second doped region 210c, and a channel region 210a connecting the first doped region 210b and the second doped region 210c. The second doped region 210c of the first switch transistor T1 can be connected to the first doped region 270b of the active layer 270 of the driving transistor DTFT. The first doped region 210b of the first switch transistor T1 can be connected to the first electrode 212 of the first switch transistor T1 through a third via K1 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 212 of the first switch transistor T1 can be connected to the data line D through a second via K14 in the fourth insulating layer 38. The control electrode 211 of the first switch transistor T1 can be connected to the scan line G through a first via K2 in the second insulating layer 34 and the third insulating layer 36.

[0125] In the present exemplary embodiment, the second switch transistor T2 can include an active layer 220, control electrodes 221a and 221b, and a first electrode 222. The active layer 220 can include channel regions 220a1, 220a2, 220a3, a first doped region 220b, and a second doped region 220c. The channel region 220a1 corresponds to the control electrode 221a, the channel region 220a3 corresponds to the control electrode 221b, and the channel region 220a2 is located between 220a1 and 220a3. The first doped region 220b of the second switch transistor T2 can be connected to the second doped region 250c of the fifth switch transistor T5. The first doped region 220b can be connected to the first electrode 222 of the second switch transistor T2 through a third via K4 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 222 of the second switch transistor T2 can be connected to the control electrode 271 of the driving transistor DTFT through a first via K5 in the third insulating layer 36 and the second insulating layer 34. The control electrodes 221a and 221b of the second switch transistor T2 can be connected to the scan line G through a first via K3 in the second insulating layer 34 and the third insulating layer 36. In the present example, the second switch transistor T2 can be used to prevent and reduce the occurrence of leakage current by being provided with double control electrodes.

[0126] In the present exemplary embodiment, the third switch transistor T3 can include an active layer 230, a control electrode 231, and a first electrode 232. The active layer 230 can include a channel region 230a, a first doped region 230b, and a second doped region 230c. The first doped region 230b of the third switch transistor T3 can be connected to the first electrode 232 through a third via hole K7 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 232 of the third switch transistor T3 can be connected to the first power line VDD through second via holes K17, K18, and K19 in the fourth insulating layer 38. The first electrode 232 of the third switch transistor T3 can also be connected to the second electrode 282 of the storage capacitor Cst through a fourth via hole K6 in the third insulating layer 36. The control electrode 231 of the third switch transistor T3 can be in one body structure with the light emission control line EM.

[0127] In the present exemplary embodiment, the fourth switch transistor T4 can include an active layer 240, a control electrode 241, and a second electrode 243. The active layer 240 of the fourth switch transistor T4 can include a channel region 240a, a first doped region 240b, and a second doped region 240c. The first doped region 240b of the fourth switch transistor T4 can be connected to the second doped region 270c of the driving transistor DTFT and the second doped region 220c of the second switch transistor T2, respectively. The second doped region 240c of the fourth switch transistor T4 can be connected to the second electrode 243 of the fourth switch transistor T4 through a third via hole K8 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The second electrode 243 of the fourth switch transistor T4 can be connected to the connection electrode 291 through a second via hole K20 in the fourth insulating layer 38. The connection electrode 291 can be connected to the anode 41 of the light emitting element through a fifth via hole K21 in the fifth insulating layer 40.

[0128] In this exemplary embodiment, the fifth switching transistor T5 may include an active layer 250, control electrodes 251a and 251b, and a first electrode 252. The active layer 250 may include channel regions 250a1, 250a2, and 220a3, a first doped region 250b, and a second doped region 250c. Channel region 250a1 corresponds to control electrode 251a, channel region 250a3 corresponds to control electrode 251b, and channel region 250a2 is located between 250a1 and 250a3. The first doped region 250b may be connected to the first doped region 220b of the second switching transistor T2. The first doped region 250b of the fifth switching transistor T5 may be connected to the second electrode 252 through a third via K9 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The control electrodes 251a and 251b of the fifth switching transistor T5 can be connected to the reset signal line RSTa through the first via K10 in the second insulating layer 34 and the third insulating layer 36. In this example, the fifth switching transistor T5, by providing dual control electrodes, can be used to prevent and reduce leakage current.

[0129] In this exemplary embodiment, the sixth switching transistor T6 may include an active layer 260, a control electrode 261, and a first electrode 262. The active layer 260 may include a channel region 260a, a first doped region 260b, and a second doped region 260c. The first doped region 260b of the sixth switching transistor T6 can be connected to the first electrode 262 via a third via K12 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 262 of the sixth switching transistor T6 can be connected to the initial signal line Vint via a second via K16 in the fourth insulating layer 38. The second doped region 260c of the sixth switching transistor T6 can be connected to the second doped region 240c of the fourth switching transistor T4. The control electrode 261 of the sixth switching transistor T6 can be connected to the reset signal line RSTb via a first via K11 in the second insulating layer 34 and the third insulating layer 36.

[0130] Figure 14 This is a top view of a plurality of sub-pixels in a display substrate according to at least one embodiment of the present disclosure. Figure 14 As shown, a row of sub-pixels can be connected to the reset signal lines RSTa and RSTb of the same row, as well as the scan line G of the same row. A column of sub-pixels can be connected to the data line D of the same column, as well as the first wire VDD of the same column. The first electrode 252 of the fifth switching transistor T5 of multiple sub-pixels can be a single integrated structure, connected to the initial signal line Vint through the second via K15. The first electrode 262 of the sixth switching transistor T6 of multiple sub-pixels can be a single integrated structure, connected to the initial signal line Vint through the second via K16. In this example, each row of sub-pixels can share one initial signal line Vint. However, this embodiment is not limited to this.

[0131] In the present exemplary embodiment, the second electrodes 282 of the storage capacitors Cst of the plurality of sub-pixels can be a unitary structure. However, the present embodiment is not limited thereto. In some examples, the second electrodes of the storage capacitors Cst of the plurality of sub-pixels can be independent structures in direct contact. By providing the second electrodes of the storage capacitors of the plurality of sub-pixels in direct contact, stable power signals can be transmitted between the plurality of sub-pixels.

[0132] Reference will now be made to Figure 7 to Figure 14 The preparation process of the display substrate of the present exemplary embodiment will be described. The "patterning process" in the present embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, and the like, which are known mature preparation processes. The deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, the coating can use known coating processes, and the etching can use known methods, which are not limited herein. In the description of the present embodiment, it should be understood that "thin film" refers to a thin film of a certain material deposited on a substrate using deposition or other processes.

[0133] The preparation process of the display substrate of the present exemplary embodiment can include the following steps.

[0134] Step 100, providing a substrate, depositing a semiconductor thin film on the substrate, and processing the semiconductor thin film using a patterning process to form a semiconductor layer, as shown in Figure 9 .

[0135] In the present exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can include one or more of glass, metal foil. The flexible substrate can include one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0136] In the present exemplary embodiment, the material for making the semiconductor layer can be polysilicon or metal oxide, which is not limited in the present embodiment.

[0137] Step 200, depositing a first insulating thin film on the semiconductor layer, processing the first insulating thin film using a patterning process to form a first insulating layer, depositing a first conductive thin film on the first insulating layer, and processing the first conductive thin film using a patterning process to form a first conductive layer, as shown in Figure 10 .

[0138] In the present exemplary embodiment, the first conductive layer can include an emission control line EM, a control electrode 211 of the first switching transistor Tl, control electrodes 221a and 221b of the second switching transistor T2, a control electrode 231 of the third switching transistor T3, a control electrode 241 of the fourth switching transistor T4, control electrodes 251a and 251b of the fifth switching transistor T5, a control electrode 261 of the sixth switching transistor T6, a control electrode 271 of the driving transistor DTFT, and a first electrode 281 of the storage capacitor Cst.

[0139] In the present exemplary embodiment, the first conductive film can employ a metal material such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or the like, or an alloy material of the above-mentioned metals such as an aluminum-niobium alloy (AlNd), a molybdenum-niobium alloy (MoNb), or the like, can be a multi-layer stacked structure such as Mo / Cu / Mo, Mo / Al / Mo, or the like, or can be a stacked structure formed of a metal and a transparent conductive material such as ITO / Ag / ITO, or the like. The first insulating film can employ silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like, or can employ a high dielectric constant (High k) material such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), or the like, can be a single layer, a multi-layer, or a composite layer. Generally, the first insulating layer 32 can be referred to as a gate insulating (GI) layer.

[0140] Step 300, depositing a second insulating film on the first conductive layer, processing the second insulating film using a patterning process to form a second insulating layer, depositing a second conductive film on the second insulating layer, processing the second conductive film using a patterning process to form a second conductive layer, as shown in Figure 11

[0141] In the present exemplary embodiment, the second conductive layer can include a second electrode 282 of the storage capacitor Cst.

[0142] In the present exemplary embodiment, the second conductive film can employ a metal material such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or the like, or an alloy material of the above-mentioned metals such as an aluminum-niobium alloy (AlNd), a molybdenum-niobium alloy (MoNb), or the like, can be a multi-layer stacked structure such as Mo / Cu / Mo, Mo / Al / Mo, or the like, or can be a stacked structure formed of a metal and a transparent conductive material such as ITO / Ag / ITO, or the like. The second insulating film can employ silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like, or can employ a high dielectric constant (High k) material such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), or the like, can be a single layer, a multi-layer, or a composite layer. Generally, the second insulating layer 34 can be referred to as a gate insulating (GI) layer. ​

[0143] Step 400, forming a third insulating thin film on the second conductive layer, processing the third insulating thin film by a patterning process to form a third insulating layer, depositing a third conductive thin film on the third insulating layer, processing the third conductive thin film by a patterning process to form a third conductive layer, as shown in Figure 12 .

[0144] In the present exemplary embodiment, the third conductive layer can include: a scan line G, reset signal lines RSTa and RSTb, a first electrode 212 of a first switch transistor Tl, a first electrode 222 of a second switch transistor T2, a first electrode 232 of a third switch transistor T3, a second electrode 243 of a fourth switch transistor T4, a first electrode 252 of a fifth switch transistor T5, and a first electrode 262 of a sixth switch transistor T6.

[0145] In the present exemplary embodiment, the third conductive thin film can be made of a metal material, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), etc., or an alloy material of the above-mentioned metals, such as aluminum-niobium alloy (AlNd), molybdenum-niobium alloy (MoNb), etc., can be a multi-layer stack structure, such as Ti / Al / Ti, etc., or can be a stack structure formed of a metal and a transparent conductive material, such as ITO / Ag / ITO, etc. The third insulating thin film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of a high dielectric constant (High k) material, such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., can be a single layer, a multi-layer, or a composite layer. Generally, the third insulating layer 36 can be referred to as an interlayer insulating layer.

[0146] Step 500, forming a fourth insulating thin film on the third conductive layer, processing the fourth insulating thin film by a patterning process to form a fourth insulating layer, depositing a fourth conductive thin film on the fourth insulating layer, processing the fourth conductive thin film by a patterning process to form a fourth conductive layer, as shown in Figure 13 .

[0147] In the present exemplary embodiment, the fourth conductive layer can include: a connection electrode 291, a data line D, a first power supply line VDD, and an initial signal line Vint.

[0148] In the present exemplary embodiment, the fourth conductive thin film can employ a metal material such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or an alloy material of the above-mentioned metals such as aluminum-niobium alloy (AlNd), molybdenum-niobium alloy (MoNb), etc., can be a multi-layer stack structure such as Mo / Cu / Mo, Mo / Al / Mo, etc., or can be a stack structure of a metal and a transparent conductive material such as ITO / Ag / ITO, etc. The fourth insulating thin film can employ silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can employ a high dielectric constant (High k) material such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., can be a single layer, a multi-layer, or a composite layer.

[0149] Step 600, forming a fifth insulating layer on the fourth conductive layer, depositing a fifth conductive thin film on the fifth insulating layer, and processing the fifth conductive thin film by a patterning process to form a fifth conductive layer; coating a pixel definition thin film on the fifth conductive layer, and forming a pixel definition layer 42 pattern by mask exposure and development to define an opening area exposing the anode 41 of the light emitting element. An organic light emitting layer 43 is formed in the opening area, a sixth conductive thin film is deposited on the organic light emitting layer, and a cathode 44 of the light emitting element is formed by processing the sixth conductive thin film by a patterning process, as shown in FIG. 4B. Figure 8

[0150] In the present exemplary embodiment, the fifth insulating layer can include an inorganic insulating layer and an organic insulating layer stacked. The material of the inorganic insulating layer can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.; and the material of the organic insulating layer can include polyimide, acrylic, polyethylene terephthalate, etc.

[0151] In the present exemplary embodiment, the pixel definition thin film can employ polyimide, acrylic, polyethylene terephthalate, etc.

[0152] In the present exemplary embodiment, the organic light emitting layer 43 can mainly include an emitting layer (EML). In some examples, the organic light emitting layer can include a hole injection layer, a hole transport layer, an emitting layer, an electron transport layer, and an electron injection layer arranged in sequence to improve the efficiency of injecting electrons and holes into the light emitting layer.

[0153] ​In some examples, the anode 41 of the light-emitting element may be made of at least one transparent conductive material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). The cathode 44 of the light-emitting element may be made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. However, this embodiment is not limited in this respect.

[0154] In the display substrate provided in this exemplary embodiment, a scan line G (for providing scan signals to sub-pixels) and a reset signal line (for providing reset signals to sub-pixels), which are connected to the scan driving circuit and extend along a first direction, are disposed in a third conductive layer. The signals transmitted by the scan line and reset signal line are transmitted back to the first conductive layer via a perforation method, thereby achieving connection with the control electrode of the transistor disposed in the first conductive layer. By disposing the scan line and reset signal line in the same layer as the first and second electrodes of the transistor, this exemplary embodiment reduces the impedance of the scan line and reset signal line extending along the first direction, thereby reducing the gate drive delay time, increasing the charging rate of the display substrate, and consequently improving the resolution and refresh rate of the display substrate. Furthermore, by disposing the first power line VDD, data line D, and initial signal line Vint extending along a second direction in a fourth conductive layer, direct intersection with the scan line and reset signal line can be avoided.

[0155] Figure 15 This is a simulation schematic diagram of the gate driving of a display substrate according to at least one embodiment of the present disclosure. Figure 15 As shown, the first signal line within the display area of ​​the display substrate used to transmit signals provided by the scan driving circuit to the sub-pixels can be represented by a simulation circuit including resistors and capacitors. In this example, a circuit including four resistors R and three capacitors C can be used to simulate the first signal line transmitting signals within the display area. The four resistors are connected in series from the output terminal GP of the shift register unit, and one end of a capacitor C is connected between two adjacent resistors, with the other end of the capacitor C grounded. However, this embodiment is not limited to this. In some examples, the simulation circuit for the first signal line within the display area may include five resistors R and four capacitors C.

[0156] In one example, when the first signal line in the display area is disposed in the same layer as the control electrode of the transistor, and the material of the control electrode layer can be, for example, Mo / Al / Mo, the simulated total resistance of the first signal line in the display area is 54.32 kΩ and the total capacitance is 175.95 pF. When the first signal line in the display area is disposed in the same layer as the first and second electrodes of the transistor, and the material of this layer can be, for example, Ti / Al / Ti, the simulated total resistance of the first signal line in the display area is 4.12 kΩ and the total capacitance is 161.49 pF. Therefore, this exemplary embodiment, by disposing the first signal line in the same layer as the first and second electrodes of the transistor, can significantly reduce the resistance on the first signal line and significantly reduce the impedance of the gate electrode layer.

[0157] Figure 16 include Figure 16 (a) and Figure 16 (b) shows a schematic diagram of the gate drive delay. Figure 16 (a) shows a schematic diagram of the gate drive delay when the first signal line and the control electrode of the transistor are set on the same layer. Figure 16 (b) shows a schematic diagram of the gate drive delay when the first signal line is set on the same layer as the first and second poles of the transistor. Figure 16 (a) and Figure 16 (b) for in Figure 15 The diagram shows simulated gate drive delays under the conditions of a first power supply terminal VGH = 7V and a second power supply terminal VGL = -7V for the shift register unit shown. Figure 16 As shown in (a), when the first signal line is disposed on the same layer as the control electrode of the transistor, the falling edge duration Tr1 = 2.3 microseconds (μs), the rising edge duration Tf1 = 2.38 μs, and the signal delay duration is 4.68 μs. Figure 16(b) As shown, when the first signal line is arranged in the same layer as the first electrode and the second electrode of the transistor, the falling edge duration of the signal transmitted by the first signal line is Tr2=0.27 μs, the rising edge duration is Tf2=0.26 μs, and the signal delay duration is 0.53 μs. For a display substrate with a resolution of 2560*1920 and a refresh frequency of 60 Hz, the duration of one frame scanning is 1 / 60 Hz=16.67 ms, and the duration of one line scanning is 16.67 ms / 1920=8.6 us. The effective charging duration of the sub-pixel in the display substrate in which the first signal line is arranged in the same layer as the control electrode of the transistor is 8.6-4.68=3.92 μs, while the effective charging duration of the sub-pixel in the display substrate in which the first signal line is arranged in the same layer as the first electrode and the second electrode of the transistor can be 8.6-0.53=8.07 μs. It can be seen that the display substrate provided in the embodiment can greatly prolong the effective charging duration by arranging the first signal line in the same layer as the first electrode and the second electrode of the transistor, thereby meeting the requirement of high resolution.

[0158] In some examples, the driving circuit of the sub-pixel is simulated under the condition that VGH=7 V, VGL=-7 V, and the data voltage value Vb=2.56 V. The charging ratio of the display substrate of the present example embodiment can be obtained according to the simulation result of the driving circuit of the sub-pixel and the charging ratio formula. The charging ratio formula is:

[0159]

[0160] wherein, VG Light_on represents the voltage of the control electrode of the driving transistor DTFT, i.e., the potential of the first node N1 in the driving circuit when the light emitting element is lighted; Vinit represents the voltage value provided by the initial signal line Vint; VData Light_on represents the data voltage value provided by the data line D when the light emitting element is lighted, and Vth represents the threshold voltage of the driving transistor DTFT.

[0161] For example, when a pixel includes RGB sub-pixels, according to simulation results, when the first signal line and the gate electrode of the display substrate with a resolution of 2560*1920 and a refresh frequency of 60 Hz are arranged in the same layer, the charging rates of the R, G, and B sub-pixels are 71.2%, 70.3%, and 68%, respectively. Since the charging rates are all less than 75%, it indicates that the charging rate of the display substrate with the first signal line and the gate electrode arranged in the same layer is insufficient at 60 Hz, and cannot meet the product requirements. According to simulation results, when the first signal line and the source-drain electrode of the display substrate with a resolution of 2560*1920 and a refresh frequency of 60 Hz are arranged in the same layer, the charging rates of the R, G, and B sub-pixels are 85%, 85%, and 84%, respectively. Since the charging rates are all greater than 75%, it indicates that the charging rate of the display substrate provided in this example embodiment is sufficient at 60 Hz. Moreover, simulation is performed on the display substrate with a resolution of 2560*1920 and a refresh frequency of 90 Hz. According to simulation results, the charging rates of the R, G, and B sub-pixels of the display substrate provided in this example embodiment are 78.9%, 79.4%, and 78.1%, respectively. Since the charging rates are all greater than 75%, it indicates that the charging rate of the display substrate provided in this example embodiment is relatively sufficient at 90 Hz. Therefore, the display substrate provided in this example embodiment can improve the refresh frequency.

[0162] Figure 17 A flowchart of a preparation method of a display substrate provided in at least one embodiment of the present disclosure is shown. As shown in Figure 17 The preparation method of the display substrate provided in at least one embodiment of the present disclosure is used to prepare the display substrate as described above, and includes the following steps: step S1, providing a substrate; and step S2, sequentially forming a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer on the substrate in a display area. The semiconductor layer can include active layers of a plurality of transistors. The first conductive layer can include control electrodes of the plurality of transistors and first electrodes of storage capacitors. The second conductive layer can include second electrodes of the storage capacitors. The third conductive layer can include a plurality of first signal lines and first electrodes and second electrodes of the plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer can be provided with a first via hole, and the first signal line can contact the control electrode of the transistor exposed by the first conductive layer through the first via hole.

[0163] In some example embodiments, the preparation method further includes: forming a fourth conductive layer on a side of the third conductive layer away from the substrate. The fourth conductive layer can include a plurality of second signal lines extending along a second direction perpendicular to the first direction. An insulating layer between the fourth conductive layer and the third conductive layer can be provided with a second via hole, and the second signal line can contact the first electrode or the second electrode of the transistor exposed by the third conductive layer through the second via hole.

[0164] In some exemplary embodiments, forming a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially on a substrate may include: forming a semiconductor layer and a first insulating layer sequentially on the substrate; forming a first conductive layer and a second insulating layer sequentially on the first insulating layer; forming a second conductive layer and a third insulating layer sequentially on the second insulating layer; forming a third conductive layer and a fourth insulating layer sequentially on the third insulating layer; and forming a fourth conductive layer on the fourth insulating layer.

[0165] In some exemplary embodiments, after forming the fourth conductive layer, the preparation method of this embodiment may further include: forming a fifth insulating layer on the fourth conductive layer; sequentially forming a fifth conductive layer, an organic light-emitting layer of the light-emitting element, and a second electrode on the fifth insulating layer; the fifth conductive layer includes a first electrode of the light-emitting element.

[0166] The fabrication process of the display substrate provided in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0167] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 18 As shown, at least one embodiment of this disclosure provides a display device 91, including a display substrate 910. The display substrate 910 can be the display substrate provided in the foregoing embodiments, and its implementation principle and effect are similar, so it will not be described again here. In some examples, the display substrate 910 can be an OLED display substrate. In some examples, the display device 91 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment is not limited to this.

[0168] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: The display area includes a plurality of sub-pixels disposed on a substrate, a plurality of first signal lines extending along a first direction, and a plurality of data lines extending along a second direction; at least one sub-pixel includes a driving circuit, the driving circuit including a plurality of transistors and at least one storage capacitor; the transistor includes at least a first conductive layer and a second conductive layer; the first direction is perpendicular to the second direction; The plurality of first signal lines are located in the third conductive layer, which is located on the side of the control electrode of the transistor of the driving circuit away from the substrate; The plurality of first signal lines include a plurality of scan lines and a reset signal line; The first conductive layer is located between the substrate and the third conductive layer; The first conductive layer further includes: a plurality of light-emitting control lines; the third conductive layer includes: a three-layer stacked structure formed of titanium, aluminum and titanium, wherein the material of the first conductive layer is different from the material of the third conductive layer.

2. The display substrate according to claim 1, characterized in that, The third conductive layer includes the first or second electrode of at least one transistor of the driving circuit.

3. The display substrate according to claim 1, characterized in that, The first signal line located in the third conductive layer transmits a signal to at least one sub-pixel through the first conductive layer.

4. The display substrate according to claim 3, characterized in that, The first conductive layer includes the control electrode of at least one transistor of the driving circuit; the first signal line is connected to the control electrode of at least one transistor of the driving circuit.

5. The display substrate according to claim 1, characterized in that, The display area also includes a plurality of first power lines extending along the second direction, the data lines and the first power lines being located on the side of the storage capacitor closest to the substrate and furthest from the substrate.

6. The display substrate according to claim 5, characterized in that, The display area further includes at least one power connection portion electrically connected to the first power line; The orthographic projection of the first power line on the substrate and the orthographic projection of the power connection portion on the substrate at least partially overlap.

7. The display substrate according to claim 6, characterized in that, The display area further includes: a fourth conductive layer disposed on the substrate, and at least one conductive layer between the fourth conductive layer and the first conductive layer.

8. The display substrate according to claim 7, characterized in that, The power connection portion is located in at least one conductive layer between the first conductive layer and the fourth conductive layer.

9. The display substrate according to claim 8, characterized in that, The power connection portion is located in the second conductive layer.

10. The display substrate according to claim 9, characterized in that, A third insulating layer is provided between the second conductive layer and the third conductive layer, and the first power line is electrically connected to the power connection part at least through a via formed in the third insulating layer.

11. The display substrate according to any one of claims 6 to 10, characterized in that, The power connection portion is electrically connected to the first electrode of the third switching transistor of the drive circuit.

12. The display substrate according to claim 11, characterized in that, The power connection part and the second electrode of the storage capacitor are an integral structure.

13. The display substrate according to claim 6, characterized in that, In the second direction, the power connection portion, in the orthographic projection of the substrate, is located between the orthographic projection of at least one scan line connected to the same row of sub-pixels and the reset signal line on the substrate.

14. The display substrate according to claim 6, characterized in that, The at least one power connection portion is connected to a plurality of sub-pixels.

15. The display substrate according to claim 14, characterized in that, The at least one power connection portion is simultaneously electrically connected to at least two of the three sub-pixels.

16. The display substrate according to claim 15, characterized in that, The plurality of sub-pixels includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel; The at least one power connection portion is electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.

17. The display substrate according to claim 16, characterized in that, The first sub-pixel is red, the second sub-pixel is green, and the third sub-pixel is blue.

18. The display substrate according to claim 5, characterized in that, The first power line forms a double-layer trace with the adjacent conductive layer in the area where the sub-pixel is located.

19. The display substrate according to claim 18, characterized in that, The double-layered trace portion of the first power line at least partially overlaps with the orthographic projection of the storage capacitor in the first direction.

20. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 19.

Images