A method of manufacturing a semiconductor device and a semiconductor device

Abstract

The embodiments of the present disclosure disclose a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises: providing a substrate, forming a gate trench on the substrate; forming a gate structure in the gate trench, the gate structure comprising a gate electrode located in the gate trench and a gate insulating layer located between the gate electrode and the gate trench; injecting fluorine ions to one side surface of the substrate where the gate structure is formed, and performing annealing to form a first doped region at the junction of at least part of the substrate and the gate insulating layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] In dynamic random access memory (DRAM) devices, as the feature size of MOS devices continues to shrink at a certain ratio, some field effects associated with MOS devices become increasingly higher, leading to serious problems such as increased leakage current in the gate and source / drain regions and short data retention time. This has a particularly significant impact on the performance of low-power DRAM products. Summary of the Invention

[0003] In view of the above, this disclosure provides a method for fabricating a semiconductor device and a semiconductor device thereof.

[0004] According to a first aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising:

[0005] A substrate is provided, on which gate trenches are formed;

[0006] A gate structure is formed within the gate trench, the gate structure including a gate electrode located within the gate trench and a gate insulating layer located between the gate electrode and the gate trench;

[0007] Fluorine ions are implanted into the surface of the substrate on one side where the gate structure is formed, and the substrate is annealed to form a first doped region at at least a portion of the junction between the substrate and the gate insulating layer.

[0008] In some embodiments, Si-F bonds are formed in the first doped region.

[0009] In some embodiments, implanting fluorine ions into the side surface of the substrate where the gate structure is formed includes:

[0010] The energy of the injected fluoride ions is 2 keV-50 keV, and the dose of the injected fluoride ions is 1 × 10⁻⁶. 11 pcs / cm 2 -1×10 16 pcs / cm 2 .

[0011] In some embodiments, the process of implanting fluorine ions into the side surface of the substrate on which the gate structure is formed and annealing it further includes: forming a second doped region at at least a portion of the junction between the gate insulating layer and the gate electrode; the second doped region forming Si-F bonds.

[0012] In some embodiments, the reaction gas used in the annealing process is N2, and the N2 gas flow rate is 100-1000 sccm.

[0013] In some embodiments, the temperature range of the reaction chamber where the annealing process is performed is 700°C to 1000°C.

[0014] In some embodiments, it also includes:

[0015] The O2 content in the reaction chamber where the annealing process is performed is less than 5 ppm.

[0016] In some embodiments, it also includes:

[0017] After annealing, the semiconductor device is removed from the reaction chamber, and the temperature outside the reaction chamber is controlled to be less than 350°C.

[0018] In some embodiments, the gate electrode includes a second gate electrode layer and a first gate electrode layer located between the second gate electrode layer and the gate insulating layer; the first gate electrode layer includes titanium nitride, and the second gate electrode layer includes tungsten metal.

[0019] In some embodiments, it also includes:

[0020] After annealing, the surface of the second gate electrode layer on the side implanted with fluorine ions is etched to remove part of the second gate electrode layer.

[0021] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising:

[0022] A substrate in which gate trenches are formed;

[0023] A gate structure is located within the gate trench; the gate structure includes a gate electrode located within the gate trench and a gate insulating layer located between the gate electrode and the gate trench;

[0024] A first doped region is located at at least a portion of the boundary between the substrate and the gate insulating layer; the first doped region contains fluorine.

[0025] In some embodiments, the first doped region contains fluorine, including:

[0026] Si-F bonds are formed in the first doped region.

[0027] In some embodiments, it also includes:

[0028] The second doped region is located at at least a portion of the boundary between the gate insulating layer and the gate electrode; the second doped region has Si-F bonds formed.

[0029] In some embodiments, the gate electrode includes a second gate electrode layer and a first gate electrode layer located between the second gate electrode layer and the gate insulating layer; the first gate electrode layer includes titanium nitride, and the second gate electrode layer includes tungsten metal.

[0030] In some embodiments, the upper surface of the second gate electrode layer is lower than the upper surface of the substrate.

[0031] In this embodiment of the present disclosure, by implanting fluorine ions on the upper surface of the substrate and the gate structure, and after annealing, a first doped region is formed at the junction of the substrate and the gate insulating layer. The first doped region contains fluorine ions, which have strong bond energy and can effectively reduce GIDL leakage current. At the same time, the annealing step can reduce the resistance of the metal in the gate structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0034] Figures 2a to 2g This is a schematic diagram of the semiconductor device during the fabrication process provided in the embodiments of this disclosure;

[0035] Figure 3 The graphs showing the effect of injecting different doses of fluoride ions on reducing GIDL leakage current;

[0036] Figure 4 The resistance test curve of the metal W in the gate structure is shown.

[0037] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0038] Explanation of reference numerals in the attached figures:

[0039] 10-Substrate;

[0040] 20 - Gate structure; 21 - Gate insulating layer; 22 - Gate electrode; 221 - First gate electrode layer; 222 - Second gate electrode layer; 201 - Gate trench;

[0041] 31 - First doped region; 32 - Second doped region;

[0042] 41 - Capacitor contact plug; 42 - Bit line contact plug. Detailed Implementation

[0043] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0045] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0050] The leakage current in MOS devices mainly includes: source-to-drain subthreshold leakage current, gate leakage current, and gate-induced drain leakage (GIDL) occurring in the gate-drain overlap region. Among these leakage currents, GIDL current dominates the leakage current when the circuit device is in the off state or in the standby state. Therefore, how to reduce GIDL leakage in DRAM devices has become an important solution to improve product performance and yield.

[0051] Taking a stacked gate oxide layer as an example, in the region where the drain and gate overlap, taking NMOS as an example, when the gate voltage V GSWhen the voltage is less than 0 and the operating voltage VDD is applied to the drain, the original N-Si bonds will be exhausted on the drain below the overlap region, resulting in leakage. Similarly, the same type of leakage will also occur in the gate and drain regions of the buried word line (BWL) structure. This leakage is an important parameter affecting the final performance and yield of DRAM products.

[0052] Meanwhile, as the critical dimension (CD) of the buried word line becomes smaller and smaller, the resistance of the metal word line will become larger and larger, affecting the speed and performance of the MOS.

[0053] Based on this, the present disclosure provides a method for fabricating a semiconductor device, as detailed in the appendix. Figure 1 As shown in the figure, the method includes the following steps:

[0054] Step 101: Provide a substrate and form a gate trench on the substrate;

[0055] Step 102: Form a gate structure in the gate trench, the gate structure including a gate electrode located in the gate trench and a gate insulating layer located between the gate electrode and the gate trench;

[0056] Step 103: Implant fluorine ions into the side surface of the substrate on which the gate structure is formed, and anneal the substrate to form a first doped region at at least a portion of the junction between the substrate and the gate insulating layer.

[0057] By implanting fluorine ions into the upper surface of the substrate and gate structure and then annealing, a first doped region is formed at the junction of the substrate and the gate insulating layer. The first doped region contains fluorine ions, which have strong bond energy and can effectively reduce GIDL leakage current. At the same time, the annealing step can reduce the resistance of the metal in the gate structure.

[0058] The method for fabricating semiconductor devices provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0059] Figures 2a to 2g This is a schematic diagram of the semiconductor device during the fabrication process provided in the embodiments of this disclosure.

[0060] First, see appendix Figure 2a Step 101 is performed. A substrate 10 is provided, and a gate trench 201 is formed on the substrate 10.

[0061] The substrate 10 can be a single-element semiconductor material substrate (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

[0062] Next, a gate trench 201 is formed on the substrate 10.

[0063] Specifically, a mask layer can first be grown on the upper surface of the substrate 10, and then the mask layer can be patterned to display the gate trench pattern to be etched. The mask layer can be patterned using a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the patterning is performed through steps such as exposure, development, and resist removal. Then, gate trenches of a certain depth are etched according to the gate trench pattern to be etched.

[0064] Here, for example, a wet or dry etching process can be used to form the gate trench 201.

[0065] Next, see the appendix. Figure 2b To be continued Figure 2d Step 102 is executed. A gate structure 20 is formed in the gate trench 201. The gate structure 20 includes a gate electrode 22 located in the gate trench 201 and a gate insulating layer 21 located between the gate electrode 22 and the gate trench 201.

[0066] Please refer to the appendix first. Figure 2b A gate insulating layer 21 is formed on the sidewall of the gate trench 201. The material of the gate insulating layer 21 may include insulating materials such as silicon oxide or silicon nitride.

[0067] Next, see the appendix. Figure 2c and attached Figure 2d A gate electrode 22 is formed on the sidewall of the gate insulating layer 21. The gate electrode includes a second gate electrode layer 222 and a first gate electrode layer 221 located between the second gate electrode layer 222 and the gate insulating layer 21; the first gate electrode layer 221 comprises titanium nitride, and the second gate electrode layer 222 comprises tungsten. It should be noted that the above-described gate electrode structure is only one embodiment; in some embodiments, the gate electrode may have only one conductive layer located within the gate trench or two conductive layers sequentially filling the gate trench.

[0068] Specifically, see Figure 2c First, a first gate electrode layer 221 is formed on the sidewall of the gate insulating layer 21; then, a second gate electrode layer 222 is formed on the sidewall of the first gate electrode layer 221.

[0069] In practice, the gate insulating layer 21, the first gate electrode layer 221 and the second gate electrode layer 222 can be formed using one or more thin film deposition processes; specifically, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or combinations thereof.

[0070] After the gate structure 20 is formed, the substrates 10 on both sides of the gate structure 20 are the active regions of the semiconductor device. Ion implantation is performed on the active regions to form source and drain regions.

[0071] The doped ions in the source region and the drain region can be N-doped ions. N-doped ions refer to ions that are electronically doped and can include at least one of phosphorus, arsenic, and antimony.

[0072] After forming the gate structure, the semiconductor device is subjected to a CMP (chemical mechanical polishing) process to grind the surface of the semiconductor device on the side where the gate structure is formed, exposing the gate structure on the surface. This ensures that during subsequent ion implantation, fluoride ions are better formed at at least partially at the interface between the substrate and the gate insulating layer, and at least partially at the interface between the gate insulating layer and the gate electrode, thereby more effectively reducing GIDL leakage current.

[0073] Next, see Figures 2e to 2f Step 103 is executed. Fluorine ions are implanted into the side surface of the substrate 10 where the gate structure 20 is formed, and annealing is performed to form a first doped region 31 at at least a portion of the interface between the substrate 10 and the gate insulating layer 21.

[0074] The depth of the first doped region 31 within the substrate 10 is less than the depth of the gate trench 201, and the depth of the first doped region 31 is 1 / 5 to 1 / 4 of the depth of the gate trench 201. This ensures that the channel conductivity of the transistor is not affected while preventing GIDL leakage.

[0075] Specifically, see Figure 2e Fluorine ions are first injected into the side surface of the substrate 10 where the gate structure 20 is formed.

[0076] In one embodiment, the energy and dose of fluoride ion implantation into the surface of the gate structure 20 are greater than the energy and dose of fluoride ion implantation into the surface of the substrate 10, so as to reduce the impact on the source and drain regions.

[0077] Specifically, the energy for fluoride ion implantation into the surface of the gate structure is 2 KeV-50 KeV, and the dose is 1 × 10⁻⁶. 11 pcs / cm 2 -1×1016 pcs / cm 2 That is, the number of fluoride ions per square centimeter is 1 × 10⁻⁶. 11 1×10 16 The ion implantation energy and dose range is moderate, which can form a suitable concentration of fluoride ions, thereby enabling the first doped region to better reduce GIDL leakage.

[0078] In actual manufacturing, fluoride ion implantation uses the BF3 ion implantation process, and during ion implantation, the twist and tilt settings are based on the single crystal orientation of the wafer.

[0079] In one embodiment, fluoride ion implantation is typically performed vertically or at a small angle. The implantation angle ranges from 0° to 3°. Vertical or small-angle fluoride ion implantation allows fluoride ions to be more dispersed within the substrate on both sides of the gate structure, reducing the diffusion of fluoride ions into the substrate below the gate structure. This does not affect the channel conductivity of the transistor and also reduces the generation of GIDL current.

[0080] Figure 3 The figure shows the effects of different doses of fluoride ion implantation on reducing GIDL leakage current. Using a saddle-fin array device as the test object, W / O F-IMP represents no fluoride ion implantation, F-dose_L represents low-dose fluoride ion implantation, F-dose_M represents medium-dose fluoride ion implantation, and F-dose_H represents high-dose fluoride ion implantation. The figure shows that fluoride ion implantation has a certain effect on reducing GIDL current, with medium-dose fluoride ion implantation having the greatest effect.

[0081] In the above embodiments, two gate structures 20 are formed in the substrate 10, and each gate structure 20 has a first doped region 31 on each of its left and right sides. In some other embodiments, the first doped region 31 may be formed only on one side of a gate structure 20, which can also reduce the GIDL current. The specific structure can be set according to the requirements of the actual fabrication process, and will not be described in detail here.

[0082] It should be explained that fluoride ion implantation can effectively reduce GIDL leakage current and lower retention time failure rate. However, fluoride ion implantation after the gate structure is formed may damage the oxide layer, affecting the quality of the gate insulating layer. Therefore, in this embodiment, after fluoride ion implantation, an annealing process is performed to repair the damaged lattice and also reduce the resistance of the metal layer of the gate structure.

[0083] Next, an annealing process is performed in the reaction chamber. Specifically, the reaction gas used in the annealing process is N2, and the N2 gas flow rate is 100–1000 sccm. Using N2 as the carrier gas and maintaining an N2 gas flow rate of 100–1000 sccm during the annealing process allows for better annealing and helps repair lattice damage.

[0084] In one embodiment, the temperature range of the reaction chamber where the annealing process is performed is 700°C to 1000°C. Within this temperature range, the annealing effect is better utilized, effectively repairing lattice damage. The temperature is neither too high, which could damage the device, nor too low, which would fail to achieve the desired effect.

[0085] Furthermore, during the annealing process, the pressure range of the main reaction steps is 500 Torr to 800 Torr.

[0086] In one embodiment, the O2 content in the reaction chamber where the annealing process is performed is less than 5 ppm. During the annealing process, the oxygen content in the reaction chamber must be strictly controlled to prevent oxidation of the metal within the semiconductor device.

[0087] After ion implantation and annealing, Si-F bonds are formed in the first doped region 31. The Si-F bonds have strong bond energies and replace the Si-Si and Si-H bonds that were originally prone to defects, thereby improving the GIDL effect of the semiconductor device.

[0088] In one embodiment, see Figure 2f The process of implanting fluorine ions into the surface of the substrate 10 on which the gate structure 20 is formed and then annealing it further includes: forming a second doped region 32 at at least a portion of the interface between the gate insulating layer 21 and the gate electrode 22; the second doped region 32 forming Si-F bonds. The second doped region formed at the interface between the gate insulating layer and the gate electrode, which also contains fluorine ions, can also reduce GIDL leakage current and decrease the resistance of the metal layer of the gate structure.

[0089] The depth of the second doped region 32 within the substrate 10 is also less than the depth of the gate trench 201. The depth of the second doped region 32 is 1 / 5 to 1 / 4 of the depth of the gate trench 201.

[0090] In the above embodiments, a second doped region 32 is formed on each of the left and right sides of the gate electrode 22. In some other embodiments, the second doped region 32 may be formed only on one side of the gate electrode 22, which can also reduce the GIDL current. The specific structure can be set according to the requirements of the actual fabrication process, and will not be described in detail here.

[0091] Figure 4 The figure shows the resistance test curves of the metal W in the gate structure. As shown, three sets of test samples were used, and the test results of the metal W before and after annealing were recorded for each of the three sets of test samples. It can be seen from the figure that the resistance of all three sets of test samples decreased after annealing, thus demonstrating that annealing can reduce the resistance of the metal W.

[0092] In one embodiment, the method for fabricating the semiconductor device further includes: after annealing, removing the semiconductor device from the reaction chamber and controlling the temperature outside the reaction chamber to be less than 350°C. Controlling the temperature outside the reaction chamber to below 350°C prevents the metal inside the semiconductor device from reacting with oxygen in the air after the device is removed from the chamber.

[0093] Next, see Figure 2g The method further includes: after annealing, etching the surface of the second gate electrode layer 222 on the side implanted with fluorine ions to remove a portion of the second gate electrode layer 222. Fluorine ion implantation affects the performance of the upper surface of the second gate electrode layer 222; therefore, removing the upper surface portion of the second gate electrode layer 222 ensures its performance. Furthermore, removing the upper surface portion of the second gate electrode layer 222 also prevents it from contacting the subsequently formed contact plug, thus avoiding any impact on device performance.

[0094] See also Figure 2g After removing part of the second gate electrode layer 222, contact plugs are formed on the upper surface of the substrate 10 on both sides of the gate structure 20.

[0095] The material of the contact plug may include polysilicon, metal silicide, metal nitride, or metal.

[0096] The contact plugs include a capacitor contact plug (NC) 41 and a bit line contact plug (BLC) 42. The capacitor contact plug 41 is located on the upper surface of the substrate 10 outside the gate structure 20; the bit line contact plug 42 is located on the upper surface of the substrate between adjacent gate structures 20.

[0097] This disclosure also provides a semiconductor device. Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0098] See Figure 5The semiconductor device includes: a substrate 10, in which a gate trench 201 is formed; a gate structure 20 located within the gate trench 201; the gate structure 20 including a gate electrode 22 located within the gate trench 201 and a gate insulating layer 21 located between the gate electrode 22 and the gate trench 201; a first doped region 31 located at at least a portion of the boundary between the substrate 10 and the gate insulating layer 21; the first doped region 31 containing fluorine.

[0099] The substrate 10 can be a single-element semiconductor material substrate (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

[0100] The material of the gate insulating layer 21 may include insulating materials such as silicon oxide or silicon nitride.

[0101] In one embodiment, the gate electrode 22 includes a second gate electrode layer 222 and a first gate electrode layer 221 located between the second gate electrode layer 222 and the gate insulating layer 21; the first gate electrode layer 221 includes titanium nitride, and the second gate electrode layer 222 includes tungsten metal.

[0102] Specifically, the gate insulating layer 21 is located on the sidewall of the gate trench 201, the first gate electrode layer 221 is located on the sidewall of the gate insulating layer 21, and the second gate electrode layer 222 is located within the first gate electrode layer 221. It should be noted that the above-described gate electrode structure is only one embodiment. In some embodiments, the gate electrode may have only one conductive layer located within the gate trench, or two conductive layers sequentially filling the gate trench.

[0103] In practice, the gate insulating layer 21, the first gate electrode layer 221 and the second gate electrode layer 222 can be formed using one or more thin film deposition processes; specifically, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or combinations thereof.

[0104] The substrates on both sides of the gate structure 20 are the active regions of the semiconductor device. After ion implantation into the active regions, source and drain regions are formed.

[0105] In one embodiment, the depth of the first doped region 31 within the substrate 10 is less than the depth of the gate trench 201, and the depth of the first doped region 31 is 1 / 5 to 1 / 4 of the depth of the gate trench 201. This ensures that the channel conductivity of the transistor is not affected while preventing GIDL leakage.

[0106] The first doped region 31 contains fluorine, including the formation of Si-F bonds within it. The Si-F bonds have strong bond energies, replacing the previously defect-prone Si-Si and Si-H bonds, thereby improving the GIDL effect of the semiconductor device.

[0107] In the above embodiments, two gate structures 20 are formed in the substrate 10, and each gate structure 20 has a first doped region 31 on each of its left and right sides. In some other embodiments, the first doped region 31 may be formed only on one side of a gate structure 20, which can also reduce the GIDL current. The specific structure can be set according to the requirements of the actual fabrication process, and will not be described in detail here.

[0108] The semiconductor device further includes a second doped region 32 located at at least a portion of the junction between the gate insulating layer 21 and the gate electrode 22; the second doped region 32 is formed with Si-F bonds. The formation of the second doped region at the junction of the gate insulating layer and the gate electrode, and the second doped region also containing Si-F bonds, can also reduce GIDL leakage current and decrease the resistance of the metal layer of the gate structure.

[0109] The depth of the second doped region 32 within the substrate 10 is also less than the depth of the gate trench 201. The depth of the second doped region 32 is 1 / 5 to 1 / 4 of the depth of the gate trench 201.

[0110] In the above embodiments, a second doped region 32 is formed on each of the left and right sides of the gate electrode 22. In some other embodiments, the second doped region 32 may be formed only on one side of the gate electrode 22, which can also reduce the GIDL current. The specific structure can be set according to the requirements of the actual fabrication process, and will not be described in detail here.

[0111] The first doped region 31 and the second doped region 32 are formed by fluorine ion implantation, wherein the energy and dose of ion implantation into the surface of the gate structure 20 are greater than the energy and dose of ion implantation into the surface of the substrate 10, so as to reduce the impact on the source and drain regions.

[0112] Specifically, the energy range for ion implantation into the surface of the gate structure is 2 KeV-50 KeV, and the dose range is 1 × 10⁻⁶. 11 pcs / cm 2 -1×10 16 pcs / cm 2 The ion implantation energy and dose range is moderate, which can form a suitable concentration of fluoride ions, thereby enabling the first doped region to better reduce GIDL leakage.

[0113] In one embodiment, fluoride ion implantation is typically performed vertically or at a small angle. The implantation angle ranges from 0° to 3°. Vertical or small-angle fluoride ion implantation allows fluoride ions to be more dispersed within the substrate on both sides of the gate structure, reducing the diffusion of fluoride ions into the substrate below the gate structure. This does not affect the channel conductivity of the transistor and also reduces the generation of GIDL current.

[0114] In one embodiment, the upper surface of the second gate electrode layer 222 is lower than the upper surface of the substrate 10. Because fluorine ion implantation affects the performance of the upper surface of the second gate electrode layer 222, the upper surface of the second gate electrode layer 222 is removed, making the upper surface of the second gate electrode layer 222 lower than the upper surface of the substrate 10. This ensures the performance of the second gate electrode layer 222, and also prevents the second gate electrode layer 222 from contacting the subsequently formed contact plugs, thus avoiding any impact on device performance.

[0115] In one embodiment, the semiconductor device further includes: contact plugs located on the upper surface of the substrate 10 on both sides of the gate structure 20.

[0116] The material of the contact plugs may include polysilicon, metal silicide, metal nitride, or metal. The contact plugs include capacitive contact plugs (NC) 41 and bit line contact plugs (BLC) 42. The capacitive contact plugs 41 are located on the upper surface of the substrate 10 outside the gate structure 20; the bit line contact plugs 42 are located on the upper surface of the substrate between adjacent gate structures 20.

[0117] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, on which gate trenches are formed; A gate structure is formed within the gate trench, the gate structure including a gate electrode located within the gate trench and a gate insulating layer located between the gate electrode and the gate trench; Fluorine ions are implanted into one side surface of the substrate on which the gate structure is formed, and annealing is performed to form a first doped region at at least a portion of the junction between the substrate and the gate insulating layer; Si-F bonds are formed in the first doped region; The implantation of fluorine ions into the side surface of the substrate on which the gate structure is formed includes: The energy of the injected fluoride ions is 2 keV-50 keV, and the dose of the injected fluoride ions is 1 × 10⁻⁶. 11 pcs / cm 2 -1×10 16 pcs / cm 2 .

2. The method according to claim 1, characterized in that, The process of implanting fluorine ions into the side surface of the substrate on which the gate structure is formed and then annealing it further includes: forming a second doped region at at least a portion of the junction between the gate insulating layer and the gate electrode; and forming Si-F bonds in the second doped region.

3. The method according to claim 1, characterized in that, The reaction gas used in the annealing is N2, and the N2 gas flow rate is 100~1000 sccm.

4. The method according to claim 1, characterized in that, The temperature range of the reaction chamber where annealing is performed is 700℃~1000℃.

5. The method according to claim 1, characterized in that, Also includes: The O2 content in the reaction chamber where annealing is performed is less than 5 ppm.

6. The method according to claim 4, characterized in that, Also includes: After annealing, the semiconductor device is removed from the reaction chamber, and the temperature outside the reaction chamber is controlled to be less than 350°C.

7. The method according to claim 1, characterized in that, The gate electrode includes a second gate electrode layer and a first gate electrode layer located between the second gate electrode layer and the gate insulating layer; the first gate electrode layer includes titanium nitride, and the second gate electrode layer includes tungsten.

8. The method according to claim 7, characterized in that, Also includes: After annealing, the surface of the second gate electrode layer on the side implanted with fluorine ions is etched to remove part of the second gate electrode layer.

9. A semiconductor device, characterized in that, include: A substrate in which gate trenches are formed; A gate structure is located within the gate trench; The gate structure includes a gate electrode located within the gate trench and a gate insulating layer located between the gate electrode and the gate trench; A first doped region is located at at least a portion of the boundary between the substrate and the gate insulating layer; the first doped region contains fluorine. The first doped region contains fluorine, including: Si-F bonds are formed in the first doped region.

10. The semiconductor device according to claim 9, characterized in that, Also includes: The second doped region is located at at least a portion of the boundary between the gate insulating layer and the gate electrode; Si-F bonds are formed in the second doped region.

11. The semiconductor device according to claim 9, characterized in that, The gate electrode includes a second gate electrode layer and a first gate electrode layer located between the second gate electrode layer and the gate insulating layer; the first gate electrode layer includes titanium nitride, and the second gate electrode layer includes tungsten.

12. The semiconductor device according to claim 11, characterized in that, The upper surface of the second gate electrode layer is lower than the upper surface of the substrate.

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