A semiconductor device and a method of forming the same
By introducing an insulating isolation layer into the MOSFET device to isolate the bonding interface between the depletion layer and the contact plug, the leakage problem of the MOSFET device is solved, and the stability and current conduction performance of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-17
- Publication Date
- 2026-05-12
AI Technical Summary
Existing MOSFET devices suffer from severe leakage current in standby mode, affecting chip power consumption and lifespan. Moreover, the leakage current problem becomes more prominent as the integration density of devices increases.
An insulating layer is introduced between the contact plug and the lower surface of the source/drain doped region to isolate the depletion layer, increase the distance between the depletion layer and the contact plug, and reduce leakage current.
It effectively reduces leakage current at the junction interface without affecting the current conduction path of the device, thereby improving the stability and service life of the device.
Smart Images
Figure CN114400249B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for forming the same. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are crucial electronic components in modern semiconductor products. The electrical performance of a MOSFET directly impacts the quality of integrated circuits. MOSFET leakage current affects power consumption in standby mode, device stability, and lifespan, and has long been a major issue limiting the development of the semiconductor industry. With increasingly higher device integration levels, suppressing MOSFET leakage current has become a pressing technical challenge. Summary of the Invention
[0003] This disclosure provides a semiconductor device, including: a substrate; a gate located on the substrate; source / drain doped regions located on both sides of the gate on the substrate; a contact plug disposed on the substrate, the bottom of the contact plug being electrically connected to the source / drain doped regions; and an isolation layer disposed within the source / drain doped regions, the isolation layer being located below the contact plug, the upper surface of the isolation layer being higher than the lower surface of the source / drain doped regions, and the material of the isolation layer including an insulating material.
[0004] In some embodiments, the width of the isolation layer along the direction parallel to the substrate is equal to the width of the cross section of the source / drain doped region along the direction parallel to the substrate.
[0005] In some embodiments, the source / drain doped region includes a first source / drain doped region and a second source / drain doped region, wherein the second source / drain doped region is located above the first source / drain doped region, and the upper surface of the isolation layer is lower than or flush with the lower surface of the second source / drain doped region.
[0006] In some embodiments, the isolation layer is a cap-shaped structure, the cap-shaped structure including a horizontal portion extending in a direction parallel to the substrate and a vertical portion extending in a direction perpendicular to the substrate, and the vertical portion being located above the horizontal portion.
[0007] In some embodiments, the contact plug includes a metal silicide layer and a conductive plug, the metal silicide layer being located between the conductive plug and the source / drain doped region, and the metal silicide layer electrically connecting the conductive plug and the source / drain doped region.
[0008] In some embodiments, the material of the insulating layer includes silicon dioxide.
[0009] This disclosure also provides a method for forming a semiconductor device, comprising: providing a substrate; forming a gate on the substrate; forming source / drain doped regions on the substrate on both sides of the gate; forming an isolation layer in the source / drain doped regions, wherein the upper surface of the isolation layer is higher than the lower surface of the source / drain doped regions, and the material of the isolation layer includes an insulating material; forming a contact plug above the isolation layer, wherein the bottom of the contact plug is electrically connected to the source / drain doped regions.
[0010] In some embodiments, forming an isolation layer within the source / drain doped region includes: implanting oxygen ions into the source / drain doped region to a depth greater than the depth of the lower surface of the source / drain doped region; and performing a heat treatment process to cause the oxygen ions to react with the material in the source / drain doped region to form an isolation layer.
[0011] In some embodiments, forming a contact plug above the isolation layer includes: forming a dielectric layer on the substrate, the dielectric layer covering the source / drain doped regions; etching the dielectric layer until the surface of the source / drain doped regions is exposed to form an opening; etching the exposed surface of the source / drain doped regions to form a groove structure, the opening and the groove structure constituting a contact hole; and depositing a conductive material to fill the contact hole to form a contact plug.
[0012] In some embodiments, forming a contact plug above the isolation layer includes: forming a metal silicide layer within the groove structure; forming a conductive plug on the metal silicide layer, the conductive plug being electrically connected to the source / drain doped region through the metal silicide layer.
[0013] In some embodiments, the width of the isolation layer along the direction parallel to the substrate is equal to the width of the cross section of the source / drain doped region along the direction parallel to the substrate.
[0014] This disclosure also provides a method for forming a semiconductor device, comprising: providing a substrate; forming a gate on the substrate; forming a first source / drain doped region prelayer on the substrate on both sides of the gate; performing oxygen ion implantation in the first source / drain doped region prelayer, wherein the implantation depth of the oxygen ions is higher than the lower surface depth of the source / drain doped region prelayer; etching the first source / drain doped region prelayer to form a trench and a first source / drain doped region located below the trench, wherein the lower surface of the trench is higher than the position of maximum concentration of the implanted oxygen ions; forming a second source / drain doped region in the trench; performing a thermal treatment process to cause the oxygen ions to react with the material in the first source / drain doped region to form an isolation layer; forming a contact plug above the isolation layer, wherein the bottom of the contact plug is electrically connected to the second source / drain doped region.
[0015] In some embodiments, forming a contact plug above the isolation layer includes: forming a dielectric layer on the substrate, the dielectric layer covering the second source / drain doped region; etching the dielectric layer until the surface of the second source / drain doped region is exposed to form an opening; etching the exposed surface of the second source / drain doped region to form a groove structure, the opening and the groove structure constituting a contact hole; and depositing a conductive material to fill the contact hole to form a contact plug.
[0016] In some embodiments, forming a contact plug above the isolation layer includes: forming a metal silicide layer within the groove structure; forming a conductive plug on the metal silicide layer, the conductive plug being electrically connected to the second source / drain doped region through the metal silicide layer.
[0017] In some embodiments, forming a second source / drain doped region within the trench includes: selectively epitaxially growing a second source / drain doped region material in the trench; and implanting source / drain doped ions into the second source / drain doped region material to form the second source / drain doped region.
[0018] This disclosure provides a semiconductor device, including: a substrate; a gate located on the substrate; source / drain doped regions located on both sides of the gate on the substrate; a contact plug disposed on the substrate, the bottom of the contact plug being electrically connected to the source / drain doped regions; and an isolation layer disposed within the source / drain doped regions, located below the contact plug, with its upper surface higher than the lower surface of the source / drain doped regions, the isolation layer being made of an insulating material. This disclosure introduces an insulating layer between the contact plug and the lower surface of the source / drain doped regions, blocking the depletion layer generated at the junction between the source / drain doped regions and the substrate, increasing the distance between the depletion layer and the contact plug, thereby reducing leakage current at the junction without affecting the current conduction path of the device.
[0019] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;
[0022] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;
[0023] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;
[0024] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;
[0025] Figure 5 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure;
[0026] Figures 6a to 6i This is a schematic diagram of the device structure during the fabrication process of a semiconductor device according to an embodiment of the present disclosure;
[0027] Figures 7a to 7b This is a schematic diagram of the device structure during the fabrication process of a semiconductor device according to another embodiment of this disclosure;
[0028] Figure 8 This is a flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure;
[0029] Figures 9a to 9i This is a schematic diagram of the device structure during the fabrication process of a semiconductor device according to an embodiment of the present disclosure;
[0030] Figures 10a to 10b This is a schematic diagram of the device structure during the fabrication process of a semiconductor device according to another embodiment of this disclosure.
[0031] Figure label:
[0032] 101-Substrate; 103-Gate; 105-Source / drain doped region; 105-1-First source / drain doped region; 105-2-Second source / drain doped region; 107-Contact plug; 109-Isolation layer; 109-1-Vertical portion; 109-2-Horizontal portion; 111-Upper surface of isolation layer; 113-Lower surface of source / drain doped region; 113-1-Lower surface of pre-layer of first source / drain doped region; 115-Substrate; 116 - Epitaxial layer; 117- Sidewall structure; 119- Dielectric layer; 121- Depletion layer; 123- Lower surface of the second source / drain doped region; 123-1- Lower surface of the trench; 124- Metal silicide layer; 125- Oxygen ions; 125-1- Implantation depth; 127- Contact hole; 127-1- Opening; 127-2- Groove structure; 129- Conductive plug; 131- Pre-layer of the first source / drain doped region; 133- Trench. Detailed Implementation
[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0038] This disclosure provides a semiconductor device, with attached... Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. (See attached diagram.) Figure 1 The semiconductor device includes: a substrate 101; a gate 103 located on the substrate 101; source / drain doped regions 105 located on the substrate 101 on both sides of the gate 103; a contact plug 107 disposed on the substrate 101, the bottom of the contact plug 107 being electrically connected to the source / drain doped regions 105; and an isolation layer 109 disposed within the source / drain doped regions 105, the isolation layer 109 being located below the contact plug 107, the upper surface 111 of the isolation layer being higher than the lower surface 113 of the source / drain doped regions, and the material of the isolation layer 109 including an insulating material.
[0039] Thus, by introducing an insulating layer between the contact plug and the lower surface of the source / drain doped region, the depletion layer 121 generated at the junction between the source / drain doped region and the substrate is blocked, increasing the distance between the depletion layer 121 and the contact plug, thereby reducing the leakage current at the junction without affecting the current conduction path of the device.
[0040] In practice, the substrate 101 can be silicon, silicon-germanium, germanium, or other suitable semiconductors. In some embodiments, the substrate 101 may further include a P-type or N-type substrate 115 and an epitaxial layer 116 formed on the substrate 115. The source / drain doped regions 105 can be formed as N-type doped regions by doping with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and can be formed as P-type doped regions by doping with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. The source / drain doped regions 105 may also include lightly doped drain (LDD) regions and Halo implantation regions. The gate 103 includes a gate dielectric layer and a gate metal layer. For example, the gate dielectric layer can be silicon oxynitride, silicon oxide, or a high-K material, and the gate metal layer can be polysilicon, tungsten, or titanium nitride. The gate 103 also includes a sidewall structure 117 outside the gate sidewall, which covers the sidewall of the gate 103. The substrate 101 also includes a dielectric layer 119, which covers the substrate 101, and the contact plug 107 is formed within the dielectric layer 119.
[0041] In practice, to improve the leakage protection of transistors, isolation layers can be provided in both the drain and source doped regions of the transistor. To simplify the process, isolation layers can be provided only in the source or drain of the transistor. Preferably, the isolation layer is provided in the drain doped region of the transistor.
[0042] In some embodiments, the width W1 of the isolation layer 109 along the direction parallel to the substrate is equal to the width W2 of the cross-section of the source / drain doped region 105 along the direction parallel to the substrate. By adjusting the widths of the isolation layer and the cross-section of the source / drain doped region along the direction parallel to the substrate to be equal, the probability of the junction depletion layer 121 bypassing the isolation layer 109 can be further reduced, thereby avoiding transistor leakage. The width W1 of the isolation layer 109 along the direction parallel to the substrate is smaller than the width W2 of the cross-section of the source / drain doped region 105 along the direction parallel to the substrate. Since the isolation layer is an insulating material, reducing the width of the isolation layer can reduce the overall resistance of the entire source / drain doped region. In a specific embodiment, the ratio of the width W1 of the isolation layer 109 along the direction parallel to the substrate to the width W2 of the cross-section of the source / drain doped region 105 along the direction parallel to the substrate is 0.56-0.87, for example, 0.62, 0.75, 0.8. When the ratio of W1 to W2 is within the above range, the isolation effect of the isolation layer on the depletion region and the overall resistance of the source / drain doped region can achieve an excellent balance.
[0043] In some embodiments, the isolation layer is made of silicon dioxide. In practice, silicon dioxide can be formed by implanting oxygen ions into the source / drain doped regions and then performing a thermal treatment process. Compared to other insulating materials, silicon dioxide is simple to prepare as an isolation layer, has good compatibility with the substrate, and its low relative permittivity provides good insulation, effectively isolating junction depletion layers. In other embodiments, the isolation layer may include a thermally oxidized layer, including but not limited to silicon oxynitride, silicon nitride, or a combination thereof.
[0044] In some embodiments, as shown in the appendix Figure 2 As shown, attached Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of the present disclosure. The source / drain doped region 105 includes a first source / drain doped region 105-1 and a second source / drain doped region 105-2, wherein the second source / drain doped region 105-2 is located above the first source / drain doped region 105-1, and the upper surface 111 of the isolation layer is lower than or flush with the lower surface 123 of the second source / drain doped region. In actual operation, the formation of the isolation layer generally contaminates or damages the source / drain doped regions, causing an increase in the resistance of the source / drain doped regions. By providing a second source / drain doped region 105-2 with a resistivity lower than that of the first source / drain doped region 105-1 on the upper surface of the isolation layer, the problem of increased contact resistance between the source / drain doped regions and the contact plug caused by the formation of the isolation layer can be alleviated, thereby improving device performance. In some specific embodiments, the doping concentration of the second source / drain doped region 105-2 can be greater than the doping concentration of the first source / drain doped region 105-1. This can further reduce the contact resistance between the contact plug and the source / drain doped regions. In some specific embodiments, the doping concentration of the second source / drain doped region 105-2 can decrease gradually or progressively along the direction from the upper surface to the lower surface. In some other embodiments, the material of the second source / drain doped region 105-2 can be different from the material of the first source / drain doped region 105-1. In practice, the material of the second source / drain doped region 105-2 includes, but is not limited to, silicon and germanium. This allows the second source / drain doped region 105-2 to apply stress to the channel, thereby improving the carrier mobility of the channel region.
[0045] In some embodiments, as shown in the appendix Figure 3 As shown, attached Figure 3This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of the present disclosure. The isolation layer 109 has a cap-shaped structure, which includes a horizontal portion 109-2 extending parallel to the substrate direction and a vertical portion 109-1 extending perpendicular to the substrate direction, with the vertical portion 109-1 located above the horizontal portion 109-2. When the width of the isolation layer is less than the width of the cross-section of the source / drain doped region along the substrate direction, the junction depletion layer may bypass the isolation layer and contact the contact plug, resulting in leakage. By providing a cap-shaped isolation layer, the vertical portion 109-1 of the cap-shaped isolation layer can reduce the probability of the junction depletion layer 121 bypassing the isolation layer and approaching the contact plug, thereby reducing or avoiding transistor leakage. In some specific embodiments, the width of the horizontal portion 109-2 along the substrate plane direction is not less than 0.87 times the width of the cross-section of the source / drain doped region along the substrate plane direction. In some specific embodiments, the ratio of the height of the vertical portion 109-1 along the vertical direction to the width of the horizontal portion 109-2 along the substrate plane is 0.22-0.53, for example, 0.33, 0.42, or 0.5. When the ratio is less than 0.22, the isolation layer is unlikely to achieve a good isolation effect; when the ratio is greater than 0.53, the vertical portion 109-1 may excessively obstruct carrier transport between the source / drain doped region 105 and the channel.
[0046] In some embodiments, as shown in the appendix Figure 4 As shown, attached Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure. The contact plug 107 includes a metal silicide layer 124 and a conductive plug 129. The metal silicide layer 124 is located between the conductive plug 129 and the source / drain doped region 105, and the metal silicide layer 124 electrically connects the conductive plug 129 and the source / drain doped region 105. In actual operation, the metal silicide layer includes silicides of iron, cobalt, nickel, platinum, or their alloys, such as low-resistivity nickel silicide, platinum silicide, cobalt silicide, or their alloys. The metal silicide layer can reduce contact resistance, reduce RC delay, and improve the operating speed of the device. At the same time, process errors in forming the metal silicide layer can more easily lead to contact between the metal silicide layer and the junction depletion layer, resulting in large leakage current. Introducing an isolation layer between the metal silicide layer and the junction can reduce contact resistance while preventing transistor leakage current.
[0047] This disclosure also provides a method for forming a semiconductor device, as detailed in the appendix. Figure 5 The method includes:
[0048] Step 501: Provide a substrate;
[0049] Step 502: Form a gate on the substrate;
[0050] Step 503: Form source / drain doped regions on the substrate on both sides of the gate;
[0051] Step 504: An isolation layer is formed within the source / drain doped region, wherein the upper surface of the isolation layer is higher than the lower surface of the source / drain doped region, and the material of the isolation layer includes an insulating material;
[0052] Step 505: A contact plug is formed above the isolation layer, and the bottom of the contact plug is electrically connected to the source / drain doped region.
[0053] The method for preparing the semiconductor structure provided in this disclosure will be further described in detail below with reference to specific embodiments.
[0054] Figures 6a to 6i This is a schematic diagram of the device structure during the fabrication process of the test structure provided in the embodiments of this disclosure.
[0055] First, proceed to step 501, see [link / reference] Figure 6a A substrate 101 is provided. The substrate may be silicon, silicon germanium, germanium, or other suitable semiconductors. In practice, the substrate 101 may also include a P-type or N-type substrate 115 and an epitaxial layer 116 formed on the substrate 115.
[0056] Next, proceed to step 502, see [link to step 502] Figure 6b A gate 103 is formed on the substrate 101. The gate 103 includes a gate dielectric layer and a gate metal layer. For example, the gate dielectric layer can be silicon oxynitride, silicon oxide, or a high-k material, and the gate metal layer can be polysilicon, tungsten, or titanium nitride. The gate 103 may also include a sidewall structure 117 outside the gate sidewall, the sidewall structure 117 covering the sidewall of the gate 103.
[0057] Next, proceed to step 503, see [link / reference] Figure 6c Source / drain doped regions 105 are formed on the substrate on both sides of the gate 103. The source / drain doped regions 105 can be formed as N-type doped regions by doping with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and as P-type doped regions by doping with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. The source / drain doped regions 105 may also include lightly doped regions (LDD) and Halo implanted regions.
[0058] Then, proceed to step 504, see [link to step 504] Figures 6d-6e An isolation layer 109 is formed within the source / drain doped region 105, the upper surface 111 of the isolation layer being higher than the lower surface 113 of the source / drain doped region, and the material of the isolation layer 109 including an insulating material.
[0059] In some embodiments, forming an isolation layer 109 within the source / drain doped region 105 includes: implanting oxygen ions into the source / drain doped region 105, wherein the implantation depth of the oxygen ions 125 is greater than the depth of the lower surface 113 of the source / drain doped region; and performing a heat treatment process to cause the oxygen ions 125 to react with the material in the source / drain doped region to form an isolation layer.
[0060] For details, see attached. Figure 6d As shown, firstly, oxygen ion implantation is performed within the source / drain doped region 105, with the implantation depth 125-1 of the oxygen ions 125 exceeding the depth of the lower surface 113 of the source / drain doped region. Ion implantation allows for precise control of the oxygen ion concentration distribution and doping depth, as well as the uniformity of oxygen ion distribution within the same plane.
[0061] Next, see the appendix. Figure 6e A heat treatment process is performed to allow the oxygen ions to react with the material in the source / drain doped region 105, thereby forming an isolation layer 109. This heat treatment process not only converts oxygen ions into an isolation layer but also eliminates lattice defects introduced by oxygen ion implantation. It should be understood that the heat treatment process can be a dedicated heat treatment process or a high-temperature process performed for other processing steps. For example, combining it with the annealing process of the source / drain doped region can effectively reduce the thermal budget and minimize high-temperature damage to the device.
[0062] Finally, proceed to step 505, see [link / reference]. Figure 6f-6i A contact plug 107 is formed above the isolation layer 109, and the bottom of the contact plug 107 is electrically connected to the source / drain doped region 105.
[0063] In some embodiments, forming a contact plug 107 above the isolation layer 109 includes: forming a dielectric layer 119 on the substrate 101, the dielectric layer 119 covering the source / drain doped region 105; etching the dielectric layer 119 until the surface of the source / drain doped region 105 is exposed, forming an opening 127-1; etching the exposed surface of the source / drain doped region 105 to form a groove structure 127-2, the opening 127-1 and the groove structure 127-2 constituting a contact hole 127; and depositing a conductive material to fill the contact hole 127 to form the contact plug 107.
[0064] For details, see attached. Figure 6f As shown, a dielectric layer 119 is first formed on the substrate 101, and the dielectric layer 119 covers the source / drain doped regions 105. The material of the dielectric layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or polymer materials.
[0065] Next, see the appendix. Figure 6g The dielectric layer 119 is etched until the surface of the source / drain doped region 105 is exposed, forming an opening 127-1. Here, for example, a wet or dry etching process can be used to form the opening 127-1.
[0066] Next, see the appendix. Figure 6h The etched surface of the source / drain doped region 105 forms a groove structure 127-2, and the opening 127-1 and the groove structure 127-2 constitute a contact hole 127.
[0067] Then, as attached Figure 6i As shown, a conductive material is deposited, and the conductive material fills the contact hole 127 to form a contact plug 107.
[0068] In some embodiments, as shown in the appendix Figures 7a-7b As shown, forming a contact plug above the isolation layer includes: forming a metal silicide layer 124 within the groove structure 127-2; forming a conductive plug 129 on the metal silicide layer 124, the conductive plug 129 being electrically connected to the source / drain doped region 105 through the metal silicide layer 124. In practice, a metal material can be formed within the groove structure, followed by heat treatment to allow the metal material to react with the substrate material, generating metal silicides. Finally, the unreacted metal material is removed. The metal silicide layer includes silicides of iron, cobalt, nickel, platinum, or their alloys, such as low-resistivity nickel silicide, platinum silicide, cobalt silicide, or their alloys. The metal silicide layer can reduce contact resistance, decrease RC delay, and improve device operating speed.
[0069] In some embodiments, as shown in the appendix Figure 6i As shown, the width W1 of the isolation layer 109 along the direction parallel to the substrate is equal to the width W2 of the cross-section of the source / drain doped region 105 along the direction parallel to the substrate. By adjusting the width W1 of the isolation layer 109 along the direction parallel to the substrate to be equal to the width W2 of the cross-section of the source / drain doped region 105 along the direction parallel to the substrate, the probability of the junction depletion layer 121 bypassing the isolation layer 109 is minimized, thereby avoiding transistor leakage.
[0070] This disclosure also provides a method for forming a semiconductor device, as detailed in the appendix. Figure 8 The method includes:
[0071] Step 801: Provide a substrate;
[0072] Step 802: Form a gate on the substrate;
[0073] Step 803: Form a first source / drain doped region pre-layer on the substrate on both sides of the gate;
[0074] Step 804: Oxygen ion implantation is performed in the first source / drain doped region pre-layer, wherein the implantation depth of the oxygen ions is higher than the lower surface depth of the source / drain doped region pre-layer;
[0075] Step 805: Etch the first source / drain doped region pre-layer to form a trench and the first source / drain doped region located below the trench, wherein the lower surface of the trench is higher than the position of the maximum concentration of the implanted oxygen ions;
[0076] Step 806: Form a second source / drain doped region within the trench;
[0077] Step 807: Perform a heat treatment process to allow the oxygen ions to react with the material in the first source / drain doped region to form an isolation layer;
[0078] Step 808: A contact plug is formed above the isolation layer, and the bottom of the contact plug is electrically connected to the second source / drain doped region.
[0079] The method for preparing the semiconductor structure provided in this disclosure will be further described in detail below with reference to specific embodiments.
[0080] Figures 9a to 9i This is a schematic diagram of the device structure during the fabrication process of the test structure provided in this embodiment. It should be understood that steps 801 to 802 in this embodiment are the same as steps 501 and 502 in the previous embodiment, and steps 801 to 802 can still be referred to the appendix. Figures 6a-6b .
[0081] First, proceed to step 801, see [link / reference]. Figure 6a A substrate 101 is provided. The substrate may be silicon, silicon germanium, germanium, or other suitable semiconductors. The substrate 101 may also be formed on top of a P-type or N-type substrate 115.
[0082] Next, proceed to step 802, see [link to step 802] Figure 6b A gate 103 is formed on the substrate 101. The gate 103 includes a gate dielectric layer and a gate metal layer. For example, the gate dielectric layer can be silicon oxynitride, silicon oxide, or a high-k material, and the gate metal layer can be polysilicon, tungsten, or titanium nitride. The gate 103 also includes a sidewall structure 117 outside the gate sidewall, which covers the sidewall of the gate 103.
[0083] Next, proceed to step 803, see [link / reference] Figure 9aA first source / drain doped region pre-layer 131 is formed on the substrate on both sides of the gate. The first source / drain doped region pre-layer 131 can be formed into an N-type doped region by doping with an n-type dopant such as phosphorus, arsenic, other n-type dopants or combinations thereof; and can be formed into a P-type doped region by doping with a p-type dopant such as boron, indium, other p-type dopants or combinations thereof.
[0084] Next, proceed to step 804, see [link / reference] Figure 9b Oxygen ion implantation is performed within the first source / drain doped region pre-layer 131, with the implantation depth 125-1 of the oxygen ions 125 exceeding the depth of the lower surface 113-1 of the first source / drain doped region pre-layer. Ion implantation allows for precise control of the oxygen ion concentration distribution and doping depth, as well as the uniformity of oxygen ion distribution within the same plane. It should be understood that an annealing step can be performed at this stage to react the oxygen ions with the material in the first source / drain doped region, thereby forming an isolation layer.
[0085] Next, proceed to step 805, see appendix. Figure 9c The first source / drain doped prelayer 131 is etched to form a trench 133 and a first source / drain doped region 105-1 located below the trench 133. The lower surface 123-1 of the trench is higher than the position of maximum concentration of the implanted oxygen ions 125. In actual operation, the trench 133 and the oxygen ions 125 have the same width along the direction parallel to the substrate, which essentially completely removes the contamination or damage areas caused by oxygen ion implantation.
[0086] Next, proceed to step 806, see appendix. Figure 9d A second source / drain doped region 105-2 is formed within the trench. This reformation of the second source / drain doped region, uncontaminated or damaged by oxygen ions, further improves device performance. In some embodiments, the doping concentration of the reformed second source / drain doped region 105-2 can be greater than that of the first source / drain doped region 105-1. This further reduces the contact resistance between the contact plug and the source / drain doped region. In some embodiments, the doping concentration of the second source / drain doped region 105-2 can decrease gradually or progressively along the direction from the upper surface to the lower surface. In other embodiments, the material of the second source / drain doped region 105-2 can be different from that of the first source / drain doped region 105-1. In practice, the material of the second source / drain doped region 105-2 includes, but is not limited to, silicon and germanium. This allows the second source / drain doped region 105-2 to apply stress to the channel, thereby improving the carrier mobility of the channel region.
[0087] In some embodiments, forming a second source / drain doped region within the trench may include: selectively epitaxially growing a second source / drain doped region material in the trench; and implanting source / drain doped ions into the second source / drain doped region material to form the second source / drain doped region. Here, for example, vapor phase epitaxy or molecular beam epitaxy may be used to form the second source / drain doped region 105-2.
[0088] Then, proceed to step 807, see appendix. Figure 9e A heat treatment process is performed to allow the oxygen ions 125 to react with the material in the first source / drain doped region, thereby forming an isolation layer 109. It should be understood that the heat treatment process can be a dedicated heat treatment process or a high-temperature process performed for other processing steps. For example, combining it with the annealing process of the source / drain doped region can effectively reduce the thermal budget and minimize high-temperature damage to the device.
[0089] Finally, proceed to step 808, as shown in the attached document. Figure 9f-9i As shown, a contact plug 107 is formed above the isolation layer 109, and the bottom of the contact plug 107 is electrically connected to the second source / drain doped region 105-2.
[0090] In some embodiments, forming a contact plug above the isolation layer includes: forming a dielectric layer on the substrate, the dielectric layer covering the second source / drain doped region; etching the dielectric layer until the surface of the second source / drain doped region is exposed to form an opening; etching the exposed surface of the second source / drain doped region to form a groove structure, the opening and the groove structure constituting a contact hole; and depositing a conductive material to fill the contact hole to form a contact plug.
[0091] For details, see attached. Figure 9f As shown, a dielectric layer 119 is first formed on the substrate, and the dielectric layer 119 covers the second source / drain doped region 105-2. The material of the dielectric layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or polymer materials.
[0092] Next, see the appendix. Figure 9g The dielectric layer 119 is etched until the surface of the second source / drain doped region is exposed, forming an opening 127-1. Here, for example, a wet or dry etching process can be used to form the opening 127-1.
[0093] Next, see the appendix. Figure 9h The surface of the second source / drain doped region exposed by etching forms a groove structure 127-2, and the opening 127-1 and the groove structure 127-2 constitute a contact hole.
[0094] Then, as attached Figure 9iAs shown, a conductive material is deposited, and the conductive material fills the contact hole 127 to form a contact plug 107.
[0095] In some embodiments, as shown in the appendix Figures 10a-10b As shown, forming a contact plug above the isolation layer includes: forming a metal silicide layer 124 within the groove structure 127-2; forming a conductive plug 129 on the metal silicide layer 124, the conductive plug 129 being electrically connected to the second source / drain doped region 105-2 through the metal silicide layer 124. In practice, a metal material can be formed within the groove structure, followed by heat treatment to allow the metal material to react with the substrate material, generating metal silicides. Finally, the unreacted metal material is removed. The metal silicide layer includes silicides of iron, cobalt, nickel, platinum, or their alloys, such as low-resistivity nickel silicide, platinum silicide, cobalt silicide, or their alloys. The metal silicide layer can reduce contact resistance, decrease RC delay, and improve device operating speed.
[0096] It should be noted that, in the embodiments of this disclosure, some steps may be executed simultaneously or sequentially, provided there is no conflict. For example, in the process of forming the contact hole 127 consisting of the opening 127-1 and the groove structure 127-2, the substrate may be etched first to form the groove structure 127-2, and then the dielectric layer 119 may be deposited, followed by etching the dielectric layer to form the opening 127-1. As another example, the source / drain doped regions 105 may be formed first, and then the gate 103 may be formed by mask deposition.
[0097] In practice, for example, step 903 can be performed first to form a dummy gate stack on the substrate, the dummy gate stack including a dummy gate electrode layer and a dummy gate dielectric layer. Next, step 904 is performed to etch the dummy gate stack to form multiple dummy gates. Then, step 902 is performed to form multiple active regions on the substrate. Specifically, a self-aligned process is used, utilizing the formed dummy gates as masks, and then multiple active regions are formed in the substrate on both sides of the dummy gates through diffusion or ion implantation.
[0098] In summary, this disclosure introduces an insulating layer between the contact plug and the lower surface of the source / drain doped region, thereby blocking the depletion layer generated at the junction between the source / drain doped region and the substrate, increasing the distance between the depletion layer and the contact plug, thus reducing leakage current at the junction without affecting the current conduction path of the device.
[0099] It should be noted that the semiconductor device and its formation method provided in this disclosure can be applied to any integrated circuit including this structure. The technical features described in each embodiment can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described formation method steps without departing from the protection scope of this disclosure.
[0100] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A gate, the gate being located on the substrate; Source and drain doped regions, wherein the source and drain doped regions are respectively located on the substrate on both sides of the gate; A contact plug is disposed on the substrate, and the bottom of the contact plug is electrically connected to the source / drain doped region; An isolation layer is disposed within the source / drain doped region, the isolation layer is located below the contact plug, the upper surface of the isolation layer is higher than the lower surface of the source / drain doped region, and the material of the isolation layer includes an insulating material; The source / drain doped region includes a first source / drain doped region and a second source / drain doped region, wherein the second source / drain doped region is located above the first source / drain doped region, and the upper surface of the isolation layer is lower than or flush with the lower surface of the second source / drain doped region.
2. The semiconductor device according to claim 1, characterized in that, The width of the isolation layer along the direction parallel to the substrate is equal to the width of the cross section of the source / drain doped region along the direction parallel to the substrate.
3. The semiconductor device according to claim 1, characterized in that, The resistivity of the second source / drain doped region is lower than that of the first source / drain doped region.
4. The semiconductor device according to claim 1, characterized in that, The isolation layer has a cap-shaped structure, which includes a horizontal portion extending parallel to the substrate direction and a vertical portion extending perpendicular to the substrate direction, with the vertical portion located above the horizontal portion.
5. The semiconductor device according to claim 1, characterized in that, The contact plug includes a metal silicide layer and a conductive plug. The metal silicide layer is located between the conductive plug and the source / drain doped region, and the metal silicide layer is electrically connected to the conductive plug and the source / drain doped region.
6. The semiconductor device according to claim 1, characterized in that, The material of the isolation layer includes silicon dioxide.
7. The semiconductor device according to claim 1, characterized in that, The doping concentration of the second source / drain doped region is greater than that of the first source / drain doped region.
8. The semiconductor device according to claim 1, characterized in that, The doping concentration of the second source / drain doped region decreases gradually along the direction from the upper surface to the lower surface.
9. The semiconductor device according to claim 1, characterized in that, The material of the second source / drain doped region is different from the material of the first source / drain doped region.
10. A method for forming a semiconductor device, characterized in that, include: Provide substrate; A gate is formed on the substrate; A first source / drain doped region pre-layer is formed on the substrate on both sides of the gate; Oxygen ion implantation is performed within the first source / drain doped region pre-layer, and the implantation depth of the oxygen ions is greater than the lower surface depth of the source / drain doped region pre-layer. The first source / drain doped region is etched to form a trench and a first source / drain doped region located below the trench, wherein the lower surface of the trench is higher than the position of the maximum concentration of the implanted oxygen ions; A second source / drain doped region is formed within the trench; A heat treatment process is performed to allow the oxygen ions to react with the material in the first source / drain doped region, thereby forming an isolation layer. A contact plug is formed above the isolation layer, and the bottom of the contact plug is electrically connected to the second source / drain doped region.
11. The forming method according to claim 10, characterized in that, A contact plug is formed above the isolation layer, including: A dielectric layer is formed on the substrate, the dielectric layer covering the second source / drain doped region; The dielectric layer is etched until the surface of the second source / drain doped region is exposed, forming an opening; The surface of the second source / drain doped region exposed by etching forms a groove structure, and the opening and the groove structure constitute a contact hole; A conductive material is deposited, and the conductive material fills the contact hole to form a contact plug.
12. The forming method according to claim 11, characterized in that, The formation of a contact plug above the isolation layer includes: A metal silicide layer is formed within the groove structure; A conductive plug is formed on the metal silicide layer, and the conductive plug is electrically connected to the second source / drain doped region through the metal silicide layer.
13. The forming method according to claim 10, characterized in that, A second source / drain doped region is formed within the trench, including: Selective epitaxial growth of a second source / drain doped region material is performed in the trench; The second source / drain doped region is formed by implanting source / drain doped ions into the material of the second source / drain doped region.
14. The forming method according to claim 10, characterized in that, The doping concentration of the second source / drain doped region is greater than that of the first source / drain doped region.
15. The forming method according to claim 10, characterized in that, The doping concentration of the second source / drain doped region decreases gradually along the direction from the upper surface to the lower surface.
16. The forming method according to claim 10, characterized in that, The material of the second source / drain doped region is different from the material of the first source / drain doped region.