Arithmetic codec byte stuffing signaling for video codecs

Abstract

Arithmetic codecs such as CABAC have high complexity. Some video codec systems limit the ratio of binary bits encoded and decoded by the arithmetic codec to the bits of the encoded data. To do this, additional padding or filler data is added to the bitstream. Embodiments include methods for reducing the overhead of such padding, and embodiments include methods for processing a video bitstream without including padding data. For example, a video encoder or decoder may encode and decode a syntax element of a video bitstream for a unit of video data, the unit of video data indicating the number of padding bits, and encode and decode the unit of video data without encoding and decoding (encoding or decoding) the padding bits in the video bitstream.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. non-provisional application No. 17 / 028,899, filed on September 22, 2020, entitled “ARITHMETIC CODER BYTE STUFFING SIGNALING FOR VIDEO CODING,” which claims the benefit of U.S. provisional application No. 62 / 904,549, filed on September 23, 2019, entitled “RICE PARAMETER DERIVATION FOR LOSSLESS / LOSSY CODING MODES FOR VIDEO CODING,” which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] The present disclosure relates to video encoding and video decoding. Background Art

[0004] Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite radio telephones, so-called "smart phones", video teleconferencing devices, video streaming devices, etc. Digital video devices implement video codec technologies, such as those described in the standards defined by the following: MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4 Part 10, Advanced Video Codec (AVC), ITU-T H.265 / High Efficiency Video Codec (HEVC), and extensions of such standards. Video devices can more efficiently send, receive, encode, decode and / or store digital video information by implementing such video codec technologies.

[0005] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or eliminate redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be partitioned into video blocks, which may also be referred to as codec tree units (CTUs), codec units (CUs), and / or codec nodes. Video blocks in an intra-frame codec (I) slice of a picture are encoded using redundant predictions relative to reference samples in neighboring blocks in the same picture. Video blocks in an inter-frame codec (P or B) slice of a picture may use spatial predictions relative to reference samples in neighboring blocks in the same picture, or temporal predictions relative to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the invention

[0006] Arithmetic codecs such as CABAC have high complexity. Some video codec systems limit the ratio of bins encoded and decoded by the arithmetic codec to the encoded data bits. To do this, additional padding or filler data is added to the bitstream. Embodiments include methods to reduce the overhead of such padding, embodiments include methods for processing a video bitstream without including padding data.

[0007] Embodiments include methods of encoding or decoding video data. One embodiment includes encoding a syntax element of a video bitstream for a video data unit into the video bitstream, the syntax element indicating a number of padding bits; and encoding the video data unit into the video bitstream without including the padding bits into the video bitstream. Another embodiment includes decoding a syntax element of the video bitstream for a video data unit from the video bitstream, the syntax element indicating a number of padding bits; and decoding the unit from the video bitstream without decoding the padding bits from the video bitstream.

[0008] Another embodiment includes an apparatus for encoding or decoding video data. The apparatus includes a memory configured to store a video data unit associated with a video bitstream and a video processor. The video processor is configured to encode and decode a syntax element of a video bitstream for the video data unit, the syntax element indicating a number of padding bits; and encode and decode the video data unit without encoding and decoding the padding bits in the video bitstream. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example video encoding and decoding system that may perform the disclosed techniques.

[0010] Figure 2A and Figure 2B is a conceptual diagram illustrating an example quadtree binary tree (QTBT) structure and a corresponding codec tree unit (CTU).

[0011] Figure 3 is a block diagram illustrating an example video encoder that may perform the techniques of this disclosure.

[0012] Figure 4 is a block diagram illustrating an example video decoder that may perform the techniques of this disclosure.

[0013] Figure 5 is a flow chart illustrating encoding video data according to some embodiments.

[0014] Figure 6 is a flow chart illustrating decoding of video data according to some embodiments.

[0015] Figure 7 is a flow chart illustrating encoding and decoding of video data according to some embodiments. DETAILED DESCRIPTION

[0016] A video codec may impose constraints on the video bitstream to limit the ratio of the number of bits in a video data unit (e.g., a picture) before encoding to the number of bits (or bytes) after encoding. This restriction helps, among other things, to limit decoding complexity, especially for hardware codec (encoder or decoder) implementations. The restriction can be used for bitstream conformance checking.

[0017] In one draft of VVC (JVET-O2001-vE draft version) (see below for more information on VVC), there is an upper limit on the bin-to-bit ratio by imposing the constraints specified in the following section of the JVET-O2001-vE.doc VVC specification (Table 1).

[0018] Table 1

[0019]

[0020]

[0021] This excerpt specifies an upper bound on the bin-to-bit ratio at the picture level for Context-Adaptive Binary Arithmetic Codec (CABAC). Basically, for bin counts in the Video Codec Layer (VCL) Network Abstraction Layer (NAL) unit of a codec picture:

[0022]

[0023]

[0024] Where NumBitsInVclUnits is 8xNumberBytesINNalUnit, and RawBitsInPicture is the total number of bits representing the original coded picture, with BitDepthY for luma samples and BitDepthC for chroma samples. If the coded picture generated by the encoder does not meet this constraint, it adds syntax elements after the trailing bits of the coded picture, for example, named cabac_zero_words (i.e., 16 zero bits) to increase NumBitsInVclUnits, thereby reducing the binary bit to bit ratio. However, inserting cabac_zero_words increases the bit rate and wastes bits.

[0025] According to some embodiments, instead of adding cabac_zero_words at the end of a coded picture, the number of padding (filler) bytes to be added by inserting cabac_zero_words can be signaled without actually sending padding bits. The encoder (or decoder) is configured to process the picture as if the codec has actually generated the signaled number of extra bytes in the video bitstream at the end of the picture, thereby saving the transmission of cabac_zero_words. The number of bytes or bits of the extra padding can be represented by a number representing the number of bytes or the number of cabac_zero_words (0x0000) or the number of bits. The value representing the number of data units (bytes, bits or cabac_zero_words (2 bytes)) can be represented by a fixed number of bits. For example, 32 bits or 16 bits. Alternatively, the syntax element can be represented by a variable number of bits using entropy coding (such as UE (V)) coding. The number assumed by the encoder for the number of padding bits or bytes can be the number of bits represented by the value, or it can be the value plus the length of a number representing the number of bytes or bits of the seasoning or any other number representing bytes or bits, such as a byte group, etc.

[0026] The following is an example implementation specified as a variation of the document JVET-O2001_vE. Specifically, the syntax may include.

[0027] 7.3.2.10 Slice-level RBSP syntax

[0028]

[0029] 7.3.2.11 RBSP slice tail bit syntax

[0030]

[0031] num_stuffing_bytes: Number of stuffing bytes.

[0032] The presence of the num_stuffing_bytes field may be conditional on the presence of a flag or a specific byte pattern preceding the num_stuffing_bytes, such as a zero byte, or as part of the rbsp_trailing_bits, where a flag indicating the presence of num_stuffing_bytes may be part of the rbsp_trailing_bits or the rbsp_trailing bits process may take into account the presence of such a flag for byte alignment.

[0033] Currently, the rbsp_trailing_bits process is as follows.

[0034] 7.3.2.12 RBSP tail bits syntax

[0035]

[0036] In one example, it changes to

[0037] 7.3.2.12 RBSP tail bits syntax

[0038]

[0039] Alternatively, it can be the last bit of the rbsp_trailing_bits process to satisfy byte alignment.

[0040] num_stuffing_bytes_flag: The num_stuffing_bytes field is present when set to 1. The following table illustrates one embodiment using italics and strikethrough to show changes relative to certain draft versions of VVC.

[0041] 7.3.2.11 RBSP slice tail bit syntax

[0042]

[0043] Alternatively, bytes may precede the num_stuffing_units field to indicate its presence, and potentially the length of the num_stuffing_bytes field (the following table illustrates one embodiment using italics and strikethrough to show changes relative to certain draft versions of VVC).

[0044] 7.3.2.11 RBSP slice tail bit syntax

[0045]

[0046] stuffing_bytes_field_length: indicates the number of bytes represented by num_stuffing_bytes. A value of zero indicates that the num_stuffing_bytes field does not exist.

[0047] The presence and indication of the number of padding bytes may also be signaled in the access unit delimiter using a similar field. An example includes (the following table illustrates one embodiment using italics and strikethrough to show changes relative to certain draft versions of VVC).

[0048] 7.3.2.7 Access Unit Separator RBSP Syntax

[0049]

[0050] In addition, BinCountsInNalUnits may be signaled in the access unit delimiter, and may be signaled per picture at the beginning of the picture, or may be signaled in the access unit delimiter rbsp field. An example may be indicated as follows (the following table is an embodiment using italics and strikethrough to show changes relative to certain draft versions of VVC).

[0051]

[0052] or

[0053]

[0054] In some embodiments, since the CABAC engine in VVC is an improvement over the engines used in AVC and HEVC, it makes sense to increase the bin-to-bit ratio limit. For example, in some embodiments, the ratio can be increased and specified as one of the following examples.

[0055] The value of BinCountsInNalUnits should be less than or equal to

[0056] 12*NumBytesInVclNalUnits+(RawMinCuBits*PicSizeInMinCbsY)÷32.

[0057] In an alternative embodiment.

[0058] The value of BinCountsInNalUnits should be less than or equal to

[0059] 56 / 5*NumBytesInVclNalUnits+(RawMinCuBits*PicSizeInMinCbsY)÷32.

[0060] Or the value of BinCountsInNalUnits should be less than or equal to

[0061] 272 / 25*NumBytesInVclNalUnits+(RawMinCuBits*PicSizeInMinCbsY)÷32.

[0062] Figure 1 1 is a block diagram illustrating an example video encoding and decoding system 100 that can perform the techniques of the present disclosure. The techniques of the present disclosure generally relate to encoding and decoding (encoding and / or decoding) video data. Generally, video data includes any data used to process video. Therefore, video data may include original unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling notification data.

[0063] like Figure 1 As shown, in this example, system 100 includes a source device 102 that provides encoded video data for decoding and display by a destination device 116. Specifically, source device 102 provides video data to destination device 116 via computer-readable medium 110. Source device 102 and destination device 116 may include any of a variety of devices, including desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets such as smartphones, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc. In some cases, source device 102 and destination device 116 may be equipped for wireless communication and, therefore, may be referred to as wireless communication devices.

[0064] exist Figure 1 In the example of , source device 102 includes video source 104, memory 106, video encoder 200 and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120 and display device 118. According to the present disclosure, the video encoder 200 of source device 102 and the video decoder 300 of destination device 116 can be configured to apply the technology disclosed herein. Therefore, source device 102 represents an example of a video encoding device, and destination device 116 represents an example of a video decoding device. In other examples, source device and destination device may include other components or arrangements. For example, source device 102 may receive video data from an external video source such as an external camera. Similarly, destination device 116 may interface with an external display device instead of including an integrated display device.

[0065] like Figure 1 The system 100 shown is only an example. The source device 102 and the destination device 116 are only examples of such codec devices, wherein the source device 102 generates encoded video data for transmission to the destination device 116. The present disclosure refers to a "codec" device as a device that performs the encoding and decoding (encoding and / or decoding) of data. Therefore, the video encoder 200 and the video decoder 300 represent examples of codec devices, specifically, examples of video encoders and video decoders, respectively. In some examples, the devices 102, 116 can operate in a substantially symmetrical manner, so that each of the devices 102, 116 includes a video encoding and decoding component. Therefore, the system 100 can support one-way or two-way video transmission between the video devices 102, 116, for example, for video streaming, video playback, video broadcasting, or video telephony.

[0066] Typically, video source 104 represents the source of video data (i.e., original, unencoded video data), and provides a continuous series of pictures (also referred to as "frames") of video data to video encoder 200, which encodes the data for these pictures. Video source 104 of source device 102 may include a video capture device such as a video camera, a video archive containing previously captured original video, and / or a video feed interface for receiving video from a video content provider. As a further alternative, video source 104 may generate computer graphics-based data as source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder 200 encodes captured, pre-captured, or computer-generated video data. Video codec 200 may rearrange pictures from the order received (sometimes referred to as "display order") into a codec order for encoding and decoding. Video codec 200 may generate a bitstream comprising encoded video data. Source device 102 may then output the encoded video data onto computer-readable medium 110 via output interface 108 for receipt and / or retrieval by, for example, input interface 122 of destination device 116 .

[0067] The memory 106 of the source device 102 and the memory 120 of the destination device 116 represent general purpose memories. In some examples, the memories 106, 120 can store original video data, for example, original video from the video source 104 and original, decoded video data from the video decoder 300. Additionally or alternatively, the memories 106, 120 can store software instructions that can be executed by, for example, the video encoder 200 and the video decoder 300, respectively. Although shown separately from the video encoder 200 and the video decoder 300 in this example, it should be understood that the video encoder 200 and the video decoder 300 can also include internal memories for functionally similar or equivalent purposes. In addition, the memories 106, 120 can store, for example, encoded video data output from the video encoder 200 and input to the video decoder 300. In some examples, portions of the memories 106, 120 can be allocated as one or more video buffers, for example to store original, decoded and / or encoded video data.

[0068] The computer-readable medium 110 may represent any type of medium or device capable of transmitting the encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to send the encoded video data directly to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. According to a communication standard such as a wireless communication protocol, the output interface 108 may modulate a transmission signal including the encoded video data, and the input interface 122 may modulate the received transmission signal. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include a router, a switch, a base station, or any other device that may be useful for facilitating communication from the source device 102 to the destination device 116.

[0069] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, Blu-ray disc, DVD, CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data.

[0070] In some examples, source device 102 may output the encoded video data to file server 114 or another intermediate storage device that may store the encoded video generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or downloading. File server 114 may be any type of server device capable of storing encoded video data and sending the encoded video data to destination device 116. File server 114 may represent a network server (e.g., for a website), a file transfer protocol (FTP) server, a content delivery network device, or a network attached storage (NAS) device. Destination device 116 may access the encoded video data from file server 114 via any standard data connection including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., DSL, cable modem, etc.) suitable for accessing the encoded video data stored on file server 114, or a combination of both. File server 114 and input interface 122 may be configured to operate according to a streaming transmission protocol, a download transmission protocol, or a combination thereof.

[0071] Output interface 108 and input interface 122 may represent wireless transmitters / receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components that operate according to any of the various IEEE 802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to communicate data, such as encoded video data, according to cellular communication standards such as 4G, 4G-LTE (Long Term Evolution), LTE Advanced, 5G, etc. In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to communicate data, such as encoded video data, according to other wireless standards (e.g., IEEE 802.11 specifications, IEEE 802.15 specifications (e.g., ZigBee 5G), etc.). TM ),Bluetooth TM Standards, etc.) to transfer data, such as encoded video data. In some examples, source device 102 and / or destination device 116 may include respective system-on-chip (SoC) devices. For example, source device 102 may include a SoC device for performing functionality attributed to video encoder 200 and / or output interface 108, while destination device 116 may include a SoC device for performing functionality attributed to video decoder 300 and / or input interface 122.

[0072] The techniques disclosed herein may be applied to support video encoding and decoding for any of a variety of multimedia applications such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission such as Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0073] The input interface 122 of the destination device 116 receives the encoded video bitstream from the computer-readable medium 110 (e.g., the storage device 112, the file server 114, etc.). The encoded video bitstream computer-readable medium 110 may include signaling notification messages defined by the video encoder 200 and also used by the video decoder 300, such as syntax elements with values ​​describing characteristics and / or processing of video blocks or other encoded units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0074] Although Figure 1 2, but in some examples, the video encoder 200 and the video decoder 300 may each be integrated with an audio encoder and / or an audio decoder and may include appropriate MUX-DEMUX units or other hardware and / or software to process multiplexed streams of both audio and video included in a common data stream. If applicable, the MUX-DEMUX units may conform to the ITU H.223 multiplexer protocol or other protocols such as the User Datagram Protocol (UDP).

[0075] The video encoder 200 and the video decoder 300 can each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When these technical parts are implemented in software, the device can store instructions for the software in a suitable, non-temporary computer-readable medium, and use one or more processors to execute these instructions in hardware to perform the technology of the present disclosure. Each of the video encoder 200 and the video decoder 300 can be included in one or more encoders or decoders, any of which can be integrated as part of a combined encoder / decoder (CODEC) in a corresponding device. The device including the video encoder 200 and / or the video decoder 300 can include an integrated circuit, a microprocessor, and / or a wireless communication device, such as a cellular phone.

[0076] The video encoder 200 and the video decoder 300 may operate according to a video codec standard, such as ITU-T H.265, also known as High Efficiency Video Codec (HEVC), or an extension thereof, such as a multi-view and / or scalable video codec extension. Alternatively, the video codec 200 and the video decoder 300 may operate according to other proprietary or industry standards, such as the Joint Exploration Test Model (JEM) or ITU-T H.266, also known as Versatile Video Codec (VVC). The latest draft of the VVC standard is described in: "Versatile Video Codec (Draft 3)" by Bross et al., Joint Video Experts Group (JVET) of ITU-T SG16WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 12th Meeting: Macau, CN, October 3-12, 2018, JVET-L1001-v9 (hereinafter referred to as "VVC Draft 3"). However, the technology of the present disclosure is not limited to any particular codec standard.

[0077] Typically, the video encoder 200 and the video decoder 300 can perform block-based encoding and decoding of pictures. The term "block" generally refers to a structure that includes data to be processed (e.g., encoded, decoded, or otherwise used in an encoding and / or decoding process). For example, a block may include a two-dimensional matrix of samples of luminance and / or chrominance data. Typically, the video encoder 200 and the video decoder 300 can encode and decode video data represented in a YUV (e.g., Y, Cb, Cr) format. That is, the video encoder 200 and the video decoder 300 can encode luminance and chrominance components instead of encoding and decoding red, green, and blue (RGB) data for picture samples, where the chrominance components may include both red hue and blue hue chrominance components. In some examples, the video encoder 200 converts the received RGB formatted data into a YUV representation before encoding, and the video decoder 300 converts the YUV representation into an RGB format. Alternatively, pre-processing and post-processing units (not shown) can perform these conversions.

[0078] The present disclosure may generally refer to the encoding and decoding of a picture (e.g., encoding and decoding) to include the process of encoding or decoding data for the picture. Similarly, the present disclosure may refer to the encoding and decoding of a block of a picture as including the process of encoding or decoding data for the block, for example, prediction and / or residual encoding and decoding. The encoded video bitstream typically includes some syntax elements that represent codec decisions (such as codec mode) and the partitioning of the picture into blocks. Therefore, references to encoding and decoding a picture or block should generally be understood as encoding and decoding the values ​​of the syntax elements that form the picture or block.

[0079] HEVC defines various blocks, including codec units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video codec (such as video encoder 200) partitions a codec tree unit (CTU) into CUs according to a quadtree structure. That is, the video codec partitions the CTU and CU into four equal, non-overlapping squares, and each node of its quadtree has zero or four child nodes. A node without child nodes may be referred to as a "leaf node", and the CU of such a leaf node may include one or more PUs and / or one or more TUs. The video codec may further partition the PU and TU. For example, in HEVC, the residual quadtree (RQT) represents the partitioning of the TU. In HEVC, PU represents inter-frame prediction data, and TU represents residual data. The intra-predicted CU includes intra-frame prediction information, such as an intra-frame mode indication.

[0080] As another example, the video encoder 200 and the video decoder 300 may be configured to operate according to JEM or VVC. According to JEM or VVC, a video codec (such as the video encoder 200) partitions a picture into multiple codec tree units (CTUs). The video encoder 200 may partition the CTU according to a tree structure such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure removes the concept of multiple partition types, such as the separation between CU, PU, ​​and TU of HEVC. The QTBT structure includes two levels: a first level partitioned according to quadtree partitioning, and a second level partitioned according to binary tree partitioning. The root node of the QTBT structure corresponds to the CTU. The leaf nodes of the binary tree correspond to codec units (CUs).

[0081] In the MTT partitioning structure, blocks can be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of ternary tree (TT) partitioning. Ternary tree partitioning is a partitioning in which a block is split into three sub-blocks. In some examples, ternary tree partitioning divides a block into three sub-blocks without dividing the original block through the center. The partitioning types in MTT (such as QT, BT, and TT) can be symmetric or asymmetric.

[0082] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT structure or MTT structure to represent each of the luma component and the chroma component, while in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT structures or MTT structures, such as one QTBT / MTT structure for the luma component and another QTBT / MTT structure for the two chroma components (or two QTBT / MTT structures for corresponding chroma components).

[0083] The video encoder 200 and the video decoder 300 may be configured to use quadtree segmentation, QTBT segmentation, MTT segmentation, or other segmentation structures in accordance with HEVC. For purposes of explanation, the techniques of the present disclosure are presented with respect to QTBT segmentation. However, it should be understood that the techniques of the present disclosure may also be applied to a video codec configured to use quadtree segmentation or other types of segmentation.

[0084] This disclosure may use "N×N" and "N by N" interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in terms of vertical and horizontal dimensions, for example, 16×16 samples or 16 by 16 samples. Typically, a 16×16 CU will have 16 samples in the vertical direction (y=16) and 16 samples in the horizontal direction (x=16). Similarly, an N×N CU typically has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. The samples in a CU may be arranged in rows and columns. In addition, a CU does not necessarily have the same number of samples in the horizontal direction as in the vertical direction. For example, a CU may include N×M samples, where M is not necessarily equal to N.

[0085] The video encoder 200 encodes video data representing prediction and / or residual information and other information for a CU. The prediction information indicates how the CU will be predicted to form a prediction block for the CU. The residual information generally indicates the sample-by-sample difference between the sample of the CU before encoding and the prediction block.

[0086] In order to predict a CU, the video encoder 200 may typically form a prediction block for the CU by inter-frame prediction or intra-frame prediction. Inter-frame prediction typically refers to predicting a CU based on data of a previously encoded picture, while intra-frame prediction typically refers to predicting a CU based on previously encoded data of the same picture. In order to perform inter-frame prediction, the video encoder 200 may use one or more motion vectors to generate a prediction block. The video encoder 200 may typically perform a motion search to identify a reference block that closely matches the CU, for example, based on the difference between the CU and the reference block. The video encoder 200 may calculate a difference metric using the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), or other such difference calculations to determine whether the reference block closely matches the current CU. In some examples, the video encoder 200 may use unidirectional prediction or bidirectional prediction to predict the current CU.

[0087] Some examples of JEM and VVC also provide an affine motion compensation mode, which can be considered an inter-frame prediction mode. In the affine motion compensation mode, the video encoder 200 can determine two or more motion vectors representing non-translational motions such as: zooming in or out, rotation, perspective motion, or other irregular motion types.

[0088] To perform intra prediction, the video encoder 200 may select an intra prediction mode to generate a prediction block. Some examples of JEM and VVC provide sixty-seven intra prediction modes, including various directional modes, as well as a plane mode and a DC mode. Typically, the video codec 200 selects an intra prediction mode that describes a neighboring sample of a current block (e.g., a block of a CU) to predict the sample of the current block based on it. Assuming that the video encoder 200 encodes and decodes CTUs and CUs in a raster scan order (from left to right, from top to bottom), such samples may typically be located above, to the upper left, or to the left of the current block in the same picture as the current block.

[0089] The video encoder 200 encodes data representing the prediction mode for the current block. For example, for the inter-frame prediction mode, the video encoder 200 may encode data representing which of the various available inter-frame prediction modes to use and the motion information for the corresponding mode. For example, for unidirectional or bidirectional inter-frame prediction, the video encoder 200 may encode the motion vector using Advanced Motion Vector Prediction (AMVP) or Merge mode. For the affine motion compensation mode, the video encoder 200 may encode using a similar mode motion vector.

[0090] After prediction of a block, such as intra prediction or inter prediction of a block, the video encoder 200 may calculate residual data for the block. Residual data such as a residual block represents the sample-by-sample difference between a block and a prediction block for the block formed using a corresponding prediction mode. The video encoder 200 may apply one or more transforms to the residual block to generate transformed data in a transform domain rather than a sample domain. For example, the video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. Additionally, the video encoder 200 may apply a secondary transform after the primary transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, a Karl-Love transform (KLT), etc. The video encoder 200 generates transform coefficients after applying one or more transforms.

[0091] As described above, after any transform used to produce transform coefficients, the video encoder 200 can perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 can reduce the bit depth associated with some or all of the coefficients. For example, during the quantization process, the video encoder 200 can round an n-bit value to an m-bit value, where n is greater than m. In some examples, to perform quantization, the video encoder 200 can perform a bitwise right shift of the value to be quantized.

[0092] After quantization, the video encoder 200 can scan the transform coefficients to produce a one-dimensional vector from a two-dimensional matrix including the quantized transform coefficients. The scan can be designed to place coefficients with higher energy (and therefore lower frequency) in front of the vector and transform coefficients with lower energy (and therefore higher frequency) in the back of the vector. In some examples, the video encoder 200 can scan the quantized transform coefficients using a predefined scan order to produce a serialized vector, and then entropy encode the quantized transform coefficients of the vector. In other examples, the video encoder 200 can perform adaptive scanning. After scanning the quantized transform coefficients to form a one-dimensional vector, the video encoder 200 can, for example, entropy encode the one-dimensional vector according to context adaptive binary arithmetic coding (CABAC). The video encoder 200 can also entropy encode values ​​for syntax elements that describe metadata associated with the encoded video data for use by the video decoder 300 when decoding the video data.

[0093] To perform CABAC, the video codec 200 may assign context within a context model to a symbol to be transmitted. The context may relate to, for example, whether the neighboring values ​​of the symbol are zero values. The probability determination may be based on the context assigned to the symbol.

[0094] The video encoder 200 may further generate, for example, block-based syntax data, picture-based syntax data, and sequence-based syntax data in a picture header, a block header, a slice header, or other syntax data such as a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS) to the video decoder 300. The video decoder 300 may also decode such syntax data to determine how to decode the corresponding video data.

[0095] In this way, the video encoder 200 can generate a bitstream that includes coded video data, such as syntax elements describing the partitioning of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Finally, the video decoder 300 can receive the bitstream and decode the coded video data.

[0096] In general, the video decoder 300 performs a process that is the reverse of the process performed by the video encoder 200 to decode the encoded video data of the bitstream. For example, the video decoder 300 may decode values ​​for syntax elements in the bitstream using CABAC in a manner substantially similar, albeit reversed, to the CABAC encoding process of the video encoder 200. The syntax elements may define partitioning information of a picture into CTUs, and partitioning of each CTU according to a corresponding partitioning structure such as a QTBT structure to define CUs of the CTU. The syntax elements may further define prediction and residual information for a block (e.g., a CU) of video data.

[0097] The residual information may be represented by, for example, quantized transform coefficients. The video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of the block to reproduce a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-frame or inter-frame prediction) and related prediction information (e.g., motion information for inter-frame prediction) to form a prediction block for the block. The video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. The video decoder 300 may perform additional processing, such as performing a deblocking process, to reduce visual artifacts along the boundaries of the blocks.

[0098] The present disclosure may generally involve "signaling" certain information, such as syntax elements. The term "signaling" may generally relate to the communication of values ​​for syntax elements and / or other data used to decode encoded video data. That is, the video encoder 200 may signal syntax elements in a bitstream. Typically, signaling involves generating values ​​in the bitstream. As described above, the source device 102 may transmit the bitstream to the destination device 116 substantially in real time or in non-real time, such as may occur when the syntax elements are stored to the storage device 112 for later retrieval by the destination device 116.

[0099] Figure 2A and Figure 2Bis a conceptual diagram illustrating an example quadtree binary tree (QTBT) structure 130, and a corresponding codec tree unit (CTU) 132. Solid lines represent quadtree splits, while dashed lines indicate binary tree splits. In each split (i.e., non-leaf) node of the binary tree, a flag is signaled to indicate which split type (i.e., horizontal or vertical) is used, where in this example, 0 indicates horizontal splitting and 1 indicates vertical splitting. For quadtree splitting, there is no need to indicate the split type because the quadtree node splits the block horizontally and vertically into 4 equally sized sub-blocks. Therefore, the video encoder 200 can encode, and the video decoder 300 can decode, syntax elements (such as split information) for the region tree level (i.e., solid lines) of the QTBT structure 130 and syntax elements (such as split information) for the prediction tree level (i.e., dashed lines) of the QTBT structure 130. The video encoder 200 may encode, and the video decoder 300 may decode, video data such as prediction and transform data for a CU represented by a terminal leaf node of the QTBT structure 130 .

[0100] generally, Figure 2B The CTU 132 may be associated with parameters defining the size of blocks corresponding to nodes at the first and second levels in the QTBT structure 130. These parameters may include a CTU size (in terms of samples, indicating the size of the CTU 132), a minimum quadtree size (MinQTSize, indicating the minimum allowed quadtree leaf node size), a maximum binary tree size (MaxBTSize, indicating the maximum allowed binary tree root node size), a maximum binary tree depth (MaxBTDepth, indicating the maximum allowed binary tree depth), and a minimum binary tree size (MinBTSize, indicating the minimum allowed binary tree leaf node size).

[0101] The root node of the QTBT structure corresponding to the CTU can have four child nodes at the first level of the QTBT structure, each of which can be segmented according to the quadtree segmentation. That is, the node of the first level is a leaf node (no child nodes) or has four child nodes. The example of the QTBT structure 130 represents such nodes as a parent node and a child node including a solid line for branching. If the nodes of the first level are not larger than the maximum allowed binary tree root node size (MaxBTSize), they can be further segmented by the corresponding binary tree. The binary tree splitting of a node can be iterated until the node obtained by the split reaches the minimum allowed binary tree leaf node size (MinBTSize) or the maximum allowed binary tree depth (MaxBTDepth). The example of the QTBT structure 130 represents such nodes as having a dotted line for branching. The binary tree leaf node is called a codec unit (CU), which is used for prediction (e.g., intra-picture or inter-picture prediction) and transformation without any further segmentation. As described above, a CU may also be referred to as a "video block" or "block".

[0102] In one example of a QTBT partitioning structure, the CTU size is set to 128×128 (luminance sample and two corresponding 64×64 chrominance samples), MinQTSize is set to 16×16, MaxBTSize is set to 64×64, MinBTSize (for both width and height) is set to 4, and MaxBTDepth is set to 4. Quadtree partitioning is first applied to the CTU to generate quadtree leaf nodes. Quadtree leaf nodes can have sizes from 16×16 (i.e., MinQTSize) to 128×128 (i.e., CTU size). If the leaf quadtree node is 128×128, it will not be further split by the binary tree because the size exceeds MaxBTSize (i.e., in this example, 64×64). Otherwise, the leaf quadtree node will be further split by the binary tree. Therefore, the quadtree leaf node is also the root node of the binary tree and has a binary tree depth of 0. When the binary tree depth reaches MaxBTDepth (4 in this example), no further splitting is allowed. When a binary tree node has a width equal to MinBTSize (4 in this example), this means that no further horizontal splitting is allowed. Similarly, a binary tree node with a height equal to MinBTSize means that no further vertical splitting is allowed for the binary tree node. As described above, the leaf nodes of the binary tree are called CUs and are further processed according to prediction and transformation without the need for further segmentation.

[0103] Figure 3 is a block diagram illustrating an example video encoder 200 that may perform the techniques of this disclosure. Figure 3The above description is provided for the purpose of explanation and should not be considered as limiting the techniques broadly illustrated and described in this disclosure. For the purpose of explanation, this disclosure describes the video encoder 200 in the context of video codec standards such as the HEVC video codec standard and the developing H.266 video codec standard. However, the techniques of this disclosure are not limited to these video codec standards and can be generally applied to video encoding and decoding.

[0104] exist Figure 3 In the example of , the video encoder 200 includes a video data memory 230, a mode selection unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filter unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any or all of the video data memory 230, the mode selection unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filter unit 216, the DPB 218, and the entropy coding unit 220 may be implemented in one or more processors or processing circuits. In addition, the video encoder 200 may include additional or alternative processors or processing circuits to perform these and other functions.

[0105] The video data memory 230 may store video data to be encoded by the components of the video encoder 200. The video encoder 200 may receive video data from, for example, the video source 104 ( Figure 1 ) receives video data stored in video data memory 230. DPB 218 can act as a reference picture memory, storing reference video data for predicting subsequent video data by video codec 200. Video data memory 230 and DPB 218 can be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM)), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 can be provided by the same memory device or separate memory devices. In various examples, video data memory 230 can be located on-chip with other components of video encoder 200, as shown in the figure, or off-chip relative to these components.

[0106] In the present disclosure, references to the video data memory 230 should not be interpreted as limited to only memory internal to the video encoder 200, unless specifically described as such, or memory external to the video encoder 200, unless specifically described as such. Rather, references to the video data memory 230 should be understood as reference memory that stores video data received by the video encoder 200 for encoding (e.g., video data for a current block to be encoded). Figure 1 The memory 106 may also provide temporary storage for outputs from the various units of the video encoder 200 .

[0107] Figure 3 Various units are illustrated to help understand the operations performed by the video encoder 200. These units can be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide specific functions and are preset on operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functionality in the operations that can be performed. For example, a programmable circuit can execute software or firmware so that the programmable circuit operates in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (for example, to receive parameters or output parameters), but the type of operation performed by the fixed-function circuit is generally immutable. In some examples, one or more of the units may be different circuit blocks (fixed-function or programmable), while in some examples, one or more of the units may be integrated circuits.

[0108] The video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video encoder 200 is performed using software executed by a programmable circuit, the memory 106 ( Figure 1 ) may store object code for software received and executed by the video encoder 200, or another memory (not shown) within the video encoder 200 may store such instructions.

[0109] The video data memory 230 is configured to store received video data. The video encoder 200 may retrieve a picture of video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be original video data to be encoded.

[0110] The mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode selection unit 202 may include additional functional units for performing video prediction according to other prediction modes. As an example, the mode selection unit 202 may include a palette unit, an intra block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, and the like.

[0111] The mode selection unit 202 typically coordinates multiple encoding passes to test combinations of encoding parameters and the resulting rate-distortion values ​​for such combinations. The encoding parameters may include the partitioning of CTUs into CUs, the prediction mode for the CU, the transform type for the residual data of the CU, the quantization parameter for the residual data of the CU, etc. The mode selection unit 202 may ultimately select a coding parameter combination that has a better distortion value than other tested combinations.

[0112] The video codec 200 may partition a picture retrieved from the video data memory 230 into a series of CTUs and encapsulate one or more CTUs in a slice. The mode selection unit 210 may partition the CTUs of the picture according to a tree structure such as a QTBT structure or the quadtree structure of HEVC described above. As described above, the video encoder 200 may form one or more CUs by partitioning the CTUs according to the tree structure. Such CUs may also be generally referred to as "video blocks" or "blocks".

[0113] Typically, the mode selection unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for the current block (e.g., the current CU, or the overlapping portion of the PU and TU in HEVC). For inter prediction of the current block, the motion estimation unit 222 can perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously coded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 can calculate a value indicating how similar the potential reference block is to the current block, for example, based on the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), etc. The motion estimation unit 222 can generally perform these calculations using the sample-by-sample difference between the current block and the reference block under consideration. The motion estimation unit 222 can identify the reference block with the lowest of these calculated values, indicating the reference block that most closely matches the current block.

[0114] The motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to a current block in a current picture. The motion estimation unit 222 may then provide the motion vectors to the motion compensation unit 224. For example, for unidirectional inter prediction, the motion estimation unit 222 may provide a single motion vector, and for bidirectional inter prediction, the motion estimation unit 222 may provide two motion vectors. The motion compensation unit 224 may then use the motion vectors to generate a prediction block. For example, the motion compensation unit 224 may use the motion vectors to retrieve data for the reference block. As another example, if the motion vectors have fractional sample precision, the motion compensation unit 224 may interpolate values ​​for the prediction block according to one or more interpolation filters. In addition, for bidirectional inter prediction, the motion compensation unit 224 may retrieve data for two reference blocks identified by the corresponding motion vectors, and combine the retrieved data, for example, by sample-by-sample averaging or weighted averaging.

[0115] As another example, for intra prediction or intra prediction codec, the intra prediction unit 226 can generate a prediction block based on samples adjacent to the current block. For example, for directional mode, the intra prediction unit 226 can generally mathematically combine the values ​​of the adjacent samples and fill these calculated values ​​in a defined direction across the current block to generate a prediction block. As another example, for DC mode, the intra prediction unit 226 can calculate the average of the adjacent samples of the current block and generate a prediction block such that for each sample of the prediction block, this obtained average is included.

[0116] The mode selection unit 202 provides the prediction block to the residual generation unit 204. The residual generation unit 204 receives the original, uncoded version of the current block from the video data memory 230 and receives the prediction block from the mode selection unit 202. The residual generation unit 204 calculates the sample-by-sample difference between the current block and the prediction block. The resulting sample-by-sample difference defines a residual block for the current block. In some examples, the residual generation unit 204 may also determine the difference between the sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, the residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0117] In an example in which the mode selection unit 202 partitions the CU into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. The video encoder 200 and the video decoder 300 may support PUs of various sizes. As described above, the size of the CU may refer to the size of the luma codec block of the CU, and the size of the PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2N×2N, the video encoder 200 may support PUs of size 2N×2N or N×N for intra-frame prediction, and symmetric PUs of size 2N×2N, 2N×N, N×2N, N×N, or similar sizes for inter-frame prediction. The video encoder 200 and the video decoder 300 may also support asymmetric partitioning of PUs of size 2N×nU, 2N×nD, nL×2N, and nR×2N for inter-frame prediction.

[0118] In an example where the mode selection unit does not further partition a CU into PUs, each CU may be associated with a luma codec block and a corresponding chroma codec block. As described above, the size of a CU may refer to the size of the luma codec block of the CU. The video encoder 200 and the video decoder 120 may support CUs of size 2N×2N, 2N×N, or N×2N.

[0119] For other video codec techniques such as intra-block copy mode codec, affine mode codec, and linear model (LM) mode codec, as several examples, the mode selection unit 202 generates a prediction block for the current block being coded via a corresponding unit associated with the codec technique. In some examples, such as palette mode codec, the mode selection unit 202 may not generate a prediction block, but instead generate syntax elements indicating a manner to reconstruct the block based on the selected palette. In such a mode, the mode selection unit 202 may provide these syntax elements to the entropy coding unit 220 for encoding.

[0120] As described above, the residual generation unit 204 receives video data for a current block and a corresponding prediction block. Then, the residual generation unit 204 generates a residual block for the current block. To generate the residual block, the residual generation unit 204 calculates the sample-by-sample difference between the prediction block and the current block.

[0121] The transform processing unit 206 applies one or more transforms to the residual block to output a block of transform coefficients (referred to herein as a "transform coefficient block"). The transform processing unit 206 may apply various transforms to the residual block to form a transform coefficient block. For example, the transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karl-Lof transform (KLT), or a conceptually similar transform to the residual block. In some examples, the transform processing unit 206 may perform multiple transforms on the residual block, for example, a primary transform and a secondary transform, such as a rotation transform. In some examples, the transform processing unit 206 does not apply a transform to the residual block.

[0122] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to produce a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode selection unit 202) may adjust the degree of quantization applied to the coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may introduce information loss, and therefore, the quantized transform coefficients may have lower precision than the original transform coefficients produced by the transform processing unit 206.

[0123] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform to the quantized transform coefficient block, respectively, to reconstruct a residual block from the transform coefficient block. The reconstruction unit 214 may generate a reconstructed block corresponding to the current block (although there may be a certain degree of distortion) based on the reconstructed residual block and the prediction block generated by the mode selection unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples of the prediction block generated by the mode selection unit 202 to generate a reconstructed block.

[0124] Filter unit 216 may perform one or more filter operations on the reconstructed block. For example, filter unit 216 may perform a deblocking operation to reduce blocking artifacts along the edges of the CU. In some examples, the operation of filter unit 216 may be skipped.

[0125] The video codec 200 stores the reconstructed blocks in the DPB 218. For example, in examples where the operation of the filter unit 216 is not required, the reconstruction unit 214 can store the reconstructed blocks to the DPB 218. In examples where the operation of the filter unit 216 is required, the filter unit 216 can store the filtered reconstructed blocks to the DPB 218. The motion estimation unit 222 and the motion compensation unit 224 can retrieve a reference picture from the DPB 218, which is formed by the reconstructed (and possibly filtered) blocks to perform inter-frame prediction on the blocks of the subsequent encoded pictures. In addition, the intra-frame prediction unit 226 can use the reconstructed blocks in the DPB 218 of the current picture to perform intra-frame prediction on other blocks in the current picture.

[0126] In general, the entropy coding unit 220 may entropy encode syntax elements received from other functions of the video encoder 200. For example, the entropy coding unit 220 may entropy encode a block of quantized transform coefficients from the quantization unit 208. As another example, the entropy coding unit 220 may entropy encode a prediction syntax element (e.g., motion information for inter-frame prediction or intra-frame mode information for intra-frame prediction) from the mode selection unit 202. The entropy coding unit 220 may perform one or more entropy coding operations on syntax elements as another example of video data to generate entropy-encoded data. For example, the entropy coding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable to variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a probability interval partitioning entropy (PIPE) coding operation, an exponential-Golomb coding operation, or another type of entropy coding operation on the data. In some examples, the entropy coding unit 220 may operate in a bypass mode in which the syntax elements are not entropy encoded.

[0127] The video encoder 200 may output a bitstream including entropy-encoded syntax elements required for reconstructing blocks of a slice or picture. Specifically, the entropy encoding and decoding unit 220 may output a bitstream.

[0128] The operations described above are described with respect to blocks. Such descriptions should be understood as operations for luma codec blocks and / or chroma codec blocks. As described above, in some examples, the luma codec blocks and chroma codec blocks are the luma and chroma components of a CU. In some examples, the luma codec blocks and chroma codec blocks are the luma and chroma components of a PU.

[0129] In some examples, operations performed with respect to the luma codec block need not be repeated for the chroma codec block. As an example, operations for identifying motion vectors (MVs) and reference pictures for the luma codec block need not be repeated for identifying MVs and reference pictures for the chroma codec block. Specifically, the MVs for the luma codec block may be scaled to determine the MVs for the chroma blocks, while the reference pictures may be the same. As another example, the intra prediction process may be the same for the luma codec block and the chroma codec block.

[0130] Video encoder 200 represents an example of a device configured to encode video data, including a memory configured to store the video data, and one or more processing units implemented in circuitry, and which is configured to encode a number of additional bits that are not signaled but that the encoder is configured to assume have been signaled, to satisfy a bin-to-bit ratio constraint.

[0131] Figure 4 is a block diagram illustrating an example video decoder 300 that may perform the techniques of this disclosure. Figure 4 The above description is provided for the purpose of explanation and is not intended to limit the techniques extensively illustrated and described in this disclosure. For the purpose of explanation, this disclosure describes a video decoder 300 according to the technical descriptions of JEM, VVC, and HEVC. However, the techniques of this disclosure may be performed by video codec devices configured for other video codec standards.

[0132] exist Figure 4 In the example of , the video decoder 300 includes a codec picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a decoded picture buffer (DPB) 314. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 may be implemented in one or more processors or processing circuits. In addition, the video decoder 300 may include additional or alternative processors or processing circuits to perform these and other functions.

[0133] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 may include additional units for performing predictions according to other prediction modes. As an example, the prediction processing unit 304 may include a palette unit, an intra block copy unit (which may form part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0134] The CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of the video decoder 300. The video data stored in the CPB memory 320 may be, for example, received from the computer-readable medium 110 ( Figure 1 ). The CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from an encoded video bitstream. In addition, the CPB memory 320 may store video data other than syntax elements of an encoded picture, such as temporary data representing outputs from various units of the video decoder 300. The DPB 314 typically stores a decoded picture, which the video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. The CPB memory 320 and the DPB 314 may be formed by any of a variety of memory devices, such as a dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM)), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM), or other types of memory devices. The CPB memory 320 and the DPB 314 may be provided by the same memory device or by separate memory devices. In various examples, the CPB memory 320 may be located on-chip with other components of the video decoder 300, or off-chip relative to these components.

[0135] Additionally or alternatively, in some examples, video decoder 300 may retrieve the video from memory 120 ( Figure 1 ) to retrieve the encoded video data. That is, memory 120 may store data as discussed above in conjunction with CPB memory 320. Likewise, when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300, memory 120 may store instructions to be executed by video decoder 300.

[0136] Figure 4 The various units shown in FIG. 3 are illustrated to help understand the operations performed by the video decoder 300. These units may be implemented as fixed function circuits, programmable circuits, or a combination thereof. Figure 3Similarly, a fixed-function circuit refers to a circuit that provides a specific function and is preset on the operations that can be performed. A programmable circuit refers to a circuit that can be programmed to perform various tasks and provides flexible functionality in the operations that can be performed. For example, a programmable circuit can execute software or firmware so that the programmable circuit operates in a manner defined by the instructions of the software or firmware. A fixed-function circuit can execute software instructions (for example, to receive parameters or output parameters), but the type of operation performed by the fixed-function circuit is generally unchangeable. In some examples, one or more of the units may be different circuit blocks (fixed function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0137] The video decoder 300 may include an ALU, an EFU, a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video decoder 300 is performed by software executed on the programmable circuit, an on-chip or off-chip memory may store instructions (e.g., object code) of the software received and executed by the video decoder 300.

[0138] Entropy decoding unit 302 may receive encoded video data from the CPB and entropy decode the video data to reproduce syntax elements. Prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, and filter unit 312 may generate decoded video data based on syntax elements extracted from the bitstream.

[0139] Typically, the video decoder 300 reconstructs a picture on a block-by-block basis. The video decoder 300 may perform a reconstruction operation on each block individually (where the block currently being reconstructed, ie, decoded, may be referred to as a "current block").

[0140] The entropy decoding unit 302 may entropy decode syntax elements defining the quantized transform coefficients of the quantized transform coefficient block and a transform such as a quantization parameter (QP) and / or (one or more) transform mode indications. The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, likewise, determine a degree of inverse quantization for the inverse quantization unit 306 to apply. The inverse quantization unit 306 may, for example, perform a bitwise left shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block including the transform coefficients.

[0141] After the inverse quantization unit 306 forms the transform coefficient block, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karl-Lof transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the coefficient block.

[0142] In addition, prediction processing unit 304 generates a prediction block based on the prediction information syntax element entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax element indicates that the current block is inter-predicted, motion compensation unit 316 can generate the prediction block. In this case, the prediction information syntax element can indicate a reference picture in DPB 314 from which the reference block is retrieved, and a motion vector that identifies the position of the reference block in the reference picture relative to the position of the current block in the current picture. Motion compensation unit 316 can generally generate a prediction block in the same manner as relative to motion compensation unit 224 ( Figure 3 ) and the inter-frame prediction process is performed in a substantially similar manner as described above.

[0143] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, the intra-prediction unit 318 can generate a prediction block according to the intra-prediction mode indicated by the prediction information syntax element. Similarly, the intra-prediction unit 318 can generally generate a prediction block in the same manner as the intra-prediction unit 226 ( Figure 3 The intra prediction process may be performed in a substantially similar manner as described above. The intra prediction unit 318 may retrieve data of neighboring samples for the current block from the DPB 314.

[0144] The reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0145] The filter unit 312 may perform one or more filter operations on the reconstructed block. For example, the filter unit 312 may perform a deblocking operation to reduce blocking artifacts along the edges of the reconstructed block. The operations of the filter unit 312 need not be performed in all examples.

[0146] The video decoder 300 may store the reconstructed blocks in the DPB 314. As described above, the DPB 314 may provide reference information to the prediction processing unit 304, such as samples of the current picture for intra-frame prediction and samples of previously decoded pictures for subsequent motion compensation. In addition, the video decoder 300 may output the decoded pictures from the DPB for subsequent display on a display device (e.g., Figure 1 is presented on a display device 118).

[0147] In this way, video decoder 300 represents an example of a video decoding device comprising a memory configured to store video data, and one or more processing units implemented in circuitry and configured to decode a number of additional bits that were not signaled but that the encoder is configured to assume were signaled to satisfy a bin-to-bit ratio constraint.

[0148] Figure 5 2 is a flowchart illustrating an example method for encoding and decoding a current block. The current block may include a current CU. Although with respect to the video codec 200 ( Figure 1 2), but it should be understood that other devices may be configured to perform similar Figure 5 method.

[0149] In this example, the video encoder 200 initially predicts the current block (350). For example, the video encoder 200 may form a prediction block for the current block. The video codec 200 may then calculate a residual block for the current block (352). To calculate the residual block, the video encoder 200 may calculate the difference between the original, unencoded block and the prediction block and the current block. The video encoder 200 may then transform and quantize the coefficients of the residual block (354). Next, the video encoder 200 may scan the quantized transform coefficients of the residual block (356). During the scan, or after the scan, the video encoder 200 may entropy encode the coefficients (358). For example, the video encoder 200 may encode the coefficients using CAVLC or CABAC. The video codec 200 may then output the entropy-encoded data of the block (360).

[0150] Figure 6 300 ( Figure 1 and Figure 3 ), but it should be understood that other devices may be configured to perform similar Figure 6 method.

[0151] The video decoder 300 may receive entropy-encoded data of a current block, such as entropy-encoded prediction information and entropy-encoded data of coefficients of a residual block corresponding to the current block (370). The video decoder 300 may entropy decode the entropy-encoded data to determine prediction information of the current block and reproduce coefficients of the residual block (372). The video decoder 300 may predict the current block (374), such as by an intra-prediction or inter-prediction mode as indicated by the prediction information of the current block, to calculate a prediction block of the current block. The video decoder 300 may then inverse scan the reproduced coefficients (376) to create a block of quantized transform coefficients. The video decoder 300 may then inverse quantize and inverse transform the coefficients to generate a residual block (378). The video decoder 300 may ultimately decode the current block by combining the prediction block and the residual block (380).

[0152] Figure 7 1 is a diagram illustrating encoding or decoding of video data according to some embodiments using a video encoder 200 or a video decoder 300. Since the process is symmetrical, both encoding and decoding of the bitstream are described together, but it should be understood that it is a complementary process performed by the encoder 200 or the decoder 300. The method includes box 402, where the video encoder 200 or the video decoder 300 encodes and decodes a syntax element for a video data unit, and the syntax element indicates the number of padding bits. Specifically, the video encoder 200 encodes and decodes the syntax element to the video bitstream, and the video decoder 300 decodes the syntax element to the video bitstream. In some embodiments, the syntax element can be encoded and decoded as part of a video codec layer. The unit of video data may include a sequence, a picture, a slice, a maximum codec unit of a slice, or a unit of any other video data. The syntax element can be encoded at any suitable video syntax level, such as a picture parameter set, a slice header, or any other syntax structure corresponding to a unit.

[0153] The method continues to block 404, where the video encoder 200 or the video decoder 300 encodes and decodes the video data unit without encoding and decoding the padding bits in the video bitstream. The video encoder 200 may encode all associated syntax structures of the video data unit. However, instead of inserting a plurality of padding bits as indicated by the syntax element, the video bitstream is encoded without the padding bits. The video codec 200 may decode all associated syntax structures of the video data unit. However, instead of expecting and processing a plurality of padding bits from the video bitstream as indicated by the syntax element, the video bitstream is decoded without decoding and processing the indicated padding bits.

[0154] It should be appreciated that, depending on the example, certain actions or events in any of the techniques described herein 2 may be performed in a different sequence, may be added, combined, or omitted entirely (e.g., not all described actions or events are necessary for the practice of the techniques). In addition, in some examples, actions or events may be performed concurrently, such as by multithreading, interrupt handling, or multiple processors, rather than sequentially.

[0155] In one or more examples, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or sent as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to tangible media such as data storage media; or communication media, including, for example, any medium that facilitates the transfer of a computer program from one place to another according to a communication protocol. In this manner, computer-readable media may generally correspond to (1) non-transitory, tangible computer-readable storage media, or (2) communication media such as signals or carrier waves. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in the present disclosure. A computer program product may include a computer-readable medium.

[0156] As an example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store the required program code in the form of instructions or data structures and can be accessed by a computer. In addition, any connection is properly referred to as a computer-readable medium. For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to send instructions from a website, server, or other remote source, then coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other temporary media, but are directed to non-temporary, tangible storage media. Disks and optical disks used herein include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVDs), floppy disks, and blue-ray disks, wherein disks usually reproduce data magnetically, and optical disks reproduce data optically with lasers. The combination of the above items should also be included in the scope of computer-readable media.

[0157] The instructions may be executed by one or more processors such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the terms "processor" and "processing circuitry" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0158] The techniques of the present disclosure may be implemented in a variety of devices or apparatuses, including wireless handheld devices, integrated circuits (ICs), or IC sets (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but are not necessarily required to be implemented by different hardware units. Instead, as described above, the various units may be combined in a codec hardware unit, or provided by a collection of interoperable hardware units including one or more processors as described above in combination with appropriate software and / or firmware.

[0159] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for encoding video data, the method comprising: encoding, into a video bitstream, a syntax element for a video data unit, the syntax element indicating a non-zero number of padding bits; as well as Encoding the video data unit into the video bitstream without including the padding bits into the video bitstream includes determining a number of bits in a bitstream for the video data unit using a number of padding bits indicated by the syntax element.

2. The method of claim 1, wherein the number of padding bits is different from the number of bits used by the syntax element in the video bitstream. The method according to claim 1 , wherein the video data unit is a picture. The method according to claim 1 , wherein the video data unit is a slice.

5. The method of claim 1, wherein encoding the syntax element comprises encoding the syntax element into a video codec layer of the video bitstream.

6. The method of claim 1, further comprising determining a ratio of context adaptive binary arithmetic coding bins to bits in the bitstream based on the determined number of bits in the bitstream for the video data unit.

7. A method for decoding video data, the method comprising: decoding, from a video bitstream, a syntax element for a video data unit, the syntax element indicating a non-zero number of padding bits; as well as Decoding the video data unit from the video bitstream without decoding the padding bits in the video bitstream includes determining a number of bits in a bitstream for the video data unit using a number of padding bits indicated by the syntax element.

8. The method of claim 7, wherein the number of padding bits is different from the number of bits used by the syntax elements in the video bitstream.

9. The method of claim 7, wherein the video data unit is a picture.

10. The method of claim 7, wherein the video data unit is a slice.

11. The method of claim 7, wherein decoding the syntax elements comprises decoding the syntax elements from a video codec layer of the video bitstream.

12. The method of claim 7, further comprising determining a ratio of context adaptive binary arithmetic coding bins to bits in the bitstream based on the determined number of bits in the bitstream for the video data unit.

13. A device for encoding or decoding video data, the device comprising: a memory configured to store video data units associated with a video bitstream; as well as a video processor configured to encode and decode a syntax element of the video bitstream for a video data unit, the syntax element indicating a non-zero number of padding bits; as well as The video data unit is encoded and decoded without encoding and decoding the padding bits in the video bitstream, wherein, in order to encode and decode the video data unit, the processor is further configured to determine the number of bits in the bitstream of the video data unit using the number of padding bits indicated by the syntax element.

14. The apparatus of claim 13, wherein the number of padding bits is different from the number of bits used by the syntax element in the video bitstream.

15. The apparatus of claim 13, wherein the video data unit is a picture.

16. The apparatus of claim 13, wherein the video data unit is a slice.

17. The apparatus of claim 13, wherein the video processor is configured to encode the syntax element into a video codec layer of the video bitstream and encode the video data unit into the video bitstream without encoding the padding bits.

18. The apparatus of claim 13, wherein the video processor is configured to decode the syntax elements from a video codec layer of the video bitstream without decoding the padding bits, and to decode the video data units from the video bitstream.

19. The apparatus according to claim 13, further comprising at least one of the following: a camera configured to capture a picture including the video data; a display configured to display the picture including the video data; A transmitter configured to transmit the video bit stream; or A receiver is configured to receive the video bit stream.

20. The apparatus of claim 13, further comprising determining a ratio of context adaptive binary arithmetic coding bins to bits in the bitstream based on the determined number of bits in the bitstream for the video data unit.

21. A computer-readable medium having program code recorded thereon, wherein the program code is executable by one or more processors to cause the processors to perform the method of any one of claims 1-12.

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