Chip, memory accessing method and computer device

Abstract

The disclosure provides a chip, a memory access method and a computer device. The chip comprises a request sending unit and a data returning unit; the request sending unit is used for obtaining memory access addresses of threads in a plurality of thread groups, merging the memory access addresses, sending a memory access request to a corresponding channel in a shared memory based on the merged memory access addresses, and sending merging information representing a merging manner of the memory access addresses to the data returning unit; and the data returning unit is used for obtaining data returned by the shared memory, and returning the data to corresponding threads based on the merging information. The chip disclosed by the disclosure can merge memory access addresses of threads in a plurality of thread groups, reduce repeated memory access requests for the same address, thereby reducing the number of memory access requests sent to the shared memory, and reducing the pressure on the memory system.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to a chip, a method for accessing memory, and a computer device. Background Technology

[0002] In computer terminal hardware such as Graphics Processing Units (GPUs) and Artificial Intelligence (AI) chips, there are high demands for computational power and speed. Multithreading is often employed to enhance processor performance and achieve parallel data processing. These parallel processing threads are numerous, resulting in a large number of memory access requests. Therefore, it is necessary to optimize memory access methods in multithreaded scenarios to improve memory access efficiency. Summary of the Invention

[0003] To overcome the problems existing in the related technologies, this disclosure provides a chip, a method for accessing memory, and a computer device to solve the defects in the related technologies.

[0004] According to a first aspect of the present disclosure, a chip is provided, the chip comprising: a request sending unit and a data returning unit; the request sending unit is configured to obtain memory access addresses of threads in multiple thread groups, merge the memory access addresses, send a memory access request to a corresponding channel in shared memory based on the merged memory access addresses, and send merging information characterizing the merging method of the memory access addresses to the data returning unit; the data returning unit is configured to obtain data returned by the shared memory, and return the data to the corresponding thread based on the merging information.

[0005] Optionally, the merging information includes intra-group merging information and inter-group merging information. The intra-group merging information is used to characterize the merging method of memory access addresses of each thread within the same thread group, and the inter-group merging information is used to characterize the merging method of memory access addresses of each thread between different thread groups.

[0006] Optionally, the request sending unit includes: an intra-group merging unit, used to merge the memory access addresses of each thread within the same thread group to obtain the intra-group merging information; and an inter-group merging unit, used to merge the memory access addresses of each thread between different thread groups to obtain the inter-group merging information.

[0007] Optionally, the intra-group merging information includes an intra-group memory access merging identifier, which indicates whether the memory access addresses of each thread in the thread group to which the thread belongs are merged with the memory access address of the thread; the intra-group merging unit includes: a comparator array, used to compare the memory access addresses of each thread in the same thread group and generate a first address equality identifier for each thread based on the comparison result, the first address equality identifier indicating whether the memory access addresses of each thread in the thread group to which the corresponding thread belongs are the same as the memory access address of the corresponding thread; and an AND gate array, used to perform an AND operation on the thread validity identifier and the first address equality identifier to obtain the intra-group memory access merging identifier, the thread validity identifier indicating whether the memory access addresses of each thread in the thread group are valid.

[0008] Optionally, the inter-group merging information includes an inter-group memory access merging identifier, which is used to uniquely identify each thread group performing inter-group memory access merging; the inter-group merging unit includes a channel address cache control unit, which includes multiple address cache units, each address cache unit corresponding to a channel; the channel address cache control unit is used to write the merged memory access address of the intra-group merging unit into the address cache unit of the corresponding channel, and to merge the same cache addresses in the same address cache unit.

[0009] Optionally, the address caching unit is further configured to cache a second address equality identifier, which is used to indicate whether each address in the address caching unit is the same as the target address; the channel address caching control unit is specifically configured to: merge the address with the target address when the second address equality identifier corresponding to an address indicates that the address is the same as the target address.

[0010] Optionally, the address caching unit is further configured to cache valid address identifiers, which are used to characterize whether each memory access address cached in the address caching unit is valid; the channel address caching control unit is specifically configured to: determine a target address from the first memory access address in the address caching unit, wherein the valid address identifier corresponding to the first memory access address indicates that the first memory access address is valid; and when a memory access request corresponding to the target address is sent to the shared storage unit, modify the valid address identifier corresponding to the target address to indicate that the first memory access address is invalid.

[0011] Optionally, the channel address cache control unit is specifically used to: send the memory access request corresponding to the target address in each of the multiple address cache units to the shared memory.

[0012] Optionally, the channel address cache control unit is specifically used to: send the memory access address to the shared memory when the sending conditions are met; the sending conditions include: the address cache unit corresponding to any channel is full, or the address cache units corresponding to all free channels are not empty, or no new memory access address merged by the group merging unit is written to the address cache unit.

[0013] Optionally, the intra-group merging information includes a thread channel mapping identifier, which is used to characterize the memory access address in the thread group corresponding to each thread in each channel; the request sending unit further includes: an address splitting unit, used to split the memory access address from the memory access request of each thread in each thread group and generate the thread channel mapping identifier.

[0014] Optionally, the data return unit includes: an information caching unit for receiving and caching the merged information; and a broadcast control unit for returning the data returned from the shared memory to the corresponding thread based on the merged information cached by the information caching unit.

[0015] Optionally, the information caching unit includes: an intra-group information caching unit for receiving and caching intra-group merging information from the request sending unit; and an inter-group information caching unit for receiving and caching inter-group merging information from the request sending unit.

[0016] Optionally, the broadcast control unit is specifically used to: firstly, broadcast between groups according to the inter-group merging information to return the data returned by the shared memory to each thread group; and then broadcast within the group according to the intra-group merging information to return the data returned by the shared memory to each thread within the same thread group.

[0017] Optionally, the data return unit further includes a data return cache unit, used to cache the data returned to each thread, and when each thread in the thread group receives the returned data, writes the data of each thread back to the register file in the processor corresponding to that thread.

[0018] According to a second aspect of the present disclosure, a method for accessing memory is provided, applied to a chip in any embodiment of the present disclosure. The method includes: obtaining memory access addresses of threads in multiple thread groups through a request sending unit in the chip; merging the memory access addresses; sending a memory access request to a corresponding channel in shared memory based on the merged memory access addresses; and sending merging information characterizing the merging method of the memory access addresses to a data return unit; obtaining data returned by the shared memory through the data return unit in the chip; and returning the data to the corresponding thread based on the merging information.

[0019] According to a third aspect of the present disclosure, a computer device is provided, including a chip according to any embodiment of the present disclosure.

[0020] The chip described in this disclosure can merge the memory access addresses of threads in multiple thread groups, reducing repeated memory access requests for the same address, thereby reducing the number of memory access requests sent to shared memory and reducing the pressure on the memory access system.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] Figure 1 This is a structural diagram of a chip according to an embodiment of this disclosure.

[0023] Figure 2 This is a detailed structural diagram of the chip according to an embodiment of this disclosure.

[0024] Figure 3 This is a flowchart of a method for merging groups within a chip according to an embodiment of this disclosure.

[0025] Figure 4 This is a schematic diagram of a method for merging groups within a chip according to an embodiment of this disclosure.

[0026] Figure 5 This is a schematic diagram of writing memory access addresses into the address cache unit in the chip according to an embodiment of this disclosure.

[0027] Figure 6 This is a schematic diagram of the address cache unit in the chip of this disclosure reading out the memory access address.

[0028] Figure 7 This is a flowchart of a method for accessing memory according to an embodiment of the present disclosure. Detailed Implementation

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0030] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0032] Figure 1 This is a structural diagram of a chip according to an embodiment of this disclosure. Figure 1 As shown, this disclosure provides a chip 100 for accessing memory in a multi-threaded environment. The chip 100 includes:

[0033] The request sending unit 110 is used to obtain the memory access addresses of threads in multiple thread groups, merge the memory access addresses, send a memory access request to the corresponding channel in the shared memory 300 based on the merged memory access address, and send the merging information representing the merging method of the memory access addresses to the data return unit 120.

[0034] The data return unit 120 is used to obtain the data returned by the shared memory 300 and return the data to the corresponding thread based on the merging information.

[0035] In this embodiment, the processor 200 can send one or more memory access requests to the chip 100, and the chip 100 can access the shared memory 300. In this disclosure, the processor 200 refers to a computer component that interprets computer instructions and processes data in computer software; it can be a central processing unit (CPU), a graphics processing unit (GPU), or an artificial intelligence chip, etc., and this disclosure does not limit this. In this embodiment, the processor 200 can be a separate processor chip independent of the chip 100. The chip 100 is directly or indirectly connected to the processor chip via inter-chip circuitry to transmit memory access requests and returned data. Alternatively, the processor 200 can be a processing unit with processor functionality integrated on the same chip as the chip 100. The chip 100 is directly or indirectly connected to the processing unit via internal circuitry to transmit memory access requests and returned data.

[0036] The chip 100 of this embodiment is capable of receiving and processing memory access requests from multiple processes of multiple processors 200. In a multi-threaded environment, the threads contained within a process can be divided into one or more thread groups.

[0037] Shared memory 300 can be used in multiprocessor computer systems and accessed by different processors. The shared memory 300 can be implemented based on physical memory, file mapping, or other methods; this disclosure does not limit the implementation method of shared memory 300. In this embodiment, the shared memory 300 accessed by chip 100 can be shared memory implemented on a separate chip independent of chip 100. In this embodiment, chip 100 is directly or indirectly connected to the chip containing the shared memory via inter-chip circuitry to access the shared memory 300. Alternatively, the shared memory 300 accessed by chip 100 can be a shared memory unit integrated on the same chip as chip 100. In this embodiment, chip 100 is directly or indirectly connected to the shared memory unit via internal circuitry to access the shared memory 300.

[0038] In this disclosure, the shared memory 300 may include one or more channels. A channel refers to a storage unit instantiated within the shared memory 300. Different channels correspond to different memory access addresses. The channel to be accessed can be determined based on the memory access address carried in the memory access request, and the data stored in that channel can be retrieved. In single-channel shared memory, different memory access addresses can be used to access a different set of data bits within the same channel (e.g., the high 16 bits or the low 16 bits of the channel); while in multi-channel shared memory, different memory access addresses can be used to access different channels, or to access a different set of data bits within the same channel. In this disclosure, different channels of multi-channel shared memory can be accessed simultaneously to improve access efficiency.

[0039] In a thread group comprising multiple threads, there are often threads that need to access the same address. In this embodiment, the chip 100 can merge the memory access addresses of threads in multiple thread groups in the request sending unit 110, reducing duplicate memory access requests for the same address, thereby reducing the number of memory access requests sent to the shared memory 300 and reducing the pressure on the memory access system. Since the memory access requests are merged in the request sending unit 110, in order to determine which thread requested the data returned by the shared memory unit, the merging method needs to be recorded as merging information while merging the memory access addresses in the request sending unit 110. This merging information is then sent to the data return unit 120. Thus, the data return unit 120 can broadcast the returned data to multiple corresponding threads according to the merging information, ensuring that all threads receive the correct returned data.

[0040] Figure 2 This is a detailed structural diagram of the chip according to an embodiment of this disclosure. (As shown...) Figure 2 As shown, the request sending unit 110 includes:

[0041] The intra-group merging unit 112 is used to merge the memory access addresses of each thread in the same thread group to obtain the intra-group merging information.

[0042] The inter-group merging unit 113 is used to merge the memory access addresses of each thread in different thread groups to obtain the inter-group merging information.

[0043] Threads within the same thread group may have identical memory access addresses. These memory access addresses can be merged, a method called intra-group merging. Similarly, threads in different thread groups may also have identical memory access addresses. These memory access addresses can be merged, a method called inter-group merging. For both intra-group and inter-group merging, the recorded merging information can be divided into two types: intra-group merging information and inter-group merging information. Intra-group merging information describes the merging method for memory access addresses of threads within the same thread group, while inter-group merging information describes the merging method for memory access addresses of threads in different thread groups.

[0044] Correspondingly, the request sending unit 110 of the chip 100 in this embodiment of the present disclosure is respectively equipped with an intra-group merging unit 112 and an inter-group merging unit 113 to realize intra-group merging and inter-group merging of memory access addresses. In the chip 100 of this embodiment of the present disclosure, intra-group merging of memory access addresses can be performed before inter-group merging. First, the intra-group merging unit 112 merges the memory access addresses of each thread in the same thread group, and then sends the intra-group merged memory access addresses to the inter-group merging unit 113, which merges the merged memory access addresses of different thread groups. After the inter-group merging unit 113 performs inter-group merging of memory access addresses, it generates a memory access request based on the inter-group merged memory access addresses and sends it to the shared memory 300 to access the corresponding channel in the shared memory 300. In the chip 100 of this embodiment, the intra-group merging unit 112 records intra-group merging information and sends it to the data return unit 120 when performing intra-group merging, while the inter-group merging unit 113 records inter-group merging information and sends it to the data return unit 120 when performing inter-group merging.

[0045] Figure 3 This is a flowchart of a method for intra-group merging in a chip according to an embodiment of this disclosure. For example... Figure 3 As shown, the method for intra-group merging in the chip 100 of this embodiment includes:

[0046] Step S301: Compare the memory access addresses of each thread in the same thread group, and generate a first address equality flag for each thread based on the comparison result;

[0047] Step S302: Perform a bitwise AND operation on the thread valid identifier and the first address equality identifier to obtain the group memory access merging identifier.

[0048] In step S301, the first address equality identifier is used to characterize whether the memory access addresses of each thread in the thread group to which the corresponding thread belongs are the same as the memory access address of the corresponding thread. In one embodiment, for a thread group containing m threads, an m-bit identifier can be used as the first address equality identifier. Each bit of the identifier corresponds to each thread in the thread group, and each data bit of the identifier uses a different value to characterize whether the memory access address of the thread corresponding to that data bit is the same as or different from the memory access address of the thread. For example, a data bit of the identifier with a value of "1" indicates that the memory access address of the thread corresponding to that bit is the same as the memory access address of the thread, and a data bit of the identifier with a value of "0" indicates that the memory access address of the thread corresponding to that bit is different from the memory access address of the thread. For example, in a thread group consisting of four threads: thread 0, thread 1, thread 2, and thread 3, assuming that the memory access addresses of each of these threads are address 0, address 1, address 2, and address 3 respectively, then in this thread group, the memory access addresses of thread 0, thread 1, thread 2, and thread 3 are compared with those of thread 0 in turn, and the first address corresponding to thread 0 is identified as 1010.

[0049] In this embodiment, the pairwise comparison of threads in the thread group can start with the thread with the smallest number and sequentially compare the memory access address of each thread in the thread group with the memory access address of the thread with the smallest number to obtain the first address equality flag for each thread. Specifically, for threads with later numbers, it is not necessary to compare them again with the memory access address of the threads with earlier numbers; instead, the bits corresponding to the earlier threads in the first address equality flag of the later threads are all set to 0. For example, in the example of the thread group of four threads mentioned above, when obtaining the first address equality flag of thread 2, it is not necessary to compare it with the memory access addresses of thread 0 and thread 1. Therefore, even if the address accessed by thread 0 is the same as the address accessed by thread 2, the bits corresponding to thread 0 in the first address equality flag of thread 2 are recorded as 0 by default, that is, the first address equality flag of thread 2 is recorded as 0010.

[0050] In step S302, the thread validity identifier is used to characterize whether the memory addresses of each thread within the thread group are valid. During the intra-group merging process, a valid memory address refers to a memory address that has not yet been merged with the memory addresses of other threads within the thread group; this memory address can still be merged with the memory addresses of other threads. An invalid memory address refers to a memory address that has already been merged with the memory addresses of other threads within the thread group. For a thread group comprising m threads, an m-bit identifier can be used as the thread validity identifier, with each data bit of this identifier corresponding to the memory address of each thread within the thread group. Each data bit of the thread validity identifier represents whether the memory address corresponding to that data bit is valid or invalid through different values. In one embodiment, "1" can be used to indicate that the memory address corresponding to that data bit is valid, and "0" can be used to indicate that the memory address corresponding to that data bit is invalid. In this embodiment of the present disclosure, when the intra-group merging begins, each bit of the thread validity identifier can be initialized to valid.

[0051] A thread's valid identifier is ANDed with its first address equality identifier to obtain the thread's intra-group memory access merging identifier. This identifier indicates whether the memory addresses of all threads in the thread group to which the thread belongs are merged with the thread's memory address. For a thread group containing m threads, an m-bit identifier can be used as the intra-group memory access merging identifier, with each bit corresponding to a thread within the group. For any thread A within the thread group, each bit in thread A's intra-group memory access merging identifier represents whether the memory address of the thread corresponding to that bit is merged with or not merged with thread A's memory address.

[0052] In one embodiment, a value of "1" can be used to indicate that the memory address of the thread corresponding to the data bit is merged with the memory address of thread A, and a value of "0" can be used to indicate that the memory address of the thread corresponding to the data bit is not merged with the memory address of thread A. In this embodiment of the present disclosure, the intra-group merging unit 112 can merge each thread in the thread group sequentially according to the thread number order. When merging the memory addresses of threads with later numbers, the thread validity identifier should remove the valid bits corresponding to the already merged threads, that is, the positions corresponding to the already merged threads should be invalidated.

[0053] For example, in a thread group consisting of four threads: thread 0, thread 1, thread 2, and thread 3, assuming the memory access addresses of these four threads are address 0, address 1, address 2, and address 2 respectively, and the first address equality identifiers corresponding to threads 0, 1, 2, and 3 in this thread group are 1010, 0100, 0010, and 0001 respectively, and the thread validity identifier corresponding to this thread group is initialized to 1111, then during the first memory access address merging within the group, the thread validity identifier and the first address equality identifier of thread 0 are ANDed, i.e., 1111 & 1010, and the result 1010 is the memory access merge identifier corresponding to thread 0 within the group; during the second memory access address merging within the group, the thread validity identifier is first stripped of the valid bits corresponding to the threads merged in the first group merge, resulting in 0101, and then ANDed with the first address equality identifier of thread 1, resulting in 0100, which is the memory access merge identifier corresponding to address 1 within the group; following the same steps, the memory access merge identifier corresponding to address 2 can be obtained as 0001.

[0054] It is worth noting that after the third memory address merging within the group, the memory address of thread 2 corresponding to the group's memory address is 0000. This means that thread 2's memory address has already been merged with the memory addresses of other threads in the previous memory address merging process. Therefore, the memory address obtained after the group merging does not need to include thread 2's memory address again, thus avoiding duplicate memory access requests. The group memory address merging identifier can completely express the correspondence between each memory address obtained after the group merging in the group merging unit 112 and each thread in the thread group, as well as the merging method of the memory addresses of each thread in the thread group. Therefore, the group memory address merging identifier can be used as the group merging information in this embodiment of the disclosure.

[0055] In step S302, before performing a bitwise AND operation on the thread validity identifier and the first address equality identifiers of all threads except the first thread in the thread group, it is necessary to remove the valid bits of merged threads from the thread validity identifier. In one embodiment, this processing can be a first method, that is, the processing can be achieved by performing a bitwise AND operation on the thread validity identifier and the memory access mask of the previous merge, and updating the value of the thread validity identifier with the operation result. The memory access mask for each merge can be obtained by negating the memory access merge identifier obtained after each merge. The memory access mask is used to represent the threads in the thread group other than the threads whose memory access addresses are merged in each merge. By removing the threads that were merged in the previous merge from the thread validity identifier, the threads in the thread group that have not yet been merged after each merge can be obtained.

[0056] For example, in the above example, the memory access mask for the first merge is 0101. By performing a bitwise AND operation between this and the thread valid identifier, i.e., 0101 & 1111, we can obtain the thread valid identifier for the second merge as 0101. Similarly, the memory access mask for the second merge is -0100, i.e., 1011, and the thread valid identifier for the third merge is 1011 & 0101, i.e., 0010.

[0057] In one embodiment, the processing can also be a second approach, where instead of updating the thread valid identifier each time a merge occurs, when obtaining the memory access mask for each merge, the value obtained by negating the intra-group memory access merge identifier after each merge is ANDed with the memory access mask of the previous merge to obtain the memory access mask for that merge. Furthermore, after performing an AND operation between the thread valid identifier and the memory access mask of the previous merge each time a merge occurs, the result is ANDed with the first address equality identifier to obtain the intra-group memory access merge identifier.

[0058] For example, in the above example, the thread validity identifier is 1111 for each merge. The memory access mask for the first merge is 0101. The AND operation for obtaining the group's memory merge identifier during the second merge is 1111&0101&0100, which equals 0100. The memory access mask for the second merge is -0100&0101, which equals 0001. This disclosure does not limit the specific method for removing the valid bits of merged threads from the thread validity identifier; it can be any of the two methods described above, or other methods.

[0059] The process of merging identical memory access addresses within the same thread group and obtaining the intra-group memory access merge identifier in the intra-group merge unit can be described as follows: Figure 4 As shown. The method for removing the valid bits of merged threads from the thread validity identifier of the thread group is the second method described above, and the result of removing the valid bits of merged threads from the thread validity identifier of the thread group is called the actual thread validity identifier of the thread group. Figure 4 In this context, adr_equal_flagm represents the first address equality flag of thread m within the thread group, cls_flgm represents the memory access merging flag of thread m within the group, tm_req represents the thread validity flag of the thread group, maskm represents the memory access mask of thread m, and m{tm_req&maskm-1[m]} represents the actual thread validity flag of the thread group obtained by performing a bitwise AND operation between the thread validity flag of the thread group and the memory access mask of thread m-1.

[0060] First, for ease of understanding, a two-dimensional matrix is ​​used to represent the address comparison process. Each address in the matrix represents the memory access address of a thread within the same thread group. The addresses of each thread are sequentially placed along the horizontal and vertical axes of the two-dimensional matrix. The values ​​on the diagonal are set to 1, the values ​​at the bottom left corner of the diagonal are set to 0, and the values ​​at the top right corner are determined by whether the memory access address in that row and column are the same. The final value of each row in the two-dimensional matrix represents the first address equality flag for the thread in that row. After obtaining the first address equality flags for each thread, a bitwise AND operation is performed between the thread's valid flag and the first address equality flag of thread 0. Memory access addresses within the thread group that are the same as those of thread 0 are merged to obtain the memory access merge flag for thread 0. Finally, the memory access mask for thread 0 is obtained by inverting this flag. Then, by performing a bitwise AND operation between the thread group's valid identifier and the memory access mask of thread 0, the actual valid identifier of thread 1 is obtained. A bitwise AND operation is then performed between the actual valid identifier of thread 1 and the first address equality identifier of thread 1. The memory access addresses of threads within the thread group with the same memory access address as thread 1 are merged to obtain the group-wide memory access merge identifier for thread 1. Finally, the inverted value of this identifier is ANDed with the memory access mask of thread 0 to obtain the memory access mask for thread 1. Similarly, by performing a bitwise AND operation between the thread group's valid identifier and the memory access mask of the previous thread, the actual valid identifier of the next thread is obtained. A bitwise AND operation is then performed between the next thread's valid identifier and the first address equality identifier of the next thread. The memory access addresses of threads within the thread group with the same memory access address as the next thread are merged to obtain the group-wide memory access merge identifier for the next thread. Finally, the inverted value of this identifier is ANDed with the memory access mask of the previous thread to obtain the memory access mask for the next thread. Finally, the group merge identifier and memory access mask of each thread in the thread group are obtained.

[0061] like Figure 2 As shown, the intra-group merging unit 112 in this embodiment may include a comparator array 1121 and an AND gate array 1122. The comparator array 1121 is used to implement... Figure 3 Step S301. The comparator array 1121 refers to an integrated circuit composed of multiple comparators. A comparator is an electronic component that can compare two input signals and set the output signal to 1 if the comparison result is equal, and set the output signal to 0 if the comparison result is unequal. It can be an integrated electronic component with the above functions, or it can be an integrated circuit with the above functions composed of multiple more basic electronic components. This disclosure does not limit this. The AND gate array 1122 is used to implement... Figure 3Step S302. The AND gate array 1122 refers to an integrated circuit composed of multiple AND gates. An AND gate is an electronic component that can perform an AND operation on an input signal and output the operation result. In this embodiment of the disclosure, the AND gate array 1122 may also contain NOT gates in addition to AND gates, which are used to negate the memory access merging flag within the group when generating the memory access mask.

[0062] like Figure 2 As shown, the inter-group merging unit 113 in this embodiment may include a channel address cache control unit 1131, and the channel address cache control unit 1131 includes multiple address cache units, each corresponding to a channel. The channel address cache control unit 1131 is used to write the memory access address merged by the intra-group merging unit 112 into the address cache unit of the corresponding channel, and to merge the same cached addresses in the same address cache unit. In this embodiment, if the number of channels is k, then the channel address cache control unit 1131 of the chip 100 is provided with k address cache units. When the channel address cache control unit 1131 receives the memory access address merged by the intra-group merging unit 112, it determines the channel corresponding to the address in the shared memory 300 based on the memory access address, and then writes it into the corresponding address cache unit. In the same address cache unit, multiple memory access addresses from different thread groups but accessing the same address may be written. Therefore, the memory access addresses can be further merged in the inter-group merging unit 113 to subtract the same memory access addresses in adjacent thread groups, thereby further reducing the memory access requests sent by the request sending unit 110 to the shared memory 300.

[0063] In one embodiment, the address cache unit can be a FIFO (First In First Out) memory. A FIFO memory has the characteristic that data written later cannot be read before data written earlier, ensuring that memory access requests corresponding to earlier written memory access addresses can be processed promptly. The FIFO memory can perform data reading and writing based on write pointers and read pointers. When the channel address cache control unit 1131 writes a memory access address into the address cache unit, it writes sequentially from the position corresponding to the write pointer of the address cache unit. After writing a memory access request, the address cache unit moves the write pointer to the next writable position according to the number of memory access requests written, that is, the write pointer is increased by the same number as the number of memory access requests written. When the channel address cache control unit 1131 reads a memory access address from the address cache unit, the target address read is the address pointed to by the read pointer. Simultaneously with reading the target address, the address cache unit also reads the memory access addresses of other caches in the address cache unit that have the same target address, thus merging the identical cache addresses in the address cache unit. After reading the target address, the address cache unit moves the read pointer to the next readable address, which is the next address in the address cache unit that is different from the sent target address. If there is no next readable address in the address cache unit, the read pointer is moved to the write pointer position. When the read pointer is at the write pointer position, the address cache unit cannot read the address.

[0064] In one embodiment, the address cache unit may further cache a second address equality identifier. The second equality identifier is used to characterize the cached addresses in the address cache unit that are identical to the target address, i.e., the address pointed to by the read pointer. For example, if address 0, address 1, address 2, and address 3 are written into an address cache unit, where address 0, address 1, and address 3 are the same address, and address 2 is a different address, then when the read pointer points to address 0, the second address equality identifiers corresponding to addresses 0, address 1, address 2, and address 3 are 1, 1, 0, and 1, respectively. Simultaneously with reading the target address from the address cache unit, the addresses in the address cache unit with the corresponding second address equality identifier set to 1 are also read, thus merging identical cached addresses in the address cache unit. After reading the target address, the next address that can be read is the address with the corresponding second address equality identifier set to 0. In the above example, addresses 0, address 1, and address 3 are read simultaneously. It is worth noting that when the read pointer moves to the next readable address, the target address becomes the next readable address. At this time, all second address equality identifiers cached in the address cache channel need to be updated accordingly based on the changed target address. In one embodiment, the second address equality identifier can also be used to characterize the next address in the address cache unit that is the same as the previous address, i.e., only consecutive addresses are compared. For example, in the address cache unit of the above example, the second address equality identifiers corresponding to addresses 0, 1, 2, and 3 are 0, 1, 0, and 0, respectively. While the address cache unit reads the target address, if the second address equality identifier of the next address is 1, then that address is read simultaneously, and the next address is judged. All consecutive addresses with a second address equality identifier of 1 are read simultaneously until the second address equality identifier of the next address is 0, thus merging the identical cached addresses in the address cache unit. After reading all addresses, the next readable address is the address at which reading stopped, and the second address equality identifier corresponding to that address is 0. In the above example, addresses 0 and 1 are read simultaneously, but address 3 is not read simultaneously. It is worth noting that although this method may read fewer addresses than the previous method when reading cached addresses from the address cache unit at one time, it does not need to update the second address equality flag in the address cache unit after each address is read. The second address equality flag only needs to be recorded when the address is written to the address cache unit.

[0065] In one embodiment, the address cache unit can also cache valid address identifiers. The valid address identifiers are used to characterize the various cached addresses in the address cache unit that have not yet been sent. The channel address cache control unit 1131 writes the merged memory access addresses within the group into the address cache unit, and simultaneously generates the valid address identifier, setting it to 1. When the address cache unit reads the target address, it sets the valid memory access identifiers of all cached addresses in the address cache unit that are identical to the target address (i.e., all cached addresses read simultaneously) to 0, thus merging identical cached addresses in the address cache unit. When reading the target address, other addresses read simultaneously may still be cached after the address pointed to by the read pointer. To avoid duplicate requests for these cached addresses, a valid address identifier of 0 can be used to indicate that the target address read by the address cache unit is a cached address with a valid address identifier of 1. After reading the target address, the next address that can be read should also be a cached address with a valid address identifier of 1. For example, if addresses 0, 1, 2, and 3 are written into an address cache unit, where addresses 0, 1, and 3 are the same address, and address 2 is a different address, then when the read pointer points to address 0, the valid address identifiers corresponding to addresses 0, 1, 2, and 3 are 1, 1, 1, and 1, respectively. After addresses 0, 1, and 3 are read out simultaneously, the read pointer moves to address 2, and the valid address identifiers corresponding to addresses 0, 1, 2, and 3 are 0, 0, 1, and 0.

[0066] Figure 5 This is a schematic diagram of writing memory access addresses into the address cache unit in the chip according to an embodiment of this disclosure. Figure 5 In the diagram, from bottom to top, are the first, second, third, and fourth positions of this address cache unit. These four positions are four consecutive positions within the address cache unit. However, this address cache unit may contain other positions besides these four (not shown in the diagram). These other positions may be located in... Figure 5 The position before the first position in the middle may also be in Figure 5 The positions following the fourth position, from left to right, represent the memory access address to be written, the second address equality flag corresponding to each address, and the valid address flag corresponding to each address. For example... Figure 5As shown, before a memory access address is written, the first location in this address cache unit has already been written with a memory access address (not shown in the figure), and this memory access address is the same as the target address pointed to by the read pointer. The other three locations have not been written with memory access addresses. Therefore, the second address equality flag corresponding to the first location in this address cache unit is 1, and the other three locations do not record the second address equality flag. The valid address flags for the four locations are 1, 0, 0, and 0 respectively, and the write pointer points to the second location. When this memory access address is written to this address cache unit, two new memory access addresses are written, and all memory access addresses with the second address equality flag of 1 are read out. Furthermore, of the newly written memory access addresses, the first memory access address is different from the next target address pointed to by the read pointer after reading, while the second memory access address is the same as the next target address pointed to by the read pointer after reading. Then, as follows... Figure 5 As shown, after the memory access address is written, since the memory access address at the first position in the address cache unit has been read, the second address equality flag and the valid address flag corresponding to the first position in the address cache unit are both reset to 0. And the first memory access address (not shown in the figure) and the second memory access address (not shown in the figure) of the newly written memory access address are written to the second and third positions in the address cache unit. Then, the second address equality flag corresponding to the second position in the address cache unit is set to 0, the second address equality flag corresponding to the third position in the address cache unit is set to 1, the valid address flags corresponding to the second and third positions in the address cache unit are both set to 1, and the write pointer moves to the fourth position.

[0067] Figure 6 This is a schematic diagram of the address cache unit in the chip of this disclosure reading out the memory access address. Figure 6 In the diagram, from bottom to top, are the first, second, third, and fourth positions of this address cache unit. These four positions are four consecutive positions within the address cache unit. Besides these four positions, it may also contain other positions (not shown in the diagram). These other positions could be... Figure 6 The position before the first position in the middle may also be in Figure 6 The positions following the fourth position in the table. From left to right, they represent the memory access address to be written, the second address equality flag corresponding to each address, and the valid address flag corresponding to each address. For example... Figure 6As shown, before a memory address is read, all four locations in this address cache unit have been written with memory addresses (not shown in the diagram). The memory addresses in the first three locations are the same, while the memory address in the fourth location is different from the other three locations. Since the read pointer points to the first location, the second address equality flags corresponding to the first three locations in the address cache unit are all 1, while the second address equality flag corresponding to the fourth location is 0. The valid address flags for all four locations are 1. When reading a memory address from this address cache unit, the target address is the memory address in the first location, and all addresses with a second address equality flag of 1 are considered to have been read. That is, the memory addresses in the first three locations have all been read, and the read pointer moves to the next unread valid address, i.e., the read pointer moves to the fourth location. Then... Figure 6 As shown, after the memory access address is read, since the memory access addresses in the first three positions of the address cache unit have been read, the second address equality flag and the valid address flag corresponding to the first three positions in the address cache unit are both reset to 0. After reading, the read pointer points to the fourth position, and the second address equality flag corresponding to the positions of the memory access addresses that are the same as the fourth position (including the fourth position) are all reset to 1.

[0068] In the inter-group merging unit 113, an inter-group memory access merging identifier can be generated based on the thread groups corresponding to the merged cache addresses in the address cache channel. This identifier represents the inter-group memory access merging of each thread group. The inter-group memory access merging identifier is sent to the data return unit 120 as inter-group merging information. For example, an address cache unit may contain address 0 from thread group 0, address 1 from thread group 1, address 2 from thread group 2, and address 3 from thread group 3. Addresses 0, 1, and 3 are the same address, while address 2 is a different address. When the read pointer points to address 0, addresses 0, 1, and 3 will be read simultaneously, and the inter-group memory access merging identifier will be recorded as 1101.

[0069] In this embodiment, since the multi-channel shared memory 300 allows different channels to access the shared memory 300 simultaneously, the channel address cache control unit 1131 can simultaneously send memory access requests corresponding to target addresses from multiple address cache units to the shared memory 300 each time it sends such requests. This allows all channels of the shared memory 300 to be utilized, improving memory access efficiency and bandwidth utilization of the memory access system. For example, in one embodiment, if there is a target address 0 to be sent on channel 0 address cache unit 11310 and a target address 1 to be sent on channel 1 address cache unit 11311, then target address 0 and target address 1 can be read from channel 0 address cache unit 11310 and channel 1 address cache unit 11311 simultaneously, and the memory access requests corresponding to target address 0 and target address 1 can be sent to the shared memory 300 simultaneously to access channel 0 and channel 1 of the shared memory 300, respectively. It is worth noting that when a memory access request is sent to the shared memory 300, the channel corresponding to the access address of the memory access request in the shared memory 300 should be idle and not processing other memory access requests, so as to avoid access conflicts and other problems.

[0070] In this embodiment, the channel address cache control unit 1131 sends the memory access address to the shared memory 300 only when the sending conditions are met. The sending conditions include: the address cache unit corresponding to any channel is full, or the address cache units corresponding to all idle channels are not empty, or no new memory access address merged by the group merging unit 112 is written to the address cache unit. The address cache unit corresponding to any channel being full means that one cache unit cannot continue to write memory access addresses, therefore the memory access address in that address cache unit needs to be read out to avoid memory address loss due to the inability to write new memory access addresses, and problems such as the corresponding thread not receiving return data. The address cache units corresponding to all idle channels being non-empty can maximize the utilization of the memory access system bandwidth, accessing multiple channels of the shared memory 300 as much as possible at the same time, reducing the number of accesses to the shared memory 300, and reducing the power consumption of the memory access system. If no new memory access address merged by the intra-group merging unit 112 is written to the address cache unit, it indicates that it is difficult to achieve a state where all address cache units corresponding to all free channels are not empty. In this case, the address cached in the address cache unit should be sent out in a timely manner to avoid increased memory access latency caused by long waiting time.

[0071] like Figure 2As shown, the request sending unit 110 in this embodiment may further include an address splitting unit 111. The address splitting unit 111 is used to split memory access addresses from the memory access requests of each thread in each thread group and generate a thread channel mapping identifier. The thread channel mapping identifier is used to characterize the memory access address in the thread group corresponding to each thread in each channel. Based on the thread channel mapping, the intra-group merging unit 112 can merge memory access addresses corresponding to different channels in the same thread group. The merged memory access address can also be directly written to the address cache unit of the corresponding channel without needing to determine the channel corresponding to the memory access address again. In one embodiment, for a thread group containing m threads, an m-bit identifier can be used as the thread channel mapping identifier. For example, in a thread group with four threads: thread 0, thread 1, thread 2, and thread 3, assuming thread 0 accesses address 0, thread 1 accesses address 1, thread 2 accesses address 0, and thread 3 accesses address 2, and addresses 0 and 2 correspond to channel 0, and address 1 corresponds to channel 1, then the thread channel mapping identifier corresponding to channel 0 is 1011, while the thread channel mapping identifier corresponding to channel 1 is 0100. In one embodiment, the thread channel mapping identifier can also be sent to the data return unit 120 as intra-group merging information.

[0072] like Figure 2 As shown, the data return unit 120 in this embodiment may include an information caching unit 121 and a broadcast control unit 122. The information caching unit 121 is used to receive and cache the merging information sent by the request sending unit 110; the broadcast control unit 122 is used to return the data returned by the shared memory 300 to the corresponding thread based on the merging information cached by the information caching unit 121.

[0073] Since the memory access request sent to shared memory 300 by request sending unit 110 is generated based on the merged memory access address, the data returned by shared memory 300 corresponds to that memory access address, not to a specific thread. Therefore, it is necessary to first determine which thread group and which thread in the thread group corresponds to the memory access address based on the merged information corresponding to that memory access address, so that all threads can receive the correct return data.

[0074] In this embodiment of the disclosure, the merging of memory access addresses can be divided into two methods: intra-group merging and inter-group merging. The merging information can also be divided into intra-group merging information and inter-group merging information. Correspondingly, the information caching unit 121 in the data return unit 120 can also include an intra-group information caching unit 1211 and an inter-group information caching unit 1212, which are used to receive and cache intra-group merging information and inter-group merging information from the request sending unit 110, respectively.

[0075] In this embodiment of the disclosure, since the merging of memory access addresses is performed first within a group and then between groups, the broadcast control unit 122 in the data return unit 120 should broadcast the returned data to the corresponding threads in the reverse order. That is, it should first perform inter-group broadcasting according to the inter-group merging information to return the data returned by the shared memory 300 to each thread group, and then perform intra-group broadcasting according to the intra-group merging information to return the data returned by the shared memory 300 to each thread in the same thread group.

[0076] For example, chip 100 receives a memory access request from processor 200, which includes thread group 0 and thread group 1. Thread group 0 includes four threads: thread 00, thread 01, thread 02 and thread 03. Thread group 1 includes four threads: thread 10, thread 11, thread 12 and thread 13. Among them, thread 00, thread 10 and thread 11 all access address 0 corresponding to channel 0, thread 01 accesses address 1 corresponding to channel 1, thread 12 accesses address 2 corresponding to channel 2, and thread 02, thread 03 and thread 13 access address 3 corresponding to channel 3. In the request sending unit, the memory addresses of the four threads in thread group 0 and the four threads in thread group 1 are first merged in the intra-group merging unit to obtain merged memory addresses 00, 01, 02, 10, 11, and 12. Memory addresses 00 and 10 are identical, both corresponding to channel 0; memory address 01 corresponds to channel 1; memory address 11 corresponds to channel 2; and memory addresses 02 and 12 are identical, both corresponding to channel 3. The intra-group merging information corresponding to each memory address can be recorded and sent to the data return unit for caching.

[0077] Then, in the inter-group merging unit, memory access addresses 00 and 10 are merged to generate memory access request 0 for accessing channel 0. Memory access request 1 for accessing channel 1 is generated based on memory access address 01, and memory access request 2 for accessing channel 2 is generated based on memory access address 11. Memory access addresses 02 and 12 are merged to generate memory access request 3 for accessing channel 3. The inter-group merging information corresponding to the addresses of each memory access request is recorded and sent to the data return unit for caching. Then, memory access requests 0, 1, 2, and 3 are sent to shared memory to access the corresponding channels. In the data return unit, after receiving data 0 from channel 0, data 1 from channel 1, data 2 from channel 2, and data 3 from channel 3 returned from shared memory, it first returns data 0 to thread group 0 and thread group 1, data 1 to thread group 0, data 2 to thread group 1, and data 3 to thread group 3 according to the inter-group merging information in the cache. Then, according to the intra-group merging information in the cache, it returns data 0 to thread 00 in thread group 0 and threads 10 and 11 in thread group 1, data 1 to thread 01 in thread group 0, data 2 to thread 12 in thread group 1, and data 3 to threads 02 and 03 in thread group 0 and thread 13 in thread group 1, so that each thread in all thread groups receives the correct return data.

[0078] like Figure 2 The data return unit 120 in this embodiment may further include a data return cache unit 123. Since multiple threads in the same thread group access the shared memory 300 through different channels in the request sending unit 110, the access time for each thread's memory address may be different. Therefore, the time it takes for each thread in the thread group to receive the data returned from the shared memory 300 may also be different. Thus, the data return cache unit 123 can be used to cache the data returned to each thread in the thread group until all threads in the thread group have received the returned data, at which point the data from each thread is written back to the register file in the processor 200 corresponding to that thread.

[0079] Corresponding to the aforementioned chip embodiments, this disclosure also provides an embodiment of a method for accessing memory applied to the chip.

[0080] like Figure 7 As shown, this disclosure provides a method for accessing memory, the method comprising:

[0081] Step S701: Obtain the memory access addresses of threads in multiple thread groups, merge the memory access addresses, send a memory access request to the corresponding channel in shared memory based on the merged memory access address, and send the merging information representing the merging method of the memory access addresses to the data return unit.

[0082] Step S702: Obtain the data returned by the shared memory, and return the data to the corresponding thread based on the merging information.

[0083] Optionally, the merging information includes intra-group merging information and inter-group merging information. The intra-group merging information is used to characterize the merging method of memory access addresses of each thread within the same thread group, and the inter-group merging information is used to characterize the merging method of memory access addresses of each thread between different thread groups.

[0084] Optionally, step S701 further includes: merging the memory access addresses of each thread within the same thread group through an intra-group merging unit to obtain the intra-group merging information; and merging the memory access addresses of each thread between different thread groups through an inter-group merging unit to obtain the inter-group merging information.

[0085] Optionally, the intra-group merging information includes an intra-group memory access merging identifier, which is used to indicate whether the memory access addresses of each thread in the thread group to which the thread belongs are merged with the memory access address of the thread; step S701 further includes: comparing the memory access addresses of each thread in the same thread group using a comparator array, generating a first address equality identifier for each thread based on the comparison result, which is used to indicate whether the memory access addresses of each thread in the thread group to which the corresponding thread belongs are the same as the memory access address of the corresponding thread; and performing an AND operation on the thread validity identifier and the first address equality identifier using an AND gate array to obtain the intra-group memory access merging identifier, which is used to indicate whether the memory access addresses of each thread in the thread group are valid.

[0086] Optionally, the inter-group merging information includes an inter-group memory access merging identifier, which is used to uniquely identify each thread group performing inter-group memory access merging; step S701 further includes: writing the merged memory access address of the intra-group merging unit into the address cache unit of the corresponding channel through the channel address cache control unit, and merging the same cache addresses in the same address cache unit.

[0087] Optionally, step S701 further includes: implementing a second address equality identifier through the address cache unit, the second address equality identifier being used to characterize whether each address in the address cache unit is the same as the target address; and implementing a merge of the address and the target address through the channel address cache control unit when the second address equality identifier corresponding to an address characterizes that the address is the same as the target address.

[0088] Optionally, step S701 further includes: implementing a cached valid address identifier through the address cache unit, the valid address identifier being used to characterize whether each memory access address cached in the address cache unit is valid; and determining a target address from the first memory access address in the address cache unit through the channel address cache control unit, the valid address identifier corresponding to the first memory access address indicating that the first memory access address is valid; and modifying the valid address identifier corresponding to the target address to indicate that the first memory access address is invalid when the memory access request corresponding to the target address is sent to the shared storage unit.

[0089] Optionally, step S701 further includes: sending memory access requests corresponding to the target address in the multiple address cache units to the shared memory each time through the channel address cache control unit.

[0090] Optionally, step S701 further includes: sending the memory access address to the shared memory each time the sending conditions are met through the channel address cache control unit; the sending conditions include: the address cache unit corresponding to any channel is full, or the address cache units corresponding to all free channels are not empty, or no new memory access address merged by the group merging unit is written to the address cache unit.

[0091] Optionally, the group merging information includes a thread channel mapping identifier, which is used to characterize the memory access address in the thread group corresponding to each thread in each channel; step S702 further includes: splitting the memory access address from the memory access request of each thread in each thread group through the address splitting unit, and generating the thread channel mapping identifier.

[0092] Optionally, step S702 further includes: receiving and caching the merged information through an information caching unit; and returning the data returned by the shared memory to the corresponding thread based on the merged information cached by the information caching unit through a broadcast control unit.

[0093] Optionally, step S702 further includes: receiving and caching intra-group merging information from the request sending unit through an intra-group information caching unit; and receiving and caching inter-group merging information from the request sending unit through an inter-group information caching unit.

[0094] Optionally, step S702 further includes: first, performing inter-group broadcasting based on the inter-group merging information to return the data returned by the shared memory to each thread group; and then performing intra-group broadcasting based on the intra-group merging information to return the data returned by the shared memory to each thread within the same thread group.

[0095] Optionally, step S702 further includes: caching the data returned to each thread through a data return cache unit, and writing the data of each thread back to the register file in the processor corresponding to that thread when each thread in the thread group has received the returned data.

[0096] In the above method, the specific steps of the memory access method provided in this disclosure embodiment can be applied to the chip described in the chip embodiment above. Step S701 is implemented by the request sending unit in the chip, and step S702 is implemented by the data return unit in the chip. The specific process can be referred to the description of the chip embodiment above. For the sake of brevity, it will not be repeated here.

[0097] In addition, this disclosure also provides a computer device, including the chip described in any of the chip embodiments described above. The specific functions of this chip can be found in the descriptions of the chip embodiments above, and for the sake of brevity, will not be repeated here.

[0098] The above description is merely a specific implementation of the embodiments of this specification. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles of the embodiments of this specification, and these improvements and modifications should also be considered within the protection scope of the embodiments of this specification.

Claims

1. A chip, characterized by The chip comprises: The request sending unit and the data returning unit; The request sending unit is used for obtaining memory access addresses of threads in a plurality of thread groups, merging the memory access addresses, sending a memory access request to a corresponding channel in a shared memory based on the merged memory access addresses, and sending merging information representing a merging manner of the memory access addresses to the data returning unit; The data returning unit is used for obtaining data returned by the shared memory and returning the data to corresponding threads based on the merging information, The merging information comprises group-in merging information, and the group-in merging information is used for representing a merging manner of memory access addresses of threads in a same thread group; The group-in merging information comprises group-in memory access merging identification, and the group-in memory access merging identification is used for representing whether memory access addresses of threads in a thread group in which a corresponding thread is located are merged with the memory access address of the corresponding thread; The request sending unit comprises a group-in merging unit, which is used for merging memory access addresses of threads in a same thread group to obtain the group-in merging information. The group-in merging unit comprises: a comparator array, which is used for comparing memory access addresses of threads in a same thread group, and generating first address equal identification of each thread according to a comparison result, the first address equal identification being used for representing whether memory access addresses of threads in a thread group in which a corresponding thread is located are the same as the memory access address of the corresponding thread; and an AND gate array, which is used for performing AND operation on thread valid identification and the first address equal identification to obtain the group-in memory access merging identification, the thread valid identification being used for representing whether memory access addresses of threads in the thread group are valid, and a valid memory access address being a memory access address that has not been merged with memory access addresses of other threads in the thread group.

2. The chip according to claim 1, characterized in that The merging information further comprises group-between merging information, and the group-between merging information is used for representing a merging manner of memory access addresses of threads between different thread groups.

3. The chip of claim 2, wherein The request sending unit further comprises: a group-between merging unit, which is used for merging memory access addresses of threads between different thread groups to obtain the group-between merging information.

4. The chip of claim 3, wherein The group-between merging information comprises group-between memory access merging identification, and the group-between memory access merging identification is used for uniquely identifying each thread group that performs group-between memory access merging; and the group-between merging unit comprises a channel address cache control unit, and the channel address cache control unit comprises a plurality of address cache units, each address cache unit corresponding to a channel; The channel address cache control unit is used for writing the memory access addresses merged by the group-in merging unit into address cache units of corresponding channels, and merging same cache addresses in a same address cache unit.

5. The chip of claim 4, wherein, The address cache unit is further used for caching second address equal identification, and the second address equal identification is used for representing whether each address in the address cache unit is the same as a target address; The channel address cache control unit is specifically used for merging one address with a target address in a case where second address equal identification corresponding to the one address represents that the one address is the same as the target address.

6. The chip according to claim 4 or 5, characterized in that The address cache unit is also configured to cache valid address identifiers, which are used to indicate whether each memory access address cached in the address cache unit is valid. The channel address cache control unit is specifically configured to: determine a target address from a first memory access address in the address cache unit, where the valid address identifier corresponding to the first memory access address indicates that the first memory access address is valid. In a case where the memory access request corresponding to the target address is sent to the shared memory unit, the valid address identifier corresponding to the target address is modified to indicate that the first memory access address is invalid.

7. The chip of claim 4, wherein The channel address cache control unit is specifically configured to: Each time a memory access request corresponding to a target address in a plurality of address cache units is sent to the shared memory.

8. The chip of claim 7, wherein, The channel address cache control unit is specifically configured to: When the sending condition is met, the memory access address is sent to the shared memory; the sending condition includes that the address cache unit corresponding to any channel is full, or the address cache units corresponding to all idle channels are not empty, or no memory access address merged by the intra-group merging unit is written into the address cache unit.

9. The chip of claim 1, wherein The intra-group merging information includes a thread channel mapping identifier, which is used to indicate that a memory access address in a thread group corresponds to each thread of each channel. The request sending unit further includes: An address splitting unit, configured to split a memory access address from a memory access request of each thread of each thread group, and generate the thread channel mapping identifier.

10. The chip of claim 1, wherein, The data returning unit includes: An information cache unit, configured to receive and cache the merging information; and A broadcast control unit, configured to return data returned by the shared memory to corresponding threads based on the merging information cached by the information cache unit.

11. The chip of claim 10, wherein, The information cache unit includes: An intra-group information cache unit, configured to receive and cache intra-group merging information from the request sending unit; and An inter-group information cache unit, configured to receive and cache inter-group merging information from the request sending unit.

12. The chip of claim 11, wherein, The broadcast control unit is specifically configured to: First, inter-group broadcasting is performed according to the inter-group merging information, so as to return data returned by the shared memory to each thread group; Then, intra-group broadcasting is performed according to the intra-group merging information, so as to return data returned by the shared memory to each thread in the same thread group.

13. The chip of claim 11, wherein, The data returning unit further includes: A data returning cache unit, configured to cache data returned to each thread, and write the data of each thread back to a register file corresponding to the thread in a processor when each thread in the thread group receives the returned data.

14. A method of accessing memory, applied to the chip of any one of claims 1 to 13, characterized in that, The method includes: Obtaining, by a request sending unit in a chip, memory access addresses of threads in a plurality of thread groups, merging the memory access addresses, sending a memory access request to a corresponding channel in a shared memory based on the merged memory access addresses, and sending merging information indicating a merging manner of the memory access addresses to a data returning unit; Obtaining, by a data returning unit in the chip, data returned by the shared memory, and returning the data to corresponding threads based on the merging information.

15. A computer device, comprising: A chip comprising any one of claims 1 to 13.

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