Heterogeneous fusion memory system, memory access method and device, equipment, medium and program

Abstract

The embodiment of the invention discloses a heterogeneous fusion memory system, a memory access method, a memory access device, equipment, a medium and a program.The system comprises a Scale-Up domain, a Scale-Out domain and a fusion proxy gateway, and the Scale-Up domain is composed of a plurality of processing units which are interconnected through a first and has a unified global address space; the Scale-Out domain is composed of a plurality of computing nodes passing through a second interconnection and is used for connecting the first interconnection and the second interconnection; the fusion proxy gateway is used as an RDMA endpoint to receive an RDMA operation request from a target domain node; converting a global address in the RDMA operation request into a physical address of a target processing unit in the Scale-Up domain; and accessing the physical memory of the target processing unit by memory semantics through the first interconnection. According to the technical scheme provided by the embodiment of the invention, low delay and high bandwidth of memory access based on the heterogeneous fusion memory system are realized, and the compatibility of the heterogeneous fusion memory system is kept.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data center architecture, and particularly relate to a heterogeneous fusion memory system, a memory access method and device, electronic equipment, a storage medium and a program. BACKGROUND

[0002] Currently, computing architectures are mainly divided into two major schools: Scale-Up and Scale-Out. The advantage of Scale-Up is that the memory access delay is extremely low and the bandwidth is high, and the programming model is simple (such as programming on a machine), but it is limited by physical constraints and the scale of expansion is limited. The advantage of Scale-Out is that the scalability is extremely strong, but the communication delay between nodes is high, the bandwidth is limited, the programming is complex, and the data movement overhead is large. With the explosive growth of demand for computing power and memory capacity in applications such as AI (Artificial Intelligence) large models, scientific computing, and super-large-scale data analysis, a single architecture has been difficult to meet the demand. The industry urgently needs a new architecture that can combine the advantages of both: it can provide strong single-node computing power and efficient memory sharing through Scale-Up, and it can achieve nearly unlimited horizontal expansion through Scale-Out.

[0003] The core technical challenge of the fusion of Scale-Up and Scale-Out is how to enable independent nodes in the Scale-Out network to efficiently and transparently access the remote and huge Scale-Up domain memory as if accessing local memory. Currently, related technologies usually use three schemes to realize the fusion of Scale-Up and Scale-Out. Among them, the first scheme is remote memory access based on traditional RDMA (Remote Direct Memory Access). In this scheme, the Scale-Out node directly reads and writes the memory of other Scale-Out nodes using RDMA such as RoCE (RDMA over Converged Ethernet) or InfiniBand (a high-performance network communication standard). To access the Scale-Up domain memory, a node in the Scale-Up domain is configured as a memory server, and part of its memory is exposed to the network through RDMA. The second scheme is called software-defined distributed shared memory (DSM). This way simulates shared memory at the software layer through the operating system or runtime library. When remote access occurs, a page fault is triggered, and the software is responsible for grabbing the data page through the network. The third scheme is a pure Scale-Up consistency domain scheme, such as Intel QPI (Intel Quick Path Interconnect) and AMD Infinity Fabric (AMD Infinity Fabric Architecture). A hardware consistency domain is built between a limited number of chips, and the domain has a unified memory view.

[0004] In the process of developing this invention, the inventors discovered the following drawbacks in existing technologies: Traditional RDMA-based remote memory access schemes require access to Scale-Up domain memory via specific proxy nodes, resulting in opaque access and suboptimal paths. Applications must explicitly use the RDMA interface and cannot access memory using ordinary pointers. All traffic must pass through the network card and protocol stack of the "memory server" acting as a proxy, preventing direct access to the memory of other chips within the Scale-Up domain, creating bottlenecks and single points of failure, and failing to fully utilize the high-speed interconnect network within the Scale-Up domain, limiting bandwidth and latency. Furthermore, RDMA requires explicit programming, violating the standard memory programming model and increasing development burden. Software-defined distributed shared memory schemes exhibit extremely poor performance. Software pitfalls, protocol processing, and multiple network round trips lead to latency far exceeding that of hardware memory access, making them unsuitable for high-performance scenarios. Pure Scale-Up consistency domain schemes are closed and limited in scale. Nodes outside the domain cannot directly access domain memory via hardware paths, resulting in a fragmented architecture. They cannot meet the needs of ultra-large-scale computing clusters. Pure Scale-Up domains cannot access Scale-Out networks, resulting in a rigid architecture and limited scalability. Traditional Scale-Out clusters cannot benefit from the low latency and high bandwidth advantages of unified hardware-level memory. Furthermore, existing solutions cannot treat the entire memory of a Scale-Up domain as a unified resource pool directly addressable by any Scale-Out node. Access is typically restricted to the local memory of a specific proxy node. Summary of the Invention

[0005] This invention provides a heterogeneous converged memory system, a memory access method, an apparatus, an electronic device, a storage medium, and a program, which achieves low latency and high bandwidth for memory access based on the heterogeneous converged memory system, while maintaining the compatibility of the heterogeneous converged memory system.

[0006] According to one aspect of the present invention, a heterogeneous converged memory system is provided, comprising: a scale-up domain, a scale-out domain, and a converged proxy gateway, wherein:

[0007] The Scale-Up domain consists of multiple processing units interconnected by a first interconnection and has a unified global address space;

[0008] The Scale-Out domain consists of multiple compute nodes connected via a second interconnect; the Scale-Out domain also includes a converged proxy gateway for connecting the first interconnect and the second interconnect.

[0009] The fusion proxy gateway is configured to: receive, as an RDMA endpoint, an RDMA operation request from a target domain node; convert a global address in the RDMA operation request into a physical address of a target processing unit within the Scale-Up domain; and access, with memory semantics, physical memory of the target processing unit through the first interconnect.

[0010] According to another aspect of the present application, there is provided a memory access method applied to a fusion proxy gateway in the heterogeneous fusion memory system of the first aspect, the method comprising:

[0011] receiving, as an RDMA endpoint, an RDMA operation request from a target domain node;

[0012] converting a global address in the RDMA operation request into a physical address of a target processing unit within the Scale-Up domain;

[0013] accessing, with memory semantics, physical memory of the target processing unit through the first interconnect.

[0014] According to another aspect of the present application, there is provided a memory access apparatus configured to a fusion proxy gateway in the heterogeneous fusion memory system of the first aspect, the apparatus comprising:

[0015] an RDMA operation request receiving module configured to receive, as an RDMA endpoint, an RDMA operation request from a target domain node;

[0016] a physical address converting module configured to convert a global address in the RDMA operation request into a physical address of a target processing unit within the Scale-Up domain;

[0017] a physical memory accessing module configured to access, with memory semantics, physical memory of the target processing unit through the first interconnect.

[0018] According to another aspect of the present application, there is provided an electronic device, the electronic device comprising:

[0019] at least one processor; and

[0020] a memory connected with the at least one processor in communication; wherein

[0021] the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the memory access method according to any one of the embodiments of the present application.

[0022] According to another aspect of the present application, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the memory access method according to any of the embodiments of the present application when executed.

[0023] According to another aspect of the present application, there is also provided a computer program product comprising a computer program for implementing the memory access method according to any of the embodiments of the present application when executed by a processor.

[0024] The embodiment of the present application comprises a heterogeneous fusion memory system by extending Scale-Up domain longitudinally, Scale-Out domain laterally and fusion proxy gateway. The Scale-Up domain is composed of multiple processing units connected by a first interconnection and has a unified global address space. The Scale-Out domain is composed of multiple computing nodes connected by a second interconnection. The Scale-Out domain further comprises a fusion proxy gateway for connecting the first interconnection and the second interconnection. In the heterogeneous fusion memory system, the fusion proxy gateway can receive an RDMA operation request from a target domain node as an RDMA endpoint, convert the global address in the RDMA operation request into a physical address of a target processing unit in the Scale-Up domain, and thus access the physical memory of the target processing unit with memory semantics through the first interconnection. In the above-mentioned heterogeneous fusion memory system, the Scale-Out node can directly access the memory of all chips in the Scale-Up domain, rather than the memory of a single node, and the entire Scale-Up domain is truly changed into a huge and unified memory pool that can be remotely accessed by the network. The Scale-Out side adopts a completely standard RDMA protocol, without the need to modify the existing Scale-Out node hardware, driver and application program, and has excellent compatibility and easy deployment. The memory access method of the fusion proxy gateway in the heterogeneous fusion memory system directly converts the RDMA request into an intra-domain memory access, avoiding the protocol stack and internal bus bottleneck of the proxy node in the traditional scheme. Therefore, the above-mentioned heterogeneous fusion memory system and the memory access method of the fusion proxy gateway realize low latency and high bandwidth for memory access based on the heterogeneous fusion memory system, and maintain the compatibility of the heterogeneous fusion memory system.

[0025] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0027] Figure 1 is a schematic diagram of a heterogeneous fusion memory system provided by the first embodiment of the present application;

[0028] Figure 2 is a structural schematic diagram of a fusion proxy gateway provided by the first embodiment of the present application;

[0029] Figure 3 is a structural schematic diagram of another fusion proxy gateway provided by the first embodiment of the present application;

[0030] Figure 4 is a flowchart of a memory access method provided by the second embodiment of the present application;

[0031] Figure 5 is a processing flowchart of a single processing unit of RDMA Scale-Out and Scale-Up domain access fusion provided by the second embodiment of the present application;

[0032] Figure 6 is a schematic diagram of a memory access device provided by the third embodiment of the present application;

[0033] Figure 7 is a structural schematic diagram of an electronic device provided by the fourth embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the person skilled in the art better understand the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort should be within the scope of protection of the present application.

[0035] It should be noted that the terms "first", "second", and the like in the description and in the claims of the application and in the above-described drawings are intended to distinguish similar objects and not necessarily to describe a particular chronological or sequential order. It is to be understood that the use of such terms herein is merely for distinguishing between objects in order to more clearly describe the application and its application to an embodiment of the application. Further, the terms "comprises", "comprising", "includes", "including" and the like are to be construed open-ended, meaning that they are intended to cover processes, methods, systems, products or devices that comprise or include, but are not limited to, the listed steps or elements, and that they are intended to cover processes, methods, systems, products or devices that are not listed but that would be apparent to one of ordinary skill in the art in view of the disclosure.

[0036] Embodiment One

[0037] Figure 1 is a schematic diagram of a heterogeneous converged memory system provided by Embodiment One of the application, as shown in Figure 1 The structure of the heterogeneous converged memory system includes: a Scale-Up domain 110, a Scale-Out domain 120, and a converged agent gateway 130, wherein: the Scale-Up domain 110 is composed of a plurality of processing units connected by a first interconnection and has a unified global address space; the Scale-Out domain 120 is composed of a plurality of computing nodes connected by a second interconnection; the Scale-Out domain 120 further includes the converged agent gateway 130, which is used to connect the first interconnection and the second interconnection; the converged agent gateway 130 is used to: receive an RDMA operation request from a target domain node as an RDMA endpoint; convert a global address in the RDMA operation request into a physical address of a target processing unit in the Scale-Up domain; and access the physical memory of the target processing unit through the first interconnection with a memory semantic.

[0038] The first interconnection mode in the Scale-Up domain 110 can be a high-speed tightly coupled interconnection mode, which can include, but is not limited to, NVLink (a bus and its communication protocol), CXL (Compute Express Link), CCIX (Cache Coherent Interconnect for Accelerators), and the like. The second interconnection in the Scale-Out domain 120 can be a standard network connection mode, which can include, but is not limited to, Ethernet and InfiniBand, and the like. The specific interconnection type of the first interconnection and the second interconnection is not limited in the embodiments of the present application. The processing unit can be a server node or a chip unit, for example, a GPU can be a processing unit, and the specific type of the processing unit in the Scale-Up domain is not limited in the embodiments of the present application. The computing node in the Scale-Out domain can be an independent device node, for example, a large number of independent server nodes. The target processing unit can be a processing unit requesting memory access. The target domain node can be any Scale-Up domain node, that is, a node in the Scale-Up domain where the fusion agent gateway 130 is located, or other Scale-Up domain nodes, and the type of the target domain node is not limited in the embodiments of the present application.

[0039] The Scale-Up domain 110 connects a small number of server nodes or chips through the first interconnection mode of the high-speed tightly coupled interconnection to form a single system with a unified memory address space. The Scale-Up domain 110 can establish an internal interconnection network through the switch SWn in the domain. The Scale-Out domain 120 connects a large number of independent server nodes through a standard network, and communicates and exchanges data through software protocols such as MPI (Multipoint Interface) and RPC (Remote Procedure Call Protocol).

[0040] In the heterogeneous fusion memory system provided by the embodiments of the present application, not every processing unit in the Scale-Up domain is connected to the Scale-Out domain switch, and each Scale-Up domain can be configured with a processing unit as a fusion agent gateway. The fusion agent gateway can be connected to the Scale-Out domain switch, so as to realize a cross-Scale-Up domain communication process with the fusion agent gateways of the Scale-Up domains. In addition to the fusion agent gateway, other processing units in the Scale-Up domain are not connected to the Scale-Out domain switch. For example,Figure 1 As shown, each Scale-Up domain adopts the processing unit 1 as the converged agent gateway 130 to connect into the Scale-Out domain switch. Alternatively, a separate hardware device (such as an intelligent network card) can also be adopted as the converged agent gateway. Or, the converged agent gateway can also be integrated into a certain boundary processing unit of the Scale-Up domain, such as an I / O (Input / Output) Hub or a switching chip with multi-path interconnection capability, as a functional module of the boundary processing unit. The embodiments of the present application do not limit the configuration manner of the converged agent gateway.

[0041] Correspondingly, the RDMA in the converged agent gateway 130 is in a start state, and the data transmission process across the tiles can be implemented through the Scale-Out domain switch. The RDMA in the processing unit of the non-converged agent gateway in the Scale-Up domain is in a non-start state, and the data transmission process across the tiles cannot be implemented through the Scale-Out domain switch. In the heterogeneous converged memory system, since each Scale-Up domain has a unified global address space, when the memory data of the processing units in different Scale-Up domains are accessed, read, and written, the memory data does not need to be written into the converged agent gateway, and the RDMA is started to complete the packaging and sending of the memory data of the converged agent gateway. The heterogeneous converged memory system of the embodiments of the present application can implement the efficient memory access process without landing in the converged agent gateway 130 based on the configured global address space and the data transmission path connecting the two domains through the converged agent gateway 130.

[0042] In the heterogeneous converged memory system provided by the embodiments of the present application, the processing unit in any Scale-Up domain can initiate a memory access request. Exemplarily, a certain processing unit in the Scale-Up domain where the converged agent gateway 130 is located (which can be the converged agent gateway 130 itself or other processing units) can initiate a memory access request, and a certain processing unit in the Scale-Up domain not including the converged agent gateway 130 can also initiate a memory access request.

[0043] If the memory access request initiated by the fusion agent gateway of the target domain node is a memory access request across the Scale-Up domain, the memory access request initiated by the fusion agent gateway of the target domain node can be regarded as a kind of RDMA operation request. Correspondingly, the fusion agent gateway of the target domain node sends the RDMA operation request to the fusion agent gateway of the corresponding Scale-Up domain through the external Ethernet switch, and the fusion agent gateway of the Scale-Up domain can receive the RDMA operation request from the target domain node as an RDMA endpoint, convert the global address in the RDMA operation request into the physical address of the target processing unit in the Scale-Up domain, and access the physical memory of the target processing unit through the first interconnection with the memory semantics.

[0044] In a specific example, when the GPU1 (hereinafter referred to as S0-GPU1) of the edge node (the edge node is also a node connected to the Scale-Out domain switch, and the fusion agent gateway) in the Scale-Up0 domain wants to move the memory data in another GPU0 in the Scale-Up0 domain to the GPU0 in the Scale-Up1 in another space of the Scale-Out domain, the traditional method needs to first write the memory data of the S0-GPU0 to the memory of the S0-GPU1 through the DMA (Direct Memory Access) of the S0-GPU1, then start the RDMA of the S0-GPU1 to package and send the memory data of the GPU to the edge node S1-GPU1 of the Scale-Up1, and then write the memory data of the GPU to the memory of the S1-GPU1 through the DMA of the S1-GPU1, and further package and send the memory data of the GPU to the target processing unit GPU0 in the Scale-Up1 through the DMA of the S1-GPU1.

[0045] In the embodiment of the application, when it is desired to move the memory data in another GPU0 in the Scale-Up0 domain to the GPU0 in the Scale-Up1 in another space of the Scale-Out domain through the S0-GPU1, it is only necessary to start the RDMA in the fusion agent gateways of the S0-GPU1 and the S1-GPU1, read the source data from the S0-GPU0 according to the global space address of the Scale-Up0, package the data through the RDMA of the S0-GPU1, complete the transmission to the S1-GPU1, and further complete the global address write operation in the Scale-Up1 domain by the RDMA in the S1-GPU1 to directly write the main memory in the S1-GPU0. As can be seen, the heterogeneous fusion memory system in the embodiment of the application can complete the memory data access process of two Scale-Up domains without landing.

[0046] In an optional embodiment of the present application, the converged proxy gateway can also be used to: generate an AXI operation request according to a memory access requirement as an RDMA source point; wherein the AXI operation request comprises a global address of a source processing unit in a source Scale-Up domain; send the AXI operation request to a link selection module through a relay module, and select a target link module from each link module through the link selection module, so as to send the AXI operation request to the source processing unit in the source Scale-Up domain to access a memory through the target link module.

[0047] The source Scale-Up domain can be a Scale-Up domain in which the converged proxy gateway is located. The source processing unit can be a certain processing unit other than the converged proxy gateway in the source Scale-Up domain, and the memory data of the source processing unit needs to be moved to another processing unit.

[0048] In the embodiment of the present application, the converged proxy gateway can generate an AXI (Advanced eXtensible Interface) operation request as an RDMA source point according to a memory access requirement, and the AXI request is a memory semantic request in a Scale-Up domain. The memory access requirement can be generated locally, or can be generated by another processing unit in the Scale-Up domain in which the converged proxy gateway is located, and the embodiment of the present application does not limit this. For example, the converged proxy gateway can access the memory data of another processing unit in the Scale-Up domain as an RDMA source point, or the converged proxy gateway can directly access the memory data of the processing unit as an RDMA source point, thereby generating an AXI operation request.

[0049] The converged proxy gateway can comprise an RDMA network interface for connecting a Scale-Out network and processing an RDMA protocol; an intra-domain interconnection interface for connecting an intra-Scale-Up domain interconnection network; an address conversion module for querying a global address mapping table; and a protocol conversion module for converting an RDMA read / write request into a memory load / store transaction supported by the intra-Scale-Up domain interconnection.

[0050] Figure 2 FIG. 1 is a structural schematic diagram of a converged proxy gateway provided by an embodiment of the present application. For example, as shown in FIG. 1, the converged proxy gateway can comprise an RDMA network interface 101, an intra-domain interconnection interface 102, an address conversion module 103, a protocol conversion module 104, a link selection module 105, and a relay module 106. Figure 2As shown, when the GPU is used as the processing unit, the fusion agent gateway can also be a GPU. When the fusion agent gateway directly accesses the memory data of the processing unit, the AXI operation request can be initiated by the RDMA of the GPU to directly access the memory memory (MEM for short) of the GPU through the on-chip NoC (Network on Chip, an on-chip communication architecture used to connect GPU cores, texture units, caches and storage units and other functional modules) link of the GPU. When the fusion agent gateway can access the memory data of the source processing unit in the source Scale-Up domain as an RDMA source point, the AXI operation request can be initiated by the RDMA of the GPU, and after being transferred by the transfer module of the GPU, the AXI operation request is sent to the link selection module, and after being selected by the link selection module, the AXI operation request is sent to the source processing unit in the source Scale-Up domain through the switch of the source Scale-Up domain to directly access the memory. Specifically, the AXI operation request is sent to the ADP (Adapter, adapter module) module of the source processing unit in the source Scale-Up domain for direct analysis and processing. Correspondingly, the ADP of the source processing unit in the source Scale-Up domain can access the memory data of the GPU through the transfer module of the GPU, and return the memory data to the RDMA of the fusion agent gateway in the original path.

[0051] As shown in Figure 2 The GPU has a main memory space or a local cache MEM inside, and the link system access process is the same, and each component uses an AXI interface protocol and is interconnected through an on-chip NoC. The DMA component can be used for on-chip data migration and provides data support for calculation, and can also be used for cross-chip access in the Scale-Up domain based on the AXI bus protocol. A unified global address space is used in the Scale-Up domain, and the DMA address can be directly configured or converted into a global address GVA (Global Virtual Address, global virtual address). For example, the global address GVA can be "GPUID+on-chip virtual / physical address", wherein "GPUID" is used to identify the GPU, and "on-chip virtual / physical address" is used to identify the access address of the GPU in the Scale-Up domain. The global address can be used for inter-chip routing in the Scale-Up domain by the on-chip network, the link module and the switch in the Scale-Up domain, and the DMA only needs to focus on the global address in the Scale-Up domain, and the global cross-chip can be completed by the link module and the switch. The cross-chip operation of the DMA can be completed in the 2TON link selection module based on a certain topology and algorithm (such as spraying or directional routing).

[0052] As shown in Figure 2As shown, in addition to the ADP module, the link module also includes an RDMA component. The RDMA component can be based on the standard RoCE v2 (RDMA over Converged Ethernet version 2) protocol, combined with the MAC (Media Access Control Address) and PCS (Physical Coding Sublayer) technologies of Ethernet, and externally connected to a standard Ethernet switch, to complete the Scale-Out domain networking. The RDMA and ADP in the link module, and the ADP and the underlying MAC can use the Stream interface to complete data transmission. The ADP module is used to complete protocol conversion, process all memory semantic requests, and perform packaging and routing calculation for the underlying data transmission, to provide the required interface content for the physical layer data transmission. The ADP and the lower packaging module are two independent modules, and the packaging module can use a custom IP (Internet Protocol Address) to complete the packaging process from the AXI five channels to the network packet. The ADP interface can include AXI and Stream, and each link module can be statically configured as a Scale-Up or Scale-Out mode. In the Scale-Up mode, the link module uses the AXI interface to complete the intra-domain cross-chip, and in the Scale-Out mode, the link module Stream interface is used to connect the underlying standard Ethernet MAC and PCS to complete the cross-chip.

[0053] In the embodiment of the present application, the RDMA operation request initiated by the RDMA source point can include the global address of the target processing unit of the Scale-Up domain where the RDMA endpoint is located. When the RDMA of the fusion agent gateway is the RDMA source point, the RDMA operation request including the global address of the source processing unit in the source Scale-Up domain can be generated according to the memory access requirement of the processing unit in the source Scale-Up domain or the source processing unit. Further, the RDMA of the fusion agent gateway can send the AXI operation request to the link selection module through the transit module of the fusion agent gateway, and select the Scale-up mode link module as the target link module from each link module through the link selection module of the fusion agent gateway, so as to send the AXI operation request using AXI through the target link module. If the fusion agent gateway as the RDMA source point needs to carry the memory data of the source processing unit in the source Scale-Up domain to a processing unit in another Scale-Up domain after reading the memory data, the fusion agent gateway as the RDMA source point can generate the RDMA operation request according to the read memory data and the global address information of the Scale-Up domain node to be carried, and send the generated RDMA operation request to the fusion agent gateway of the corresponding Scale-Up domain node through the external Ethernet switch.

[0054] Correspondingly, the fusion agent gateway of the corresponding Scale-Up domain node can receive the RDMA operation request sent by the fusion agent gateway as the RDMA source point in the target domain node (here the target domain node represents the Scale-Up domain where the fusion agent gateway as the RDMA source point is located) as the RDMA endpoint, and analyze the RDMA operation request, convert the global address in the RDMA operation request into the physical address of the target processing unit in the Scale-Up domain, and then access the physical memory of the target processing unit through the first interconnection of the Scale-Up domain with the memory semantics. It can be understood that the physical address of the target processing unit can be the physical address of the fusion agent gateway as the RDMA endpoint in the Scale-Up domain, or the physical address of another processing unit in the Scale-Up domain where the fusion agent gateway as the RDMA endpoint is located.

[0055] Specifically, the RDMA only in the processing unit and Scale-Out domain workflow can be: in the establishment of QP (Queue Pair, queue pair) pairing between different processing units of RDMA, complete the initialization and establishment. Source RDMA through AXI interface and NoC complete intra-chip memory read operation, packaged as a standard RoCE v2 packet in RDMA as RDMA operation request, through the Stream interface and the underlying standard Ethernet MAC and PCS connected, complete and serial conversion, sent to the external standard Ethernet switch. The external standard Ethernet switch will send the RDMA operation request to the target receiving side of the fusion agent gateway according to the routing information, and further send it to the ADP of the target processing unit through the target receiving side of the fusion agent gateway for access. The ADP of the target processing unit sends memory access requests to the on-chip through different operation types, reads and writes main memory or local storage.

[0056] In an optional embodiment of the present application, the processing unit of the Scale-Up domain can also be used to: send a cross-chip AXI operation request through the DMA, convert the global address in the cross-chip AXI operation request to the physical address of the target processing unit in the Scale-Up domain; send the cross-chip AXI operation request to the target link module, so that the target link module packs the cross-chip AXI operation request according to the physical address of the target processing unit in the cross-chip AXI operation request, and then accesses the physical memory of the target processing unit through the first interconnection with memory semantics.

[0057] Among them, the cross-chip AXI operation request can be a DMA cross-chip memory data transfer request, which can be a read request or a write request of memory data, and the request includes request type and global address information.

[0058] In related technologies, the memory addresses of each processing unit in a single Scale-Up domain are independent of each other, and in this case, the DMA of the processing unit cannot implement the cross-chip memory data moving process. However, the embodiment of the present application configures a unified global address space for the Scale-Up domain, so that the DMA of each processing unit in the same Scale-Up domain can implement the cross-chip data moving process based on the unified global address space.

[0059] Figure 3 is another structure diagram of the fusion agent gateway provided by the embodiment one of the present application. In a specific example, as Figure 3As shown, when the GPU is used as a processing unit, the DMA can send a cross-chip AXI operation request, which can complete address substitution before entering the NoC, so that the cross-chip AXI operation request carries an address of GVA (GPU ID + target address). The in-chip NoC is delivered to the link selection module 2TON according to the GVA mark, the link selection module 2TON can complete the selection of N link modules according to the fixed GPU ID, determine the target link module, and send the cross-chip AXI operation request to the target link module. Further, the cross-chip AXI operation request completes address format conversion carrying the target GPU ID according to the packaging routing IP requirement in the ADP, and obtains the USER (user), ID and ADDR (Address, address) definition mode conforming to the IP requirement. The packaging module completes the network packet packaging of different AXI channels according to the GPU ID, and completes the request transmission to the target processing unit end through the external customized Scale-Up domain switch or the direct connection topology in the Scale-Up domain. The bottom layer packet module of the target processing unit completes the restoration of the network packet to the AXI channel interface. Further, the target processing unit is converted to an in-chip memory access format in the ADP, and accesses the physical memory through the NoC. Correspondingly, the B / R (WriteResponse Channel‌ / Read Data Channel, write response channel‌ / read data channel) channel response of the target processing unit to the cross-chip AXI operation request is the same as the memory access path of the cross-chip AXI operation request.

[0060] In summary, the embodiment of the present application directly converts the RDMA operation request into Scale-Up domain memory access through the fusion agent gateway, avoids the protocol stack and internal bus bottleneck of the proxy node in the traditional scheme, and realizes the extreme memory access performance of nearly direct connection, low delay and high bandwidth. In this case, the Scale-Out node can directly access the memory of all processing units of the Scale-Up domain, not the memory of a single processing unit, and truly turns the entire Scale-Up domain into a huge and unified memory pool that can be remotely accessed by the network, realizing the integrity of resource pooling. Since the Scale-Out side uses a completely standard RDMA protocol, there is no need to modify the existing Scale-Out node hardware, driver and application program, only the GAL address needs to be specified, and the standardization and compatibility are excellent, easy to deploy. The above-mentioned heterogeneous fusion memory system perfectly combines the advantages of large-capacity unified memory of Scale-Up architecture and large-scale expansion capability of Scale-Out architecture, and the powerful architecture advantage provides ideal underlying architecture support for the next generation of data centers and HPC (High Performance Computing, high-performance computing) systems. The above-mentioned heterogeneous fusion memory system also makes full use of the high-speed interconnection network in the Scale-Up domain for the final data transmission, and its bandwidth is much higher than that of the traditional Ethernet, so that the remote access can also obtain the bandwidth experience similar to the local bus.

[0061] The embodiment of the present application comprises a heterogeneous fusion memory system by longitudinally extending Scale-Up domain, transversely extending Scale-Out domain and fusion proxy gateway. The Scale-Up domain is composed of multiple processing units connected by a first interconnection and has a unified global address space. The Scale-Out domain is composed of multiple computing nodes connected by a second interconnection. The Scale-Out domain further comprises a fusion proxy gateway for connecting the first interconnection and the second interconnection. In the heterogeneous fusion memory system, the fusion proxy gateway can receive an RDMA operation request from a target domain node as an RDMA endpoint, convert a global address in the RDMA operation request into a physical address of a target processing unit in the Scale-Up domain, and access the physical memory of the target processing unit with memory semantics through the first interconnection. In the above-mentioned heterogeneous fusion memory system, the Scale-Out node can directly access the memory of all chips in the Scale-Up domain, rather than the memory of a single node, and the entire Scale-Up domain is truly changed into a huge and unified memory pool that can be remotely accessed by the network. The Scale-Out side adopts a completely standard RDMA protocol, without the need to modify the existing Scale-Out node hardware, driver and application program, and has excellent compatibility and easy deployment. The memory access method of the fusion proxy gateway in the heterogeneous fusion memory system directly converts the RDMA request into an intra-domain memory access, avoiding the protocol stack and internal bus bottleneck of the proxy node in the traditional scheme. Therefore, the above-mentioned heterogeneous fusion memory system and the memory access method of the fusion proxy gateway realize low latency and high bandwidth of memory access based on the heterogeneous fusion memory system, and maintain the compatibility of the heterogeneous fusion memory system.

[0062] Embodiment two

[0063] Figure 4 is a flowchart of a memory access method provided by the second embodiment of the present application. The embodiment can be applied to the case that the fusion proxy gateway in the heterogeneous fusion memory system converts the RDMA request into an intra-domain memory access. The method can be executed by a memory access device, which can be realized by software and / or hardware, and can be generally integrated in an electronic device. The electronic device can be a terminal device or a server device, as long as it can execute the memory access method. The specific type of the electronic device is not limited in the present application. Correspondingly, as shown in Figure 4 , the method comprises the following operations:

[0064] S410, receiving an RDMA operation request from a target domain node as an RDMA endpoint.

[0065] S420, converting a global address in the RDMA operation request into a physical address of a target processing unit in the Scale-Up domain.

[0066] In an optional embodiment of the present invention, the step of converting the global address in the RDMA operation request into the physical address of the target processing unit within the Scale-Up domain may include: obtaining a global address mapping table; querying the global address mapping table according to the global address in the RDMA operation request to obtain the physical address of the target processing unit corresponding to the global address in the RDMA operation request.

[0067] The global address mapping table can be a mapping table between global addresses and the physical addresses of processing units within the Scale-Up domain.

[0068] When the converged proxy gateway receives an RDMA operation request from a target domain node, it parses the request to obtain the included global address, and further retrieves the global address mapping table. The parsed global address is then used to query the global address mapping table to obtain the physical address of the target processing unit corresponding to the global address in the RDMA operation request. Optionally, the global address mapping table can be centrally stored in the converged proxy gateway or a distributed storage method can be used, such as storing a copy in each processing unit within the Scale-Up domain. The converged proxy gateway obtains the mapping relationship by querying the request.

[0069] S430, Access the physical memory of the target processing unit in memory semantics via the first interconnect.

[0070] In an optional embodiment of the present invention, the above method may further include: generating an AXI operation request as an RDMA source point based on memory access requirements; wherein the AXI operation request includes the global address of the source processing unit within the source Scale-Up domain; sending the AXI operation request to the link selection module through a relay module, and selecting a target link module from among the link modules through the link selection module, so as to send the AXI operation request to the source processing unit within the source Scale-Up domain to access memory through the target link module.

[0071] Figure 5 This is a schematic diagram of the processing flow of a single processing unit that integrates RDMA Scale-Out and Scale-Up domain access, provided in Embodiment 2 of the present invention. In a specific example, such as Figure 5As shown, assuming that GPU1 in each Scale-Up domain is configured as a converged proxy gateway, and LINK_UNIT0 (link module identified as UNIT0) in each GPU is statically configured in Scale-Out mode, while the remaining link modules LINK_UNIT are configured in Scale-Up mode. Only the RDMA within the link module configured in Scale-Out mode can initiate cross-chip memory access requests. When it is necessary to move memory data from GPU0 (S0-GPU0) in Scale-Up domain 0 to GPU0 (S1-GPU0) in Scale-Up domain 1, RDMA0 (S0-GPU1-RDMA0) in S0-GPU1 and RDMA0 (S1-GPU1-RDMA0) in S1-GPU1 establish a QP pair, exchange QP information, and are interconnected through a standard Ethernet switch to form a Scale-Out network. Each converged proxy gateway can initiate read / write operations to any global address within its Scale-Up domain (not limited to the local GPU). The RDMA of the converged proxy gateway does not recognize whether the read / write operation is to the local GPU address. In other words, read / write operations in the Scale-Up domain are completely transparent to the RDMA of the converged proxy gateway.

[0072] Specifically, S0-GPU1-RDMA0, acting as the RDMA source, initiates an AXI operation request to read the global address of S0-GPU0. This AXI operation request includes the global address of S0-GPU0. The global address of S0-GPU0 is converted to a GVA address (GPUID + target internal address) through address substitution. After S0-GPU1 is merged by the relay module NTO1, the AXI operation request is checked against the address information to determine if it is a GVA and if it is the address of this GPU. If not, the AXI operation request is sent from the relay module NTO1 through the link selection module to select one of the target link modules in Scale-Up mode. After ADP processing by the target link module, the chip is output. Further, the AXI operation request is sent to a specific Scale-Up mode link module of S0-GPU0 through the switch in the Scale-Up domain, based on routing information. The link module receiving the AXI operation request parses the request, obtains the memory data of this chip, and packages it to generate a response data packet for the AXI operation request. Furthermore, S0-GPU0 returns the generated response data packet via the link module that received the AXI operation request to S0-GPU1-RDMA0. This operation is an AXI operation, which differs from an RDMA operation in that it packages the AXI channel within the Scale-Up domain for reading and writing.

[0073] S0-GPU1-RDMA0 receives the response data packet, acquires its memory data, and further packages it to generate a new RDMA (RoCE v2 standard packet, using standard switch routing) operation request for processing. This RDMA operation request includes the global address of S0-GPU0. Further, S0-GPU1-RDMA0 processes the RDMA operation request generated from the response data packet through the ADP of the target link module and outputs it to S1-GPU1-RDMA0. S1-GPU1-RDMA0 takes the received RDMA operation request (the request generated by the AXI operation), merges it through the relay module NTO1 on S1-GPU1, selects one of the target link modules in Scale-Up mode through the link selection module, processes it through the ADP of the target link module, outputs it, and sends it to a specific Scale-Up mode link module of S1-GPU0 through the switch in the Scale-Up domain according to the routing information. The link module receiving the RDMA operation request on S1-GPU0 parses the RDMA operation request, acquires the transferred memory data, and stores the parsed memory data in the memory of this chip.

[0074] This demonstrates that a unified global address space within the Scale-Up domain enables Scale-Out domain RDMA access to any address within the Scale-Up domain, thereby merging Scale-Up and Scale-Out domain access.

[0075] It should be noted that, in this embodiment of the invention, the RDMA protocol can be lightweightly extended according to actual business needs, carrying additional information in the data packets, such as the source node ID and QoS (Quality of Service) level, to enable the converged proxy gateway to perform more intelligent routing and scheduling. For scenarios requiring cache consistency, caching can be introduced in the converged proxy gateway or client, along with a directory-based software / hardware consistency protocol, to ensure data consistency when multiple Scale-Out nodes access the same GVA address. A large-scale in-memory database can also be configured specifically, placing the entire database in a Scale-Up memory pool, allowing a large number of Scale-Out computing nodes to perform extremely fast parallel queries and transaction processing via RDMA. Depending on the specific application scenario requirements, massive model parameters can be stored in the Scale-Up domain, allowing thousands of trainers to read weights and write gradients via high-frequency RDMA, breaking the GPU memory barrier. In a cloud environment, the Scale-Up domain can also be used as a shared "memory-as-a-service" resource, providing tenants with a much larger memory capacity than a single virtual machine. The converged proxy gateway can also function as a high-performance virtual switch, providing a low-latency virtual network based on RDMA between Scale-Out nodes. The data plane is fully accelerated by the Scale-Up domain memory, enabling high-speed virtualized switching.

[0076] This invention utilizes a converged proxy gateway within a heterogeneous converged memory system as an RDMA endpoint to receive RDMA operation requests from target domain nodes. It translates the global address in the RDMA operation request into the physical address of the target processing unit within the Scale-Up domain, thereby accessing the physical memory of the target processing unit in memory semantics via a first interconnect. The Scale-Out nodes in this heterogeneous converged memory system can directly access the memory of all chips in the Scale-Up domain, rather than the memory of a single node, truly transforming the entire Scale-Up domain into a vast, unified memory pool accessible remotely over the network. The Scale-Out side employs a fully standard RDMA protocol, requiring no modification to existing Scale-Out node hardware, drivers, and applications, resulting in excellent compatibility and ease of deployment. The memory access method of the converged proxy gateway within the heterogeneous converged memory system directly translates RDMA requests into domain-wide memory access, avoiding the protocol stack and internal bus bottlenecks of proxy nodes in traditional solutions. Therefore, the aforementioned memory access method of the converged proxy gateway achieves low latency and high bandwidth for memory access based on a heterogeneous converged memory system while maintaining the compatibility of the heterogeneous converged memory system.

[0077] It should be noted that all information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant regions.

[0078] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0079] Example 3

[0080] Figure 6 This is a schematic diagram of a memory access device provided in Embodiment 3 of the present invention. This device is configured in the converged proxy gateway of the heterogeneous converged memory system described in any embodiment of the present invention, such as... Figure 6 As shown, the device includes: an RDMA operation request receiving module 610, a physical address translation module 620, and a physical memory access module 630, wherein:

[0081] RDMA operation request receiving module 610 is used as an RDMA endpoint to receive RDMA operation requests from target domain nodes.

[0082] The physical address translation module 620 is used to translate the global address in the RDMA operation request into the physical address of the target processing unit within the Scale-Up domain;

[0083] The physical memory access module 630 is used to access the physical memory of the target processing unit in memory semantics through the first interconnect.

[0084] This invention utilizes a converged proxy gateway within a heterogeneous converged memory system as an RDMA endpoint to receive RDMA operation requests from target domain nodes. It translates the global address in the RDMA operation request into the physical address of the target processing unit within the Scale-Up domain, thereby accessing the physical memory of the target processing unit in memory semantics via a first interconnect. The Scale-Out nodes in this heterogeneous converged memory system can directly access the memory of all chips in the Scale-Up domain, rather than the memory of a single node, truly transforming the entire Scale-Up domain into a vast, unified memory pool accessible remotely over the network. The Scale-Out side employs a fully standard RDMA protocol, requiring no modification to existing Scale-Out node hardware, drivers, and applications, resulting in excellent compatibility and ease of deployment. The memory access method of the converged proxy gateway within the heterogeneous converged memory system directly translates RDMA requests into domain-wide memory access, avoiding the protocol stack and internal bus bottlenecks of proxy nodes in traditional solutions. Therefore, the aforementioned memory access method of the converged proxy gateway achieves low latency and high bandwidth for memory access based on a heterogeneous converged memory system while maintaining the compatibility of the heterogeneous converged memory system.

[0085] Optionally, the physical address translation module 620 is further configured to: obtain a global address mapping table; query the global address mapping table according to the global address in the RDMA operation request to obtain the physical address of the target processing unit corresponding to the global address in the RDMA operation request.

[0086] Optionally, the above apparatus further includes an AXI operation request generation module, used as an RDMA source point to generate an AXI operation request based on memory access requirements; wherein, the AXI operation request includes the global address of the source processing unit within the source Scale-Up domain; the AXI operation request is sent to the link selection module through a relay module, and the link selection module selects a target link module from among the link modules, so as to send the AXI operation request to the source processing unit within the source Scale-Up domain to access memory through the target link module.

[0087] The memory access device described above can execute the memory access method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the memory access method provided in any embodiment of the present invention.

[0088] Since the memory access device described above is an apparatus capable of executing the memory access method in the embodiments of the present invention, those skilled in the art can understand the specific implementation methods and various variations of the memory access device in this embodiment based on the memory access method described in the embodiments of the present invention. Therefore, how the memory access device implements the memory access method in the embodiments of the present invention will not be described in detail here. Any apparatus used by those skilled in the art to implement the memory access method in the embodiments of the present invention falls within the scope of protection of this application.

[0089] Example 4

[0090] Figure 7 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0091] like Figure 7 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0092] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0093] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as memory access methods.

[0094] Optionally, the memory access method is applied to the converged proxy gateway in the heterogeneous converged memory system according to any embodiment of the present invention. The method may include: receiving an RDMA operation request from a target domain node as an RDMA endpoint; converting the global address in the RDMA operation request into the physical address of the target processing unit within the Scale-Up domain; and accessing the physical memory of the target processing unit in memory semantics through the first interconnect.

[0095] In some embodiments, the memory access method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the memory access method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the memory access method by any other suitable means (e.g., by means of firmware).

[0096] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0098] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0100] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0101] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0102] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A heterogeneous fused memory system, characterized in that, include: Vertical scaling of the Scale-Up domain, horizontal scaling of the Scale-Out domain, and converged proxy gateway, wherein: The Scale-Up domain consists of multiple processing units interconnected by a first interconnection and has a unified global address space; The Scale-Out domain consists of multiple compute nodes connected via a second interconnect; the Scale-Out domain also includes a converged proxy gateway for connecting the first interconnect and the second interconnect. The converged proxy gateway is used to: receive RDMA operation requests from target domain nodes as a remote direct memory access (RDMA) endpoint; The global address in the RDMA operation request is translated into the physical address of the target processing unit within the Scale-Up domain; the physical memory of the target processing unit is accessed in memory semantics via the first interconnect.

2. The system according to claim 1, characterized in that, The fusion proxy gateway is also used for: As an RDMA source, it generates an AXI operation request based on memory access requirements; wherein, the AXI operation request includes the global address of the source processing unit within the source Scale-Up domain; The AXI operation request is sent to the link selection module through the relay module, and the target link module is selected from each link module through the link selection module so that the AXI operation request can be sent to the source processing unit access memory in the source Scale-Up domain through the target link module.

3. The system according to claim 1, characterized in that, The processing unit of the Scale-Up domain is also used for: Send cross-chip AXI operation requests via Direct Memory Access (DMA), and convert the global address in the cross-chip AXI operation request to the physical address of the target processing unit within the Scale-Up domain; The cross-chip AXI operation request is sent to the target link module, which then packages the cross-chip AXI operation request according to the physical address of the target processing unit and accesses the physical memory of the target processing unit in memory semantics through the first interconnect.

4. A memory access method, characterized in that, The method, applied to a converged proxy gateway in any of the heterogeneous converged memory systems described in claims 1-3, comprises: Receive RDMA operation requests from the target domain node as an RDMA endpoint; The global address in the RDMA operation request is translated into the physical address of the target processing unit within the Scale-Up domain; The physical memory of the target processing unit is accessed in memory semantics via the first interconnect.

5. The method according to claim 4, characterized in that, The step of converting the global address in the RDMA operation request to the physical address of the target processing unit within the Scale-Up domain includes: Obtain the global address mapping table; The physical address of the target processing unit corresponding to the global address in the RDMA operation request is obtained by querying the global address mapping table based on the global address in the RDMA operation request.

6. The method according to claim 4, characterized in that, Also includes: As an RDMA source, it generates an AXI operation request based on memory access requirements; wherein, the AXI operation request includes the global address of the source processing unit within the source Scale-Up domain; The AXI operation request is sent to the link selection module through the relay module, and the target link module is selected from each link module through the link selection module so that the AXI operation request can be sent to the source processing unit access memory in the source Scale-Up domain through the target link module.

7. A memory access device, characterized in that, A converged proxy gateway configured in any one of the heterogeneous converged memory systems according to claims 1-3, the device comprising: The RDMA operation request receiving module is used as an RDMA endpoint to receive RDMA operation requests from the target domain node. The physical address translation module is used to translate the global address in the RDMA operation request into the physical address of the target processing unit within the Scale-Up domain; A physical memory access module is used to access the physical memory of the target processing unit in memory semantics via the first interconnect.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that is executed by the at least one processor to enable the at least one processor to perform the memory access method according to any one of claims 4-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the memory access method according to any one of claims 4-6.

10. A computer program product, characterized in that, Includes a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the memory access method according to any one of claims 4-6.

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