Memory controller, memory address processing method thereof and computing system

By constructing a reverse mapping table, the memory controller translates system physical addresses into usable DRAM addresses, solving the data error problem caused by bad DRAM cells, and enabling the provision of contiguous memory space and improving system stability.

CN121858355APending Publication Date: 2026-04-14深圳市因梦晶凯测试技术有限公司
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Patent Information

Application Number
CN202610315676.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-16
Publication Date
2026-04-14

AI Technical Summary

Technical Problem

Existing memory controllers cannot effectively utilize bad cell information in DRAM, causing data errors or crashes when the computing system accesses bad cells, and failing to provide continuous available memory space, affecting memory utilization and system reliability.

Method used

By constructing a reverse mapping table, the memory controller translates the system physical address issued by the processor into a usable DRAM physical address, shields bad cell regions, provides a contiguous system physical address space, and improves the effective utilization of DRAM and the stability of the computing system.

Benefits of technology

Without changing the processor's memory access method, bad cell regions are masked, providing a continuous system physical address space, improving the effective utilization of DRAM and the operational stability of the computing system, and reducing the risk of the entire memory becoming unavailable due to local memory failures.

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Abstract

The invention discloses a memory controller, a memory address processing method thereof and a computing system.The method comprises the steps that a reverse mapping table between a system physical address area and an available DRAM physical address area is obtained through bad area data based on a DRAM, and during running, the memory controller sends a system physical address sent by a processor to the DRAM physical address area according to the reverse mapping table; the method comprises the following steps: dynamically remapping to a DRAM physical address of a non-failure unit, and generating a corresponding control signal for accessing the DRAM, thereby shielding a DRAM physical region containing a failure storage unit, providing a continuous and complete system physical address space for an upper layer, improving the effective utilization rate of the DRAM and the operation stability of a computing system, and improving the reliability of the computing system on the premise of not changing the memory access mode of a processor. And the risk that the whole memory is unavailable due to local storage failure is reduced.
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