Memory controller, memory address processing method thereof and computing system

Abstract

The invention discloses a memory controller, a memory address processing method thereof and a computing system.The method comprises the steps that a reverse mapping table between a system physical address area and an available DRAM physical address area is obtained through bad area data based on a DRAM, and during running, the memory controller sends a system physical address sent by a processor to the DRAM physical address area according to the reverse mapping table; the method comprises the following steps: dynamically remapping to a DRAM physical address of a non-failure unit, and generating a corresponding control signal for accessing the DRAM, thereby shielding a DRAM physical region containing a failure storage unit, providing a continuous and complete system physical address space for an upper layer, improving the effective utilization rate of the DRAM and the operation stability of a computing system, and improving the reliability of the computing system on the premise of not changing the memory access mode of a processor. And the risk that the whole memory is unavailable due to local storage failure is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit and computer architecture technology, and in particular to a memory controller and its memory address processing method, and a computing system. Background Technology

[0002] As storage density continues to increase, Dynamic Random Access Memory (DRAM) inevitably produces bad cells during manufacturing and use. To improve yield, new DRAM chips can store bad area data to identify the location of bad cells. However, existing system-on-chip (SoC) memory controllers typically still access DRAM according to a standard, contiguous physical address space, and cannot actively read and utilize the bad area data. Accessing address regions containing bad cells can easily lead to data errors or even system crashes.

[0003] To address the issue of bad cells in DRAM, existing technologies mainly employ methods such as redundant row / column repair, ECC error correction, or software-level bad block masking. Redundant row / column repair relies on limited redundant resources within the chip, repairing only a fixed number of bad rows or columns, and is typically completed in a single step at the factory, making it unable to handle new bad cells generated during operation. ECC technology focuses on error detection and correction, lacking address remapping capabilities, and struggles to prevent computing system anomalies caused by multi-bit errors. Software-level bad block masking requires the operating system to be aware of bad sector data in advance and causes fragmentation of the physical address space, making it difficult to transparently provide the computing system with contiguous usable memory space.

[0004] In other words, the memory controller cannot, at the hardware level, mask the physical addresses of DRAM containing bad cells based on the bad data stored in DRAM, and further reconstruct a continuous system physical address space that is transparent to the processor. Due to this lack of capability, the computing system still needs to access DRAM according to the original DRAM physical address space. Once accessing the bad DRAM physical address region, errors may occur, and the remaining available storage resources cannot be effectively utilized, resulting in limitations on memory utilization and computing system reliability. Summary of the Invention

[0005] This application provides a memory controller and its memory address processing method, as well as a computing system, which can provide continuous and reliable available memory space to the upper layer, improve the effective utilization of DRAM and the operational stability of the computing system, and reduce the risk of the entire memory becoming unavailable due to local memory failure.

[0006] One technical solution adopted in this application is to provide a memory controller for use in a computing system, the memory controller comprising: A mapping table acquisition unit is used to acquire a reverse mapping table between the system physical address region and the available DRAM physical address region based on DRAM bad sector data; wherein, the bad sector data is used to indicate the DRAM physical address region containing at least one failed memory cell; The address translation engine is used to convert the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table in the memory access path, and generate a physical address for accessing the DRAM.

[0007] Another technical solution adopted in this application is: a memory address processing method applied to a computing system, the computing system including a memory controller, dynamic random access memory (DRAM), and a processor, the memory address processing method including the following steps: During the computing system startup phase or memory configuration phase, bad sector data is read from the non-volatile memory cells associated with the DRAM, wherein the bad sector data is used to indicate a DRAM physical address region containing at least one failed memory cell; Based on the physical structure identifier of the bad sector data of the DRAM, a reverse mapping table between the system physical address region and the available DRAM physical address region is constructed; The reverse mapping table is written into the memory controller so that during memory access, the memory controller can convert the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table, and generate a physical address for accessing the DRAM.

[0008] Another technical solution adopted in this application is: the computing system includes a processor, at least one dynamic random access memory (DRAM), and a memory controller as described in any of the above; wherein the memory controller is connected to the processor and the DRAM.

[0009] Another technical solution adopted in this application is: providing an electronic device, the electronic device comprising: Memory, used to store executable program code; A processor is configured to call and run the executable program code from the memory, causing the electronic device to perform the memory address processing method described in any of the above descriptions.

[0010] Another technical solution adopted in this application is to provide a computer-readable storage medium that stores a computer program, which, when executed by a processor, implements the memory address processing method described in any of the above claims.

[0011] The beneficial effects of this application embodiment are: by obtaining a reverse mapping table between the system physical address region and the available DRAM physical address region based on the bad area data of DRAM, during runtime, the memory controller dynamically remaps the system physical address issued by the processor to the DRAM physical address without failed cells according to the reverse mapping table, and generates corresponding control signals for accessing DRAM. Thus, without changing the processor's memory access method, the DRAM physical region containing failed memory cells is shielded, providing a continuous and complete system physical address space to the upper layer, improving the effective utilization of DRAM and the operational stability of the computing system, and reducing the risk of the entire memory becoming unavailable due to local memory failure. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the architecture of an embodiment of the memory controller of this application; Figure 2 This is a schematic diagram of the architecture of another embodiment of the memory controller of this application; Figure 3 This is a schematic diagram of the execution flow of an embodiment of the memory controller of this application; Figure 4 This is a flowchart illustrating an embodiment of the memory address processing method of this application; Figure 5 This is an exemplary structural block diagram of an electronic device using the memory address processing method of this application; Figure 6 This is an exemplary structural block diagram of a computer-readable storage medium for the memory address processing method of this application. Detailed Implementation

[0013] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0014] Please see Figure 1 , Figure 1 This is a schematic diagram of the architecture of one embodiment of the memory controller of this application. Figure 1 The illustrated embodiment of a memory controller can be applied to a computing system. In this embodiment, when the processor performs a memory access operation, it can issue a system physical address to the memory controller to identify the storage location. This system physical address is represented as a continuously increasing address sequence on the processor side, used to satisfy the processor and its upper-level software's access requirements for contiguous storage areas.

[0015] On the other hand, the actual storage structure of DRAM consists of multiple storage levels. Due to manufacturing defects or failed memory cells generated during operation, there may be DRAM physical addresses in DRAM that contain at least one failed row. In this embodiment, such DRAM physical addresses are marked as unusable DRAM physical address regions, and the remaining regions that do not contain failed memory cells are marked as usable DRAM physical address regions.

[0016] To prevent the processor from accessing unusable DRAM physical address regions, this embodiment does not change the form of the system physical address issued by the processor. Instead, the memory controller parses and converts the system physical address issued by the processor in the memory access path. Specifically, it maps the system physical address to the corresponding system physical address region and constructs a reverse mapping table to convert the system physical address region into the corresponding usable DRAM physical address region, thereby generating a physical address for accessing DRAM. Thus, while maintaining the original memory access behavior of the processor and upper-layer software, the memory controller can automatically shield DRAM physical address regions containing failed memory cells at the hardware level and present the processor with a continuous, securely accessible sequence of system physical address numbers.

[0017] In some embodiments, the memory controller includes a mapping table acquisition unit and an address translation engine.

[0018] A mapping table acquisition unit is used to acquire a reverse mapping table between the system physical address region and the available DRAM physical address region based on DRAM bad sector data; wherein the bad sector data is used to indicate the DRAM physical address containing at least one failed memory cell.

[0019] The bad sector data can be used to indicate the physical address of a DRAM containing at least one faulty memory cell. The bad sector data can mark these damaged areas for subsequent mapping and redirection. In this embodiment, the bad sector data may include physical region identifiers, which can describe specific DRAM physical addresses within the DRAM. For example, a triplet identifier consisting of Rank, Bank, and Block uniquely identifies each region.

[0020] The system physical address can be the address output by the processor after address translation by the Memory Management Unit, used to access system memory. This address is the input address received by the memory controller and used to initiate a memory access request.

[0021] A DRAM physical address is address information obtained by the memory controller from the system physical address and used to drive the DRAM chip to access memory. DRAM physical addresses can be represented by the physical structure hierarchy of the DRAM, including combinations of address signals such as Rank address, Bank address, Row address, and Column address.

[0022] Because some DRAM physical addresses contain at least one failed memory cell, these DRAM physical addresses are marked as unavailable regions. Therefore, the mapping table acquisition unit and address translation engine can be implemented either purely in hardware logic to build and look up the reverse mapping table in real time during memory access; or they can be implemented in a software-hardware co-operation approach, where software generates and configures the reverse mapping table between the system physical address region and the available DRAM physical address region, while the hardware address translation engine performs the table lookup and address translation operations in the memory access path.

[0023] In some specific implementations, the mapping table acquisition unit can construct a reverse mapping table based on bad area data. During chip initialization or power-on, the mapping table acquisition unit detects bad address regions in DRAM or reads pre-stored bad area data from non-volatile memory; based on the bad area data, the mapping table acquisition unit constructs a reverse mapping table between the system physical address region and the available DRAM physical address region; during normal operation, the address translation engine looks up the table in real time during each memory access; converting the system physical address into the corresponding available DRAM physical address region.

[0024] In some other specific implementations, the mapping table acquisition unit can receive a reverse mapping table written by software.

[0025] The reverse mapping table differs from the traditional forward address mapping method, which directly resolves physical addresses to their physical locations. By renumbering available DRAM physical address regions during initialization, a continuous numbered space is created for the system physical address regions. Each system physical address region number corresponds to an actual, usable DRAM physical address. This allows system physical address regions that would otherwise be mapped to bad DRAM physical addresses to be remapped to other usable DRAM physical addresses, effectively masking DRAM physical addresses containing bad sectors at the logical level. In other words, the reverse mapping table can be used as a data structure to mask bad DRAM physical addresses and transparently redirect system physical addresses, enabling the memory controller to present a continuous, bad-sector-free system physical address space to the upper layers without altering the DRAM physical structure.

[0026] In some implementations, to ensure the reliability of bad data, integrity checks can be performed on the bad data when it is read. Specifically, when bad data is stored in a non-volatile storage unit, verification information corresponding to the bad data can be stored simultaneously, such as a cyclic redundancy check (CRC) code, checksum, or other integrity verification identifiers.

[0027] In some implementations, bad sector data can also be stored in an encrypted manner. For example, when writing bad sector data to a non-volatile memory cell, the bad sector data can be encrypted using a preset encryption algorithm. When reading bad sector data, the encrypted data can be decrypted first, and then the decrypted bad sector data can be parsed and used. The decryption process can be implemented by software, by a hardware module in the memory controller, or by a combination of software and hardware.

[0028] The address translation engine is used to convert the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table in the memory access path, and generate a physical address for accessing the DRAM.

[0029] The address translation engine can be configured within the memory access path of the memory controller to perform real-time address translation of memory access requests issued by the processor during the runtime of the computing system. When the processor issues a system physical address access request, the system physical address is resolved to its corresponding system physical address region. Then, based on this system physical address region, the address translation engine queries the reverse mapping table generated and stored by the mapping table retrieval unit to determine the available DRAM physical address region corresponding to the system physical address region. After obtaining the available DRAM physical address region, the address translation engine combines the remaining address fields in the system physical address that are not involved in region mapping to generate the physical address used to access the DRAM.

[0030] In some embodiments, the physical address used to access DRAM may be a control signal containing Rank, Bank, Row, and Column.

[0031] Because the address translation process is handled by the memory controller at the hardware level, the upper-level processor, operating system, and applications do not need to be aware of bad sectors in the DRAM, thus ensuring the software transparency and compatibility of the computing system. Therefore, the memory controller can transparently guide access requests to the actual available physical storage areas at runtime, avoiding access to areas containing bad memory cells, thereby improving the stability and reliability of the computing system.

[0032] In some embodiments, during the computing system startup phase or memory configuration phase, the reverse mapping table written by software is received and stored inside the memory controller for use by the address translation engine.

[0033] As an example, the reverse mapping table is pre-built by software and written to the memory controller. During the system startup or memory configuration phase, software modules in the system construct the correspondence between the system's physical address regions and the available DRAM physical address regions based on the bad sector data of the target memory, forming a reverse mapping table. The software module can be a bootloader, firmware, or memory initialization module in the operating system, which writes the reverse mapping table to the memory controller through a preset configuration interface.

[0034] After receiving the reverse mapping table written by software, the memory controller's mapping table acquisition unit stores the reverse mapping table in its internal on-chip storage unit, such as on-chip static random access memory or a register array, for use in subsequent memory access processes. The reverse mapping table remains valid after the system enters normal operation and does not require software updates during normal memory access processes.

[0035] In the memory access path, the address translation engine translates the system physical address issued by the processor based on a reverse mapping table stored inside the memory controller. Specifically, the address translation engine determines the system physical address region to which the system physical address belongs, and uses this system physical address region as an index to look up the reverse mapping table to obtain the corresponding available DRAM physical address region, thereby generating a DRAM physical address for accessing the target memory. In this way, without the need for software-assisted real-time address translation, DRAM physical addresses containing failed memory cells can be avoided, allowing the processor to transparently access the target memory using a contiguous system physical address space.

[0036] By having the software construct and write the reverse mapping table during the system startup or memory configuration phase, and then having the hardware address translation engine directly look up the table and perform address translation during normal operation, the system overhead during runtime is reduced, and the determinism and stability of memory access paths are improved.

[0037] In some embodiments, please refer to Figure 2 The memory controller includes a bad sector data acquisition unit, a mapping table acquisition unit, and an address translation engine.

[0038] In some embodiments, the bad sector data acquisition unit is configured to read bad sector data from a non-volatile memory cell associated with the DRAM through the communication interface during the memory initialization phase, wherein the bad sector data includes multiple sets of physical structure identifiers, each set of physical structure identifiers being used to characterize a DRAM physical address region in the DRAM.

[0039] Dynamic Random Access Memory (DRAM) is based on the JEDEC standard, and its internal storage structure is divided in a hierarchical manner. Non-volatile memory cells can be integrated inside the DRAM package, such as serial EEPROM and OTP non-volatile storage media, which can be used to record bad sector data corresponding to the DRAM instance. During the memory initialization phase, the bad sector data acquisition unit of the memory controller actively reads the bad sector data, enabling the computing system to obtain the physical location of defects within the DRAM before entering normal memory access.

[0040] The bad sector data includes multiple sets of physical structure identifiers, each representing a DRAM physical address region within the DRAM. Based on the DRAM's physical structure hierarchy, the bad sector data contains identifier information corresponding to the DRAM physical address of the faulty memory cell. Its identifier fields may include hierarchical parameters such as Rank, Bank, and Block, enabling the memory controller to determine the DRAM physical address containing the faulty memory cell.

[0041] The mapping table acquisition unit is used to construct a reverse mapping table between the system physical address region and the available DRAM physical address region based on the physical structure identifier of the bad sector data of the DRAM.

[0042] The mapping table acquisition unit can traverse and compare all DRAM physical address regions based on the physical structure identifiers contained in the bad sector data. When the physical structure identifier of a certain DRAM physical address matches any set of identifier information in the bad sector data, it can be determined that the DRAM physical address contains at least one failed memory cell, and the DRAM physical address is identified as an unusable DRAM physical address region. Meanwhile, DRAM physical addresses not identified as unusable DRAM physical address regions can be identified as usable DRAM physical address regions. Then, based on the usable DRAM physical address regions, the mapping table acquisition unit constructs the correspondence between the system physical address regions and the usable DRAM physical address regions according to preset rules, and generates a reverse mapping table.

[0043] The address translation engine is used to convert the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table in the memory access path, and generate a physical address for accessing the DRAM.

[0044] In some embodiments, the memory controller is connected to the DRAM through multiple memory channels; the mapping table acquisition unit is used to acquire the reverse mapping table corresponding to each memory channel, wherein each reverse mapping table is constructed based on the bad sector data of the corresponding memory channel.

[0045] As an example, in a scenario with multiple memory channels, each memory channel is typically physically independent, and its corresponding memory cells may have different failure distributions. Therefore, the mapping table acquisition unit in this embodiment can acquire the reverse mapping table corresponding to each memory channel. Specifically, each memory channel can construct an independent reverse mapping table based on the bad sector data corresponding to that channel, which describes the correspondence between the system physical address region and the available DRAM physical address region within that memory channel. The bad sector data is used to characterize the DRAM physical address containing at least one failed memory cell in the corresponding memory channel, thereby masking or skipping the relevant DRAM physical addresses when constructing the reverse mapping table.

[0046] Meanwhile, the address translation engine is used to call the reverse mapping table corresponding to the target memory channel for address translation when accessing the target memory channel, so that the bad sector management of different memory channels is independent of each other.

[0047] As an example, during memory access, the address translation engine can select and invoke the reverse mapping table corresponding to the target memory channel based on the target memory channel pointed to by the current access request for address translation processing. In this way, bad sector management in different memory channels can be performed independently, meaning that bad sectors in one memory channel will not affect the mapping relationship of available DRAM physical address regions in other memory channels. This avoids the potential problem of mismasking of available regions when multiple memory channels share the same bad sector information, thereby improving the utilization rate of available storage resources in the entire storage system and enhancing the stability and reliability of memory access.

[0048] In some embodiments, the memory storing bad sector data in DRAM can be placed inside the DRAM package or exist as a separate chip in the system.

[0049] In some implementations, the non-volatile memory cell used to store bad sector data in DRAM can be integrated with the DRAM at the package level. That is, the non-volatile memory cell and the DRAM chip are packaged together in the same package structure, so that the bad sector data can be read through a corresponding interface during the system initialization phase. For example, the non-volatile memory cell can be a serial EEPROM, Flash memory, or embedded multimedia card eMMC, and can be integrated with the DRAM in a multi-chip package.

[0050] In other implementations, the non-volatile memory cells used to store bad sector data can also be independently located in the computing system, without being integrated with the DRAM at the package level. For example, the non-volatile memory cells can be mounted as independent storage devices on the system circuit board and connected to the processor or memory controller via communication interfaces such as I²C, SPI, or eMMC. During the system startup or memory initialization phase, the computing system reads the bad sector data from the non-volatile memory cells through the communication interface and uses this data to construct or obtain a reverse mapping table between the system physical address region and the available DRAM physical address region.

[0051] In some embodiments, the bad sector data is stored in a protective storage area within a non-volatile storage unit, and the protective storage area is accessed via a preset dedicated command.

[0052] In some embodiments, the non-volatile memory cell is integrated with the DRAM in a co-package as an embedded multi-chip package (eMCP), and bad sector data stored in the protective memory region is used to characterize the physical failure information of the DRAM co-packaged with it.

[0053] As an example, the non-volatile storage unit can be implemented using an embedded multimedia card (eMMC). Specifically, the eMMC has a protected storage area that can be accessed via preset eMMC-specific commands. In other words, conventional software read / write processes cannot directly access this protected storage area; data can only be read or written during system initialization or specific configuration phases by sending control commands conforming to the protocol to the eMMC.

[0054] In this embodiment, bad sector data is pre-stored in the protected storage area of ​​the eMMC to record physical failure information related to the dynamic random access memory (DRAM), such as a physical structure identifier representing the physical address of the DRAM containing at least one failed memory cell. The eMMC and the DRAM are integrated into an embedded multi-chip package (eMCP) in a co-packaged form, so that there is a one-to-one correspondence between the bad sector data stored in the eMMC and its co-packaged DRAM.

[0055] In this way, during system startup or memory initialization, the memory controller or startup code can read bad sector data in the protected storage area through the eMMC command interface and complete the identification and masking of failed DRAM physical addresses in the DRAM. Since the bad sector data is stored in the protected area of ​​the eMMC, it will not be overwritten or destroyed by normal storage access processes, thus providing long-term and reliable physical failure information support for the DRAM, improving the stability and consistency of the system's management of memory bad sectors.

[0056] Furthermore, the DRAM in this embodiment is based on the JEDEC standard, and its internal storage structure exhibits a distinct hierarchical feature, including multiple levels such as Rank, Bank, Row, and Column. This allows the actual physical storage space to be organized and addressed according to the aforementioned hierarchical structure. Here, Rank represents a set of memory chips operating in parallel; Bank represents a memory array within a Rank that can be independently activated and accessed; Row represents a row of memory cells located within the same Bank and selected by the same word line, i.e., a storage row; and Column represents the bit line position within a Row.

[0057] During the manufacturing and use of DRAM, due to factors such as process fluctuations, device aging, or changes in the operating environment, some rows may fail, resulting in the corresponding DRAM physical addresses being unreliable or data access errors. Since DRAM access is based on structures such as Banks and Rows, hitting a failed row can easily lead to data errors, and may even cause computing system malfunctions or crashes. Therefore, this embodiment effectively identifies and manages the physical regions containing failed memory cells at the memory control level. To achieve efficient management of bad sectors, this embodiment proposes a logical partitioning method for row blocks and DRAM physical addresses (Regions) based on the Rank and Bank levels defined by the JEDEC standard. A Block is a logical sub-region formed by further dividing a Row within a single Bank.

[0058] Specifically, all rows within a Bank are divided into N row blocks based on the high-order bits of their addresses, where N is a power of 2. Each row block contains 1 / N of the rows in the Bank. The row block number is determined by the high-order bits of the row address, thus creating a finer management granularity at the Bank level than for the entire Bank but coarser than for a single row.

[0059] Based on this, to achieve bad sector masking and address remapping, this embodiment uniquely identifies a DRAM physical address using a set of physical structure identifiers. Each DRAM physical address corresponds to a contiguous physical address space within the DRAM, the size of which depends on the specific structural parameters of the DRAM and the row / block partitioning method. The entire DRAM physical address space can be divided into a number of DRAM physical addresses. Each set of physical structure identifiers includes at least a Rank identifier field, a Bank identifier field, and a Block identifier field, uniquely identified by a (Rank_ID, Bank_ID, Block_ID) triple. For example, for a DRAM containing multiple Ranks, each Rank containing multiple Banks, after equally dividing the Rows of each Bank, the entire DRAM space can be represented as a set of multiple DRAM physical addresses, each with a unique physical structure identifier. Based on this DRAM physical address, DRAMs of different generations and structures (including DDR3, DDR4, DDR5, and LPDDR series) can all be described using (Rank, Bank, Block) triples, thereby achieving dynamic adaptation to different DRAM structure types.

[0060] Furthermore, in this embodiment, the bad sector data is bad sector information described at the DRAM physical address granularity. Specifically, the bad sector data includes multiple sets of physical structure identifiers, each set of physical structure identifiers corresponding to a DRAM physical address in the DRAM. When a DRAM physical address contains at least one failed memory row, that DRAM physical address is determined as an unusable DRAM physical address region containing failed memory cells; DRAM physical addresses that do not contain failed memory rows are determined as usable DRAM physical address regions.

[0061] By using DRAM physical addresses as the basic unit for bad sector management, this embodiment can completely mask the DRAM physical addresses containing failed memory cells without changing the DRAM physical organization and based on the JEDEC standard. At the same time, it avoids the excessively high mapping complexity caused by using single rows or columns as the granularity.

[0062] In some embodiments, the bad zone data acquisition unit includes an interface access subunit, a bad zone parsing subunit, and a bad zone caching subunit.

[0063] The interface access subunit is used during the memory initialization phase to access the non-volatile memory cell associated with the DRAM through a communication interface to read the bad sector data.

[0064] The interface access subunit can establish a connection with the non-volatile memory unit through a standard or dedicated communication interface. For example, the communication interface can be I²C, SPI, or other interface forms suitable for on-chip or package-level communication. Thus, during the memory initialization phase, the interface access subunit can sequentially or in batches read bad sector data from the non-volatile memory unit according to a predetermined access timing and protocol.

[0065] The bad sector parsing subunit is used to parse the bad sector data to obtain physical structure identifiers that characterize the hierarchical physical structure of the DRAM.

[0066] Among them, after receiving the bad sector data read by the interface access subunit, the bad sector parsing subunit performs format parsing, field splitting and semantic decoding on the bad sector data, converting the bad sector data into a physical structure identifier that can reflect the hierarchical physical structure of DRAM, so that the bad sector data can be transformed from the original storage format into a structured identifier form suitable for the internal logic processing of the memory controller.

[0067] The bad sector cache subunit, connected to the mapping table acquisition unit, is used to store the physical structure identifier inside the memory controller for use by the mapping table acquisition unit.

[0068] The bad sector cache subunit is used to temporarily or persistently store the physical structure identifier in the memory controller's internal storage structure. This storage structure can be on-chip SRAM, register sets, FIFO buffers, or other storage structures suitable for high-speed access.

[0069] Simultaneously, the bad-side cache sub-unit can establish a data path with the mapping table acquisition unit, enabling the mapping table acquisition unit to access cached physical structure identifiers when constructing the mapping relationship between the system physical address region and the DRAM physical address. Therefore, during the mapping table construction phase, the number of repeated accesses to non-volatile memory units can be reduced, thereby reducing initialization latency and improving the startup efficiency of the computing system.

[0070] In some embodiments, the physical structure identifier includes multiple identifier fields for distinguishing different storage tiers, wherein each set of the identifier fields corresponds to an independently identifiable DRAM physical address in the DRAM.

[0071] The physical address space of DRAM is divided into multiple independently identifiable DRAM physical addresses, each corresponding to a fixed combination of physical hierarchy structures within the DRAM. A physical structure identifier is a data structure describing this combination relationship, containing multiple identifier fields that represent different memory level locations. Each combination of identifier field values ​​uniquely corresponds to a DRAM physical address, allowing the memory controller to independently identify, mark, and manage that DRAM physical address.

[0072] For example, in one implementation, the identifier field may include a Rank identifier field, a Bank identifier field, and a Block identifier field; in other implementations, depending on the DRAM standard, additional identifier fields such as Bank Group and sub-channel may be included.

[0073] In some embodiments, the mapping table acquisition unit includes an available area determination subunit, a consecutive number generation subunit, a reverse mapping generation subunit, and a mapping table storage subunit.

[0074] The available area determination subunit is used to determine and mark unusable DRAM physical address regions containing at least one failed memory cell based on the physical structure identifier of the bad area data, and to filter the unmarked available DRAM physical address regions from all DRAM physical address regions.

[0075] The available region determination subunit determines the DRAM physical addresses in the DRAM based on physical structure identifiers. When the physical structure identifier corresponding to a certain DRAM physical address indicates that the region contains at least one faulty memory cell (e.g., bad row, bad column, or bad block), the DRAM physical address is marked as an unavailable DRAM physical address region that cannot be accessed normally. Then, the available region determination subunit removes the portion of the DRAM physical address regions marked as unavailable from all DRAM physical address regions, retaining the unmarked available DRAM physical address regions. This allows skipping physical regions containing faulty memory cells during the address mapping stage.

[0076] Because some DRAM physical address regions are determined to be unusable and are masked, the remaining usable DRAM physical address regions may be discontinuous in terms of physical numbering or distribution. Directly accessing addresses based on physical numbers can easily lead to gaps in the system's physical address space. Therefore, a continuous numbering generation subunit can be used to renumber the usable DRAM physical address regions according to a preset order rule. The continuous numbering generation subunit is used to allocate the usable DRAM physical address regions as contiguous system physical address regions according to a preset order.

[0077] The order rule can be the original numbering order of physical addresses, the hierarchical order of physical structures, or a combination thereof. Through a continuous numbering mechanism, a logically continuous and physically reliable address space can be constructed without altering the actual physical structure of the DRAM.

[0078] The reverse mapping generation subunit generates the reverse mapping table based on the correspondence between the continuous system physical address regions and the available DRAM physical address regions.

[0079] The reverse mapping generation sub-unit generates the allocation results of the consecutively numbered sub-units, records the mapping relationship between each system physical address region and its actual corresponding available DRAM physical address region, and generates a hardware reverse mapping table based on the mapping relationship.

[0080] The mapping table storage subunit is used to embed the reverse mapping table into the on-chip storage unit inside the memory controller.

[0081] To ensure the real-time performance and reliability of the address translation process, the reverse mapping table needs to be accessed quickly. Therefore, the mapping table storage subunit can embed the reverse mapping table into the on-chip storage structure inside the memory controller, thereby uniformly constraining the address access range during system operation and ensuring that the processor and operating system access the system's physical address space that has been determined to be safe and usable.

[0082] The sequential numbering generation subunit includes a sorting processing subunit, a numbering generation subunit, and a system physical address space limitation subunit.

[0083] The sorting subunit is used to sort the available DRAM physical address regions according to the initial physical number order corresponding to all DRAM physical address regions, and obtain the sorting result.

[0084] As an example, each DRAM physical address in DRAM has a corresponding initial physical number when it is manufactured or defined by the computing system. This initial physical number is used to reflect the predetermined order of the DRAM physical address in the physical structure hierarchy or physical address organization.

[0085] It should be noted that the definition of the initial physical number is preferably in accordance with the address mapping rules actually used in the computing system, so that the numbering order of the DRAM physical addresses is consistent with the increasing direction of the system physical addresses.

[0086] For example, when the system physical address mapping rule adopts the Bank–Row–Column (BRC) order, initial physical numbers can be assigned to DRAM physical addresses in a manner where the Bank dimension changes fastest, followed by the Row dimension. This ensures that the DRAM physical address numbers change continuously as the system physical address increments. When the system physical address mapping rule adopts the Row–Bank–Column (RBC) order, initial physical numbers can be assigned in a manner where the Row dimension changes first, followed by the Bank dimension. These methods ensure that the order of the initial physical numbers conforms to the access order characteristics of the system physical address space.

[0087] For example, DRAM physical addresses can also be defined using the representation {rank, segment}. Specifically, all rows in each bank can be divided into several parts according to a preset number, with each part forming a row region, such as row region 0, row region 1, and so on up to row region n. Then, row regions with the same number in each bank are combined; for example, all row regions 0 in all banks form segment 0, all row regions 1 in all banks form segment 1, and so on, thus forming several segments in the entire DRAM. Therefore, the physical address space of DRAM can be identified by a combination of rank and segment, where each segment represents a set of DRAM physical addresses composed of corresponding row regions from multiple banks.

[0088] After completing the screening of available DRAM physical address regions, the sorting processing subunit performs unified sorting processing on the available DRAM physical address regions according to the order rules determined by the initial physical number, so that the subsequent logical number generation process is consistent with the original physical organization structure and system address mapping rules of DRAM, and avoids unordered mapping between system physical addresses and physical addresses.

[0089] The numbering generation subunit is used to perform logical numbering processing on the available DRAM physical address regions based on the sorting result, and skips the unavailable DRAM physical address regions during the numbering process, so that the system physical address region numbers allocated to each of the available DRAM physical address regions are logically continuous.

[0090] The numbering generation subunit sequentially performs logical number generation processing on the sorted DRAM physical addresses. During this numbering process, the subunit assigns system physical address region numbers to DRAM physical addresses that have been determined to be usable; for DRAM physical addresses marked as unusable DRAM physical address regions, they are skipped during the logical numbering process and no corresponding system physical address region number is assigned to them. This ensures that the system physical address region numbers assigned to each usable DRAM physical address region logically exhibit a continuous increasing relationship, preventing numbering breaks or gaps in the system physical address space due to the presence of invalid regions in the DRAM physical addresses.

[0091] The system physical address space limitation subunit is used to determine the upper limit of the processor's access to the system physical address space based on the maximum value of the system physical address region number.

[0092] The maximum value of the system physical address region number theoretically corresponds to the maximum storage capacity supported by the current computing system. However, in embodiments of the present invention, the maximum available value of the system physical address region number does not necessarily need to be equal to the maximum storage capacity, but can be determined according to the actual configuration requirements of the system. That is, when the storage capacity supported by the computing system is greater than the actual configured storage capacity, the maximum available value of the system physical address region number corresponds to the actual configured storage capacity, so that the system will not access the system physical address space beyond the actual configured capacity range during memory access.

[0093] In this case, the number of available DRAM physical address regions obtained by recalculating the DRAM physical address based on the bad block region information stored in the non-volatile memory cell should not be less than the maximum available value of the system physical address region number, so as to ensure that the system physical address regions can be mapped to available DRAM physical addresses within the actual configured capacity range, thereby ensuring that the system meets the predetermined capacity configuration requirements during normal operation.

[0094] In some embodiments, the address translation engine includes a configurable system physical address numberer, a reverse mapping query subunit, and an address reassembly subunit.

[0095] A configurable system physical address numberer is used to extract the address field from the system physical address issued by the processor in the memory access path to determine the system physical address region to which it belongs, based on a pre-configured address mapping strategy, so as to determine the corresponding system physical address region number.

[0096] The configurable system physical address region numbering subunit allows you to set the parsing method for each address field in the system physical address through configuration parameters, thereby extracting the address field used to determine the system physical address region to which the system physical address belongs. The address field can correspond to address region dimensions such as Rank, Bank, and Block in a logical sense, or it can be a combination or equivalent representation of the above dimensions.

[0097] Based on this, a configurable system physical address numberer can generate a corresponding system physical address region number according to the extracted address field. This system physical address region number is used to uniquely identify the system physical address region to which the current system physical address belongs, and is the core index information used to perform reverse mapping queries.

[0098] Therefore, the memory controller in this embodiment can adapt to different DRAM physical structure organization methods and address mapping strategies adopted by different SoCs, so that the division and generation of the system physical address region has good flexibility and scalability.

[0099] The reverse mapping query subunit uses the system physical address region number as an index to query the reverse mapping table to obtain the physical structure identifier corresponding to the available DRAM physical address region corresponding to the current system physical address region.

[0100] The address reassembly subunit is used to decode the physical structure identifier, reassemble the system physical address issued by the processor based on the decoded physical structure parameters, and generate a physical address for accessing the DRAM.

[0101] The address reassembly subunit is used to decode the physical structure identifier, reassemble the system physical address issued by the processor based on the decoded memory physical structure parameters, and generate a physical address for accessing the DRAM.

[0102] The address reconstruction subunit decodes the physical structure identifier to reconstruct the corresponding memory physical structure parameters. These parameters characterize the physical organization of the DRAM, including but not limited to memory hierarchy partitioning, address bit allocation rules, and the positional relationships of DRAM physical addresses. After decoding the physical structure parameters, the address reconstruction subunit reconstructs the original system physical address issued by the processor, recombining relevant address fields into a physical address conforming to DRAM physical addressing rules. Thus, the memory controller can transparently convert logically contiguous system physical address spaces into physical addresses valid for the DRAM physical structure, thereby automatically avoiding unusable DRAM physical address regions and ensuring the correctness and reliability of memory access.

[0103] Please see Figure 3 In a specific exemplary embodiment, the memory controller manages bad sectors in the DRAM connected to it and enables the processor to access the DRAM transparently and sequentially by constructing a reverse mapping table. This process mainly includes the construction of the reverse mapping table during the initialization phase and the address translation processing during the runtime phase.

[0104] During the computing system initialization phase, i.e., after the computing system is powered on or reset but before the operating system starts, such as during the bootloader or firmware execution phase, in one embodiment, the reverse mapping table construction process is completed before DRAM self-refresh and memory training operations to ensure that the storage areas used for training are all normally accessible areas, thereby avoiding training failure due to accessing faulty storage cells.

[0105] During the initialization phase, the memory controller acquires bad sector information associated with the DRAM. Specifically, the memory controller can access the non-volatile memory cell (e.g., in-package EEPROM) associated with the DRAM via an I²C interface or an SPI interface, and read a pre-stored bad sector index list. The bad sector index list contains multiple sets of physical structure identifiers, each set of physical structure identifiers representing a DRAM physical address in the DRAM, for example, represented in the form of a combination of (Rank, Bank, Block).

[0106] Subsequently, the memory controller determines the total number of divisible DRAM physical addresses based on the current DRAM type and capacity parameters. Specifically, it calculates the total number of DRAM physical addresses: Total Regions = Rank_Count × Bank_Count × Block_Count, based on the number of Ranks, the number of Banks in each Rank, and the number of Blocks in each Bank. Each of these DRAM physical addresses corresponds to a unique DRAM physical address P.

[0107] Based on this, the memory controller traverses all DRAM physical address regions and checks each DRAM physical address. When the physical structure identifier corresponding to a certain DRAM physical address appears in the bad sector information, the DRAM physical address is marked as a masked DRAM physical address; the remaining unmarked DRAM physical addresses are determined as usable DRAM physical address regions.

[0108] After bad sector marking is completed, the memory controller performs logical numbering on the available DRAM physical address regions. Specifically, all available DRAM physical address regions are arranged in ascending order of their original DRAM physical addresses, and, skipping those marked as masked DRAM physical addresses, each available DRAM physical address region is assigned a continuously increasing system physical address region number L. This forms a one-to-one correspondence between system physical address region numbers and DRAM physical addresses, where the system physical address region numbers are logically consecutive and do not include numbers corresponding to masked DRAM physical addresses.

[0109] In the absence of bad sectors, the system physical address region number corresponding to the maximum DRAM physical address is the same as its physical address number. However, in the presence of bad sectors, the maximum system physical address region number is less than the maximum DRAM physical address, with the difference equal to the number of masked DRAM physical addresses that are skipped. Based on this maximum system physical address region number and the capacity of a single region, the maximum range of system physical addresses that the processor can safely access can be determined. This information can be configured in the operating system or kernel to limit its access to DRAM, thereby avoiding access to unavailable DRAM physical addresses.

[0110] After completing the logical number allocation, the memory controller constructs a reverse mapping table. This reverse mapping table uses the system physical address region number L as an index to record the corresponding DRAM physical address P, i.e., ReverseMap[L] = P. Subsequently, the reverse mapping table is written into the on-chip storage unit inside the memory controller, such as a small-capacity SRAM or a one-time programmable memory unit, for use in address translation operations during runtime.

[0111] During runtime, when the processor initiates a read / write access request to DRAM via the system bus, the memory controller performs address translation within the address resolution pipeline of its memory access path. This process is typically completed within one to two clock cycles and is completely transparent to the processor.

[0112] Specifically, the system physical address issued by the processor is sent to the address resolution unit of the memory controller. The address resolution unit includes a configurable system physical address region number generation subunit. This subunit extracts the address field from the system physical address to determine its corresponding system physical address region number L, based on a pre-configured address mapping strategy. The address mapping strategy can be implemented using bit-field direct mapping, lookup table, or microcode control to adapt to different address mapping strategies.

[0113] Then, the memory controller uses the system physical address region number L as an index to look up the reverse mapping table and obtain the corresponding DRAM physical address P. The memory controller further decodes this DRAM physical address to obtain the corresponding physical structure identifier, including physical structure parameters such as Rank, Bank, and Block.

[0114] After obtaining the physical structure identifier, the memory controller reassembles the system physical address issued by the processor. Specifically, the row address (lower bits), column address, and byte offset fields in the system physical address remain unchanged, while the higher bits representing the physical location are replaced with the decoded physical structure parameters, thereby generating a physical address conforming to the JEDEC specification. Based on this physical address, the memory controller sends the corresponding memory access command to the DRAM physical layer and provides the returned data to the processor.

[0115] In some embodiments, to reduce the performance impact of the address translation process on the memory access path, the address translation engine may further include a parallel lookup table unit. The parallel lookup table unit is used to perform parallel queries on the reverse mapping table to obtain the physical structure identifier corresponding to the system physical address region number.

[0116] The parallel lookup table unit can perform parallel lookup operations on the reverse mapping table. Upon receiving the system physical address region number, it can simultaneously or nearly simultaneously access multiple mapping entries, thereby quickly obtaining the physical structure identifier corresponding to the system physical address region number. By adopting a parallel lookup method, the access latency of the reverse mapping table can be significantly reduced, allowing the address translation process to adapt to the processor's high-concurrency memory access requirements and improving the overall memory access throughput.

[0117] In some embodiments, because the DRAM adopts a hierarchical physical structure organization, the physical structure identifiers corresponding to different system physical address regions may involve different physical hierarchy information. To adapt to this hierarchical mapping relationship, the address translation engine sets up multi-level independent table access channels. These multi-level independent table access channels are used for parallel access to the reverse mapping tables at different levels.

[0118] The multi-level independent table access channel is used to support independent access to mapping information at different levels in the reverse mapping table, decoupling the mapping query process at each level and avoiding the serialization limitations caused by a single access channel. By setting up a multi-level independent table access channel, the physical structure identifiers at different levels can be obtained in parallel on the hardware, thereby further improving address translation efficiency and enhancing the adaptability to different DRAM physical structure organization forms.

[0119] In some embodiments, the address translation engine may further include an address reassembly pipeline for replacing a predetermined high bit of the system physical address based on the physical structure identifier to generate a corresponding DRAM physical address.

[0120] The address reassembly pipeline is used to streamline the process of converting system physical addresses to physical addresses after completing the reverse mapping lookup. In this pipeline, based on the physical structure identifier output by the parallel lookup table unit, a predetermined high-order bit in the system physical address is replaced to generate a physical address that conforms to the DRAM physical addressing rules.

[0121] The predetermined high-order bits can be used to characterize the system physical address region to which the system physical address belongs, while the low-order address information can directly inherit the corresponding field in the system physical address to maintain the address offset relationship unchanged. By replacing the high-order address field, the mapping from the system physical address region to the available DRAM physical address region can be achieved without changing the access granularity and address continuity.

[0122] Using a pipelined approach to perform address reorganization operations is beneficial for achieving continuous address translation in high-frequency access scenarios, improving address generation efficiency, and avoiding adverse effects on memory access timing.

[0123] Through parallel lookup table units, multi-level independent table access channels, and address reassembly pipelines, the address translation engine ensures the correctness of the system physical address to physical address mapping while implementing a high-concurrency, low-latency hardware-level address translation mechanism. This allows the memory controller to present a continuous and stable system physical address space to the processor even when invalid DRAM physical addresses are masked.

[0124] In some embodiments, the memory controller further includes a post-processing unit for receiving a physical address for accessing the DRAM output by the address translation engine, and detecting whether the physical address for accessing the DRAM falls into the physical address region marked as unavailable DRAM.

[0125] The address translation engine translates the system physical address issued by the processor into the corresponding physical address using a reverse mapping table. To improve the security and reliability of memory access, the memory controller also includes a post-processing unit.

[0126] The post-processing unit is located between the address translation engine and the DRAM. It is used to re-detect the physical address output by the address translation engine to determine whether the physical address falls into the DRAM physical address area that has been marked as unusable. This can prevent illegal access caused by abnormal states, inconsistent mapping table updates, or extreme access conditions at the hardware level.

[0127] In some embodiments, the post-processing unit includes a bad area access detection subunit, a silent error correction subunit, and a malicious error reporting subunit.

[0128] A bad sector access detection subunit is used to detect accesses to the unavailable DRAM physical address region; The bad sector access detection subunit compares the currently accessed physical address with a marked unavailable DRAM physical address region to detect any access to the unavailable DRAM physical address region. The unavailable DRAM physical address region is a DRAM physical address that has been identified and marked during the mapping construction phase and contains at least one failed memory cell. This allows for real-time identification of access requests to failed or unavailable DRAM physical address regions, providing triggering conditions for subsequent error correction or anomaly handling.

[0129] A silent error correction subunit is used to return an error code or redirect the access to a redundant region when an access to the unavailable DRAM physical address region is detected. When the bad sector access detection subunit detects access to an unavailable DRAM physical address region, the silent error correction subunit processes the access request without interrupting the computing system.

[0130] In one implementation, the silent error correction subunit can return a predefined error code to the processor to indicate that the current access failed to complete. In another implementation, the silent error correction subunit can redirect the access request to a pre-configured redundant area, thereby allowing the access operation to continue without exposing underlying physical defects. This allows for the silent handling of some abnormal accesses at the hardware level, reducing the risk of frequent exceptions triggered by occasional or tolerable errors in the computing system and improving system stability.

[0131] For abnormal access scenarios that are difficult to handle through silent correction, such as continuous access to unavailable DRAM physical address regions or abnormal access patterns, the post-processing unit further includes a malicious error reporting subunit, which is used to report the status to the computing system through an abnormal signal when an abnormal access is detected.

[0132] The malicious error reporting subunit is used to send an abnormal signal to the system when the above-mentioned abnormal access is detected, so as to trigger the processor or operating system to execute the corresponding abnormal handling process. By distinguishing between errors that can be handled silently and serious errors that need to be reported, the system can avoid unnecessary performance loss while ensuring reliability, and realize a flexible abnormal management strategy.

[0133] This embodiment presents a hardware-based memory address remapping system and method that can be integrated into various computing systems and is suitable for applications with high requirements for memory reliability, memory utilization, or cost control. It is particularly suitable for system architectures equipped with novel dynamic random access memory (DRAM) that has built-in non-volatile memory capable of storing bad sector data. The memory controller reads and parses bad sector data during the computing system initialization phase, reconstructing a continuously available system physical address region at the hardware level, thereby transparently shielding the upper-level processor and operating system from bad sector access.

[0134] In one embodiment, this embodiment can be applied to the SoC architecture of mobile terminals such as smartphones and tablets. Such computing systems typically integrate an application processor, graphics processing unit, neural network processing unit, and memory controller within the SoC, and connect to low-power DRAM (such as LPDDR4 and LPDDR5) via package-on-package (PoP) or board-level routing. During the boot phase of the computing system, the memory controller can access non-volatile memory cells within the DRAM chip or package via a low-speed communication interface, read bad sector data, and construct a reverse mapping table. After the operating system boots, the memory space perceived by the processor is a contiguous and usable system physical address region. This approach improves the stability of the memory computing system and reduces the requirements for memory yield without altering the operating system's memory management mechanism.

[0135] In another embodiment, this embodiment can be applied to server and data center computing platforms. These computing systems typically connect multiple DDR4 or DDR5 memory modules through multiple memory channels, placing high demands on memory capacity, continuity, and reliability. During the computing system firmware initialization phase (such as the BIOS or UEFI phase), the memory controller can read bad sector data from the DRAM chips corresponding to different memory modules or different ranks, and construct corresponding reverse mapping relationships based on their respective physical structure identifiers. This enables unified system physical address space reorganization in multi-channel, multi-rank scenarios. This method avoids the entire memory module becoming unusable due to local bad blocks, improving memory resource utilization.

[0136] In a further embodiment, this embodiment can also be applied to embedded industrial control systems and automotive electronic systems. These computing systems typically employ industrial-grade or automotive-grade processors, which have stringent requirements for long-term operational stability and fault tolerance. During the power-on self-test or initialization phase of the computing system, the memory controller completes the reading and mapping of bad sector data, ensuring that subsequent real-time operating systems or automotive operating systems only access confirmed available DRAM physical address regions, thereby improving the reliability of the computing system under long-term operation or complex environmental conditions.

[0137] Furthermore, this embodiment is also applicable to Internet of Things (AIoT) and edge computing devices. These devices are typically highly sensitive to power consumption and cost, operate in complex environments, and are more prone to partial memory failures. By integrating a bad sector data acquisition and mapping mechanism into the memory controller and storing the reverse mapping table in an on-chip memory unit, hardware-level shielding of bad sectors can be achieved without increasing the complexity of the computing system.

[0138] In a further embodiment, this embodiment can also be applied to heterogeneous computing systems or computing systems with chiplet architecture. In such computing systems, computing chips and storage chips are directly interconnected through advanced packaging technology. The memory controller can obtain bad sector data of the storage chip through a dedicated low-speed channel and complete address mapping processing on-chip, thereby achieving fine-grained bad sector management in high-bandwidth, low-latency scenarios.

[0139] In summary, this embodiment is not limited to a specific processor architecture or a specific DRAM type. It includes, but is not limited to, DRAM chips that can provide bad sector data associated with their physical structure; and memory controllers that possess corresponding interfaces and address mapping capabilities. Therefore, this embodiment has good platform versatility and scalability, and is suitable for memory management enhancement scenarios in various computing systems.

[0140] In some embodiments, the execution is performed by software running during the computer system startup or memory configuration phase, such as by the bootloader, firmware, or early initialization program. During this phase, the operating system has not yet started, and memory is not yet used as general-purpose running memory; therefore, the configuration parameters of the memory controller can be set once by software.

[0141] Please see Figure 4 , Figure 4 This is a flowchart illustrating an embodiment of the memory address processing method of this application. It should be noted that if substantially the same result is achieved, the method of this application does not necessarily differ. Figure 4 The illustrated process sequence is limited. For example... Figure 4 As shown, the memory address processing method includes: S401, during the computing system startup phase or memory configuration phase, bad sector data of the DRAM is read from the non-volatile memory cell associated with the DRAM, wherein the bad sector data is used to indicate a DRAM physical address region containing at least one failed memory cell.

[0142] As an example, after the computing system powers on or resets, the software first reads the bad sector data associated with the DRAM. This bad sector data can be stored in non-volatile memory cells associated with the DRAM, such as the protection memory area of ​​EEPROM, eMMC, or other non-volatile configuration memory spaces. This bad sector data indicates the physical address of the DRAM containing at least one failed memory cell, and is typically given in the form of a physical structure identifier describing the location of the DRAM physical address within the DRAM's physical organization.

[0143] S402, based on the physical structure identifier of the bad sector data, construct a reverse mapping table between the system physical address region and the available DRAM physical address region.

[0144] As an example, based on the read bad sector data, the software analyzes and processes all DRAM physical address regions, marking DRAM physical addresses containing failed memory cells as unusable. Then, based on the remaining usable DRAM physical address regions, it constructs a reverse mapping table between system physical address regions and usable DRAM physical address regions according to preset rules. This reverse mapping table describes the correspondence between each system physical address region in the system physical address space and the actual usable DRAM physical addresses, ensuring the continuity of the system physical address space from the perspectives of the software and the processor.

[0145] In some embodiments, S402 may include: determining and marking unusable DRAM physical address regions containing at least one failed memory cell based on the physical structure identifier of the bad sector data, and filtering unmarked usable DRAM physical address regions from all DRAM physical address regions; allocating the usable DRAM physical address regions as consecutive system physical address regions in a preset order; and generating the reverse mapping table according to the correspondence between the consecutive system physical address regions and the usable DRAM physical address regions.

[0146] S403, the reverse mapping table is written into the memory controller so that during memory access, the memory controller converts the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table, and generates a physical address for accessing the DRAM.

[0147] As an example, the software writes the reverse mapping table into the memory controller's internal storage resources, such as on-chip registers or on-chip memory cells. After writing, the memory controller can directly use the reverse mapping table during subsequent memory accesses to translate the system physical address issued by the processor at the hardware level: that is, based on the system physical address region to which the system physical address belongs, it queries the corresponding available DRAM physical address region and generates a physical address for accessing the DRAM. Through the above hardware-software collaborative approach, a memory bad sector masking mechanism is implemented, where the software completes the mapping relationship construction in one go, and the hardware efficiently completes the address translation at runtime.

[0148] This embodiment obtains a reverse mapping table between the system physical address region and the available DRAM physical address region based on bad sector data of DRAM. During operation, the memory controller dynamically remaps the system physical address issued by the processor to the DRAM physical address without failed cells according to the reverse mapping table, and generates corresponding control signals for accessing DRAM. In this way, without changing the processor's memory access mode, the DRAM physical region containing failed memory cells is shielded, providing a continuous and complete system physical address space to the upper layer, improving the effective utilization of DRAM and the operational stability of the computing system, and reducing the risk of the entire memory becoming unavailable due to local memory failure.

[0149] Please see Figure 5 , Figure 5 This is an exemplary structural block diagram of an electronic device using the memory address processing method of this application. For example... Figure 5 As shown, the electronic device 500 of this application may include a processor 501 and a memory 502, wherein the processor 501 and the memory 502 communicate via a bus. The memory 502 stores program instructions for memory address processing. When the program instructions are executed by the processor 501, the processor performs the aforementioned method steps to implement a memory address processing method in the above embodiments.

[0150] Please see Figure 6 , Figure 6 This is an exemplary structural block diagram of a computer-readable storage medium for the memory address processing method of this application. For example... Figure 6 As shown, the computer-readable storage medium 600 stores a computer program 601. When the computer program 601 is run by the processor on the computer, it causes the computer to perform the above-described related method steps to implement a memory address processing method in the above embodiments.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed methods, electronic devices, and storage media can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0152] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0153] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0154] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the memory address processing method described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0155] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A memory controller, applied in a computing system, the computing system comprising a memory controller, a dynamic random access memory (DRAM), and a processor, characterized in that, The memory controller includes: A mapping table acquisition unit is used to acquire a reverse mapping table between the system physical address region and the available DRAM physical address region based on the bad sector data of the DRAM; wherein the bad sector data is used to indicate the DRAM physical address region containing at least one failed memory cell; The address translation engine is used to convert the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table in the memory access path, and generate a physical address for accessing the DRAM.

2. The memory controller according to claim 1, characterized in that, The mapping table acquisition unit is configured as follows: During the startup phase or memory configuration phase of the computing system, the reverse mapping table written by software is received and stored inside the memory controller for use by the address translation engine.

3. The memory controller according to claim 1, characterized in that, The memory controller also includes a bad sector data acquisition unit and a communication interface; The bad sector data acquisition unit is used to read bad sector data from the non-volatile memory cell associated with the DRAM through the communication interface during the memory initialization phase. The bad sector data includes multiple sets of physical structure identifiers, and each set of physical structure identifiers is used to characterize a DRAM physical address region in the DRAM. The mapping table acquisition unit is used to construct a reverse mapping table between the system physical address region and the available DRAM physical address region based on the physical structure identifier of the bad sector data of the DRAM.

4. The memory controller according to claim 3, characterized in that, The mapping table acquisition unit includes: The available area determination subunit is used to determine and mark unusable DRAM physical address regions containing at least one failed memory cell based on the physical structure identifier of the bad area data, and to filter the unmarked available DRAM physical address regions from all DRAM physical address regions. A sequential numbering subunit is used to allocate the available DRAM physical address region as a continuous system physical address region according to a preset order; A reverse mapping generation subunit is used to generate the reverse mapping table based on the correspondence between the continuous system physical address regions and the available DRAM physical address regions; A mapping table storage subunit is used to embed the reverse mapping table inside the memory controller.

5. The memory controller according to claim 4, characterized in that, The sequentially numbered sub-units include: The sorting subunit is used to sort the available DRAM physical address regions according to the initial physical number order corresponding to all DRAM physical address regions, and obtain the sorting result; The numbering generation subunit is used to perform logical numbering processing on the available DRAM physical address regions based on the sorting result, and skips unavailable DRAM physical address regions during the numbering process, so that the system physical address region numbers allocated to each available DRAM physical address region are logically continuous. The system physical address space limitation subunit is used to determine the upper limit of the processor's access to the system physical address space based on the maximum value of the system physical address region number.

6. The memory controller according to claim 3, characterized in that, The address translation engine includes: A configurable system physical address numberer is used to extract the address field from the system physical address issued by the processor in the memory access path according to a pre-configured address mapping strategy, so as to determine the corresponding system physical address region number. The reverse mapping query subunit uses the system physical address region number as an index to query the reverse mapping table and obtain the corresponding physical structure identifier. The address reassembly subunit is used to decode the physical structure identifier, reassemble the system physical address issued by the processor based on the decoded physical structure parameters, and generate a physical address for accessing the DRAM.

7. The memory controller according to claim 6, characterized in that, The address translation engine also includes: A parallel lookup table unit is used to perform parallel queries on the reverse mapping table to obtain the physical structure identifier corresponding to the physical address region number of the system. Multi-level independent table access channels are used for parallel access to the reverse mapping tables at different levels; An address reassembly pipeline is used to replace a predetermined high bit of the system physical address based on the physical structure identifier to generate a corresponding DRAM physical address.

8. The memory controller according to claim 1, characterized in that, The memory controller is connected to the DRAM through multiple memory channels; The mapping table acquisition unit is used to acquire the reverse mapping table corresponding to each memory channel respectively, wherein each reverse mapping table is constructed based on the bad zone data of the corresponding memory channel; The address translation engine is used to call the reverse mapping table corresponding to the target memory channel to perform address translation when accessing the target memory channel, so that the bad sector management of different memory channels is independent of each other.

9. The memory controller according to claim 1, characterized in that, The memory controller further includes a post-processing unit for receiving the physical address for accessing the DRAM output by the address translation engine, and detecting whether the physical address for accessing the DRAM falls into a DRAM physical address region marked as unavailable. The post-processing unit includes: The bad sector access detection subunit is used to detect accesses to the unavailable DRAM physical address region; A silent error correction subunit is used to return an error code or redirect the access to a redundant region when an access to the unavailable DRAM physical address region is detected. The malicious error reporting subunit is used to report the status to the computing system via an error signal when abnormal access is detected.

10. A memory address processing method, applied to a computing system, the computing system comprising a memory controller, a dynamic random access memory (DRAM), and a processor, characterized in that, The memory address processing method includes the following steps: During the computing system startup phase or memory configuration phase, bad sector data of the DRAM is read from the non-volatile memory cells associated with the DRAM, wherein the bad sector data is used to indicate a DRAM physical address region containing at least one failed memory cell; Based on the physical structure identifier of the bad sector data, a reverse mapping table between the system physical address region and the available DRAM physical address region is constructed. The reverse mapping table is written into the memory controller so that during memory access, the memory controller can convert the system physical address region to which the system physical address issued by the processor belongs to the corresponding available DRAM physical address region according to the reverse mapping table, and generate a physical address for accessing the DRAM.

11. The memory address processing method according to claim 10, characterized in that, The physical structure identifier based on the bad sector data of the DRAM is used to construct a reverse mapping table between the system physical address region and the available DRAM physical address region, including: Based on the physical structure identifier of the bad sector data, unusable DRAM physical address regions containing at least one failed memory cell are identified and marked, and unmarked usable DRAM physical address regions are filtered from all DRAM physical address regions. The available DRAM physical address regions are allocated as contiguous system physical address regions according to a preset order; The reverse mapping table is generated based on the correspondence between the continuous system physical address regions and the available DRAM physical address regions.

12. A computing system, characterized in that, The computing system includes a processor, at least one dynamic random access memory (DRAM), and a memory controller as described in any one of claims 1-9; wherein the memory controller is connected to the processor and the DRAM.

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