Tensor data transformation method, tensor processing unit, processor, system on chip, and computing device

Abstract

Provided in the embodiments of the present disclosure are a tensor data transformation method, a tensor processing unit, a processor, a system on a chip, and a computing device. The tensor processing unit comprises: a register array unit, which comprises at least a source address register, a destination address register, and a source tensor parameter register; an instruction decoding unit, which parses an acquired transformation operation instruction, so as to obtain a transformation operation type indicated by an operation type field and obtain respective register serial numbers of the source address register, the destination address register, and the source tensor parameter register; and an instruction execution unit, which accesses the source address register, the destination address register, and the source tensor parameter register on the basis of their respective register serial numbers, reads a source memory address field, a destination memory address field, and a source tensor parameter, reads a source tensor on the basis of the source memory address field, performs, on the source tensor, a transformation operation indicated by the transformation operation type, and writes, on the basis of the source tensor parameter, a destination tensor obtained after the transformation operation into the destination memory address field.

Description

Tensor data transformation methods, tensor processing units, processors, on-chip systems, and computing devices.

[0001] This disclosure claims priority to Chinese Patent Application No. 202411425681.6, filed with the China Patent Office on October 12, 2024, entitled "Tensor Data Transformation Method, Tensor Processing Unit, Processor, System-on-Chip, and Computing Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of computer technology, and more particularly to a tensor data transformation method, a tensor processing unit, a processor, a system-on-a-chip, and a computing device. Background Technology

[0003] In computing devices used for applications such as AI (Artificial Intelligence) / HPC (High Performance Computing), tensor transformation operations typically involve mathematical or logical manipulation of multidimensional arrays to achieve specific data processing goals. Specifically, tensor transformation operations include, but are not limited to, transpose, scale, rotate, slice, concatenate, flatten, pad, and convolution. For example, in deep learning, convolutional neural networks (CNNs) and other complex models often require tensor transformation operations such as transpose, scale, and rotate on the input data to enhance the model's performance and generalization ability.

[0004] Tensor transformation operations are common computational tasks in machine learning and data science, which can significantly improve the efficiency of data processing and model training based on neural network models. Therefore, in tensor processing units such as general-purpose computing on graphics processing units (GPGPUs), the transformation operation instructions of tensor transformation operations are beneficial to improving the computational efficiency of tensor processing units. For example, the parallel architecture of GPGPUs can reduce the number of clock cycles per instruction to accelerate the computation process.

[0005] However, current tensor processing units use transformation operation instructions to perform tensor data calculations, resulting in low efficiency of tensor transformation operations and room for improvement in computational efficiency. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a tensor data transformation method, a tensor processing unit, a processor, a system-on-a-chip, and a computing device to solve the above problems.

[0007] According to a first aspect of the present disclosure, a tensor processing unit is provided, comprising: a register array unit, including at least a source address register, a destination address register, and a source tensor parameter register; an instruction decoding unit, which parses an acquired transformation operation instruction to obtain transformation operation information indicated by an operation type field, and obtains register numbers for the source address register, the destination address register, and the source tensor parameter register respectively; and an instruction execution unit, which accesses the source address register, the destination address register, and the source tensor parameter register according to each register number, reads a source memory address segment, a destination memory address segment, and source tensor parameters, reads a source tensor according to the source memory address segment, performs a transformation operation indicated by the transformation operation information on the source tensor, and writes the transformed destination tensor to the destination memory address segment according to the source tensor parameters.

[0008] According to a second aspect of the present disclosure, a tensor transformation method is provided, comprising: parsing an acquired transformation operation instruction to obtain transformation operation information indicated by an operation type field, and obtaining register numbers for a source address register, a destination address register, and a source tensor parameter register, respectively; accessing the source address register, the destination address register, and the source tensor parameter register according to each register number, and reading a source memory address segment, a destination memory address segment, and source tensor parameters; reading a source tensor according to the source memory address segment, performing the transformation operation indicated by the transformation operation information on the source tensor, and writing the transformed destination tensor into the destination memory address segment according to the source tensor parameters.

[0009] According to a third aspect of the present disclosure, a processor is provided, the processor including a plurality of tensor processing units, wherein each tensor processing unit is a tensor processing unit according to the first aspect.

[0010] According to a fourth aspect of the present disclosure, a system-on-a-chip is provided, the system-on-a-chip including a processor as described in the third aspect and a memory for storing the source tensor and the destination tensor, as well as transformation operation instructions.

[0011] According to a fifth aspect of the present disclosure, a computing device is provided, the computing device including a processor board, on which a system-on-a-chip according to the fourth aspect is disposed.

[0012] According to a sixth aspect of the present disclosure, a computer-readable storage medium is provided that stores a computer program / instructions that, when executed by a processor, implement the tensor processing unit described above.

[0013] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the tensor processing unit described above.

[0014] In the scheme of this embodiment, the instruction decoding unit can parse each field of the transformation operation instruction. Each field of the transformation operation instruction includes an operation type field and register numbers for the source address register, destination address register, and source tensor parameter register. The instruction execution unit can access the corresponding register according to the register number and obtain instruction execution parameters such as the source memory address segment, destination memory address segment, and source tensor parameters. Based on the instruction execution parameters, the transformed destination tensor is written to the destination memory address segment. Since the transformation operation instruction includes register numbers for the source address register, destination address register, and source tensor parameter register, it can be deconstructed with these registers, improving the processing efficiency of the instruction decoding unit. This, in turn, forms a pipeline for tensor transformation operations with the instruction execution unit, improving tensor transformation efficiency and consequently, computational efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 is a schematic structural diagram of a tensor processing unit according to some embodiments of the present disclosure;

[0017] Figure 2 is a schematic structural diagram of the tensor data transformation process in some examples of the embodiment of Figure 1;

[0018] Figures 3A-3C are schematic diagrams of the software configuration of exemplary registers in the register array unit of the embodiment of Figure 1;

[0019] Figure 4A is a schematic diagram of register operation instructions for the embodiment of Figure 1;

[0020] Figure 4B is a schematic diagram of the transformation operation instructions of the embodiment in Figure 1;

[0021] Figures 5A-5D are schematic diagrams of tensor transformation operations for some examples of the embodiment in Figure 1;

[0022] Figures 6A and 6B are schematic diagrams of the Row2Tile operation process of the embodiment in Figure 1;

[0023] Figures 7A and 7B are schematic diagrams of the Tile2Row operation process of the embodiment in Figure 1;

[0024] Figure 8 is a flowchart of the steps of a tensor data transformation method according to some other embodiments of the present disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in the embodiments of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art should fall within the protection scope of this disclosure.

[0026] The specific implementation of the embodiments of this disclosure will be further described below with reference to the accompanying drawings.

[0027] Generally, tensor transformation operations performed by computing devices include, but are not limited to, transpose, scale, rotate, slice, concatenate, flatten, fill, and convolution. For example, in deep learning, convolutional neural networks (CNNs) and other complex models often require tensor transformation operations such as transpose, scale, and rotate on the input data to enhance the model's performance and generalization ability. For instance, the tensor transpose operation is used to swap the dimensions of a tensor, such as interchanged rows and columns of a matrix. The tensor concatenation operation combines multiple partitioned tensors into a larger tensor; the tensor partitioning operation (Row2Tile) splits a tensor into multiple tensor partitions according to a preset size. The tensor flattening operation (Im2col) converts a multidimensional tensor into a one-dimensional tensor. The tensor filling operation (Tile2Row) adds specific values ​​to the boundary positions of a tensor.

[0028] Figure 1 illustrates a tensor processing unit according to some embodiments of the present disclosure. The tensor processing unit 100 may be a processing core of a processor such as a general-purpose computing on graphics processing units (GPGPU); that is, multiple tensor processing units may constitute a processor such as a GPGPU. Further, the processor accesses memory storing tensor data (e.g., source tensors and destination tensors) to perform tensor data operations, including tensor data transformations. In some examples, the processor and memory may constitute a system-on-a-chip, configured in a processor board.

[0029] Specifically, in the tensor processing unit 100, tensor data transformation operation instructions can be processed in a pipelined manner at multiple stages. These stages are typically pipelined within the tensor processing unit to improve the processing efficiency and parallelism of the transformation operation instructions. Specifically, the tensor processing unit 100 in Figure 1 includes: a register array unit 110, an instruction decoding unit 120, and an instruction execution unit 130.

[0030] Specifically, the register array unit 110 includes at least a source address register, a destination address register, and a source tensor parameter register.

[0031] In addition, the tensor processing unit 100 may also include an instruction fetching unit 140. The instruction fetching unit 140 fetches a transformation operation instruction, which includes at least the register numbers of the operation type field, the source address register, the destination address register, and the source tensor parameter register. This helps to reduce the instruction length of the transformation operation instruction and improves the transmission efficiency of the transformation operation instruction.

[0032] After the tensor transformation operation program is compiled, corresponding register operation instructions and transformation operation instructions are obtained and stored in an instruction memory such as memory. The tensor processing unit 100 retrieves the register operation instructions from the instruction memory such as memory and configures each register according to configuration parameters, for example, setting the configuration parameters of each register. Similarly, the tensor processing unit 100 retrieves transformation operation instructions from the instruction memory such as memory. In a pipelined architecture, this may involve fetching transformation operation instructions from memory to a cache, and then fetching transformation operation instructions from the cache, to reduce the latency of directly reading transformation operation instructions from memory.

[0033] Furthermore, the instruction decoding unit 120 parses the acquired tensor transformation instruction, obtains the transformation operation information indicated by the operation type field, and obtains the register numbers of the source address register, destination address register, and source tensor parameter register. For example, after obtaining the transformation operation instruction, the decoder parses the instruction to determine the required operation type and operands. For tensor transformation operations, the decoder will identify specific operations, such as tensor copying, tensor transpose, tensor padding, tensor flattening, tensor partitioning, and tensor concatenation. As another example, the register numbers of the source address register, destination address register, and source tensor parameter register can be their respective index fields.

[0034] In addition, the instruction execution unit 130 accesses the source address register, destination address register, and source tensor parameter register according to each register number, reads the source memory address segment, destination memory address segment, and source tensor parameters, reads the source tensor according to the source memory address segment, performs the transformation operation indicated by the transformation operation information on the source tensor, and writes the transformed destination tensor to the destination memory address segment according to the source tensor parameters.

[0035] For example, during the instruction execution phase, the source tensor can be moved as a whole to obtain the destination tensor, and / or element-wise computations can be performed on the source tensor to obtain the destination tensor. Element-wise computations are used to perform arithmetic operations such as matrix multiplication, matrix addition, and matrix multiplication-accumulation based on floating-point or integers. In some examples, in tensor processing units such as GPGPUs, the instruction execution unit can be designed as a parallel processing unit capable of processing multiple data items simultaneously.

[0036] In the scheme of this embodiment, the instruction decoding unit can parse each field of the transformation operation instruction. Each field of the transformation operation instruction includes an operation type field and register numbers for the source address register, destination address register, and source tensor parameter register. The instruction execution unit can access the corresponding register according to the register number and obtain instruction execution parameters such as the source memory address segment, destination memory address segment, and source tensor parameters. Based on the instruction execution parameters, the transformed destination tensor is written to the destination memory address segment. Since the transformation operation instruction includes register numbers for the source address register, destination address register, and source tensor parameter register, it can be deconstructed with these registers, improving the processing efficiency of the instruction decoding unit. This, in turn, forms a pipeline for tensor transformation operations with the instruction execution unit, improving tensor transformation efficiency and consequently, computational efficiency.

[0037] In some embodiments, as shown in FIG2, the data processing system in which the tensor processing unit 100 is located can be a system-on-a-chip (SoC), which includes an instruction memory 150 and a data memory 160. The instruction memory 150 can be the memory of the instruction fetch unit 140 or a cache for transformation operation instructions. For example, the instruction fetch unit 140 sends an instruction fetch command to the instruction memory 150 and receives the returned transformation operation instruction. Furthermore, the data memory 160 can be the memory accessed by the instruction execution unit 130 or a cache for source or destination tensors.

[0038] Furthermore, the instruction execution unit 130 accesses the register array unit 110 through the register access interface 10 to obtain the source memory address and the destination memory address, etc.

[0039] The instruction execution unit 130 also accesses the data memory 160 through the data access interface 20, reads the source tensor as the operand of the transformation operation instruction, and writes the destination tensor back to the data memory 160.

[0040] In addition, the data processing system includes a scheduler, which performs data forwarding, directly passing data generated during the execution phase to the next relevant instruction in the pipeline. Furthermore, the scheduler manages the flow of transformation operation instructions throughout the pipelined processing, ensuring that each stage of the pipeline is fully utilized, while handling various issues that arise in the pipeline, such as data conflicts, pipeline stalls, and resource scheduling.

[0041] In addition, if any anomalies or conditional branching are encountered in the transformation operation instructions in the pipeline, the scheduler will perform corresponding processing, such as pausing and rescheduling.

[0042] Furthermore, the instruction execution unit 130 accesses the register array unit 110 through the register access interface 10 to obtain the source memory address segment and the destination memory address segment, etc. The register array unit 110 includes tensor address registers, tensor parameter registers, tensor location registers, etc.

[0043] In some examples, the Tensor Address Register (TAR) includes a source address register (e.g., the Scr_tar field shown in Figure 4B) for storing the memory address segment of the source tensor, and a destination address register (e.g., the Dst_tar field shown in Figure 4B) for storing the memory address segment of the destination tensor. As shown in Figure 3A, the Tensor Address Register can contain 16 registers, numbered from 0 to 15 (TAR[15:0]), and address configuration operations are performed via register write instructions indicated by operation type 4'b0100 (as shown in Figure 4A). Each address register is 32 bits wide and is used to store the tensor memory address segment (e.g., the 16-bit immediate value shown in Figure 4A is either the high 16 bits or the low 16 bits of the memory address, specified by the HL field). In some specific examples, the tensor data can be 16-byte aligned, with the lower 4 bits of each register being 0 to ensure address alignment.

[0044] It should be understood that the number of registers, the bit width of the registers, and the bit width of the high-order, low-order, and reserved bit fields in the registers mentioned above are merely exemplary. In other embodiments, they may be other values ​​or multiples.

[0045] In other examples, the Tensor Dimension Register (TDR) includes a source tensor parameter register (e.g., the Scr_tdr field shown in Figure 4B) for storing source tensor parameters (e.g., dimensions) and a destination address register (e.g., the Dst_tdr field shown in Figure 4B) for storing destination tensor parameters (dimensions). As shown in Figure 3A, the tensor parameter register may contain 16 registers, numbered from 0 to 15 (TDR[15:0]), corresponding to the register operation instruction indicated by address 4'b0011 (as shown in Figure 4A). Each register is 32 bits wide and is used to store tensor parameters (e.g., dimensions). In the tensor parameter register, as shown in Figure 4A, the high-order bits (Bit[27:16]) can be used to represent the number of rows (M) of the matrix, and the low-order bits (Bit[11:0]) can be used to represent the number of columns (N) of the matrix. In addition, the tensor parameter register also includes reserved bit fields, such as Bit[31:28] and Bit[15:12] shown in Figure 3B.

[0046] It should be understood that the number of registers, the bit width of the registers, and the bit width of the high-order, low-order, and reserved bit fields in the registers mentioned above are merely exemplary. In other embodiments, they may be other values ​​or multiples.

[0047] In other examples, the Tensor Position Register (TPR) is used to store the displacement or offset information of the source tensor in the destination tensor (e.g., the Dst_tpr field shown in Figure 4B). As shown in Figure 3C, the tensor coordinate register file can contain 16 registers, numbered from 0 to 15 (TPR[15:0]), corresponding to the register operation instruction indicated by address 4'b0010 (as shown in Figure 4A). Each register is 32 bits wide and is used to store the coordinates of the tensor currently being processed. In the tensor position register, as shown in Figure 4A, the high-order bits (Bit[27:16]) represent the x-coordinate (X) of the matrix, and the low-order bits (Bit[11:0]) represent the y-coordinate (Y) of the matrix. In addition, the tensor position register may also contain reserved bit fields, such as Bit[31:28] and Bit[15:12].

[0048] It should be understood that the number of registers, the bit width of the registers, and the bit width of the high-order, low-order, and reserved bit fields in the registers mentioned above are merely exemplary. In other embodiments, they may be other values ​​or multiples.

[0049] In some examples, the instruction fetching unit can fetch transformation operation instructions. As shown in Figure 4B, the transformation operation instruction includes at least an operation type field, the register number of the source address register, the register number of the destination address register, and the register number of the source tensor parameter register. The transformation operation instruction is exemplarily 32 bits wide. For example, the operation type field is represented as the instruction header field (e.g., 4 bits wide); the register number of the source address register is the Scr_tar field; the register number of the destination address register is the Dst_tar field; the register number of the source tensor parameter register is the Scr_tdr field; the register number of the destination tensor parameter register is the Dst_tdr field; and the register number of the tensor position register is the Dst_tpr field. It should be understood that the register numbers of each register can be identifiers with a width of 4 bits.

[0050] Additionally, as shown in Figure 4B, the transformation operation instruction can also include a field e_size indicating the size of the tensor elements, for example, with a width of 2 bits. For example, 2'b00 indicates a size of 1 byte; 2'b01 indicates a size of 2 bytes; 2'b10 indicates a size of 4 bytes; and 2'b11 indicates a reserved custom number of bytes. Furthermore, as shown in Figure 4B, the Padding field indicates a padding parameter field, for example, with a width of 4 bits. Additionally, the Stride and Kernel fields are convolution kernel parameter fields, where Stride[3:2] indicates the convolution kernel stride field with a width of 2 bits, i.e., the 2nd and 3rd bits. For example, stride value = binary value + 1: 2'b00 indicates a stride of 1; 2'b01 --> a stride of 2; 2'b10 is a reserved definition; and 2'b11 is a reserved definition. Furthermore, Kernel_sz[5:4] indicates the convolution kernel parameter field with a width of 2 bits, i.e., the 4th and 5th bits. For example, 2'b00 represents a 2x2 convolution kernel; 2'b01 is a 3x3 convolution kernel; 2'b10 is a 4x4 convolution kernel; and 2'b11 is a reserved kernel size.

[0051] In addition, Tiled_size[2] represents a 2-bit wide block size parameter, 1'b0 represents a 2x16 tensor block; 1'b1 represents a 2x32 tensor block.

[0052] Without loss of generality, after the tensor transformation program is compiled, corresponding register operation instructions and transformation operation instructions are obtained. The instruction execution unit executes the register operation instructions (e.g., the first register operation instruction), sets the memory address segments of the source tensor and the destination tensor, and stores the memory address segment of the source tensor (i.e., an example of configuration parameters) in the source address register and the destination tensor in the destination address register. The instruction execution unit executes the register operation instructions (e.g., the second register operation instruction), sets the source tensor parameters, and stores the source tensor parameters (i.e., an example of configuration parameters) in the source tensor parameter register and the destination tensor parameters in the destination tensor parameter register. The instruction execution unit executes the register operation instructions (e.g., the third register operation instruction), sets the displacement or offset information of the source tensor in the destination tensor, and stores the displacement or offset information (i.e., an example of configuration parameters) in the tensor position register.

[0053] It should be understood that the above-described register configuration process can also be accomplished by executing unified register operation instructions through the instruction execution unit.

[0054] Then, the instruction execution unit executes the transformation operation instructions, parses the index fields of each configured register to obtain the corresponding configuration parameters, and performs tensor transformation operations based on each configuration parameter.

[0055] In some embodiments, the instruction decoding unit parses the register number of the destination tensor parameter register to obtain the destination tensor parameters. Accordingly, the instruction execution unit determines the write memory address that has row and column position values ​​relative to the destination memory address segment, and writes the source tensor as at least a portion of the destination tensor to the destination memory address segment while preserving the source tensor parameters. For example, the instruction execution unit executes register operation instructions to set the write memory address and executes transformation operation instructions to determine the write memory address.

[0056] In other words, when the source tensor is moved during a tensor transformation operation, and its parameters remain unchanged in both the source and destination memory address segments, the write memory address with row and column positions relative to the destination memory address segment can be determined. Furthermore, the source tensor is written to the destination memory address segment as at least a part of the destination tensor, improving the write efficiency of the source tensor in the tensor transformation operation. Additionally, based on the parameters of the destination tensor, the remaining part of the destination tensor can be written to the destination memory address segment, thus completing the tensor transformation operation.

[0057] In some embodiments, the tensor transpose operation involves swapping the rows and columns of a matrix (or tensor). For example, the instruction decoding unit determines the matrix transpose operation indicated by the operation type field. Accordingly, the instruction execution unit determines the number of the first row and the number of the first column included in the source tensor parameters as the number of the second column and the number of the second row, respectively, and writes multiple elements as the destination tensor to the destination memory address segment based on the number of the second column and the number of the second row. That is, without needing to read the destination tensor parameters through the destination tensor parameter register, the number of the second column and the number of the second row are determined as the destination tensor parameters from the number of the first row and the number of the first column in the source tensor parameters, which facilitates efficient and accurate execution of the matrix transpose operation.

[0058] In some examples, the instruction decoding unit is used to determine the source tensor memory address segment, the destination tensor memory address segment, and the source tensor size. For example, by executing a register operation instruction, the source tensor's memory address segment is set to 0x0200_0110 and stored in the TAR0 register, with the lower 4 bits of the memory address segment being 0, conforming to 16-byte alignment. As another example, by executing a register operation instruction, the destination tensor's memory address segment is set to 0x0210_0110 and stored in the TAR1 register, with the memory address segment being 16-byte aligned. As yet another example, as shown in Figure 5A, the instruction decoding unit determines the source tensor size to be 3x4 and the destination tensor size to be 4x3. As shown in Figure 4B, the transformation operation type is indicated by the address 4'b1001 field. In the TDR0 register, the source tensor size is encoded as Bit[27:16]:3 (matrix row size M) and Bit[11:0]:4 (matrix column size N).

[0059] As shown in Figure 5A, the instruction execution unit transposes the data of the source tensor (3x4 size), swapping its rows and columns, and stores the result in the destination tensor. The transposed matrix will then be 4x3. That is, the transpose operation does not change the storage order of the elements (they are still stored row-wise), but it does change the position of the elements within the matrix. Furthermore, TAR1 and TAR0 are the address registers of the source and destination tensors, respectively, and TDR0 is the size register of the source tensor.

[0060] In some embodiments, the register array unit includes an offset position register. The instruction decoding unit determines the matrix copy operation indicated by the operation type field and reads the row and column position values ​​based on the offset position register. That is, the matrix copy operation is performed efficiently using the row and column position values.

[0061] In some examples, for the transformation operation type indicated by the address 4'b1100 field shown in Figure 4B, the instruction decoding unit is used to determine the source tensor memory address segment, the destination tensor memory address segment, the source tensor size, the destination tensor size, the destination tensor location, etc. For example, by executing a register operation instruction, the memory address segment of the source tensor is set to 0x0200_0100 and stored in the TAR0 register. The tensor memory address segment is aligned to 16 bytes, and the lower 4 bits of the memory address segment are 0. As another example, by executing a register operation instruction, the memory address segment of the destination tensor is set to 0x0210_0100 and stored in the TAR1 register. The address is aligned to 16 bytes. As yet another example, the instruction decoding unit determines that the size of the source tensor is 2x2, and in the TDR0 register, the size of the source tensor is encoded as Bit[27:16]:2 (matrix row size M) and Bit[11:0]:2 (matrix column size N). As yet another example, the instruction decoding unit determines that the size of the destination tensor is 3x4. In the TDR1 register, the size of the destination tensor is encoded as Bit[27:16]:3 (matrix row size M) and Bit[11:0]:4 (matrix column size N). For example, the instruction decoding unit determines the position coordinates of the destination tensor as (1,1). In the TPR0 register, the coordinates of the source tensor within the destination tensor are encoded as Bit[27:16]:1 (matrix x-coordinate X) and Bit[11:0]:1 (matrix column y-coordinate Y).

[0062] Further, as shown in Figure 5B, the instruction execution unit copies the contents of the source tensor into the destination tensor, starting from position (1,1) of the destination tensor. Since the size of the destination tensor is 3x4 and the size of the source tensor is 2x2, the copy operation will cover the region of the destination tensor from (1,1) to (2,2).

[0063] For example, for the transformation operation type indicated by the address 4'b1100 field as shown in Figure 4B, the instruction execution unit copies from the source tensor address pointed to by TAR0 to the destination tensor address pointed to by TAR1. The size of the destination tensor is determined by TDR1 (3x4); the size of the source tensor is determined by TDR0 (2x2); the copy operation starts at position (1,1) of the destination tensor, determined by TPR0; the size of the copied element can be 1 byte or any other number of bytes.

[0064] In some embodiments, matrix filling operations are used to expand a smaller matrix into a larger matrix. This is typically achieved by adding extra elements around the smaller matrix to adjust the data size to meet the needs of a specific algorithm. For example, the register array unit includes a destination tensor parameter register. Accordingly, the instruction decoding unit parses the register number of the destination tensor parameter register to obtain the destination tensor parameters and determines the matrix filling operation indicated by the operation type field, as well as the filling parameters for the matrix filling operation. Accordingly, the instruction execution unit determines the row and column positions of the source tensor relative to the destination memory address segment based on the filling parameters and the destination tensor parameters. That is, determining the row and column positions of the source tensor based on the filling parameters and the destination tensor parameters improves the writing efficiency of the source tensor during matrix filling operations.

[0065] In some examples, the padding parameters include at least the proximity positions of multiple edge padding elements of the source tensor to the source tensor. The instruction execution unit writes these edge padding elements to the destination memory address segment based on the padding parameters and the destination tensor parameters. In other words, by using the padding parameters and the destination tensor parameters, edge padding elements are filled efficiently and accurately, thereby improving the efficiency of the matrix filling operation.

[0066] Furthermore, in some examples, for the transformation operation type indicated by the address 4'b1101 field shown in Figure 4B, the instruction decoding unit is used to determine the source tensor memory address segment, the destination tensor memory address segment, the source tensor size, the destination tensor size, etc. For example, by executing a register operation instruction, the memory address segment of the source tensor is set to 0x0200_0100 and stored in the TAR0 register, with the lower 4 bits of the memory address segment being 0, conforming to 16-byte alignment. As another example, by executing a register operation instruction, the memory address segment of the destination tensor is set to 0x0210_0100 and stored in the TAR1 register, with the memory address segment being 16-byte aligned. As yet another example, the instruction decoding unit determines the size of the source tensor to be 3x3, and in the TDR0 register, the size of the source tensor is encoded as Bit[27:16]:3 (matrix row size M) and Bit[11:0]:3 (matrix column size N). For example, the instruction decoding unit determines that the size of the destination tensor is 5x5. In the TDR1 register, the size of the destination tensor is encoded as Bit[27:16]:5 (matrix row size M) and Bit[11:0]:5 (matrix column size N).

[0067] As shown in Figure 5C, the instruction execution unit copies the data from the source tensor (3x3) to the center of the destination tensor (5x5), while adding padding around the source tensor. The content and direction of the padding are specified by 0xf, and the padding value is typically 0 (or other specific values), depending on the hardware implementation. The padding element is two bytes in size, meaning the data type is either a 16-bit integer or a 32-bit floating-point number. After the padding elements, the destination tensor will contain the data from the source tensor, with additional space around it for scenarios such as image scaling in image processing and input size adjustment in deep learning.

[0068] Furthermore, when the instruction execution unit performs the matrix filling operation, TAR1 and TAR0 are the address registers of the target and source tensors, respectively, and TDR1 and TDR0 are the size registers of the target and source tensors, respectively. 0xf indicates the filling direction, meaning that filling is performed in all four directions (up, down, left, and right).

[0069] In some embodiments, the tensor flattening operation is also called the image-to-column (Im2Col) operation, a common technique in convolutional neural networks (CNNs) in deep learning. It converts an image (or matrix) into a column vector so that it can be multiplied by the weight matrix, thereby accelerating the convolution operation. For example, the register array unit includes a destination tensor parameter register. Accordingly, the instruction decoding unit parses the register number of the destination tensor parameter register to obtain the destination tensor parameters and determines the tensor flattening operation indicated by the operation type field, as well as the convolution kernel parameters for the tensor flattening operation. The convolution kernel parameters include at least the convolution kernel size and the convolution kernel stride. Accordingly, the instruction execution unit performs the tensor flattening operation on the source tensor according to the convolution kernel parameters and writes the result of the tensor flattening operation to the destination memory address segment according to the destination tensor parameters. That is, convolution kernel parameters such as the convolution kernel size and convolution kernel stride can be configured in the fields of the transformation operation instruction, improving the processing efficiency of the tensor flattening operation through these parameters.

[0070] In some examples, for the transformation operation type indicated by the address 4'b1110 field shown in Figure 4B, the instruction decoding unit is used to determine the source tensor memory address segment, the destination tensor memory address segment, the source tensor size, the destination tensor size, etc. For example, by executing a register operation instruction, the memory address segment of the source tensor is set to 0x0200_0100 and stored in the TAR0 register, with the lower 4 bits of the memory address segment being 0, conforming to 16-byte alignment. As another example, by executing a register operation instruction, the memory address segment of the destination tensor is set to 0x0210_0100 and stored in the TAR1 register, with the memory address segment being 16-byte aligned. As yet another example, the instruction decoding unit determines the size of the source tensor to be 4x3, and in the TDR0 register, the size of the source tensor is encoded as Bit[27:16]:4 (matrix row size M) and Bit[11:0]:3 (matrix column size N). For example, the instruction decoding unit determines that the size of the destination tensor is 4x6. In the TDR1 register, the size of the destination tensor is encoded as Bit[27:16]:4 (matrix row size M) and Bit[11:0]:6 (matrix column size N).

[0071] As shown in Figure 5D, the instruction execution unit flattens the data in the source tensor (4x3 size) with a 2x2 convolution kernel size and a stride of 1, and stores the result in the destination tensor (4x6 size). That is, the flattening operation converts each 2x2 region in the source tensor into a column vector and stores them row by row in the destination tensor.

[0072] Furthermore, when the instruction execution unit performs the image-to-column operation, TAR1 and TAR0 are the address registers of the target and source tensors, respectively, and TDR1 and TDR0 are the size registers of the target and source tensors, respectively. 0x2 indicates that the size of the convolution kernel used is 2x2, and the element values ​​in the convolution kernel are random values ​​or sequentially increasing values.

[0073] In other embodiments, tensor tile operations are commonly used in tensor processing units to optimize memory access and improve computational efficiency. For example, tensor tile operations are typically used in calculations such as matrix multiplication; tile operations reduce cache misses and improve computational efficiency. That is, the data of the source tensor is reorganized and stored in the destination tensor so that subsequent calculations can be performed more efficiently. For example, the instruction decoding unit determines the matrix tile operation indicated by the operation type field, as well as the row and column tile sizes of the matrix tile operation. Accordingly, the instruction execution unit determines the row and column positions of each piece of data to be tiled in the source tensor based on the row and column tile sizes and the destination tensor parameters. In other words, the row and column positions of each piece of data to be tiled are indirectly determined by the row and column tile sizes, and the matrix tile operation is performed efficiently using these row and column positions.

[0074] In some examples, for the transformation operation type indicated by the address 4'b0111 field shown in Figure 4B, the instruction decoding unit is used to determine the source tensor memory address segment, the destination tensor memory address segment, the source tensor size, the destination tensor size, etc. For example, by executing a register operation instruction, the memory address segment of the source tensor is set to 0x0200_0100 and stored in the TAR0 register. The lower 4 bits of the memory address segment are 0, conforming to 16-byte alignment. As another example, by executing a register operation instruction, the memory address segment of the destination tensor is set to 0x0210_0100 and stored in the TAR1 register, the memory address segment being 16-byte aligned. As yet another example, the instruction decoding unit determines the size of the source tensor to be 4x32, and in the TDR0 register, the size of the source tensor is encoded as Bit[27:16]:4 (matrix row size M) and Bit[11:0]:32 (matrix column size N). For example, the instruction decoding unit determines that the size of the destination tensor is 8x16. In the TDR1 register, the size of the destination tensor is encoded as Bit[27:16]:8 (matrix row size M) and Bit[11:0]:16 (matrix column size N).

[0075] Figure 6A shows the case where the data to be divided into blocks are aligned during the Row2Tile transformation operation, while Figure 6B shows the case where the data to be divided into blocks are not aligned during the Row2Tile transformation operation.

[0076] For example, in Figure 6A, the instruction execution unit reorganizes the data of the source tensor (M1: 4x32 size) (stored in rows) according to the requirements of the destination tensor (M2: 8x16 size) (stored in tiles), resulting in 4 blocks. As shown in Figure 6A, the row addresses of the source tensor stored in rows are addresses 0, 64, 128, and 192, respectively. In the 4 blocks, the row addresses of the first block are addresses 0 and 32, the row addresses of the second block are addresses 64 and 96, the row addresses of the third block are addresses 128 and 160, and the row addresses of the fourth block are addresses 192 and 224. Each block is 2x16 in size, processing 2 rows of data at a time, with 16 columns per row. Tensor elements are two bytes in size, and the data type is either a 16-bit integer or a 32-bit floating-point number.

[0077] For example, in Figure 6B, the instruction execution unit reorganizes the data of the source tensor (M1: 3x30 size) (stored in rows) according to the requirements of the destination tensor (M2: 8x16 size) (stored in tiles), resulting in 4 blocks. Unaligned elements are padded with zeros. As shown in Figure 6B, the row addresses of the source tensor stored in rows are addresses 0, 64, and 128. In the 4 blocks, the row addresses of the first block are addresses 0 and 32; the row addresses of the second block are addresses 64 and 96, with zeros padded at positions where elements are 0; the row addresses of the third block are addresses 128 and 160, with zeros padded at positions where elements are 0; and the row addresses of the fourth block are addresses 192 and 224, with zeros padded at positions where elements are 0. Each block is 2x16 in size, processing 2 rows of data at a time, with 16 columns per row. Tensor elements are two bytes in size, and their data type is either a 16-bit integer or a 32-bit floating-point number.

[0078] Further, as shown in Figure 4B, the instruction execution unit is used to perform line-to-block operations. That is, TAR1 and TAR0 are the address registers of the target and source tensors, respectively. TDR1 and TDR0 are the size registers of the target and source tensors, respectively.

[0079] In other embodiments, the matrix concatenation operation (Tile2Row) describes the operation of reorganizing tensor tiles into rows to optimize memory access and improve computational efficiency. For example, in computations such as matrix multiplication, tensor partitioning can reduce cache misses and improve computational efficiency. That is, the data of the source tensor is reorganized and stored in the destination tensor so that subsequent computations can be performed more efficiently. For example, the instruction decoding unit determines the matrix concatenation operation indicated by the operation type field, as well as the row and column block sizes of the matrix concatenation operation.

[0080] The instruction execution unit determines the row and column positions of each block of data in the source tensor based on the row and column block sizes and the destination tensor parameters. In other words, the row and column positions of each block of data are indirectly determined by the row and column block sizes, and the matrix concatenation operation is performed efficiently using the row and column positions.

[0081] In some examples, for the transformation operation type indicated by the address 4'b0110 field shown in Figure 4B, the instruction decoding unit is used to determine the source tensor memory address segment, the destination tensor memory address segment, the source tensor size, the destination tensor size, etc. For example, by executing a register operation instruction, the memory address segment of the source tensor is set to 0x0200_0100 and stored in the TAR0 register. The lower 4 bits of the memory address segment are 0 and are 16-byte aligned. As another example, by executing a register operation instruction, the memory address segment of the destination tensor is set to 0x0210_0100 and stored in the TAR1 register; the memory address segment is 16-byte aligned. As yet another example, the instruction decoding unit determines the size of the source tensor to be 8x16. In the TDR0 register, the size of the source tensor is encoded as Bit[27:16]:8 (matrix row size M) and Bit[11:0]:16 (matrix column size N). For example, the instruction decoding unit determines that the size of the destination tensor is 4x32. In the TDR1 register, the size of the destination tensor is encoded as Bit[27:16]:4 (matrix row size M) and Bit[11:0]:32 (matrix column size N).

[0082] Figure 7A shows the case where the data blocks are aligned during the Tile2Row transformation operation, while Figure 7B shows the case where the data blocks are not aligned during the Tile2Row transformation operation.

[0083] For example, in Figure 7A, the instruction execution unit reorganizes the data (stored as tiles) of each block of data (M1: 8x16 in size) of the source tensor according to the row requirements (i.e., stored as rows) of the destination tensor (4x32 in size) to obtain the destination tensor. As shown in Figure 7A, in the four blocks of data M1, the row addresses of the first block are 0 and 32, the row addresses of the second block are 64 and 96, the row addresses of the third block are 128 and 160, and the row addresses of the fourth block are 192 and 224. The row addresses of the destination tensor M2, stored as rows, are 0, 64, 128, and 192. Each block of data (tile) is 2x16 in size, that is, two rows of data are processed at a time, with 16 columns per row. The tensor element size is two bytes, for example, the data type of the element is a 16-bit integer or a 32-bit floating-point number.

[0084] For example, in Figure 7B, the instruction execution unit reorganizes the data of each block of the source tensor (M1: 8x16 in size) (stored as a tile) according to the row requirements of the destination tensor (3x30 in size), to obtain the destination tensor. As shown in Figure 7B, in the four blocks of data M1, the row addresses of the first block are 0 and 32; the row addresses of the second block are 64 and 96, with zeros padded at positions where elements are 0; the row addresses of the third block are 128 and 160, with zeros padded at positions where elements are 0; and the row addresses of the fourth block are 192 and 224, with zeros padded at positions where elements are 0. The row addresses of the destination tensor M2, stored as a row, are 0, 64, and 128. Each block of data (tile) is 2x16 in size, meaning that two rows of data are processed at a time, with 16 columns per row. Tensor elements are two bytes in size; for example, the data type of an element is a 16-bit integer or a 32-bit floating-point number.

[0085] In some examples, as shown in Figure 4B, when the instruction execution unit performs the block-to-line operation, TAR1 and TAR0 are the address registers of the target and source tensors, respectively, and TDR1 and TDR0 are the size registers of the target and source tensors, respectively.

[0086] The tensor data transformation method according to some other embodiments of the present disclosure will now be described in detail with reference to FIG8. The tensor transformation method 800 of FIG8 includes:

[0087] S810: Parse the obtained transformation operation instructions, obtain the transformation operation information indicated by the operation type field, and obtain the register numbers of the source address register, destination address register, and source tensor parameter register.

[0088] S820: Access the source address register, the destination address register, and the source tensor parameter register according to each register number, and read the source memory address segment, the destination memory address segment, and the source tensor parameter.

[0089] S830: Read the source tensor according to the source memory address segment, perform the transformation operation indicated by the transformation operation information on the source tensor, and write the transformed destination tensor into the destination memory address segment according to the source tensor parameters.

[0090] In the scheme of this embodiment, the instruction decoding unit can parse each field of the transformation operation instruction. Each field of the transformation operation instruction includes an operation type field and register numbers for the source address register, destination address register, and source tensor parameter register. The instruction execution unit can access the corresponding register according to the register number and obtain instruction execution parameters such as the source memory address segment, destination memory address segment, and source tensor parameters. Based on the instruction execution parameters, the transformed destination tensor is written to the destination memory address segment. Since the transformation operation instruction includes register numbers for the source address register, destination address register, and source tensor parameter register, it can be deconstructed with these registers, improving the processing efficiency of the instruction decoding unit. This, in turn, forms a pipeline for tensor transformation operations with the instruction execution unit, improving tensor transformation efficiency and consequently, computational efficiency.

[0091] In other embodiments, the tensor data transformation method further includes: obtaining a transformation operation instruction, wherein the transformation operation instruction includes at least the operation type field, the source address register, the destination address register, and the register number of the source tensor parameter register.

[0092] In other embodiments, the tensor data transformation method further includes: parsing the register number of the destination tensor parameter register to obtain the destination tensor parameters. Accordingly, reading the source tensor according to the source memory address segment, performing the transformation operation indicated by the transformation operation information on the source tensor, and writing the transformed destination tensor into the destination memory address segment according to the source tensor parameters, includes: determining a write memory address that has row and column positions relative to the destination memory address segment; writing the source tensor as at least a portion of the destination tensor into the destination memory address segment while maintaining the source tensor parameters; and writing the remaining portion of the destination tensor into the destination memory address segment according to the destination tensor parameters.

[0093] In other embodiments, the tensor data transformation method further includes: determining the matrix copy operation indicated by the operation type field, and reading the row position and column position values ​​according to the offset position register.

[0094] In other embodiments, parsing the acquired transformation operation instructions yields transformation operation information indicated by the operation type field, and also obtains the register numbers of the source address register, destination address register, and source tensor parameter register, including: determining the matrix partitioning operation indicated by the operation type field, and the row block size and column block size of the matrix partitioning operation. Correspondingly, the source tensor is read according to the source memory address segment, the transformation operation indicated by the transformation operation information is performed on the source tensor, and the transformed destination tensor is written to the destination memory address segment according to the source tensor parameters, including: determining the row position and column position of each block of data to be partitioned in the source tensor according to the row block size, the column block size, and the destination tensor parameters.

[0095] In other embodiments, parsing the acquired transformation operation instructions yields transformation operation information indicated by the operation type field, and also obtains the register numbers of the source address register, destination address register, and source tensor parameter register, including: determining the matrix concatenation operation indicated by the operation type field, and the row block size and column block size of the matrix concatenation operation. Correspondingly, the source tensor is read according to the source memory address segment, the transformation operation indicated by the transformation operation information is performed on the source tensor, and the transformed destination tensor is written to the destination memory address segment according to the source tensor parameters, including: determining the row position and column position of each block of data in the source tensor according to the row block size, the column block size, and the destination tensor parameters.

[0096] In other embodiments, parsing the acquired transformation operation instructions to obtain the transformation operation information indicated by the operation type field, and obtaining the register numbers of the source address register, destination address register, and source tensor parameter register, includes: parsing the register number of the destination tensor parameter register to obtain the destination tensor parameters, and determining the matrix filling operation indicated by the operation type field, and the filling parameters of the matrix filling operation. Accordingly, reading the source tensor according to the source memory address segment, performing the transformation operation indicated by the transformation operation information on the source tensor, and writing the transformed destination tensor into the destination memory address segment according to the source tensor parameters, includes: determining the row position and column position of the source tensor's write memory address relative to the destination memory address segment based on the filling parameters and the destination tensor parameters.

[0097] In other embodiments, the tensor data transformation method further includes: writing the plurality of edge padding elements into the destination memory address segment according to the padding parameters and the destination tensor parameters. The padding parameters include at least the proximity positions between the plurality of edge padding elements of the source tensor and the source tensor.

[0098] In other embodiments, the tensor data transformation method further includes: parsing the register number of the destination tensor parameter register to obtain the destination tensor parameters, and determining the tensor flattening operation indicated by the operation type field, and the convolution kernel parameters of the tensor flattening operation, wherein the convolution kernel parameters include at least the convolution kernel size and the convolution kernel stride. Correspondingly, reading the source tensor according to the source memory address segment, performing the transformation operation indicated by the transformation operation information on the source tensor, and writing the transformed destination tensor to the destination memory address segment according to the source tensor parameters includes: performing a tensor flattening operation on the source tensor according to the convolution kernel parameters, and writing the result of the tensor flattening operation to the destination memory address segment according to the destination tensor parameters.

[0099] In other embodiments, the tensor data transformation method further includes: determining the matrix transpose operation indicated by the operation type field; the source tensor parameters include the first row number and the first column number. Accordingly, reading the source tensor according to the source memory address segment, performing the transformation operation indicated by the transformation operation information on the source tensor, and writing the transformed destination tensor into the destination memory address segment according to the source tensor parameters, includes: determining the first row number and the first column number as the second column number and the second row number, respectively; and writing the plurality of elements as the destination tensor into the destination memory address segment according to the second column number and the second row number.

[0100] It should be understood that the specific implementation of each step in the tensor data transformation method can be found in the description of the corresponding unit in the tensor processing unit above, and has corresponding beneficial effects, which will not be elaborated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above tensor data transformation method and steps can be referred to the description of the corresponding unit in the tensor processing unit, and will not be elaborated here.

[0101] This disclosure also provides a computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the tensor processing unit described above.

[0102] This disclosure also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the tensor processing unit described above.

[0103] It should be understood that the various embodiments in this disclosure are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to in the description of other embodiments.

[0104] It should be understood that the foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0105] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0106] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments of this disclosure should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A tensor processing unit, comprising: A register array unit includes at least a source address register, a destination address register, and a source tensor parameter register; The instruction decoding unit parses the acquired transformation operation instruction, obtains the transformation operation information indicated by the operation type field, and obtains the register numbers of the source address register, the destination address register, and the source tensor parameter register, respectively. The instruction execution unit accesses the source address register, the destination address register, and the source tensor parameter register according to each register number, reads the source memory address segment, the destination memory address segment, and the source tensor parameters, reads the source tensor according to the source memory address segment, performs the transformation operation indicated by the transformation operation information on the source tensor, and writes the transformed destination tensor into the destination memory address segment according to the source tensor parameters.

2. The tensor processing unit according to claim 1, wherein, The tensor processing unit further includes an instruction acquisition unit for acquiring transformation operation instructions, wherein the transformation operation instructions include at least the operation type field, the source address register, the destination address register, and the register number of the source tensor parameter register.

3. The tensor processing unit according to claim 1 or 2, wherein, The register array unit further includes a destination tensor parameter register; wherein, the instruction decoding unit is further configured to: parse the register number of the destination tensor parameter register to obtain the destination tensor parameter; wherein, the instruction execution unit is specifically configured to: determine the write memory address having row position and column position values ​​with respect to the destination memory address segment; while maintaining the source tensor parameter, write the source tensor as at least a part of the destination tensor into the destination memory address segment; and write the remaining part of the destination tensor into the destination memory address segment according to the destination tensor parameter.

4. The tensor processing unit according to claim 3, wherein, The register array unit includes a position register; wherein, the instruction decoding unit is specifically used to: determine the matrix copy operation indicated by the operation type field, and read the row position and column position according to the position register.

5. The tensor processing unit according to claim 3, wherein, The instruction decoding unit is specifically used to: determine the matrix partitioning operation indicated by the operation type field, and the row partitioning size and column partitioning size of the matrix partitioning operation; wherein, the instruction execution unit is specifically used to: determine the row position and column position of each data block to be partitioned in the source tensor according to the row partitioning size, the column partitioning size, and the destination tensor parameters.

6. The tensor processing unit of claim 3, wherein, The instruction decoding unit is specifically used to: determine the matrix concatenation operation indicated by the operation type field, and the row block size and column block size of the matrix concatenation operation; wherein, the instruction execution unit is specifically used to: determine the row position and column position of each block of data in the source tensor according to the row block size, the column block size, and the destination tensor parameters.

7. The tensor processing unit of claim 1, wherein, The register array unit further includes a destination tensor parameter register; wherein, the instruction decoding unit is further configured to: parse the register number of the destination tensor parameter register to obtain the destination tensor parameter, and determine the matrix filling operation indicated by the operation type field, and the filling parameter of the matrix filling operation; wherein, the instruction execution unit is specifically configured to: determine the row position and column position of the source tensor's write memory address relative to the destination memory address segment based on the filling parameter and the destination tensor parameter.

8. The tensor processing unit of claim 7, wherein, The padding parameters include at least the proximity positions between multiple edge padding elements of the source tensor and the source tensor, wherein the instruction execution unit is specifically configured to: write the multiple edge padding elements into the destination memory address segment according to the padding parameters and the destination tensor parameters.

9. The tensor processing unit according to claim 1, wherein, The register array unit further includes a destination tensor parameter register; wherein, the instruction decoding unit is further configured to: parse the register number of the destination tensor parameter register to obtain the destination tensor parameters, and determine the tensor flattening operation indicated by the operation type field, and the convolution kernel parameters of the tensor flattening operation, wherein the convolution kernel parameters include at least the convolution kernel size and the convolution kernel stride; wherein, the instruction execution unit is specifically configured to: perform a tensor flattening operation on the source tensor according to the convolution kernel parameters, and write the operation result after the tensor flattening operation to the destination memory address segment according to the destination tensor parameters.

10. The tensor processing unit of any one of claims 1-9, wherein, The instruction decoding unit is specifically used to: determine the matrix transpose operation indicated by the operation type field; the source tensor parameters include the first row number and the first column number; wherein, the instruction execution unit is specifically used to: determine the first row number and the first column number as the second column number and the second row number respectively; and write the plurality of elements as the destination tensor into the destination memory address segment according to the second column number and the second row number.

11. A tensor transformation method, comprising: The obtained transformation operation instructions are parsed to obtain the transformation operation information indicated by the operation type field, and the register numbers of the source address register, destination address register, and source tensor parameter register are obtained respectively. According to each register number, access the source address register, the destination address register, and the source tensor parameter register respectively, and read the source memory address segment, the destination memory address segment, and the source tensor parameter; The source tensor is read from the source memory address segment, the transformation operation indicated by the transformation operation information is performed on the source tensor, and the transformed destination tensor is written to the destination memory address segment according to the source tensor parameters.

12. A processor, comprising: A plurality of tensor processing units, wherein each tensor processing unit is a tensor processing unit according to any one of claims 1-10.

13. A system-on-a-chip, comprising: The processor according to claim 12; The memory stores the source tensor and the destination tensor, as well as transformation operation instructions.

14. A computing device, comprising: A processor board, wherein the processor board is provided with the system-on-a-chip according to claim 13.

15. A computer readable storage medium, wherein, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the tensor processing unit as described in any one of claims 1-10.

16. A computer program product, wherein, It includes a computer program that, when executed by a processor, implements the tensor processing unit as described in any one of claims 1-10.

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