Multi-chip system interrupt transmission method, chip and multi-chip system

Abstract

The invention provides a multi-chip system interrupt transmission method, chips and a multi-chip system, and aims to solve the problems of complex design and low efficiency caused by lack of an effective interrupt transmission mechanism in the prior art. The method comprises the following steps: receiving and collecting a local interrupt message which needs to be reported to the basic core particle by controlling an interrupt action of a first interrupt repeater arranged in the functional core particle; the first interrupt relay initiates an AXI write request, and writes a local interrupt message containing a global interrupt identifier into a specific target address pre-allocated by system software; and packaging the AXI write request into a data packet in a core grain interconnection protocol format through a core grain interconnection protocol controller of the functional core grain, and triggering the processor of the basic core grain to interrupt in response to the write-in of the local interrupt message.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a method for interrupt transmission in a multi-chip system, a chip, and a multi-chip system. Background Technology

[0002] This invention relates to the field of integrated circuit technology, specifically to a chip-level interconnect architecture, and more particularly to a method and related apparatus for reliably and efficiently transmitting interrupt signals across chips in a multi-chip system built on a chiplet interconnect interface protocol.

[0003] As semiconductor manufacturing processes approach their physical limits, chiplet technology has become a crucial path to perpetuating Moore's Law. This technology breaks down large system-on-a-chip (SoC) chips into multiple small chips with specific functions, integrating and packaging them through high-speed interconnect interfaces (such as UCIe, BoW, and other chiplet interconnect protocols) to improve yield, reduce costs, and achieve heterogeneous integration.

[0004] In chip-based systems, there is typically a base chip (such as a chip with an integrated CPU) responsible for global control and coordination, and multiple function chips (such as GPUs, NPUs, and I / O controllers) that perform specific tasks. During operation, function chips generate various events or exceptions that need to be promptly notified to the base chip's CPU in the form of interrupts for processing. In traditional single-chip SoCs, all modules share the same on-chip interconnect (such as the AXI bus), and interrupts can be directly transmitted through standard interrupt controllers (such as ARM GICs, RISC-VPLICs, etc.) and interrupt lines.

[0005] However, in physically separated chip systems connected via protocol links, interrupt propagation faces fundamental challenges: 1) Traditional level- or edge-triggered interrupt signals cannot be directly transmitted across chip physical boundaries via serial protocol links; 2) Each chip has an independent address space and interrupt hierarchy, lacking a unified, hardware-recognizable cross-chip interrupt routing and propagation mechanism. Currently, the industry lacks a feasible solution for efficiently and standardizedly implementing cross-chip interrupt propagation in a multi-chip architecture based on chip interconnect protocols. This leads to complex system design, high software overhead, and difficulty in guaranteeing the real-time performance and reliability of interrupts, becoming a key bottleneck restricting the widespread application of chip interconnect technology. Summary of the Invention

[0006] In view of this, the present invention aims to provide a method and apparatus for implementing interrupt cross-chip transfer in a multi-chip system based on a chip interconnect interface protocol, so as to solve the problems of design complexity and low efficiency caused by the lack of an effective interrupt transfer mechanism in the prior art.

[0007] To achieve the above objectives, the present invention provides a multi-chip system interrupt propagation method, which transmits local interrupt messages received by at least one functional chip to the processor of at least one base chip, and controls the interrupt action of the processor of the base chip. The method is characterized by comprising: receiving and aggregating local interrupt messages to be reported to the base chip by controlling the interrupt action of a first interrupt relay configured in the functional chip; initiating an AXI write request by the first interrupt relay, writing the local interrupt message containing a global interrupt identifier to a specific target address pre-allocated by system software, wherein the specific target address points to the address space of the base chip; encapsulating the AXI write request into a data packet in the chip interconnect protocol format by the chip interconnect protocol controller of the functional chip, and sending it to the base chip; receiving the data packet by the chip interconnect protocol controller of the base chip, and parsing it back into an AXI write request; writing the local interrupt message to the corresponding address according to the specific target address in the restored AXI write request; and triggering an interrupt in the processor of the base chip in response to the writing of the local interrupt message.

[0008] Furthermore, preferably, in the multi-chip system interrupt transmission method of the present invention, writing the local interrupt message to the corresponding address includes: if the interrupt controller of the basic chip supports message signal interrupt, then the local interrupt message is directly written to the message register of the interrupt controller to trigger an interrupt.

[0009] Furthermore, preferably, in the multi-chip system interrupt transmission method of the present invention, writing the local interrupt message to the corresponding address includes: if the interrupt controller of the base chip does not support message signal interrupt, then writing the local interrupt message to a second interrupt repeater located on the base chip; the second interrupt repeater parses the local interrupt message and drives its output pin to generate a level signal, which triggers the interrupt controller through the interrupt line.

[0010] Furthermore, preferably, in the multi-chip system interrupt propagation method of the present invention, the global interrupt identifier and the specific target address are uniformly allocated and configured to the hardware module by the system software on the basic chip during the system initialization phase.

[0011] Furthermore, preferably, the present invention also provides a chip for implementing any of the above-described multi-chip system interrupt propagation methods, wherein the chip is integrated as a functional chip in the multi-chip system, and the chip includes: at least one local interrupt source; at least one interrupt relay connected to the at least one local interrupt source, configured to receive and aggregate local interrupt information and generate a local interrupt message containing a global interrupt identifier; a bus interface configured to encapsulate the local interrupt message into an AXI write request; and a chip interconnect protocol controller connected to the bus interface, configured to encapsulate the AXI write request into a data packet conforming to the chip interconnect interface protocol and send it to the base chip via a physical link.

[0012] Furthermore, preferably, the present invention also provides a chip for implementing any of the above-described multi-chip system interrupt propagation methods, wherein the chip is integrated as a basic chip in the multi-chip system, and the chip includes: a chip interconnect protocol controller configured to receive data packets conforming to the chip interconnect interface protocol from functional chips and parse them into AXI write requests, wherein the AXI write requests contain local interrupt messages; a system interconnect bus connected to the chip interconnect protocol controller; an interrupt handling module connected to the system interconnect bus, configured to trigger a processor interrupt in response to a write operation to a specific target address by the AXI write request; and a processor connected to the interrupt handling module, configured to respond to the interrupt.

[0013] Furthermore, preferably, in the chip of the present invention, the interrupt handling module is an interrupt controller that supports message signal interrupts; the specific target address of the AXI write request points to the message register address of the interrupt controller.

[0014] Furthermore, preferably, in the chip of the present invention, the interrupt handling module includes: an interrupt controller, which receives an interrupt signal through an interrupt line; and an interrupt repeater, connected between the system interconnect bus and the interrupt controller, configured to receive and parse the local interrupt message from the system interconnect bus, and generate an interrupt signal to the interrupt controller by driving the interrupt line.

[0015] Furthermore, preferably, the present invention also provides a multi-chip system employing any of the above-mentioned multi-chip system interrupt transmission methods, wherein the functional chip and the basic chip are connected via a chip interconnect interface protocol link.

[0016] This invention cleverly solves the problem of transmitting interrupt signals across physical chips by "packaging" interrupt information into a standard memory write transaction (AXI write request) and transmitting it using existing chip interconnect protocol channels designed for data transmission. Specific advantages are as follows: Standardization and reusability: Fully utilizes the mature AXI bus and chip interconnect protocol stack, eliminating the need to define additional proprietary interrupt physical links or protocols, resulting in simple hardware implementation and good compatibility.

[0017] Flexibility and compatibility: Through the "interrupt repeater" and two receiving-side processing paths (directly writing to the MSI controller or converting to traditional interrupts via the repeater), it can be compatible with various interrupt controller architectures that support MSI (such as GIC ITS, AIA) and do not support MSI (such as traditional GIC, PLIC, x86 APIC), making it highly adaptable.

[0018] Centralized management: Global interrupt identifiers and target addresses are uniformly allocated by the base chip operating system / firmware, realizing centralized and transparent management of cross-chip interrupt resources and reducing software complexity.

[0019] High efficiency and reliability: It adopts a memory writing method, which ensures reliable interrupt information transmission, and can utilize the protocol's flow control, error checking and other mechanisms to ensure transmission quality. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the interrupt delivery processing principle of a multi-chip system according to a preferred embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram illustrating the interrupt delivery processing principle of a multi-chip system according to yet another preferred embodiment of the present invention.

[0022] Figure 3 This is a flowchart illustrating the interrupt delivery process of a multi-chip system according to yet another preferred embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0024] It should be noted that the "chip interconnect interface protocol" mentioned in this embodiment can be UCIe, BoW or other similar protocols; "AXI bus" is a widely used on-chip interconnect protocol, which can also be replaced by other bus protocols with similar read and write transaction functions.

[0025] Example 1: Interruption Transmission Method refer to Figure 1 and Figure 2This embodiment describes the interrupt propagation process in a system comprising a base chip and a function chip.

[0026] A. System initialization phase (software configuration) During system startup, the operating system or firmware running on the base chip performs the following configuration: Assign a globally unique interrupt identifier (Global InterruptID) to the interrupt source that needs to be reported across chips.

[0027] Determine the interrupt reception handling method: Method 1 (if the interrupt controller supports MSI): Configure the address of a message register in the interrupt controller as the target address (Message Addr).

[0028] Method 2 (if the interrupt controller does not support MSI): Deploy an interrupt repeater on the base chip and configure the address of one of its internal registers as the target address (Message Addr).

[0029] The aforementioned global interrupt identifier and target address information are written to the corresponding configuration register of the interrupt relay in the functional core via a configuration bus (such as APB). Simultaneously, the system memory map is configured to ensure that AXI write requests originating from the functional core, with target addresses belonging to the base core's address space, can be correctly routed.

[0030] B. Interrupt Triggering and Transmission (Function Chip Side) An interrupt is generated by a local interrupt source within the functional core (such as DMA completion, compute unit exception, etc.).

[0031] The interrupt is fed into the interrupt repeater within the chip. This repeater is a hardware module responsible for aggregating and managing multiple local interrupt sources.

[0032] The interrupt repeater encapsulates the corresponding Global Interrupt ID into a data segment according to the pre-configured settings, forming an interrupt message.

[0033] The interrupt repeater initiates an AXI WriteTransaction via a bus interface (such as the AXI Master interface). The target address of this request is the "Message Addr" configured during the initialization phase, and the data to be written is an interrupt message containing the global interrupt identifier.

[0034] The functional chip's interconnect protocol controller (such as a UCIe controller) monitors the system bus and captures this AXI write request destined for a remote end (base chip). It encapsulates the request's address, data, attributes, and other information according to the format of the interconnect interface protocol (such as the UCIe protocol), forming a link layer data packet (Flit / Packet), and sends it out through the physical layer link (such as the silicon interposer or encapsulated circuitry).

[0035] C. Interrupt reception and processing (basic chip side) The chip interconnect protocol controller of the basic chip receives data packets from the link, parses them to restore the original AXI write request, and submits it to the on-chip interconnect network (such as an AXI switch) of the basic chip.

[0036] Continue to refer to Figure 2 Note that, depending on whether "Method 1" or "Method 2" is configured during the initialization phase, subsequent processing follows two paths: Method 1 (Systems that support message interruption) The recovered AXI write request arrives at the on-chip interconnect network. Since the target address points to the interrupt controller's message register, the write request is routed to an interrupt controller that supports Message Signaled Interrupts (MSI), such as the ITS module of ARM GICv4 or RISC-V AIA.

[0037] The interrupt controller receives the write operation and writes the data (i.e., the global interrupt identifier) ​​into its corresponding internal message register.

[0038] The interrupt controller identifies this write as an interrupt signal, determines the interrupt source and priority based on the global interrupt identifier written, and after standard procedures such as interrupt masking and priority arbitration, sends an interrupt request to the connected CPU (such as pulling the INT line high or sending an inter-core interrupt).

[0039] When the CPU responds to an interrupt, it jumps to the corresponding interrupt service routine (ISR) for execution.

[0040] Method 2 (for systems that do not support message interruption) The recovered AXI write request is routed to the interrupt repeater on the base chip.

[0041] The interrupt repeater receives write requests and parses the global interrupt identifier from the data.

[0042] The interrupt repeater internally converts this global interrupt identifier into one (or more) specific interrupt line (IRQ Line) numbers connected to a traditional interrupt controller (such as GIC Distributor, PLIC, or x86 IOAPIC) based on a pre-stored mapping table.

[0043] The interrupt repeater drives the corresponding physical output pin to generate a low-level (or edge) signal, which is the traditional wire-interrupt.

[0044] Traditional interrupt controllers detect signal changes on the interrupt line, identify the number and prioritize it, and then report the interrupt to the CPU.

[0045] The CPU responds to the interrupt and executes the ISR. For x86 systems, after receiving a line interrupt, IOAPIC converts it into an interrupt message and sends it to the target CPU's LAPIC via the system bus. Essentially, it still utilizes message interrupts, but it is presented to the outside world as a traditional line interrupt interface.

[0046] Example 2: Functional Core Device refer to Figure 1 The functional core in this embodiment includes: Local interrupt sources: such as computing units, memory controllers, peripheral interfaces, etc.

[0047] Interrupt repeater: Includes configuration register, interrupt status register, interrupt convergence logic, and AXI master interface generation logic. It is connected to the local interrupt source and can be programmed via the configuration bus.

[0048] System interconnect bus (such as AXI bus): connects the interrupt repeater to the chip interconnect protocol controller.

[0049] Core Interconnect Protocol Controller: Implements a complete protocol stack (physical layer, link layer, transaction layer), and has the ability to encapsulate / decapsulate local AXI transactions into protocol packets.

[0050] Example 3: Basic Core Device Continue to refer to Figure 2 Note that the basic core of this embodiment includes: Core Interconnect Protocol Controller: Functionally similar to its peer module in the functional core, but in the opposite direction.

[0051] System interconnect bus.

[0052] Interrupt handling module: This module has two implementation forms: a) Type 1: An interrupt controller (such as GIC ITS) that supports Message Signal Interrupt (MSI). Its message register address space is mapped to the system bus.

[0053] b) Format 2: A traditional interrupt controller (such as a GIC Distributor) plus an interrupt repeater. The interrupt repeater has a similar structure to that in the functional chip, but its output directly drives the input interrupt line of the interrupt controller.

[0054] Processor (CPU): Connected to the interrupt handling module to respond to interrupt requests.

[0055] Example 4: Multi-chip system The system comprises at least one functional chip as described in Example 2 and a basic chip as described in Example 3. The chips are interconnected via physical links (such as microbump connections based on silicon interposers) through a chip interconnect interface protocol to form a logically unified computing system.

[0056] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

[0057] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0060] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for interrupt propagation in a multi-chip system, comprising propagating a local interrupt message received by at least one functional chip to the processor of at least one basic chip, thereby controlling the interrupt action of the processor of the basic chip, characterized in that, The method includes: By controlling the interrupt action of the first interrupt relay set in the functional core, local interrupt messages that need to be reported to the basic core are received and collected. The first interrupt relay initiates an AXI write request to write a local interrupt message containing a global interrupt identifier to a specific target address pre-allocated by the system software, wherein the specific target address points to the address space of the base chip; The AXI write request is encapsulated into a data packet in the core interconnect protocol format by the core interconnect protocol controller of the functional core and sent to the base core. The data packet is received by the chip interconnection protocol controller of the basic chip and parsed and restored into an AXI write request; The local interrupt message is written to the corresponding address based on the specific target address in the restored AXI write request; In response to the writing of the local interrupt message, a processor interrupt is triggered on the base chip.

2. The multi-chip system interrupt transmission method according to claim 1, characterized in that, Write the local interrupt message to the corresponding address, including: If the interrupt controller of the basic chip supports message signal interrupts, the local interrupt message is directly written into the message register of the interrupt controller to trigger an interrupt.

3. The multi-chip system interrupt transmission method according to claim 1, characterized in that, Write the local interrupt message to the corresponding address, including: If the interrupt controller of the base chip does not support message signal interrupts, the local interrupt message is written to the second interrupt repeater located on the base chip. The second interrupt repeater parses the local interrupt message and drives its output pin to generate a level signal, which triggers the interrupt controller through the interrupt line.

4. The multi-chip system interrupt transmission method according to any one of claims 1-3, characterized in that, The global interrupt identifier and the specific target address are uniformly allocated and configured to the hardware module by the system software on the basic chip during the system initialization phase.

5. A chip for implementing the multi-chip system interrupt transfer method as described in any one of claims 1-3, characterized in that, The chip is integrated as a functional chip in a multi-chip system, and the chip includes: At least one local interrupt source; At least one interrupt relay is connected to the at least one local interrupt source and configured to receive and aggregate local interrupt information and generate a local interrupt message containing a global interrupt identifier. The bus interface is configured to encapsulate the local interrupt message as an AXI write request; The ChipInterconnect Protocol Controller, connected to the bus interface, is configured to encapsulate the AXI write request into a data packet conforming to the ChipInterconnect interface protocol and send it to the base chip via a physical link.

6. A chip for implementing the multi-chip system interrupt transfer method as described in any one of claims 1-3, characterized in that, The chip is integrated as a basic component in a multi-chip system, and the chip includes: The ChipInterconnect Protocol Controller is configured to receive data packets conforming to the ChipInterconnect Interface Protocol from functional chips and parse them into AXI write requests, wherein the AXI write requests contain local interrupt messages; The system interconnect bus is connected to the chip interconnect protocol controller; An interrupt handling module, connected to the system interconnect bus, is configured to trigger a processor interrupt in response to a write operation to a specific target address in response to the AXI write request; A processor, connected to the interrupt handling module, is configured to respond to the interrupt.

7. The chip according to claim 6, characterized in that, The interrupt handling module is an interrupt controller that supports message signal interrupts; the specific target address of the AXI write request points to the message register address of the interrupt controller.

8. The chip according to claim 6, characterized in that, The interrupt handling module includes: The interrupt controller receives interrupt signals via the interrupt line. An interrupt repeater, connected between the system interconnect bus and the interrupt controller, is configured to receive and parse the local interrupt message from the system interconnect bus, and generate an interrupt signal to the interrupt controller by driving the interrupt line.

9. A multi-chip system employing the multi-chip system interrupt transfer method according to any one of claims 1 to 3, wherein, The functional core and the basic core are connected via a core interconnect interface protocol link.

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