FPGA Inter-Chip Data Transmission Method When Transmission Bandwidth Mismatch

Abstract

The present invention discloses a method for transmitting data between FPGA chips when there is a transmission bandwidth mismatch. The method comprises determining the required transmission rate for AD data; obtaining the actual transmission rate based on the line transmission rate and encoding method of the high-speed transceiver; obtaining the user port sampling clock frequency; determining the number of transmission lines; determining the least common multiple of the number of transmission lines and the AD data bit width, and obtaining integers P and Q; calculating parameters A, B, and C; framing the AD data obtained by A·Q samplings, and then transmitting them in B·P times through the transmitting end of an N-channel high-speed transceiver; incrementing the sequence number of subsequent AD data by 1 after each A·Q sampling of AD data; and preparing to receive AD data from each channel starting at the same sequence number. After receiving the user port clock data from B·P high-speed transceivers, the data is reframed to obtain the A·Q sampling of AD data. The present invention uses K code to improve overall transmission stability, but transmission of AD data will continue uninterrupted.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a method for transmitting data between FPGA chips when transmission bandwidth is mismatched. Background Art

[0002] Radars using broadband signals can achieve very high distance resolution. At the same time, in order to improve the radar's own anti-interference ability, radars usually have the ability to change frequency agility, which places higher requirements on the operating bandwidth of the reconnaissance and jamming system. Therefore, in order to obtain radar digital signals, an ADC with an extremely high sampling rate is usually required, which places higher requirements on the inter-chip transmission of high-speed AD data.

[0003] High-speed serial interface technology plays a huge role in FPGA inter-chip transmission. However, the single-line transmission rate limit of the LVDS protocol is 1.6Gbps. To achieve high-speed AD data transmission, multiple transmission lines must be used in parallel. This not only wastes IO resources, but also requires a closed-loop method to ensure synchronization between multiple lines.

[0004] The upper limit of the GTH single-line transmission rate based on the SerDes protocol is 13.1Gbps. However, in order to ensure the reliability of transmission, K code needs to be inserted during the transmission process, which is not conducive to the transmission of AD data, which requires continuous and uninterrupted transmission. Summary of the Invention

[0005] The object of the present invention is to provide a method for transmitting data between FPGA chips when the transmission bandwidth is mismatched, so as to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solution: a method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs, comprising the following steps:

[0007] Determine the required transmission rate of AD data based on the ADC sampling rate and AD data bit width;

[0008] According to the line transmission rate and encoding method of the high-speed transceiver, the actual transmission rate is obtained;

[0009] Calculate the user port sampling clock frequency according to the actual transmission rate and the data bit width of the high-speed transceiver user port;

[0010] Determine the number of transmission lines of the required high-speed transceiver, where the number of transmission lines is an integer;

[0011] Determine the lowest common multiple of the number of transmission lines and the AD data bit width, and calculate the integers P and Q based on the lowest common multiple;

[0012] Calculate parameters A, B, and C;

[0013] The AD data obtained by sampling A·Q times is framed and sent out in B·P times through the transmitting end of the N-channel high-speed transceiver;

[0014] After each A·Q sampling of AD data is completed, the sequence number of the AD data obtained by subsequent sampling is increased by 1;

[0015] Each channel of the receiving end of the high-speed transceiver prepares to receive AD data starting from the same sequence number. After receiving the user port clock data of B·P high-speed transceivers, it reframes the AD data obtained by A·Q sampling.

[0016] Preferably, the formula for calculating the transmission rate is:

[0017] M=W*fs

[0018] Where M is the required transmission rate for AD data, W is the AD data bit width, and fs is the ADC sampling rate.

[0019] Preferably, the formula for calculating the actual transmission rate is:

[0020] L'=L*0.8

[0021] Where L' is the actual transmission rate and L is the line transmission rate.

[0022] Preferably, the calculation formula of the sampling clock frequency is:

[0023]

[0024] Among them, G is the data bit width of the high-speed transceiver user port, L' is the actual transmission rate, f u-clk is the sampling clock frequency.

[0025] Preferably, the formula for obtaining the number of transmission lines is:

[0026]

[0027] Where M is the required transmission rate for AD data, L' is the actual transmission rate, N is the number of transmission lines, Indicates rounding up.

[0028] Preferably, the formula for obtaining integers P and Q is:

[0029] K=G*N*P=Q*W

[0030] Among them, K is the least common multiple of K and W, G is the data bit width of the high-speed transceiver user port, also expressed as the data bit width of the transmission line port, N is the number of transmission lines, and W is the AD data bit width.

[0031] Preferably, the calculation formulas for parameters A, B and C are:

[0032]

[0033] Where fs is the ADC sampling rate, G is the data bit width of the high-speed transceiver user port, and L' is the actual transmission rate.

[0034] Preferably, the encoding method is 8B10B.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The present invention frames the AD data obtained by A·Q sampling and transmits it in B·P times through the transmitting end of the N-channel high-speed transceiver. This eliminates the need to use multiple transmission lines in parallel, saves IO resources, and eliminates the need to use a closed-loop method to ensure synchronization between multiple lines.

[0037] 2. The present invention adopts the form of K code to improve the stability of the overall transmission, but the transmission of AD data will be uninterrupted. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flow chart of an embodiment of the present invention;

[0039] Figure 2 Schematic diagram of AD data (temporarily replaced by increasing numbers) at the transmitting end of a high-speed transceiver according to an embodiment of the present invention;

[0040] Figure 3 This is a GTH user-end data flow diagram after data reorganization at the transmitting end of the high-speed transceiver according to an embodiment of the present invention;

[0041] Figure 4 Schematic diagram of AD data (temporarily replaced by increasing numbers) recovered by a receiving end of a high-speed transceiver according to an embodiment of the present invention;

[0042] Figure 5 This is an AD data diagram recovered by the receiving end of the high-speed transceiver according to an embodiment of the present invention;

[0043] Figure 6 Schematic diagram of open-loop high-speed AD data inter-FPGA chip transmission based on GTH according to an embodiment of the present invention;

[0044] Figure 7 Schematic diagram of bandwidth matching, i.e., data reassembly and synchronous transmission at the transmitting end of a high-speed transceiver according to an embodiment of the present invention;

[0045] Figure 8 FIG. 4 is a schematic diagram of bandwidth matching, namely, data reassembly and synchronous reception at the receiving end of a high-speed transceiver according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] Before describing the following embodiments, the terms used in the embodiments are first explained in conjunction with the embodiments:

[0048] High-speed transceiver (GTH): is a device for high-speed signal conversion.

[0049] See also Figure 1-8 ,in, Figure 1 is a flow chart of an embodiment of the present invention; Figure 2 Schematic diagram of AD data (temporarily replaced by increasing numbers) at the transmitting end of a high-speed transceiver according to an embodiment of the present invention; Figure 3 This is a GTH user-side data flow diagram after data reorganization at the transmitter end of a high-speed transceiver according to an embodiment of the present invention. In the diagram, the data in bold is a combination of index and K code, which can ensure the normal operation of the GTH and achieve open-loop synchronization of multiple GTHs. Figure 4 Schematic diagram of AD data (temporarily replaced by increasing numbers) recovered by a receiving end of a high-speed transceiver according to an embodiment of the present invention; Figure 5 This is a diagram of AD data recovered by the receiving end of the high-speed transceiver according to an embodiment of the present invention. As can be seen from the figure, the recovered AD data pattern is consistent with that of the transmitting end; Figure 6 Schematic diagram of open-loop high-speed AD data inter-FPGA chip transmission based on GTH according to an embodiment of the present invention;

[0050] Figure 7 Schematic diagram of bandwidth matching, i.e., data reassembly and synchronous transmission at the transmitting end of a high-speed transceiver according to an embodiment of the present invention; Figure 8 Schematic diagram of bandwidth matching, i.e., data reassembly and synchronous reception, at the receiving end of a high-speed transceiver according to an embodiment of the present invention. The present invention provides a technical solution: a method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs, comprising the following steps:

[0051] The required transmission rate of AD data is determined based on the ADC sampling rate and AD data bit width.

[0052] In this embodiment, the ADC sampling rate is 6.4 GHz, the AD data bit width is 12 bits, and the formula for calculating the transmission rate is:

[0053] M=W*fs=76.8Gbps

[0054] Where M is the required transmission rate for AD data, W is the AD data bit width, and fs is the ADC sampling rate.

[0055] The actual transmission rate is obtained based on the line transmission rate and encoding method of the high-speed transceiver.

[0056] In this embodiment, the actual transmission rate is calculated as follows: L'=L*0.8=6.4 Gbps.

[0057] The user port sampling clock frequency is obtained according to the actual transmission rate and the data bit width of the high-speed transceiver user port.

[0058] In this embodiment, the data bit width of the high-speed transceiver user port is 32 bits, and the calculation formula of the sampling clock frequency is:

[0059]

[0060] In the above formula, G is the data bit width of the high-speed transceiver user port, L' is the actual transmission rate, and f u-clk is the sampling clock frequency.

[0061] The number of transmission lines of the required high-speed transceiver is determined, where the number of transmission lines is an integer.

[0062] In this embodiment, the formula for calculating the number of transmission lines is:

[0063]

[0064] In the above formula, M is the required transmission rate for AD data, L' is the actual transmission rate, N is the number of transmission lines, Indicates rounding up.

[0065] Determine the lowest common multiple of the number of transmission lines and the AD data bit width, and calculate integers P and Q based on the lowest common multiple.

[0066] In this embodiment, K=G*N*P=Q*W, wherein G is not used in the calculation process, and the calculation can be obtained:

[0067]

[0068] Calculate the parameters A, B, and C.

[0069] In this embodiment, the calculation formulas for parameters A, B, and C are:

[0070]

[0071] Where fs is the ADC sampling rate, G is the data bit width of the high-speed transceiver user port, and L' is the actual transmission rate;

[0072] From the above formula, we can conclude that:

[0073] A=1

[0074] B=1

[0075] C=1

[0076] The AD data obtained by sampling A·Q times is framed and sent out in B·P times through the transmitting end of the N-channel high-speed transceiver;

[0077] After each A·Q sampling of AD data is completed, the sequence number of the AD data obtained by subsequent sampling is increased by 1;

[0078] Each channel of the high-speed transceiver's receiving end prepares to receive AD data starting from the same sequence number. After receiving the clock data of the user ports of B·P high-speed transceivers, it reframes the AD data obtained by A·Q sampling;

[0079] In this embodiment, the AD data obtained by sampling 416 times is framed and sent out 12 times through a 13-channel high-speed transceiver. That is, after each 416 AD data samples are completed, the transmission is completed within 12 high-speed transceiver user port clocks. From the above steps, it can be seen that within the time of sampling 416 AD data, the high-speed transceiver can not only forward the AD data but also forward C times of other data, where C is 1. In the present invention, the data is set as a combination of sequence number and encoding. Specifically, K28.0 and K28.5 (1CBC) in 8B10B are used in combination with the sequence number. The K code helps the GTH work stably, and the sequence number solves the synchronization problem of multiple GTHs. The K code helps the high-speed transceiver work stably, and the sequence number solves the synchronization problem of multiple high-speed transceivers.

[0080] In an optional implementation, the encoding method is 8B10B, specifically 1CBC encoding, which can better improve the working stability of the high-speed transceiver.

[0081] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs, characterized in that: The steps include: Determine the required transmission rate of AD data based on the ADC sampling rate and AD data bit width; According to the line transmission rate and encoding method of the high-speed transceiver, the actual transmission rate is obtained; Calculate the user port sampling clock frequency according to the actual transmission rate and the data bit width of the high-speed transceiver user port; Determining the required number of transmission lines of the high-speed transceiver, wherein the number of transmission lines is an integer; Determine the least common multiple of the number of transmission lines and the AD data bit width, and calculate integers P and Q based on the least common multiple; Calculate parameters A, B, and C; The AD data obtained by sampling A·Q times is framed and sent out in B·P times through the transmitting end of the N-channel high-speed transceiver; After each A·Q sampling of AD data is completed, the sequence number of the AD data obtained by subsequent sampling is increased by 1; Each channel of the receiving end of the high-speed transceiver prepares to receive the AD data starting from the same sequence number. After receiving B·P user port clock data of the high-speed transceiver, it reframes to obtain AD data obtained by A·Q sampling.

2. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 1, wherein: The formula for calculating the transmission rate is: M=W*fs Where M is the required transmission rate for AD data, W is the AD data bit width, and fs is the ADC sampling rate.

3. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 1, wherein: The formula for calculating the actual transmission rate is: L'=L*0.8 Where L' is the actual transmission rate and L is the line transmission rate.

4. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 1, wherein: The calculation formula of the sampling clock frequency is: Among them, G is the data bit width of the high-speed transceiver user port, L' is the actual transmission rate, f u-clk is the sampling clock frequency.

5. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 1, wherein: The formula for calculating the number of transmission lines is: Where M is the required transmission rate for AD data, L' is the actual transmission rate, N is the number of transmission lines, Indicates rounding up.

6. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 1, wherein: The formula for obtaining the integers P and Q is: K=G*N*P=Q*W Wherein, K is the least common multiple of N and W, G is the data bit width of the high-speed transceiver user port, also expressed as the data bit width of the transmission line port, N is the number of transmission lines, and W is the AD data bit width.

7. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 6, wherein: The calculation formulas for the parameters A, B and C are: Where fs is the ADC sampling rate, G is the data bit width of the high-speed transceiver user port, and L' is the actual transmission rate.

8. The method for transmitting data between FPGA chips when transmission bandwidth mismatch occurs according to claim 1, wherein: The encoding method is 8B10B.

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