Simulation Method and System Based on SPICE Model

Abstract

The present invention belongs to the field of semiconductor simulation technology, and mainly provides a simulation method and a simulation system based on a SPICE model. A device architecture of a simulation device is established, and its electrical curve is simulated; parameters for wafer acceptance test of the simulation device are defined, and electrical tests are performed on the simulation device according to the electrical curve to obtain first electrical parameters; electrical simulation data for wafer acceptance test is obtained through simulation, and the electrical simulation data is compared with the first electrical parameters to obtain LDE input parameters and electrical change parameters for wafer acceptance test; based on the LDE input parameters and the electrical change parameters, neural network training is performed to obtain neural network weighting parameters and a neural network architecture; the obtained neural network weighting parameters and the neural network architecture are written into a model card, so as to realize the simulation of the device based on the model card of the SPICE model, which can avoid the problem that in the current LDE simulation, users need to write functions into the model card, resulting in a large amount of test work.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor simulation, and particularly relates to a simulation method and a simulation system based on a SPICE model. Background Art

[0002] The layout dependent effect (LDE) is an important phenomenon affecting devices because the stress and electric field around the devices directly affect the device performance. In the model card of the Simulation Program Integrated Circuit Emphasis (SPICE), the LDE phenomenon must be accurately described to achieve accurate SPICE to Silicon (S2S).

[0003] In the current LDE simulation of the SPICE model card, usually various LDE effects that significantly affect the electrical performance are drawn and then put into the SPICE test pattern. However, this operation will make the area of the LDE test account for more than 50% of the SPICE-related test area, resulting in more than 50% of the test resources. This not only increases the test workload but also seriously squeezes the test time of other projects. Summary of the Invention

[0004] The purpose of the present invention is to provide a simulation method and a simulation system based on a SPICE model, aiming to solve the problem of excessive consumption of test resources in the current LDE test.

[0005] The embodiment of the present application also provides a simulation method based on a SPICE model. The simulation method includes:

[0006] Establish the device architecture of the simulation device and simulate its electrical curve;

[0007] Define the parameters of the wafer acceptance test for the simulation device, and perform electrical tests on the simulation device according to the electrical curve to obtain the first electrical parameters;

[0008] Obtain the electrical simulation data of the wafer acceptance test through simulation, and compare the electrical simulation data with the first electrical parameters to obtain the LDE input parameters and the electrical change parameters of the wafer acceptance test;

[0009] Perform neural network training based on the LDE input parameters and the electrical change parameters to obtain the neural network weighted parameters and the neural network architecture;

[0010] Write the obtained neural network weighted parameters and the neural network architecture into the model card.

[0011] In one embodiment, the neural network training based on the LDE input parameters and the electrical property change parameters includes:

[0012] Regarding the LDE input parameters as the input data for the neural network training;

[0013] Regarding the electrical property change parameters of the wafer acceptance test as the output data for the neural network training.

[0014] In one embodiment, the LDE input parameters include source-drain region size parameters, and the first electrical parameters include threshold voltage, on-current, and leakage current;

[0015] The electrical property change parameters of the wafer acceptance test are △VT / △Ion, where △VT is the change in threshold voltage and △Ion is the change in on-current.

[0016] In one embodiment, defining the parameters of the wafer acceptance test for the simulation device and performing electrical tests on the simulation device according to the electrical property curve to obtain the first electrical parameters includes:

[0017] Using TCAD simulation software to simulate the IV curve of the device based on the defined wafer acceptance test and performing electrical tests on the simulation device to obtain the first electrical parameters.

[0018] In one embodiment, the electrical property curve includes an IV curve and a CV curve.

[0019] In one embodiment, establishing the device architecture of the simulation device includes:

[0020] Using TCAD simulation software to establish the device architecture of the simulation device and simulate its IV curve and CV curve.

[0021] The second aspect of the embodiments of the present application also provides a simulation system based on the SPICE model. The simulation system includes:

[0022] A model establishment module for establishing the device architecture of the simulation device and simulating its electrical property curve;

[0023] A test simulation module for defining the parameters of the wafer acceptance test for the simulation device and performing electrical tests on the simulation device according to the electrical property curve to obtain the first electrical parameters;

[0024] A test comparison module for obtaining electrical simulation data of the wafer acceptance test through simulation and comparing the electrical simulation data with the first electrical parameters to obtain the LDE input parameters and the electrical property change parameters of the wafer acceptance test;

[0025] A training module, configured to perform neural network-like training based on the LDE input parameters and the electrical property change parameters to obtain neural network-like weighting parameters and a neural network-like architecture;

[0026] A model import module, configured to write the obtained neural network-like weighting parameters and the neural network-like architecture into a model card.

[0027] In one embodiment, the training module is specifically configured to:

[0028] Regard the LDE input parameters as the input data for the neural network-like training;

[0029] Regard the electrical property change parameters of the wafer acceptance test as the output data for the neural network-like training.

[0030] In one embodiment, the LDE input parameters include source-drain region size parameters, and the first electrical parameters include threshold voltage, on-current, and leakage current;

[0031] The electrical property change parameters of the wafer acceptance test are △VT / △Ion, where △VT is the change in threshold voltage and △Ion is the change in on-current.

[0032] In one embodiment, the test simulation module is specifically configured to:

[0033] Use TCAD simulation software to obtain the IV curve of the device based on the defined wafer acceptance test simulation, and perform electrical tests on the simulated device to obtain the first electrical parameters.

[0034] The embodiments of the present application provide a simulation method and a simulation system based on a SPICE model, which establish the device architecture of a simulated device and simulate its electrical curve; define the parameters of the wafer acceptance test of the simulated device, and perform electrical tests on the simulated device according to the electrical curve to obtain the first electrical parameters; obtain the electrical simulation data of the wafer acceptance test through simulation, and compare the electrical simulation data with the first electrical parameters to obtain the LDE input parameters and the electrical property change parameters of the wafer acceptance test; perform neural network-like training based on the LDE input parameters and the electrical property change parameters to obtain neural network-like weighting parameters and a neural network-like architecture; write the obtained neural network-like weighting parameters and the neural network-like architecture into a model card, so as to implement the simulation of the device based on the model card of the SPICE model, which can avoid the problem that the current LDE simulation requires users to write functions into the model card, resulting in a large amount of test work. Description of the Drawings

[0035] Figure 1 It is a schematic flowchart of the simulation method provided by an embodiment of the present application;

[0036] Figure 2a 、Figure 2b , Figure 2c Structural diagrams of multiple simulation devices provided by an embodiment of the present application;

[0037] Figure 3 Schematic diagram of obtaining VT and Ion from the IV curve provided by an embodiment of the present application;

[0038] Figure 4a , Figure 4b Schematic diagram of the result of neural network-like training provided by an embodiment of the present application;

[0039] Figure 5 Schematic diagram of the simulation system provided by an embodiment of the present application. Detailed implementation manners

[0040] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] The embodiment of the present application also provides a simulation method based on the SPICE model. Refer to Figure 1 as shown, the simulation method includes steps S10 to step S60.

[0042] In step S10, a device architecture of a simulation device is established, and its electrical characteristics curve is simulated.

[0043] In this embodiment, by establishing the device architecture to be simulated and simulating its electrical characteristics curve, the WAT result is defined through subsequent wafer acceptance test (WAT).

[0044] In one embodiment, the electrical characteristics curve at least includes an IV curve and a CV curve.

[0045] In this embodiment, the IV curve refers to the volt-ampere characteristic curve of the device, and the CV curve represents the capacitance-voltage relationship curve of the device.

[0046] In one embodiment, in step S10, specifically, the device architecture of the simulation device can be established by using TCAD simulation software, and its IV curve and CV curve are simulated.

[0047] The full name of TCAD is Technology Computer Aided Design, which refers to semiconductor process simulation and device simulation tools. TCAD tools can be Athena and Atlas software of Silvaco Company, or TSupprem and Medici of Synopsys Company, etc.

[0048] In step S20, the parameters for the wafer acceptance test of the simulation device are defined, and the simulation device is electrically tested according to the electrical curve to obtain the first electrical parameter.

[0049] In this embodiment, its parameters are defined through the wafer acceptance test (WAT), and the simulation device is electrically tested according to the electrical curve to obtain the first electrical parameter as the WAT result.

[0050] In a specific application embodiment, the parameters defined through the wafer acceptance test (WAT) may include the SA value of the LOD. By adjusting the SA value, the electrical curve of the simulation device also changes accordingly. At this time, the WAT results obtained from the electrical tests are also completely corresponding. In order to obtain sufficient electrical simulation data, in a specific application, multiple types of parameters can be randomly combined to form new simulation devices, and their electrical curves can be obtained.

[0051] For example, Figure 2a 、 Figure 2b 、 Figure 2c is a MOS device with 4 fins. As shown in Fig. 2a, the MOS device has multiple fins 110, which can implement multiple control channels for the MOS transistor. The source 112 and the drain 113 are respectively arranged between adjacent polysilicon gates 111.

[0052] Figure 2a 、 Figure 2b and Figure 2c are respectively the structural schematic diagrams when the SA for defining its diffusion length (Length of Diffusion, LOD) is SA = 0.1um, SA = 0.6um, and SA = 0.8um. By defining its parameters, the simulation device is electrically tested to obtain the first electrical parameter and the WAT result.

[0053] LOD is the abbreviation of Length of Diffusion, which is the effect of the change in the electrical characteristics of the device caused by the change in the distance between the gate and the shallow trench isolation (Shallow Trench Isolation, STI) in the channel extension direction of the MOS transistor. The LOD stress effect mainly affects the saturated source-drain current (Idsat) and the threshold voltage (Vth) of the device. This effect can be described by the parameters SA and SB. SA is the distance from the MOS transistor gate to one edge of the active region. Specifically, refer to Figure 2a as shown, and SB is the distance from the MOS transistor gate to the other edge of the active region.

[0054] Due to the drain-induced barrier lowering (DIBL) effect, when the drain voltage of a short-channel MOSFET increases from the linear region to the saturation region, the downward jump of its threshold voltage will be more severe. This effect is called drain-induced barrier lowering. See Figure 3 As shown, the IV curve of the device is obtained through TCAD simulation. The horizontal axis is the gate-source voltage V GS , and the vertical axis is the source-drain current I DS . According to the SA value of the LOD defined by WAT, each device with an SA value has its corresponding IV curve. Due to the DIBL effect introduced at the drain end, the drain-source voltage V DS has a great impact on the threshold voltage of the device. For example, the schematic diagram of the curve when the drain-source voltage V DS = VDD, and the schematic diagram of the curve when the drain-source voltage V DS = 0.05V. Based on the IV curve, it can be known that when the obtained V DS is different, there are also differences in the threshold voltage VT(sat) or VT(Iin) obtained from the electrical test and the on-state current Ion.

[0055] In step S30, the electrical simulation data of the wafer acceptance test is obtained through simulation, and the electrical simulation data is compared with the first electrical parameter to obtain the LDE input parameter and the electrical change parameter of the wafer acceptance test.

[0056] In this embodiment, the electrical simulation data of the wafer acceptance test (such as WAT data) is obtained through simulation, and the electrical simulation data is compared with the above first electrical parameter to obtain the LDE input parameter and the electrical change parameter of the wafer acceptance test. For example, when the SA as the LDE input parameter changes, the corresponding WAT test parameters also change correspondingly.

[0057] In one embodiment, the IV curve of the device can be obtained through TCAD simulation software based on the defined wafer acceptance test simulation, and the first electrical parameter can be obtained by performing electrical tests on the simulated device.

[0058] In step S40, based on the LDE input parameter and the electrical change parameter, neural network training is performed to obtain the neural network weighting parameter and the neural network architecture.

[0059] In one embodiment, specifically, the LDE input parameter can be used as the input data for the neural network training; the electrical change parameter of the wafer acceptance test can be used as the output data for the neural network training.

[0060] In a specific application, each piece of data collected on the chip is used as input and output for training a neural network to obtain the weighted parameters of the neural network and the neural network architecture. The electrical change parameters in the wafer acceptance test can be the electrical changes of the LDE input parameters (such as SA parameters) and the output data device WAT. For example, when the input SA = 0.1um, the corresponding WAT electrical parameter change is used as the training output data. The WAT electrical parameter changes include threshold voltage change (△VT), on-current change (Ion), leakage current change, etc. Each input SA corresponds to a set of WAT electrical parameter changes, and several SA values correspond to several sets of WAT electrical parameter changes.

[0061] In this embodiment, the powerful computing power of the neural network (NN) can be introduced to find a suitable function to fit the LDE phenomenon. Finally, by writing the training results of the NN into the model card, it can replace the time for users to think about functions and trial and error, saving a large amount of labor costs.

[0062] In one embodiment, a large number of LDE input parameters (such as parameter SA) are used as the input data for neural network training, and the electrical change parameters of the wafer acceptance test are used as the output data for neural network training. Through fitting calculations with a large amount of input data and output data, the weighted parameters of the neural network and the neural network architecture are obtained, forming a fitting function, thus avoiding a large amount of manpower and material resources to find a suitable LDE function.

[0063] In a specific application, the neural network training has a three-layer structure: an input layer, a hidden layer, and an output layer. In the input layer, variables are input into the neural network, and in the hidden layer and the output layer, calculations are performed and outputs are generated. On the hidden layer of the neural network, there are "neurons" that rely on activation functions for operations.

[0064] In a specific application embodiment, taking the backpropagation algorithm as an example, in the backpropagation algorithm, the error function is obtained through forward calculation and the gradient is calculated by backward derivation for gradient descent. Assume that K sets of LDE input parameters and electrical change parameters are used as training data. By continuously training to minimize a custom error function, which can be a sum-of-squares function. Specifically, some self-variables of the neural network are initialized, and then the initialized variables are substituted into the neural network, along with all the training data, to obtain the initial error function value. Then, the self-variables of the neural network are continuously updated so that the error function of the neural network shrinks under the updated self-variables. For example, the gradient is continuously decreased through the Newton method or the least squares method until the error function shrinks to a preset range, thus completing the neural network training.

[0065] In step S50, the obtained neural network weighted parameters and the neural network architecture are written into the model card.

[0066] The layout dependent effect (LDE) is an important phenomenon affecting devices because the stress and electric field around the device directly affect device performance. In the model card of the Simulation Program Integrated Circuit Emphasis (SPICE), the LDE phenomenon must be accurately described to achieve accurate SPICE to Silicon (S2S).

[0067] New process development or device architectures will generate new LDEs. In traditional simulation methods, users usually need to write the corresponding LDE functions into the SPICE model card for verification, which consumes a large amount of manpower and material resources. In this application, neural network training is performed using LDE input parameters and the electrical change parameters, and the obtained neural network weighted parameters and the neural network architecture are written into the model card as the LDE function to perform simulation processing on the simulated device, which can save a large amount of test resources and labor costs.

[0068] In one embodiment, the LDE input parameters include source-drain region size parameters, and the first electrical parameters include threshold voltage, on-current, and leakage current;

[0069] The electrical change parameter for the wafer acceptance test is △VT / △Ion, where △VT is the change in threshold voltage and △Ion is the change in on-current.

[0070] Referring to FIG. 4, the Y-axis is the electrical change △Vt Iin (change in VT / change in Ion), the X-axis is SA (the input function of the LOD function), Si is the representative value (median) of a large amount of data collected, the solid line Original is the result of the traditional LDE process, and users usually perform fitting optimization using polynomial functions. The dashed line Improve is the result of neural network training. Combining FIG. 4, it can be seen that the result of neural network training is better than the traditional process. The execution method is to perform input and output training on each piece of data collected on the chip to obtain the neural network weighted parameters and the neural network architecture, and then write them into the model card to obtain the fitted LDE function.

[0071] The embodiment of the present application also provides a simulation system based on the SPICE model. Referring to Figure 5 shown, the simulation system includes: a model establishment module 610, a test simulation module 620, a test comparison module 630, a training module 640, and a model import module 650.

[0072] The model building module 610 is used to build a device architecture of a simulation device and simulate its electrical curve.

[0073] In this embodiment, the device architecture of the device to be simulated is established through the model building module 610 , and its electrical curve is simulated, and a wafer acceptance test (WAT) result is obtained through subsequent WAT definition.

[0074] In this embodiment, the electrical curves include at least an IV curve and a CV curve. The IV curve refers to the volt-ampere characteristic curve of the device, and the CV curve represents the capacitance-voltage relationship curve of the device.

[0075] The test simulation module 620 is used to define parameters of a wafer acceptance test of the simulation device, and perform an electrical test on the simulation device according to the electrical curve to obtain a first electrical parameter.

[0076] In this embodiment, wafer acceptance test (WAT) parameters are defined by the test simulation module 620 , and an electrical test is performed on the simulated device according to the electrical curve to obtain a first electrical parameter as a WAT result.

[0077] The test comparison module 630 is configured to obtain electrical simulation data of a wafer acceptance test through simulation, and compare the electrical simulation data with the first electrical parameters to obtain LDE input parameters and electrical change parameters of the wafer acceptance test.

[0078] In this embodiment, the test comparison module 630 simulates and obtains electrical simulation data (e.g., WAT data) for the wafer acceptance test. The electrical simulation data is then compared with the aforementioned first electrical parameter to obtain an LDE input parameter and an electrical change parameter for the wafer acceptance test. The electrical change parameter can be a change in the LDE input parameter (e.g., SA) and the electrical property of the output data device WAT.

[0079] The training module 640 is used to perform neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture.

[0080] The training module 640 uses the LDE input parameters as input data for the neural network training; and uses the electrical property change parameters of the wafer acceptance test as output data for the neural network training.

[0081] In specific applications, every piece of data collected on the chip is used as input and output to perform neural network training to obtain neural network weighted parameters and neural network architecture.

[0082] In this embodiment, by introducing the powerful computing power of a neural network (NN), a suitable function can be found to fit the LDE phenomenon. Finally, by writing the training results of the NN into the model card, the time for users to think about functions and conduct trial and error can be replaced, saving a large amount of labor costs.

[0083] The model import module 650 is used to write the obtained weighted parameters of the neural network and the neural network architecture into the model card.

[0084] New process development or device architectures will generate new LDEs. In traditional simulation methods, users usually need to write the corresponding LDE function into the model card of SPICE for verification, which consumes a large amount of manpower and material resources. In this application, a neural network is trained using the LDE input parameters and the electrical change parameters, and the obtained weighted parameters of the neural network and the neural network architecture are written into the model card through the model import module 650, and the simulation device is simulated using the LDE function as the LDE function, which can save a large amount of test resources and labor costs.

[0085] In one embodiment, the training module 640 is specifically configured to: use the LDE input parameters as the input data for the neural network training; use the electrical change parameters of the wafer acceptance test as the output data for the neural network training.

[0086] In a specific application, each piece of data collected on the chip is used as the input and output for neural network training to obtain the weighted parameters of the neural network and the neural network architecture. By introducing the powerful computing power of a neural network (neural network, NN), a suitable function can be found to fit the LDE phenomenon. Finally, by writing the training results of the NN into the model card, the time for users to think about functions and conduct trial and error can be replaced, saving a large amount of labor costs.

[0087] In one embodiment, the LDE input parameters include source-drain region size parameters, and the first electrical parameters include threshold voltage, on-current, and leakage current; the electrical change parameters of the wafer acceptance test are ΔVT / ΔIon, where ΔVT is the change in threshold voltage and ΔIon is the change in on-current.

[0088] In one embodiment, the test simulation module 620 is specifically configured to: use TCAD simulation software to obtain the IV curve of the device based on the defined wafer acceptance test simulation, and perform electrical tests on the simulation device to obtain the first electrical parameters.

[0089] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above-mentioned division of each functional unit and module is used as an example for illustration. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of distinguishing each other and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0090] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0092] In the embodiments provided in this application, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical or other forms.

[0093] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0094] In addition, each functional unit in various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0095] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of the present application, it can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device that can carry the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0096] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included within the protection scope of the present application.

Claims

1. A simulation method based on a SPICE model, characterized in that: The simulation method comprises: Establish the device architecture of the simulation device and simulate its electrical curve; Defining parameters for a wafer acceptance test of the simulation device, and performing an electrical test on the simulation device according to the electrical curve to obtain first electrical parameters; the first electrical parameters include a threshold voltage, an on-current, and a leakage current; Obtaining electrical simulation data of a wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain LDE input parameters and electrical change parameters of the wafer acceptance test; each SA of the LDE input parameter corresponds to a set of WAT test parameters, and the electrical change parameters of the wafer acceptance test include threshold voltage change, on-current change, and leakage current change; Performing neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture; Write the obtained neural network weight parameters and neural network architecture into the model card.

2. The simulation method according to claim 1, wherein: The performing of neural network-like training based on the LDE input parameters and the electrical property change parameters includes: Taking the LDE input parameters as input data for the neural network training; The electrical property change parameters of the wafer acceptance test are used as output data of the neural network training.

3. The simulation method according to claim 2, wherein: The LDE input parameters include source and drain region size parameters, and the first electrical parameters include threshold voltage, on-current, and leakage current; The electrical change parameter of the wafer acceptance test is ΔVT / ΔIon, where ΔVT is the change in threshold voltage and ΔIon is the change in on-state current.

4. The simulation method according to claim 1, wherein: Defining parameters of a wafer acceptance test of the simulation device and performing an electrical test on the simulation device according to the electrical curve to obtain a first electrical parameter includes: The IV curve of the device is obtained by simulating the defined wafer acceptance test using TCAD simulation software, and the simulated device is electrically tested to obtain the first electrical parameter.

5. The simulation method according to claim 1, wherein: The electrical curves include IV curves and CV curves.

6. The simulation method according to claim 5, wherein: The device architecture of the simulation device is established, including: TCAD simulation software is used to establish the device architecture of the simulation device, and to simulate its IV curve and CV curve.

7. A simulation system based on a SPICE model, characterized in that: The simulation system comprises: A model building module is used to establish the device architecture of the simulation device and simulate its electrical curve; A test simulation module, configured to define parameters for a wafer acceptance test of the simulated device, and perform an electrical test on the simulated device according to the electrical curve to obtain first electrical parameters; the first electrical parameters include a threshold voltage, an on-state current, and a leakage current; a test comparison module, configured to obtain electrical simulation data of a wafer acceptance test through simulation, and compare the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test; wherein each SA of the LDE input parameter corresponds to a set of WAT test parameters, and the electrical change parameters of the wafer acceptance test include a threshold voltage change, an on-current change, and a leakage current change; A training module, configured to perform neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture; The model import module is used to write the obtained neural network-like weighted parameters and neural network-like architecture into the model card.

8. The simulation system according to claim 7, wherein: The training module is specifically used for: Taking the LDE input parameters as input data for the neural network training; The electrical property change parameters of the wafer acceptance test are used as output data of the neural network training.

9. The simulation system according to claim 7, wherein: The LDE input parameters include source and drain region size parameters, and the first electrical parameters include threshold voltage, on-current, and leakage current; The electrical change parameter of the wafer acceptance test is ΔVT / ΔIon, where ΔVT is the change in threshold voltage and ΔIon is the change in on-state current.

10. The simulation system according to claim 7, wherein: The test simulation module is specifically used for: The IV curve of the device is obtained by simulating the defined wafer acceptance test using TCAD simulation software, and the simulated device is electrically tested to obtain the first electrical parameter.

Images