Shielded gate field-effect transistor and its formation method

Abstract

This invention provides a shielded gate field-effect transistor and its formation method. Specifically, during the fabrication of the gate dielectric layer, by controlling the thickness of the dielectric layer on the trench sidewalls and the thickness on the top surface of the substrate, the thickness of the dielectric layer on the top surface of the substrate is increased while ensuring transistor performance. This enhances the protection of the top surface of the substrate, avoids substrate damage caused by the polishing process, and improves the performance of the formed device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a shielded gate field-effect transistor and a method for forming the same. Background Technology

[0002] Shielded gate field-effect transistors (SGTs) offer greater flexibility in semiconductor integrated circuit applications due to their low gate-drain capacitance (Cgd), very low on-resistance, and high breakdown voltage. Specifically, by placing a shielding electrode below the gate electrode, the gate-drain capacitance is significantly reduced. Furthermore, the drift region of the SGT exhibits a high concentration of impurity carriers, providing additional benefits to the device's breakdown voltage and consequently reducing on-resistance.

[0003] Currently, when fabricating the gate electrode of a shielded gate field-effect transistor, a back-etching process with sufficient over-etching is typically used after depositing the gate electrode material layer to ensure that the gate electrode material on the top surface of the substrate outside the trench can be completely removed. However, this also results in a large depression on the top surface of the gate electrode within the trench after back-etching, and the presence of this depression will pose many risks in subsequent processes. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming a shielded gate field-effect transistor to improve the quality of the gate electrode in the transistor device and avoid damage to the substrate.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a shielded gate field-effect transistor, comprising:

[0006] A substrate is provided, and trenches are formed in the substrate;

[0007] A shielding electrode is formed in the lower part of the trench, and an isolation layer is formed on the shielding electrode;

[0008] A thermal oxidation process is performed to form a first dielectric layer, the first dielectric layer covering at least the upper portion of the sidewalls of the trench, to form a first gate dielectric layer;

[0009] A deposition process is performed to form a second dielectric layer having a sidewall portion covering the upper portion of the sidewall of the trench, the sidewall portion constituting a second gate dielectric layer, and the second dielectric layer further having a mesa portion covering the top surface of the substrate, wherein the thickness of the mesa portion is greater than the thickness of the sidewall portion; and,

[0010] A gate electrode material layer is deposited, which fills the upper portion of the trench and also covers the top surface of the substrate. Then, a polishing process is performed on the gate electrode material layer, and the polishing stops at the mesa of the second dielectric layer to remove the gate electrode material on the top surface of the substrate.

[0011] Optionally, the thickness of the platform portion in the second medium layer is 2 to 4 times the thickness of the sidewall portion.

[0012] Optionally, the substrate has multiple trenches formed therein, and the spacing between adjacent trenches is smaller than the opening size of a single trench.

[0013] Optionally, the spacing between adjacent trenches is less than or equal to 1.0 μm, and the opening size of a single trench is greater than or equal to 1.5 μm.

[0014] Optionally, the total thickness of the first gate dielectric layer and the second gate dielectric layer is less than or equal to... And the thickness of the first gate dielectric layer is The thickness of the second gate dielectric layer is

[0015] Optionally, the second dielectric layer may be formed using atmospheric pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0016] Optionally, the substrate is made of silicon, the gate electrode material layer is made of polycrystalline silicon, and the gate electrode material layer is polished using a chemical mechanical polishing process.

[0017] Optionally, during the grinding of the gate electrode material layer, the second dielectric layer is also ground down to the top surface of the substrate, and the mesa portion of the second dielectric layer is partially consumed.

[0018] The present invention also provides a shielded gate field-effect transistor fabricated using the formation method described above, comprising:

[0019] A substrate in which trenches are formed;

[0020] A shielding electrode is formed in the lower portion of the trench;

[0021] An isolation layer is formed on the shielding electrode;

[0022] A first dielectric layer is formed at least on the upper portion of the sidewall of the trench to constitute a first gate dielectric layer;

[0023] A second dielectric layer is formed at least on the upper portion of the sidewall of the trench to constitute a second gate dielectric layer; and,

[0024] The gate electrode is filled in the upper part of the trench.

[0025] Optionally, the second dielectric layer further covers the isolation layer, and the thickness of the second dielectric layer covering the isolation layer is greater than the thickness of the second dielectric layer covering the trench sidewall.

[0026] In the method for forming a shielded gate field-effect transistor provided by this invention, the fabrication process of the gate dielectric layer is adjusted to control the thickness of the dielectric layer on the top surface of the substrate to be greater than its thickness on the trench sidewalls. This allows for increasing the thickness of the dielectric layer on the top surface of the substrate without affecting device performance. Based on this, when a subsequent polishing process is performed to form the gate electrode, the flatness advantage of the polishing process ensures the morphology of the formed gate electrode, and the top surface of the substrate is prevented from being exposed and eroded during polishing, thereby helping to guarantee the performance of the formed transistor device. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a shielded gate field-effect transistor whose substrate surface is damaged during its fabrication process.

[0028] Figure 2 This is a schematic flowchart of a method for forming a shielded gate field-effect transistor according to an embodiment of the present invention.

[0029] Figures 3-7 This is a schematic diagram of the fabrication process of a shielded gate field-effect transistor according to an embodiment of the present invention.

[0030] The reference numerals in the attached figures are as follows:

[0031] 10 / 100-substrate;

[0032] 11 / 110 - Groove;

[0033] 200 - Shielding electrode;

[0034] 210 - Shielding dielectric layer;

[0035] 300 - Isolation layer;

[0036] 410 - First dielectric layer;

[0037] 420 - Second dielectric layer;

[0038] 421 - Side wall portion;

[0039] 422-Taiwanese face;

[0040] 500a - Gate electrode material layer;

[0041] 50 / 500 - Gate electrode. Detailed Implementation

[0042] As described in the background section, the existing fabrication process of shielded gate field-effect transistors is prone to causing the top surface of the formed gate electrode to be recessed, which in turn affects the performance of the device.

[0043] To address the problems described above, one improvement is to planarize the gate electrode material layer using a chemical mechanical polishing (CMP) process after deposition. This removes the gate electrode material from the top surface of the substrate outside the trenches, allowing the remaining gate electrode material to fill the trenches and form the gate electrode. This solves the problem of a recessed top surface on the gate electrode, as described above.

[0044] However, this improvement also has certain limitations. For details, please refer to... Figure 1 As shown, for high-voltage shielded gate field-effect transistors, the opening size of their trenches is usually large, while the spacing between adjacent trenches is usually small. Therefore, during chemical mechanical polishing (CMP), the small substrate surface area between adjacent trenches is easily exposed and damaged (e.g., ...). Figure 1 As shown, the top surface of the substrate will be eroded by the polishing process, resulting in a certain loss.

[0045] Therefore, this invention further improves the fabrication method of shielded gate field-effect transistors to ensure that the gate electrode has a better morphology while avoiding damage to the top surface of the substrate. For details, please refer to... Figure 2 As shown, the method for forming the shielded gate field-effect transistor includes the following steps.

[0046] Step S100: Provide a substrate and form trenches in the substrate.

[0047] In step S200, a shielding electrode is formed in the lower part of the trench, and an isolation layer is formed on the shielding electrode.

[0048] Step S300: Perform a thermal oxidation process to form a first dielectric layer, the first dielectric layer at least covering the upper portion of the sidewalls of the trench to form a first gate dielectric layer.

[0049] Step S400: Perform a deposition process to form a second dielectric layer. The second dielectric layer has a sidewall portion covering the upper portion of the sidewall of the trench, the sidewall portion constituting a second gate dielectric layer. The second dielectric layer also has a mesa portion covering the top surface of the substrate, and the thickness of the mesa portion is greater than the thickness of the sidewall portion.

[0050] Step S500: Deposit a gate electrode material layer that fills the upper portion of the trench and also covers the top surface of the substrate. Then, perform a polishing process on the gate electrode material layer and polish until the mesa of the second dielectric layer is reached to remove the gate electrode material from the top surface of the substrate.

[0051] The following is in conjunction with the appendix Figures 3-7 The shielded gate field-effect transistor and its formation method proposed in this invention will be further described in detail with specific embodiments. Figures 3-7 This is a schematic diagram illustrating the fabrication process of a shielded gate field-effect transistor according to an embodiment of the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0052] In step S100, please refer to the following for details. Figure 3 As shown, a substrate 100 is provided, and a trench 110 is formed in the substrate 100. In subsequent processes, the trench 110 is used to sequentially accommodate a shielding electrode and a gate electrode from bottom to top.

[0053] The method for forming the trench 110 includes, for example, forming a mask layer on the top surface of the substrate 100 to define the pattern of the trench using the mask layer 600; and then etching the substrate 100 using the mask layer as a mask to form the trench 110.

[0054] In this embodiment, a high-voltage-resistant transistor device is further formed based on the trench 110, therefore the opening of the trench 110 can be configured to have a large opening size CD1. For example, the opening size CD1 of a single trench 110 can be greater than or equal to 1.5 μm, or even further greater than or equal to 2.4 μm. Furthermore, a plurality of trenches 110 are formed in the substrate 100, and the spacing size CD2 between adjacent trenches 110 is smaller than the opening size CD1 of a single trench 110. By reducing the spacing size between adjacent trenches 110, the high-voltage-resistant performance of the device can be further improved. Specifically, the spacing size CD2 between adjacent trenches 110 is, for example, less than or equal to 1.0 μm.

[0055] In step S200, continue to refer to Figure 3 As shown, a shielding electrode 200 is formed in the lower part of the trench 110, and an isolation layer 300 is formed on the shielding electrode 200, the isolation layer 300 covering the shielding electrode 200.

[0056] Furthermore, a shielding dielectric layer 210 is formed between the shielding electrode 200 and the inner wall of the trench 110. Specifically, the method for forming the shielding dielectric layer 210 and the shielding electrode 200 may include the following steps.

[0057] The first step is to form a shielding dielectric layer 210 on the inner wall of the trench 110. That is, the shielding dielectric layer 210 covers the bottom and sidewalls of the trench 110. The shielding dielectric layer 210 can be formed using a thermal oxidation process, in which case the material of the formed shielding dielectric layer 210 can include silicon oxide. Furthermore, the thickness of the shielding dielectric layer 210 can be adjusted according to the voltage withstand requirements of the shielded gate field-effect transistor formed.

[0058] The second step involves filling the trench 110 with a shielding electrode material layer, which completely fills the trench 110. The material of the shielding electrode material layer may include, for example, polycrystalline silicon, and the shielding electrode material layer may be formed using a deposition process.

[0059] The third step involves etching the shielding electrode material layer to reduce its height, thereby forming the shielding electrode 200. At this point, under the protection of the shielding dielectric layer 210, the trench sidewalls are prevented from being exposed during the re-etching of the shielding electrode material layer, thus avoiding etching damage to the trench sidewalls.

[0060] In a further embodiment, the portion of the shielding dielectric layer 210 above the shielding electrode 200 can be further removed. Specifically, the shielding dielectric layer 210 can be partially removed using a dry etching process or a wet etching process.

[0061] Next, refer to Figure 3 As shown, after the shielding electrode 200 is formed, an isolation layer 300 can be formed in the trench 110. The method for forming the isolation layer 300 specifically includes: first, filling the trench 110 with an isolation material layer (the material of the isolation material layer, for example, includes silicon oxide) using a high-density plasma (HDP) process; then, etching the isolation material layer to partially remove it, and using the remaining isolation material layer to form the isolation layer 300, which covers the top surface of the shielding electrode 200.

[0062] In step S300, please refer to the following for details. Figure 4As shown, a thermal oxidation process is performed to form a first dielectric layer 410, which at least covers the upper portion of the sidewalls of the trench 110 to form a first gate dielectric layer. Furthermore, the first dielectric layer 410 is also formed on the top surface of the substrate between adjacent trenches 110.

[0063] Specifically, the total thickness of the first gate dielectric layer and the second gate dielectric layer can be controlled to be less than or equal to... In this embodiment, the thickness of the first gate dielectric layer (i.e., the first dielectric layer 410) can be set to approximately [missing information]. Or it could be further...

[0064] In step S400, please refer to the following for details. Figure 5 As shown, a deposition process is performed to form a second dielectric layer 420, the second dielectric layer 420 having a sidewall portion 421 covering the upper portion of the sidewall of the trench 110, the sidewall portion 421 constituting a second gate dielectric layer, and the second dielectric layer 420 also having a mesa portion 422 covering the top surface of the substrate, and the thickness of the mesa portion 422 is greater than the thickness of the sidewall portion 421.

[0065] That is, the gate dielectric layer of the transistor device includes a first gate dielectric layer composed of a first dielectric layer 410 and a second gate dielectric layer composed of a second dielectric layer 420. The first dielectric layer 410, formed by a thermal oxidation process, has high density and effectively ensures the dielectric constant of the gate dielectric layer. The second gate dielectric layer is formed using a deposition process to further compensate for the total thickness of the gate dielectric layer. In this embodiment, the thickness of the second gate dielectric layer (i.e., the sidewall portion 421 of the second dielectric layer) can be set to...

[0066] Furthermore, in this embodiment, the thickness of the mesa 422 of the second dielectric layer 420 on the top surface of the substrate is further adjusted so that the thickness of the mesa 422 is sufficient to meet the consumption of the subsequent polishing process, thus preventing the top surface of the substrate 100 from being exposed and damaged during the polishing of the gate electrode material layer. Specifically, the thickness of the mesa 422 in the second dielectric layer 420 can be 2 to 4 times the thickness of its sidewall portion 421. In this way, on the one hand, the performance requirements of the fabricated transistor device can be met, and on the other hand, the protection of the dielectric layer with a large thickness on the top surface of the substrate can be ensured.

[0067] In a specific embodiment, the process parameters of the deposition process can be adjusted to make the lateral film formation rate higher than the longitudinal film formation rate during deposition, thereby resulting in the thickness of the mesa 422 of the formed second dielectric layer 420 being greater than the thickness of its sidewall portion 421. In this embodiment, atmospheric pressure chemical vapor deposition (AP-CVD) or plasma-enhanced chemical vapor deposition (PE-CVD) can be used to deposit the second dielectric layer 420, which simplifies the adjustment of process parameters and makes it easier to widen the difference between the lateral and longitudinal film formation rates. That is, under atmospheric pressure chemical vapor deposition (AP-CVD) or plasma-enhanced chemical vapor deposition (PE-CVD), the lateral film formation rate will be higher than the longitudinal film formation rate, thereby making the thickness of the mesa 422 of the formed second dielectric layer greater than the thickness of its sidewall portion 421.

[0068] Furthermore, the second dielectric layer 420 can be a silicon oxide layer. Based on this, silane can be used as the silicon source to perform the chemical vapor deposition process. For example, silane (SiH4) can be used as the reaction source to perform the chemical vapor deposition process as described above. Specifically, when using silane (SiH4) to perform plasma-enhanced chemical vapor deposition (PE-CVD), the reaction gas may further include oxygen (O2) and / or nitric oxide (N2O), and the specific reaction temperature is, for example, 200°C to 400°C.

[0069] In this embodiment, the second dielectric layer 420 also covers the top surface of the isolation layer 300, and the thickness of the top surface of the isolation layer 300 is greater than the thickness of the sidewall portion 421. It can be considered that the portion of the second dielectric layer 420 covering the top surface of the isolation layer 300 also constitutes a mesa portion of the second dielectric layer 420, and the thickness of the mesa portion on the top surface of the isolation layer 300 is the same as or close to the thickness of the mesa portion on the top surface of the substrate; that is, the thickness of the mesa portion on the top surface of the isolation layer 300 is 2 to 4 times the thickness of the sidewall portion 421. By compensating the second dielectric layer 420 on the isolation layer 300, it is beneficial to improve the isolation performance between the shielding electrode 200 below it and the gate electrode subsequently formed above it.

[0070] In a further embodiment, after forming the second dielectric layer 420, a heat treatment process is performed to further densify the second dielectric layer 420, so that the second dielectric layer 420 formed by the deposition process can be closer in structure and performance to the first dielectric layer 410 formed by thermal oxidation, thereby improving the quality of the gate dielectric layer.

[0071] In step S500, please refer to the following for details. Figure 6 and Figure 7As shown, a gate electrode material layer 500a is deposited, which fills the upper portion of the trench 110 and also covers the top surface of the substrate 100. A polishing process is then performed on the gate electrode material layer 500a, stopping at the mesa 422 of the second dielectric layer 420 to remove the gate electrode material from the top surface of the substrate 100. The remaining gate electrode material fills the upper portion of the trench 110, forming the trench gate electrode 500.

[0072] Specifically, the gate electrode material layer 500a includes, for example, polycrystalline silicon. Furthermore, a chemical mechanical polishing (CMP) process can be performed on the gate electrode material layer 500a to increase the polishing rate of the gate electrode material layer 500a.

[0073] It should be noted that, in order to ensure that the gate electrode material on the top surface of the substrate can be completely removed, a certain amount of over-polishing is usually added when polishing the gate electrode material layer 500a, which will over-polish down to the second dielectric layer 420 on the top surface of the substrate, thus consuming a certain amount of the mesa 422 on the top surface of the substrate. Since the second dielectric layer 420 in this embodiment has a relatively large thickness, it can meet the consumption amount during over-polishing, avoiding exposure and damage to the top surface of the substrate 100, and even preventing exposure of the first dielectric layer 410 on the top surface of the substrate. In particular, if the substrate 100 is made of silicon, the chemical mechanical polishing process on the polycrystalline silicon gate electrode material layer 500a also results in a large amount of polishing consumption on the silicon substrate 100. If the substrate 100 is exposed in this case, it will cause even more severe damage to the substrate 100.

[0074] Furthermore, the method for forming the shielded gate field-effect transistor further includes: forming a body region (not shown) and a source region (not shown) in a substrate 100. The body region is formed in the substrate 100 between adjacent trenches 110 and extends inward from the top surface of the substrate into the interior of the substrate; and the source region is formed within the body region and also extends inward from the top surface of the substrate into the interior of the substrate, and the bottom boundary of the source region is higher than the bottom boundary of the body region.

[0075] It should be recognized that if the top surface of the substrate 100 is damaged during the polishing process, it will affect the size of the body region and the source region, thereby damaging the performance of the device.

[0076] The structure of the shielded gate field-effect transistor fabricated using the method described above is explained in detail below. For more details, please refer to [link / reference needed]. Figure 7As shown, the shielded gate field-effect transistor includes: a trench 110 formed in a substrate 100; a shielding electrode 200 formed in a lower portion of the trench 110; a gate dielectric layer and a gate electrode 500 formed in an upper portion of the trench 110; and an isolation layer 300 located between the shielding electrode 200 and the gate electrode 500.

[0077] The gate dielectric layer includes a first gate dielectric layer formed using a first dielectric layer 410 and a second gate dielectric layer formed using a second dielectric layer 420. Specifically, the first dielectric layer 410 is formed on the upper portion of the sidewall of the trench 110 using a thermal oxidation process with self-alignment, and the first dielectric layer 410 may further be formed on the top surface of the substrate 100. The second dielectric layer 420 is formed using a deposition process. In this embodiment, the second dielectric layer 420 covers the upper portion of the sidewall of the trench 110 to form the second gate dielectric layer, and the second dielectric layer 420 also covers the top surface of the isolation layer 300 and the top surface of the substrate 100.

[0078] Furthermore, the thickness of the isolation layer 300 in the second dielectric layer 420 is greater than the thickness of the trench sidewall in the second dielectric layer 420. For example, the thickness of the isolation layer 300 in the second dielectric layer 420 is 2 to 4 times the thickness of the trench sidewall in the second dielectric layer 420, which improves the isolation performance between the gate electrode 500 and the shield electrode 200.

[0079] In summary, in the method for forming a shielded gate field-effect transistor provided in this embodiment, by adjusting the fabrication process of the gate dielectric layer, the thickness of the dielectric layer on the top surface of the substrate is made greater than the thickness on the trench sidewall. This can improve the thickness of the dielectric layer on the top surface of the substrate while ensuring device performance, effectively improving the protection strength of the top surface of the substrate, avoiding substrate damage caused by the polishing process, and improving the performance of the formed device.

[0080] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0081] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for forming a shielded gate field-effect transistor, characterized in that, include: A substrate is provided, and trenches are formed in the substrate; A shielding electrode is formed in the lower part of the trench, and an isolation layer is formed on the shielding electrode; A thermal oxidation process is performed to form a first dielectric layer, the first dielectric layer covering at least the upper portion of the sidewalls of the trench, to form a first gate dielectric layer; A deposition process with a lateral deposition rate higher than a longitudinal deposition rate is performed to form a second dielectric layer. The second dielectric layer has a sidewall portion covering the upper portion of the sidewall of the trench, the sidewall portion constituting a second gate dielectric layer. The second dielectric layer also has a mesa portion covering the top surface of the substrate, and the thickness of the mesa portion is greater than the thickness of the sidewall portion. A gate electrode material layer is deposited, which fills the upper portion of the trench and also covers the top surface of the substrate. Then, a polishing process is performed on the gate electrode material layer, and the polishing stops at the mesa of the second dielectric layer to remove the gate electrode material on the top surface of the substrate.

2. The method for forming a shielded gate field-effect transistor as described in claim 1, characterized in that, The thickness of the platform portion in the second dielectric layer is 2 to 4 times the thickness of the sidewall portion.

3. The method for forming a shielded gate field-effect transistor as described in claim 1, characterized in that, The substrate has multiple trenches formed therein, and the spacing between adjacent trenches is smaller than the opening size of a single trench.

4. The method for forming a shielded gate field-effect transistor as described in claim 3, characterized in that, The spacing between adjacent trenches is less than or equal to 1.0 μm, and the opening size of a single trench is greater than or equal to 1.5 μm.

5. The method for forming a shielded gate field-effect transistor as described in claim 1, characterized in that, The total thickness of the first gate dielectric layer and the second gate dielectric layer is less than or equal to And the thickness of the first gate dielectric layer is The thickness of the second gate dielectric layer is 6. The method for forming a shielded gate field-effect transistor as described in claim 1, characterized in that, The second dielectric layer is formed using atmospheric pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

7. The method for forming a shielded gate field-effect transistor as described in claim 1, characterized in that, The substrate is made of silicon, the gate electrode material layer is made of polycrystalline silicon, and the gate electrode material layer is polished using a chemical mechanical polishing process.

8. The method for forming a shielded gate field-effect transistor as described in claim 1, characterized in that, During the grinding of the gate electrode material layer, the second dielectric layer is also ground down to the top surface of the substrate, and the mesa portion of the second dielectric layer is partially consumed.

9. A shielded gate field-effect transistor fabricated using the formation method according to any one of claims 1-8, characterized in that, include: A substrate in which trenches are formed; A shielding electrode is formed in the lower portion of the trench; An isolation layer is formed on the shielding electrode; A first dielectric layer is formed at least on the upper portion of the sidewall of the trench to constitute a first gate dielectric layer; A second dielectric layer is formed at least on the upper portion of the sidewall of the trench to constitute a second gate dielectric layer; as well as, The gate electrode is filled in the upper part of the trench.

10. The shielded gate field-effect transistor as described in claim 9, characterized in that, The second dielectric layer also covers the isolation layer, and the thickness of the second dielectric layer covering the isolation layer is greater than the thickness of the second dielectric layer covering the trench sidewall.

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