Protection structure of GaN device and manufacturing method thereof

Abstract

The invention discloses a protection structure of a GaN device and a manufacturing method thereof. The protection structure comprises an ion implantation region arranged outside the GaN device and an ohmic contact metal layer and an interconnection structure sequentially stacked on the ion implantation region. The ion implantation region is an active region. The ion implantation region, the ohmic contact metal layer and the interconnection structure below the metal layer of the uppermost interconnection structure form a ring structure. The interconnection structure comprises a dielectric layer and a metal layer. A through hole is provided on the dielectric layer. The through hole is arranged above the upper surface of the ohmic contact metal layer or the metal layer of the interconnection structure of the next layer. Two adjacent interconnection structures are connected by a metal layer filled in the through hole. The metal layer of the interconnection structure of the lower layer is connected to the ohmic contact metal layer. The metal layer of the interconnection structure of the uppermost layer is connected to the source pad of the GaN device to form an electrostatic diffusion channel. The source of the GaN device is grounded, so the charge generated by ESD can be released, thereby improving the yield of the device in the manufacturing process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a protection structure of a GaN device and a manufacturing method thereof. Background Art

[0002] Since GaN materials have shown many advantages in high temperature, optoelectronics, high power, microwave radio frequency and other fields, GaN semiconductor technology has developed rapidly in the past 20 years. In particular, the development of GaN material epitaxial technology has enabled GaN-based devices to develop rapidly. AlGaN / GaN high electron mobility transistors (HEMTs) have broad application prospects in the microwave radio frequency and high power fields due to their high breakdown electric field and excellent electron transmission characteristics. Although GaN-based HEMT devices have a high breakdown electric field, existing electrostatic discharge (ESD) tests on GaN-based devices show that GaN-based HEMT devices are also susceptible to ESD damage.

[0003] At present, the existing anti-static methods in the production process of GaN-based HEMT devices are mostly controlled by machine parameters, adding ion fans, etc., which can prevent ESD damage to devices during the production process and improve device yield. However, the existing anti-static methods have limited effect on the electrostatic protection of GaN-based HEMT devices. In particular, during electrical testing and packaging, it is easy for the HEMT device to be broken down due to static electricity accumulation, resulting in damage to the HEMT device.

[0004] The existing ESD protection ring is generally provided separately and uses devices such as transistors, diodes or capacitors to form an ESD protection circuit, which occupies a certain device area, thereby increasing the device area, making the structure complex and the cost relatively high. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a protection structure for a GaN device and a method for manufacturing the same.

[0006] In order to achieve the above purpose, the technical solution of the present invention is:

[0007] A protection structure for a GaN device comprises an ion implantation region, an ohmic contact metal layer and a plurality of interconnection structures stacked in sequence above the ion implantation region, the interconnection structure comprising a dielectric layer and a metal layer, the ion implantation region, the ohmic contact metal layer and the interconnection structure below the metal layer of the uppermost interconnection structure constitute a ring structure surrounding the GaN device, the area between the ion implantation region and the GaN device is a passive area, the ion implantation region is an active area, the dielectric layer of the interconnection structure covers the upper surface and sidewalls of all interconnection structures or the ohmic contact metal layer below it, and a through hole is provided above the metal layer of the interconnection structure of the next layer or the upper surface of the ohmic contact metal layer, the metal layer of the interconnection structure covers above the through hole and is connected to the metal layer of the interconnection structure of the next layer or the ohmic contact metal layer, and the metal layer of the uppermost interconnection structure is connected to the source of the GaN device.

[0008] In some embodiments, the metal layer in the interconnect structure is filled in a through hole of the dielectric layer and extends to the dielectric layer at both ends of the through hole.

[0009] In some embodiments, the through hole is a closed annular through hole that is consistent with the circumferential direction of the annular structure.

[0010] In some embodiments, closed-loop openings are provided at different positions of metal layers of interconnect structures of different layers, and the closed-loop openings communicate the inner side and the outer side of the annular structure.

[0011] In some embodiments, the projection area of ​​the metal layer of the interconnection structure on the ion implantation region is located within the projection area of ​​the metal layer of the interconnection structure of the next layer or the ohmic contact metal layer on the ion implantation region, and the side edge of the metal layer of the interconnection structure is 1-3 microns away from the side edge of the metal layer of the interconnection structure of the next layer or the ohmic contact metal layer.

[0012] In some embodiments, the side edge of the through hole of the dielectric layer of the interconnect structure is 2-4 microns away from the side edge of the metal layer or ohmic contact metal layer of the next interconnect structure.

[0013] In some embodiments, the ion implantation region includes an inner edge and an outer edge, and two side edges of the ohmic contact metal layer are 1-3 microns away from the inner edge and the outer edge, respectively.

[0014] In some embodiments, the metal layer of the topmost interconnect structure includes a surrounding portion and an external portion, the surrounding portion is arranged above the dielectric layer of the topmost interconnect structure and surrounds the annular structure to form a semi-annular structure, one end of the external portion is connected to the source pad of the GaN device, and the other end is respectively connected to the ends of the semi-annular structure.

[0015] In some embodiments, the ohmic contact metal layer and the metal layer are Ti / Pt / Au / Ti, and the dielectric layer is SiN, SiO2 or SiON.

[0016] A method for manufacturing a protective structure based on the above-mentioned GaN device comprises the following steps:

[0017] 1) providing a wafer structure having a GaN device, and forming an ion implantation region on a GaN epitaxial layer of the wafer structure by an ion implantation process, wherein a region between the ion implantation region and the GaN device is a passive region, and the ion implantation region is an active region;

[0018] 2) fabricating an ohmic contact metal layer on the ion implantation region by using photolithography and evaporation processes;

[0019] 3) depositing a dielectric layer and etching to form a through hole, wherein the through hole is disposed above the upper surface of the ohmic contact metal layer or the next metal layer;

[0020] 4) using photolithography and evaporation processes to manufacture a metal layer, wherein the metal layer is filled in the through hole and connected to the ohmic contact metal layer or a metal layer of a next layer;

[0021] 5) Repeat steps 3-4 to produce a plurality of dielectric layers and metal layers stacked in sequence to form a plurality of interconnect structures, wherein the ion implantation region, the ohmic contact metal layer, and the interconnect structure below the metal layer of the topmost interconnect structure constitute a ring structure surrounding the GaN device, and the metal layer of the topmost interconnect structure is connected to the source of the GaN device.

[0022] The beneficial effects of the present invention are:

[0023] (1) The presence of ESD during the manufacturing process of the GaN device of the present invention will cause a high electric field to exist around the device. By providing a protective structure around the GaN device and connecting the protective structure to the source of the GaN device, the source of the GaN device is grounded, and the high electric field generated by static electricity can be isolated, thereby reducing the impact of ESD on active devices.

[0024] (2) The present invention forms a protective structure for GaN devices by stacking interconnect structures in sequence and the metal layers connected to each other, thereby protecting GaN devices, reducing the impact of ESD, and effectively improving the yield to more than 90%. The more layers of the interconnect structure, the stronger the ability to resist ESD.

[0025] (3) The present invention forms an ion implantation area by means of an ion implantation process, and then forms an ohmic contact metal layer and an interconnection structure on the ion implantation area in sequence through processes such as evaporation, passivation and etching to form a ring structure, which can protect the GaN device, prevent device damage caused by the wafer cutting process, and prevent chemical damage caused by water vapor or other pollutants, and realize electrostatic protection in the ring structure, effectively reducing the area of ​​the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a cross-sectional view of a protection structure of a GaN device according to an embodiment of the present invention;

[0027] Figure 2 FIG. 4 is a top view of a protection structure of a GaN device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The various drawings of the present invention are only for illustration to make it easier to understand the present invention, and the specific proportions can be adjusted according to design requirements. The upper and lower relationships of the relative elements and the definitions of the front / back in the figures described in the text should be understood by those skilled in the art to refer to the relative positions of the components, so they can all be flipped to present the same components, which should all fall within the scope disclosed in this specification.

[0029] Example

[0030] Taking a GaN-based HEMT device as an example, the protection structure of the GaN device and the manufacturing method thereof of the present invention are described in detail below.

[0031] refer to Figure 1 and Figure 2, the protective structure of the embodiment of the present application includes an ion implantation region 1 and an ohmic contact metal layer 2 and an interconnection structure 3 stacked in sequence above the ion implantation region 1. The ion implantation region 1, the ohmic contact metal layer 2 and the interconnection structure below the metal layer 32' of the topmost interconnection structure 3' are an annular structure surrounding the HEMT device 4. A metal connection is formed between the ohmic contact metal layer 2 and the interconnection structure 3 to form an electrostatic diffusion channel, and finally connected to the source of the HEMT device 4, so that electrostatic shielding can be achieved and the yield can be improved. The ion implantation region 1 is defined at the periphery of the HEMT device 4, and since the ion implantation region 1 can be connected to the source ground as an active region, the breakdown voltage of the device can be effectively increased and the leakage current of the device can be reduced. The ion implantation region 1 is provided with an ohmic contact metal layer 2, and the ohmic contact metal layer 2 is provided with a plurality of interconnection structures 3 stacked in sequence. The ohmic contact metal layer 2 and the interconnection structure 3 are made above the ion implantation region 1, and the metal of the ohmic contact metal layer 2 and the interconnection structure 3 can be interconnected with the 2DEG of the HEMT device 4. The ion implantation area 1 is an annular area surrounding the HEMT device 4, and the annular area includes an inner edge and an outer edge, and the width between the inner edge and the outer edge is 20-50 microns. There is a passive area (i.e., an insulating area) between the ion implantation area 1 and the GaN device, and the ion implantation area 1 is an active area, so the ESD generated during the process can be conducted to the protective structure for grounding. The annular structure formed above the ion implantation area 1 can not only achieve the effect of anti-ESD, but also protect the GaN device, prevent device damage caused by the wafer cutting process, and prevent chemical damage caused by water vapor or other pollutants.

[0032] In a specific embodiment, the ohmic contact metal layer 2 is disposed between the inner edge and the outer edge of the annular region, and the two sides of the ohmic contact metal layer 2 are 1-3 microns away from the inner edge and the outer edge, respectively, preferably 1 micron. A plurality of interconnection structures 3 are stacked in sequence above the ohmic contact metal layer 2, wherein each of the interconnection structures 3 is composed of a dielectric layer 31 and a metal layer 32 thereon, and the dielectric layer 31 has a through hole 5, and the through hole 5 is disposed above the metal layer of the interconnection structure of the next layer or the upper surface of the ohmic contact metal layer 2, with a width range of 10-30 microns, and the shape of the projection area of ​​the through hole 5 on the ion implantation region 1 is annular, specifically a closed annular through hole corresponding to the surrounding range of the annular structure. The metal layer 32 is filled in the through hole 5 of the dielectric layer 31 and extends to the dielectric layer 31 at both ends of the through hole 5, and the metal layers 32 between two adjacent interconnection structures 3 are stacked in sequence, and the metal layer 32 filled in the through hole 5 forms an electrical connection between the interconnection structures 3 of the upper and lower layers, forming an electrostatic diffusion channel, and realizing electrostatic shielding. In a preferred embodiment, the ohmic contact metal layer 2 and the metal layer 32 are Ti / Pt / Au / Ti, and the dielectric layer 31 is SiN, SiO2 or SiON. The interconnection structure 3 includes a bottom interconnection structure and a top interconnection structure 3', the ohmic contact metal layer 2 and the bottom interconnection structure and two adjacent interconnection structures 3 are connected through the metal layer 32, and the metal layer 32' of the top interconnection structure 3' is connected to the source of the HEMT device 4.

[0033] In a specific embodiment, the dielectric layer of the bottom interconnect structure covers the ohmic contact metal layer 2, not only covers the upper surface and sidewall of the ohmic contact metal layer 2, but also extends to the ion implantation area 1, and the through hole 5 is provided on the upper surface of the ohmic contact metal layer 2, and the side edge of the through hole 5 is 2-4 microns away from the side edge of the ohmic contact metal layer 2, preferably 2 microns. The metal layer of the bottom interconnect structure covers the dielectric layer, fills the through hole 5 and extends to the dielectric layer on both sides of the through hole 5, and the projection edge of the metal layer of the bottom interconnect structure on the ion implantation area 1 is located on the dielectric layer of the bottom interconnect structure and the ohmic contact metal layer 2, and the side edge of the metal layer of the bottom interconnect structure is 1-3 microns away from the side edge of the ohmic contact metal layer 2, preferably 1 micron.

[0034] Specifically, there is at least an uppermost interconnection structure 3' above the lowermost interconnection structure. In other embodiments, a plurality of adjacent interconnection structures 3 are provided between the lowermost interconnection structure and the uppermost interconnection structure 3'. The more layers of the interconnection structure 3, the better the anti-ESD effect. Two adjacent interconnection structures 3 include a first interconnection structure and a second interconnection structure below it. The projection edge of the metal layer of the first interconnection structure on the ion implantation region 1 is located on the metal layer of the second interconnection structure. The side edge of the metal layer of the first interconnection structure is 1-3 microns away from the side edge of the metal layer of the second interconnection structure. The side edge of the through hole of the dielectric layer of the first interconnection structure is 2-4 microns away from the side edge of the metal layer of the second interconnection structure, preferably 2 microns. The ohmic contact metal layer 2 and the interconnection structure film layer below the metal layer 32' of the uppermost interconnection structure 3' are annular structures arranged in the annular region. The metal layer 32 of the interconnection structure 3 has a closed loop opening, and the positions of the closed loop openings of the annular structures of the metal layers 32 of the two adjacent interconnection structures 3 are inconsistent. Since wet etching is required to strip the photoresist after the evaporation process, in order to allow the corrosive liquid to flow into the annular structure through the closed loop opening to etch the photoresist during wet etching, the metal layer 32 of the interconnect structure 3 cannot be set as a complete closed loop, otherwise the photoresist cannot be stripped.

[0035] In a specific embodiment, the metal layer 32' of the uppermost interconnect structure 3' includes a surrounding portion 321 and an external portion 322. The surrounding portion 321 is provided above the dielectric layer 31' of the uppermost interconnect structure 3' and surrounds the ion implantation region 1 to form two mutually spaced semi-annular structures. The external portion 322 is extended from both ends of each semi-annular structure toward the source of the HEMT device 4. One end of the external portion 322 is connected to the source pad 41 of the HEMT device 4, and the other end of the external portion 322 is respectively connected to the end of the semi-annular structure. Finally, the metal layer 32' of the uppermost interconnect structure 3' is connected to the source pad 41 of the HEMT device 4. During the electrical property test of the HEMT device manufacturing process, the source pad 41 of the HEMT device 4 is grounded, so that the layers inside the protection structure have equal potentials. Therefore, the charges generated by ESD during the manufacturing process can be grounded, and the charges generated by ESD can be released to protect the HEMT device 4 from electrostatic damage, thereby improving the yield of the device in the manufacturing process and increasing the yield of the HEMT device to 90%. In addition to the HEMT device, the protection structure in the embodiment of the present application can also be set on the periphery of other GaN devices.

[0036] Corresponding to the above-mentioned protection structure of the GaN device, an embodiment of the present invention further proposes a method for manufacturing a protection structure of the GaN device, which is specifically described below using a HEMT device as an example. The manufacturing method includes the following steps:

[0037] 1) providing a wafer structure having a HEMT device, and forming an ion implantation region on a GaN epitaxial layer of the wafer structure by an ion implantation process, wherein the implanted ions are N or He, and the ion implantation region is an annular region surrounding the HEMT device, and a passive region (i.e., an insulating region) is provided between the annular region and the HEMT device, and the annular region has an inner edge and an outer edge, and a width between the inner edge and the outer edge is in a range of 20-50 microns;

[0038] 2) coating a photoresist on the ion implantation area, defining an ohmic contact metal layer pattern through development and exposure, depositing a metal on the ion implantation area using an evaporation process, wherein the deposited metal is Ti / Pt / Au / Ti, and then stripping the photoresist using a chemical solution such as N-methylpyrrolidone, leaving the desired metal pattern to form an ohmic contact metal layer, wherein the width of the ohmic contact metal layer is 1-3 microns smaller than that of the ion implantation area;

[0039] 3) depositing a dielectric layer by PECVD, wherein the dielectric layer is SiN or SiO2 or SiON, defining a through-hole pattern by photoresist, etching the dielectric layer by dry etching to form a through-hole, and then stripping the photoresist, wherein the through-hole is arranged above the upper surface of the ohmic contact metal layer or the metal layer of the next layer, and the side of the through-hole is 2-4 microns away from the side of the ohmic contact metal layer or the metal layer of the next layer, preferably 2 microns;

[0040] 4) coating a photoresist on the ion implantation area, defining a metal layer pattern through development and exposure, depositing a metal by an evaporation process, wherein the deposited metal is Ti / Pt / Au / Ti, and then stripping the photoresist with a chemical solution such as N-methylpyrrolidone, leaving a desired metal pattern to form a metal layer, wherein the metal layer is filled in the through hole and extends to the dielectric layer on both sides of the through hole, wherein a projection area of ​​the metal layer on the ion implantation area is located within a projection area of ​​the ohmic contact metal layer or a metal layer of a next layer on the ion implantation area, and a side edge of the metal layer is 1-3 microns away from a side edge of the ohmic contact metal layer of a next layer or a metal layer of an interconnection structure;

[0041] 5) Repeat steps 3-4 to manufacture a plurality of dielectric layers and metal layers, stack them to form a plurality of interconnect structures, two adjacent interconnect structures are connected by the metal layer, the ion implantation region, the ohmic contact metal layer and the interconnect structure below the metal layer of the top interconnect structure form a ring structure surrounding the HEMT device, and the metal layer of the top interconnect structure is connected to the source of the HEMT device.

[0042] Since the source of the HEMT device is grounded, the internal layers of the protection structure are kept at equal potential, and the charge generated by ESD is grounded, thereby releasing the charge generated by ESD, so that the protection structure of the HEMT device has an electrostatic protection function, and improves the yield of the device in the process. The above-mentioned method for making the protection structure is not only applicable to HEMT devices, but also to other GaN devices.

[0043] The protection structure of the embodiment of the present application has an ESD protection structure. A sealing ring is provided on the periphery of the HEMT device and no ESD protection structure is provided as a comparative example. The yield of the HEMT device process of the protection structure of the embodiment of the present application and the comparative example is compared. The results are shown in the following table:

[0044] Yield Example 90％ Comparative Example 60％

[0045] By comparing with the comparative example, it can be seen that the protection structure of the embodiment of the present application can effectively improve the yield of the HEMT device process, and does not occupy too much area in structure, and can achieve a very good protection effect.

[0046] The above embodiments are only used to further illustrate a protective structure of a GaN device and a manufacturing method thereof of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A protection structure for a GaN device, characterized in that: The invention comprises an ion implantation region formed on a GaN epitaxial layer, an ohmic contact metal layer and a plurality of interconnection structures stacked in sequence above the ion implantation region, wherein the interconnection structure comprises a dielectric layer and a metal layer, wherein the ion implantation region, the ohmic contact metal layer and the interconnection structure below the metal layer of the uppermost interconnection structure form an annular structure surrounding the GaN device, wherein the region between the ion implantation region and the GaN device is a passive region, and the ion implantation region is an active region, wherein the dielectric layer of the interconnection structure covers the upper surface and sidewalls of all interconnection structures or the ohmic contact metal layer below it, and a through hole is provided above the metal layer of the interconnection structure of the next layer or the upper surface of the ohmic contact metal layer, wherein the metal layer of the interconnection structure covers above the through hole and is connected to the metal layer of the interconnection structure of the next layer or the ohmic contact metal layer, wherein the metal layer of the uppermost interconnection structure is connected to the source of the GaN device, and wherein the metal layer of the uppermost interconnection structure comprises a surrounding portion, wherein the surrounding portion is provided above the dielectric layer of the uppermost interconnection structure and surrounds the annular structure to form two semi-annular structures spaced from each other.

2. The protection structure of the GaN device according to claim 1, characterized in that: The metal layer in the interconnection structure is filled in the through hole of the dielectric layer and extends to the dielectric layer at both ends of the through hole.

3. The protection structure of the GaN device according to claim 1, characterized in that: The through hole is a closed annular through hole which is consistent with the circumferential direction of the annular structure.

4. The protection structure of the GaN device according to claim 1, characterized in that: Closed-loop openings are provided at different positions of the metal layers of the interconnection structures of different layers, and the closed-loop openings communicate the inner side and the outer side of the annular structure.

5. The protection structure of the GaN device according to claim 1, characterized in that: The projection area of ​​the metal layer of the interconnection structure on the ion implantation area is located within the projection area of ​​the metal layer of the interconnection structure of the next layer or the ohmic contact metal layer on the ion implantation area, and the side edge of the metal layer of the interconnection structure is 1-3 microns away from the side edge of the metal layer of the interconnection structure of the next layer or the ohmic contact metal layer.

6. The protection structure of the GaN device according to claim 1, characterized in that: The side edge of the through hole of the dielectric layer of the interconnection structure is 2-4 microns away from the side edge of the metal layer or ohmic contact metal layer of the next interconnection structure.

7. The protection structure of the GaN device according to claim 1, characterized in that: The ion implantation region comprises an inner edge and an outer edge, and two side edges of the ohmic contact metal layer are respectively 1-3 microns away from the inner edge and the outer edge.

8. The protection structure of the GaN device according to claim 1, characterized in that: The metal layer of the uppermost interconnect structure further includes an external connection portion, one end of which is connected to the source pad of the GaN device, and the other end of which is respectively connected to the ends of the semi-ring structure.

9. The protection structure of the GaN device according to claim 1, characterized in that: The ohmic contact metal layer and the metal layer are Ti / Pt / Au / Ti, and the dielectric layer is SiN, SiO2 or SiON.

10. A method for manufacturing a protection structure of a GaN device according to any one of claims 1 to 9, characterized in that: The following steps are involved: 1) Providing a wafer structure having a GaN device, and forming an ion implantation region on a GaN epitaxial layer of the wafer structure by an ion implantation process, wherein a region between the ion implantation region and the GaN device is a passive region, and the ion implantation region is an active region; 2) fabricating an ohmic contact metal layer on the ion implantation area by photolithography and evaporation process; 3) depositing a dielectric layer and etching to form a through hole, wherein the through hole is disposed above the upper surface of the ohmic contact metal layer or the next metal layer; 4) using photolithography and evaporation processes to manufacture a metal layer, wherein the metal layer is filled in the through hole and connected to the ohmic contact metal layer or a metal layer of a next layer; 5) Repeat steps 3)-4) to produce a plurality of dielectric layers and metal layers stacked in sequence to form a plurality of interconnect structures, wherein the ion implantation region, the ohmic contact metal layer, and the interconnect structure below the metal layer of the topmost interconnect structure constitute a ring structure surrounding the GaN device, and the metal layer of the topmost interconnect structure is connected to the source of the GaN device.

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