Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing an initial structure, the initial structure comprising a stack structure and a plurality of capacitor holes formed in the stack structure, a lower electrode being formed in each capacitor hole; forming a hard mask layer covering a top surface of the initial structure; forming a plurality of first openings by etching the hard mask layer with an etching gas; the etching gas comprising a first gas, the first gas comprising a gas containing nitrogen component and / or hydrogen component, to avoid a chemical reaction between the first gas and a material of the lower electrode. In the present disclosure, the hard mask layer is etched by the gas containing nitrogen component and / or hydrogen component, and the etching product does not react with the material of the lower electrode, thereby avoiding the loss of the material of the lower electrode, so that the formed capacitor structure has higher capacitor storage capacity.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Capacitors, as one of the important components in integrated circuits, are widely used in memory chips. Currently, integrated circuits are developing towards miniaturization, requiring corresponding integrated circuits to have higher integration density and smaller feature sizes. The feature size of capacitors will also decrease accordingly. During the capacitor manufacturing process, some of the bottom electrode material may be lost, affecting the electrical performance and yield of the capacitor. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0005] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] An initial structure is provided, the initial structure including a stacked structure and a plurality of capacitor holes formed in the stacked structure, the capacitor holes penetrating the stacked structure, and a lower electrode being formed in each capacitor hole;

[0007] A hard mask layer is formed, which covers the top surface of the initial structure;

[0008] A portion of the hard mask layer is etched by an etching gas to form a plurality of first openings in the hard mask layer, each first opening exposing a portion of the top surface of the stacked structure and a portion of the top surface of at least one of the lower electrodes;

[0009] The etching gas includes a first gas, which includes a nitrogen-containing and / or hydrogen-containing gas, to prevent the first gas from reacting with the material of the lower electrode.

[0010] According to some embodiments of this disclosure, the first gas includes nitrogen-hydrogen gases.

[0011] According to some embodiments of this disclosure, the first gas includes one or more of NH3 or N2H2.

[0012] According to some embodiments of this disclosure, forming the hard mask layer includes:

[0013] A first material is deposited, which covers the top surface of the initial structure to form a first material layer;

[0014] A second material is deposited, which covers the top surface of the first material layer to form a second material layer;

[0015] Under discharge conditions, the first material reacts with the plasma generated by the ionization of the first gas to produce volatile substances, and the first material has a higher etching selectivity than the second material.

[0016] According to some embodiments of this disclosure, the etching of a portion of the hard mask layer by etching gas includes:

[0017] The second material layer is etched with a second gas to form multiple initial openings in the second material layer;

[0018] The first material layer exposed by the first gas through the initial openings is etched until the top surface of the stacked structure is reached, thus forming the first openings.

[0019] According to some embodiments of this disclosure, the manufacturing method further includes:

[0020] Using the retained hard mask layer as a mask, the top layer of the stacked structure is etched to transfer the pattern of the first opening into the top layer, forming a plurality of capacitor opening holes in the top layer.

[0021] According to some embodiments of this disclosure, the manufacturing method further includes:

[0022] The remaining hard mask layer is removed by etching with the first gas.

[0023] According to some embodiments of this disclosure, the laminated structure includes alternately stacked sacrificial layers and support layers; the manufacturing method further includes:

[0024] According to the capacitor opening, the sacrificial layer and part of the support layer of the stacked structure are removed sequentially, and the remaining support layer forms a support structure.

[0025] According to some embodiments of this disclosure, the manufacturing method further includes:

[0026] A dielectric layer is formed, which covers the lower electrode and the support structure;

[0027] An upper electrode is formed, which covers the dielectric layer.

[0028] According to some embodiments of this disclosure, providing the initial structure includes:

[0029] A substrate is provided, and sacrificial layers and support layers are alternately formed on the substrate to form an initial stacked structure, wherein the top layer of the initial stacked structure is the support layer;

[0030] A first mask layer is formed on the top surface of the initial stacked structure;

[0031] The initial stacked structure is etched according to the first mask layer to form a plurality of capacitor holes in the initial stacked structure. The capacitor holes penetrate the initial stacked structure along the stacking direction of the initial stacked structure and expose a portion of the substrate.

[0032] The lower electrode is formed in the capacitor hole.

[0033] According to some embodiments of this disclosure, the projections formed by each of the first openings on the substrate and the projections formed by the capacitor holes on the substrate have partially overlapping regions, or the projections formed by each of the first openings on the substrate and the projections formed by some of the capacitor holes on the substrate have partially overlapping regions.

[0034] According to some embodiments of this disclosure, there is a partial overlap between the projection of each of the first openings on the substrate and the projections of the three to five capacitor holes on the substrate.

[0035] According to some embodiments of this disclosure, forming the lower electrode in the capacitor hole includes:

[0036] A deposition electrode material is formed to cover the sidewalls and bottom surface of the capacitor aperture, thus forming the lower electrode.

[0037] According to some embodiments of this disclosure, forming the lower electrode in the capacitor hole includes:

[0038] A deposition electrode material is used to fill the capacitor hole, forming the lower electrode.

[0039] A second aspect of this disclosure provides a semiconductor structure fabricated according to the semiconductor structure fabrication method described above.

[0040] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, the hard mask layer is etched by a gas containing nitrogen and / or hydrogen. The etching product does not react with the material of the lower electrode, thus avoiding material loss of the lower electrode and enabling the formed capacitor structure to have higher capacitance storage capacity.

[0041] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0043] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0044] Figure 2 This is a flowchart illustrating the provision of an initial structure according to an exemplary embodiment.

[0045] Figure 3 This is a flowchart illustrating the formation of a hard mask layer according to an exemplary embodiment.

[0046] Figure 4 This is a flowchart illustrating the formation of a plurality of first openings in a hard mask layer according to an exemplary embodiment.

[0047] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0048] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0049] Figure 7 This is a schematic diagram illustrating the formation of an initial stacked structure according to an exemplary embodiment.

[0050] Figure 8 This is a schematic diagram illustrating the formation of a plurality of capacitor holes according to an exemplary embodiment.

[0051] Figure 9 This is a schematic diagram illustrating the formation of a lower electrode according to an exemplary embodiment.

[0052] Figure 10 yes Figure 9 Top view.

[0053] Figure 11 This is a schematic diagram illustrating the formation of a hard mask layer according to an exemplary embodiment.

[0054] Figure 12 This is a schematic diagram illustrating the formation of a lower electrode according to an exemplary embodiment.

[0055] Figure 13 This is a schematic diagram illustrating the formation of a hard mask layer according to an exemplary embodiment.

[0056] Figure 14 This is a schematic diagram illustrating the formation of an initial opening according to an exemplary embodiment.

[0057] Figure 15 This is a schematic diagram illustrating the formation of a first opening according to an exemplary embodiment.

[0058] Figure 16 yes Figure 15 Top view.

[0059] Figure 17 This is a schematic diagram illustrating the formation of a capacitor opening according to an exemplary embodiment.

[0060] Figure 18 This is a schematic diagram illustrating the removal of the remaining hard mask layer according to an exemplary embodiment.

[0061] Figure 19 yes Figure 18 Top view.

[0062] Figure 20 This is a schematic diagram illustrating the removal of the second sacrificial layer according to an exemplary embodiment.

[0063] Figure 21 This is a schematic diagram illustrating the removal of the first support layer according to an exemplary embodiment.

[0064] Figure 22 This is a schematic diagram illustrating the removal of the first sacrificial layer according to an exemplary embodiment.

[0065] Figure 23 This is a schematic diagram illustrating the formation of a dielectric layer according to an exemplary embodiment.

[0066] Figure 24 This is a schematic diagram illustrating the formation of an upper electrode according to an exemplary embodiment.

[0067] Figure 25 This is a schematic diagram illustrating a formed semiconductor structure according to an exemplary embodiment.

[0068] Figure 26 yes Figure 25 A magnified view of a portion at point A.

[0069] Figure 27 This is a schematic diagram illustrating the removal of the second sacrificial layer according to an exemplary embodiment.

[0070] Figure 28 This is a schematic diagram illustrating the removal of the first support layer according to an exemplary embodiment.

[0071] Figure 29 This is a schematic diagram illustrating the removal of the first sacrificial layer according to an exemplary embodiment.

[0072] Figure 30 This is a schematic diagram illustrating the removal of the remaining hard mask layer according to an exemplary embodiment.

[0073] Figure 31 This is a schematic diagram illustrating a formed semiconductor structure according to an exemplary embodiment.

[0074] Figure label:

[0075] 01. First opening; 011. Initial opening; 02. Capacitor opening hole; 100. Initial structure; 110. Stacked structure; 110a. Initial stacked structure; 111. Sacrificial layer; 111a. First sacrificial layer; 111b. Second sacrificial layer; 112. Support layer; 112a. First support layer; 112b. Second support layer; 120. Capacitor hole; 130. Hard mask layer; 131. First material layer; 132. Second material layer; 140. Substrate; 150. Isolation layer; 160. Photoresist layer; 160a. Photoresist pattern; 170. First mask layer; 170a. First mask pattern; 200. Lower electrode; 300. Support structure; 400. Dielectric layer; 500. Upper electrode; 600. Gap filling structure. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0077] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 7-31 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 7-31 The methods for fabricating semiconductor structures are introduced.

[0078] This embodiment does not limit the semiconductor structure. The following description will take Dynamic Random Access Memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0079] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0080] Step S110: Provide an initial structure, which includes a stacked structure and a plurality of capacitor holes formed in the stacked structure. The capacitor holes penetrate the stacked structure, and a lower electrode is formed in each capacitor hole.

[0081] During the implementation of this step, such as Figure 9 Or such as Figure 12 As shown, the initial structure 100 includes a stacked structure 110, which includes alternating sacrificial layers 111 and support layers 112. The specific number and height of the sacrificial layers 111 and support layers 112 in the stacked structure 110 are set according to the height of the lower electrode 200. Multiple independently arranged capacitor holes 120 are formed in the stacked structure 110, and a lower electrode 200 is correspondingly arranged in each capacitor hole 120. The top surface of the lower electrode 200 is flush with the top surface of the stacked structure 110. The lower electrode 120 can be a cup-shaped structure or a column-shaped structure.

[0082] The sacrificial layer 111 is made of silicon oxide or BPSG (Boro-phospho-silicate glass), and may be doped with boron or phosphorus. The support layer 112 is made of any one or any combination of two or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0083] Step S120: Form a hard mask layer that covers the top surface of the initial structure.

[0084] like Figure 11 Or such as Figure 13 As shown, the hard mask layer 130 includes a first material. Under discharge conditions, the first material reacts with the plasma generated by the ionization of the first gas to produce volatile substances. Neither the volatile substances nor the plasma generated by the ionization of the first gas reacts chemically with the material of the lower electrode 200. The hard mask layer 130 can be a single-layer or multi-layer structure. When the hard mask layer 130 is a multi-layer structure, at least one layer is made of the first material. The first material can be, for example, crystalline carbon or amorphous carbon.

[0085] Step S130: Part of the hard mask layer is etched by etching gas to form a plurality of first openings in the hard mask layer, each first opening exposing a portion of the top surface of the stacked structure and a portion of the top surface of at least one lower electrode.

[0086] The etching gas includes a first gas, which comprises a nitrogen-containing and / or hydrogen-containing gas to prevent a chemical reaction between the first gas and the material of the lower electrode. For example, the first gas may include a nitrogen-hydrogen gas. For instance, the first gas may include one or more of NH3 or N2H2.

[0087] like Figure 15 As shown, refer to Figure 11 Under discharge conditions, a first gas is used to etch the hard mask layer 130, forming a first opening 01 on the hard mask layer 130. During the etching process, the first gas is ionized to generate nitrogen plasma or hydrogen plasma. The first material in the hard mask layer 130 reacts with the nitrogen plasma or hydrogen plasma to form etching products. The etching products are volatile substances containing nitrogen or hydrogen. These volatile substances escape into the process environment. The volatile substances and the plasma generated by the ionization of the first gas do not react with the lower electrode material, thus avoiding contamination of the lower electrode material by the etching products. On the other hand, once these volatile substances are generated, they will evaporate and will not be stored at the lower electrode, thus preventing damage to the lower electrode during subsequent support and improving the capacitance storage capacity of the capacitor structure.

[0088] According to an exemplary embodiment, this embodiment describes the implementation of step S110 described above. During implementation, as follows... Figure 2 As shown, according to some embodiments of this disclosure, an initial structure is provided, including the following steps:

[0089] Step S111: Provide a substrate, and alternately form a sacrificial layer and a support layer on the substrate to form an initial stacked structure. The top layer of the initial stacked structure is the support layer.

[0090] like Figure 7 As shown, substrate 140 is a semiconductor substrate, comprising a silicon-containing material. Substrate 140 may include a silicon substrate, a silicon-germanium substrate, or an SOI (silicon on insulator) substrate. In one example, an isolation layer 150 may be disposed on the top surface of substrate 140. The number of layers and the layer thickness of the initial stacked structure 110a are set according to the height of the lower electrode to be formed.

[0091] Step S112: Form a first mask layer on the top surface of the initial stacked structure.

[0092] like Figure 7 As shown, the first mask layer 170 includes a first mask pattern 170a, which exposes a portion of the top surface of the initial stacked structure 110a.

[0093] Step S113: Etch the initial stacked structure according to the first mask layer to form multiple capacitor holes in the initial stacked structure. The capacitor holes penetrate the initial stacked structure along the stacking direction of the initial stacked structure and expose part of the substrate.

[0094] like Figure 8 As shown, refer to Figure 7 Using the first mask layer 170 as a mask, the support layer 112 and the sacrificial layer 111 exposed by the first mask pattern 170a are etched sequentially to form a plurality of capacitor holes 120 penetrating the initial stacked structure 110a in the initial stacked structure 110a, and the retained initial stacked structure 110a is formed into the stacked structure 110.

[0095] Step S114: Form the lower electrode in the capacitor hole.

[0096] like Figure 9 or Figure 12 As shown, the lower electrode 200 can be a cup-shaped structure or a columnar structure. For example... Figure 9 As shown, the cup-shaped lower electrode 200 covers the sidewalls and bottom surface of the capacitor hole 120; that is, along the stacking direction of the laminated structure 110, the cross-section of the cup-shaped lower electrode 200 is U-shaped. Figure 12 The lower electrode 200 of the columnar structure shown fills the capacitor hole 120.

[0097] In some embodiments, refer to Figure 9 The lower electrode 200, which forms a cup-shaped structure in the capacitor hole 120, includes: depositing electrode material, the electrode material covering the sidewalls and bottom surface of the capacitor hole 120 to form the lower electrode 200.

[0098] Electrode material can be deposited using atomic layer deposition (ALD) process. The electrode material covers the sidewalls and bottom surface of the capacitor hole 120 and the top surface of the stacked structure 110. The electrode material covering the top surface of the stacked structure 110 is removed by etching back, and the retained electrode material forms the lower electrode 200, which covers the sidewalls and bottom surface of the capacitor hole 120.

[0099] In other embodiments, reference is made to Figure 12 The lower electrode 200, which forms a columnar structure in the capacitor aperture 120, includes: depositing electrode material to fill the capacitor aperture 120 and forming the lower electrode 200 with a columnar structure. Exemplarily, the electrode material can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0100] The material of the lower electrode 200 includes compounds formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0101] The initial structure formed in this embodiment can have a cup-shaped or columnar structure as its lower electrode. The fabrication method of this embodiment is applicable to lower electrodes with various structures, thus expanding the applicability of the fabrication method in this embodiment.

[0102] According to an exemplary embodiment, this embodiment describes the implementation of step S120 described above. During implementation, as follows... Figure 3 As shown, according to some embodiments of this disclosure, a hard mask layer is formed, including:

[0103] Step S121: Deposit a first material, which covers the top surface of the initial structure to form a first material layer.

[0104] Reference Figure 11 A first material is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes, and the first material covers the top surface of the initial structure 100 to form a first material layer 131.

[0105] Under discharge conditions, the first material reacts with the plasma generated by the ionization of the first gas to produce volatile substances. For example, the first material can be a carbide, such as crystalline carbon or amorphous carbon.

[0106] Step S122: Deposit a second material, which covers the top surface of the first material layer to form a second material layer.

[0107] Reference Figure 11 A second material is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes, and the second material covers the top surface of the first material layer 131 to form a second material layer 132.

[0108] Under the discharge conditions of the first gas, the first material has a higher etching selectivity than the second material. That is, under the discharge regulation of the first gas, the etching rate of the first material layer by the first gas is much greater than the etching rate of the second material layer. In other words, when the first gas etches the first material layer, the second material layer is in a state close to not being etched by the first gas.

[0109] For example, the second material can be any material that satisfies the above-described etching selectivity ratio. For instance, the second material can be silicon nitride, silicon oxynitride, or similar materials.

[0110] The hard mask layer formed in this embodiment includes a double-layer structure of a first material layer and a second material layer. Under discharge conditions, the first material has a high etching selectivity relative to the second material, so that the second material layer will not be etched and damaged when the first material layer is etched, thus ensuring that the first opening formed by subsequent etching has a high-precision morphology and size.

[0111] According to an exemplary embodiment, this embodiment describes the implementation of step S130 described above. During implementation, as follows... Figure 4 As shown, according to some embodiments of this disclosure, a plurality of first openings are formed in the hard mask layer by etching a portion of the hard mask layer with an etching gas, including:

[0112] Step S131: The second material layer is etched by the second gas to form multiple initial openings in the second material layer.

[0113] Reference Figure 11 , or refer to Figure 13 A photoresist layer 160 is formed on the top surface of the second material layer 132. A photoresist pattern 160a is formed on the photoresist layer 160, and the photoresist pattern 160a exposes part of the top surface of the second material layer 132.

[0114] This embodiment will be described using the cup-shaped lower electrode 200 as an example. Figure 14 As shown, refer to Figure 11 The photoresist layer 160 is used to etch the second material layer 132, forming a plurality of initial openings 011 in the second material layer 132. These initial openings 011 expose the top surface of the first material layer 131 and transfer the photoresist pattern 160a into the second material layer 132. In this embodiment, the etching gas used to etch the second material layer 132 is a second gas, which may include a fluorine-containing gas or a bromine-containing gas. For example, the second gas may be fluorine (F2), bromine (Br2), or nitrogen trifluoride (NF3).

[0115] Step S132: The first material layer exposed by the multiple initial openings is etched by the first gas until the top surface of the stacked structure is reached, forming multiple first openings.

[0116] like Figure 15 , Figure 16 As shown, refer to Figure 14The first material layer 131 exposed by the initial opening 011 is etched by the first gas. The top surface of the stacked structure 110 is used as the etching stop layer to transfer the pattern of the initial opening 011 into the first material layer 131, forming the first opening 01 in the hard mask layer 130. That is, the first opening 01 is formed based on the initial opening 011, and the first opening 01 includes the initial opening 011.

[0117] In this embodiment, when the first gas etches the first material layer, the second material layer will not react with the plasma generated by the ionization of the first gas. The size of the initial opening will not increase when the first material layer is etched, ensuring that the size of the first opening is uniform and the size accuracy of the first opening is higher.

[0118] like Figure 5 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0119] Step S210: Provide an initial structure, which includes a stacked structure and a plurality of capacitor holes formed in the stacked structure. The capacitor holes penetrate the stacked structure, and a lower electrode is formed in each capacitor hole.

[0120] The initial structure 100 includes a substrate 140, a stacked structure 110 disposed on the substrate 140, and a plurality of capacitor holes 120 disposed in the stacked structure 110, each capacitor hole 120 being filled with a lower electrode 200.

[0121] This embodiment will be described using the cup-shaped lower electrode 200 as an example. Figure 9 As shown, in this embodiment, the stacked structure 110 includes a first sacrificial layer 111a, a first support layer 112a, a second sacrificial layer 111b, and a second support layer 112b, which are sequentially stacked on the substrate 140.

[0122] Step S220: Form a hard mask layer. The hard mask layer covers the top surface of the initial structure. The hard mask layer includes a first material layer and a second material layer. The second material layer covers the top surface of the first material layer.

[0123] Step S220 in this embodiment is implemented in the same way as step S120 in the above embodiment, and will not be described again here.

[0124] Step S230: Part of the hard mask layer is etched by etching gas to form a plurality of first openings in the hard mask layer, each first opening exposing a portion of the top surface of the stacked structure and a portion of the top surface of at least one lower electrode.

[0125] like Figure 16 As shown, refer to Figure 10The projections of each first opening 01 on the substrate 140 and the projections of a capacitor hole 120 on the substrate 150 have a partially overlapping region, or the projections of each first opening 01 on the substrate 140 and the projections of some of the capacitor holes 120 on the substrate 140 have a partially overlapping region.

[0126] like Figure 16 As shown, refer to Figure 10 When there is a partial overlap between the projection of each first opening 01 on the substrate 140 and the projection of the capacitor hole 120 on the substrate 140, the area of ​​the overlapping area is 30% to 60% of the total area of ​​the projection of the capacitor hole 120 on the substrate 140.

[0127] like Figure 16 As shown, refer to Figure 10 When the projection of each first opening 01 onto the substrate 140 and the projections of some of the capacitor holes 120 onto the substrate 140 partially overlap, the capacitor holes 120 are divided into multiple groups, each group including several adjacent capacitor holes 120. The projections of each first opening 01 onto the substrate 140 and the projections of several capacitor holes 120 in a group all partially overlap. The area of ​​the overlapping region of the projections of each capacitor hole 120 is 20% to 50% of the total area of ​​the projections of the capacitor holes 120. For example, a group of capacitor holes may include two capacitor holes 120, four capacitor holes 120, six capacitor holes 120, eight capacitor holes 120, or other numbers of capacitor holes 120.

[0128] The larger the overlap area between the projection of each capacitor aperture 120 on the substrate 140 and the projection of the first opening 01 on the substrate 140, the larger the area of ​​the lower electrode 200 exposed by the first opening 01 in the capacitor aperture 120. This increases the risk of etching damage to the lower electrode 200 during the subsequent etching of the stacked structure 110. However, if the overlap area is too small, the process window for the subsequent etching of the stacked structure 110 will be too small. Therefore, in this embodiment, three to five capacitor apertures 120 are grouped together, and the projection of each first opening 01 on the substrate 140 and the projection of each of the three to five capacitor apertures 120 in each group on the substrate 140 have a partial overlap area. This ensures that the area of ​​each lower electrode 200 exposed by the first opening 01 is small, reducing the wear on the lower electrode 200 caused by the subsequent etching of the stacked structure 110, while also ensuring that the first opening 01 can provide a sufficiently large process window for the subsequent etching of the stacked structure 110, guaranteeing the smooth progress of subsequent processes.

[0129] Step S240: Using the retained hard mask layer as a mask, etch the top layer of the stacked structure to transfer the pattern of the first opening into the top layer structure, forming multiple capacitor open holes in the top layer structure.

[0130] like Figure 17 As shown, refer to Figure 15 Using the hard mask layer 130 as a mask, the second support layer 112b of the stacked structure 110 is dry etched to transfer the 01 pattern of the first opening into the second support layer 112b, forming a capacitor opening hole 02, which exposes part of the top surface of the second sacrificial layer 111b.

[0131] It should be noted that the top layer of the stacked structure 110 is the support layer 112.

[0132] In this embodiment, a first material layer 131 is provided on the top surface of the stacked structure 110 and the first material layer 131 is etched by a first gas so that no etching products reacting with the material of the lower electrode 200 are generated during the etching of the first material layer 131, thereby avoiding the etching products reacting with the material of the lower electrode 200 and damaging the lower electrode 200, and ensuring that the formed capacitor structure has a high charge storage capacity.

[0133] Step S250: Remove the remaining hard mask layer by first gas etching.

[0134] like Figure 18 As shown, refer to Figure 17 The first gas may include nitrogen- or hydrogen-based gases. In this embodiment, the first gas may include one or more of NH3 or N2H2. The etching product obtained by removing all the hard mask layer 130 with the first gas is a volatile substance containing nitrogen or hydrogen, and the etching product will not react with the material of the lower electrode 200.

[0135] Step S260: Remove the sacrificial layer and part of the support layer of the stacked structure in sequence according to the capacitor opening hole, and the remaining support layer forms the support structure.

[0136] In performing this step, such as Figure 18 , Figure 19 As shown, the capacitor opening 02 exposes part of the second sacrificial layer 111b. (As...) Figure 20 As shown, refer to Figure 18 Acid is injected into the capacitor's open hole 02 to dissolve the second sacrificial layer 111b, thereby completely removing it and exposing the first support layer 112a. Figure 21 As shown, refer to Figure 20 The pattern of the capacitor opening hole 02 is transferred to the first support layer 112a by dry etching, exposing the first sacrificial layer 111a. For example... Figure 22 As shown, refer to Figure 21 Acid is injected into the first sacrificial layer 111a through the capacitor opening hole 02, and the acid dissolves and removes all of the first sacrificial layer 111a.

[0137] Reference Figure 22 The retained first support layer 112a and second support layer 112b form a support structure 300, and a portion of the sidewall of each lower electrode 200 is covered by the support structure 300. In this embodiment, a portion of the sidewall of each lower electrode 120 in each group of capacitor holes is covered by the support structure 300. The support structure 300 connects multiple lower electrodes 200 into a whole, reducing the risk of the lower electrode 200 tipping over due to an excessively large aspect ratio.

[0138] Step S270: Form a dielectric layer that covers the lower electrode and the support structure.

[0139] like Figure 23 As shown, refer to Figure 22 The dielectric layer 400 can be deposited using atomic layer deposition (ALD). The dielectric layer 400 is made of a high-k dielectric material, which has a dielectric constant greater than that of silicon dioxide. The dielectric layer 400 covers the exposed sidewalls of the lower electrode 200 and the support structure 300.

[0140] In this embodiment, the dielectric layer 400 may be a compound containing one or more components selected from rare earth elements, Hf, Rh, Ba, and Al. Specifically, the dielectric layer 400 may be made of hafnium oxide, titanium dioxide, aluminum oxide, lanthanum oxide, etc.

[0141] Step S280: Form the upper electrode, which is covered by a dielectric layer.

[0142] like Figure 24 As shown, refer to Figure 23 The upper electrode 500 can be formed by atomic layer deposition (ALD). The material of the upper electrode 500 includes compounds formed from one or two of metal nitrides and metal silicides. In this embodiment, the material of the upper electrode 500 may include one or two of titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0143] like Figure 25 , Figure 26 As shown, refer to Figure 24 In this embodiment, after the upper electrode 500 is formed, a conductive material is deposited to fill the gaps between the upper electrodes 500, forming a gap-filling structure 600. The material of the gap-filling structure 600 includes a silicon-germanium compound.

[0144] In this embodiment, during the etching of the first support layer, a portion of the second support layer is etched away, resulting in the top surface of the remaining second support layer being lower than the top surface of the lower electrode. The semiconductor structure formed in this embodiment exposes more of the lower electrode, increasing the contact area of ​​the lower electrode and thus improving the electrical performance of the formed capacitor structure.

[0145] like Figure 6 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0146] Step S310: Provide an initial structure, which includes a stacked structure and a plurality of capacitor holes formed in the stacked structure. The capacitor holes penetrate the stacked structure, and a lower electrode is formed in each capacitor hole.

[0147] Step S320: Form a hard mask layer. The hard mask layer covers the top surface of the initial structure. The hard mask layer includes a first material layer and a second material layer. The second material layer covers the top surface of the first material layer.

[0148] Step S330: Part of the hard mask layer is etched by etching gas to form a plurality of first openings in the hard mask layer, each first opening exposing a portion of the top surface of the stacked structure and a portion of the top surface of at least one lower electrode.

[0149] Step S340: Using the retained hard mask layer as a mask, etch the top layer of the stacked structure to transfer the pattern of the first opening into the top layer structure, forming multiple capacitor open holes in the top layer structure.

[0150] Steps S310-S340 in this embodiment are implemented in the same way as steps S210-S240 in the above embodiment, and will not be described again here.

[0151] Step S350: Remove the sacrificial layer and part of the support layer of the stacked structure in sequence according to the capacitor opening hole, and the remaining support layer forms the support structure.

[0152] The difference between this embodiment and the previous embodiment is that, as Figure 27 , Figure 28 , Figure 29As shown, in this embodiment, the retained hard mask layer 130 is used as an etching buffer layer to etch the second sacrificial layer 111a, the first support layer 112a, and the second sacrificial layer 111b, so as to prevent the second support layer 112b at the top of the stacked structure 110 from being etched away when the second sacrificial layer 111a, the first support layer 112a, or the second sacrificial layer 111b of the stacked structure 110 is removed. That is to say, in this embodiment, the hard mask layer 130 is removed after the support structure is formed.

[0153] Step S360: Remove the remaining hard mask layer by first gas etching.

[0154] In this embodiment, as Figure 30 As shown, refer to Figure 29 After removing the second sacrificial layer 111a, the first support layer 112a, and the second sacrificial layer 111b of the stacked structure 110, if there are still some hard mask layers 130 remaining on the top surfaces of the support structure 300 and the lower electrode 200, the remaining hard mask layers 130 are removed by first gas etching to expose the entire top surface of the lower electrode 200 and the entire top surface of the support structure 300 for subsequent capacitor structure formation processes.

[0155] Step S370: Form a dielectric layer that covers the lower electrode and the support structure.

[0156] Step S380: Form the upper electrode, which is covered by a dielectric layer.

[0157] Steps S370-S380 in this embodiment are implemented in the same way as steps S270-S280 in the above embodiment, and will not be described again here.

[0158] The semiconductor structure in this embodiment is as follows: Figure 31 As shown, the top surface of the retained second support layer is flush with the top surface of the lower electrode. That is, the contact area between the support structure formed in this embodiment and the top of the lower electrode is larger. The support structure can provide greater support for the top of the lower electrode, and the support structure is more effective in preventing the lower electrode from tipping over. The manufacturing method of this embodiment is suitable for the process of forming a capacitor structure with a larger aspect ratio.

[0159] This disclosure provides an exemplary embodiment of a semiconductor structure, which is fabricated according to the semiconductor structure fabrication method described above. For example... Figure 25 Or such as Figure 31As shown, the semiconductor structure of this embodiment is disposed on the substrate 140. The semiconductor structure includes: a lower electrode 200, a support structure 300, a dielectric layer 400, and an upper electrode 500. The support structure 300 includes a first support layer 112a and a second support layer 112b. The first support layer 112a covers a portion of the sidewall of the middle part of the lower electrode 200, and the second support layer 112b covers a portion of the sidewall of the top part of the lower electrode 200. The top surface of the second support layer 112b is at the same height as or lower than the top surface of the lower electrode 200. The dielectric layer 400 covers the lower electrode 200 and the support structure 300, and the upper electrode 500 covers the dielectric layer 400.

[0160] According to an exemplary embodiment, such as Figure 25 Or such as Figure 31 As shown, the semiconductor structure of this embodiment also includes a gap-filling structure 600 filling the gaps between the upper electrodes 500. In this embodiment, the lower electrode structure is complete, and the charge storage capacity of the capacitor structure is higher.

[0161] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0162] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0163] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0164] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0165] It is understood that the terms "first," "second," etc., used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0166] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: An initial structure is provided, the initial structure including a stacked structure and a plurality of capacitor holes formed in the stacked structure, the capacitor holes penetrating the stacked structure, and a lower electrode being formed in each capacitor hole; A hard mask layer is formed, which covers the top surface of the initial structure; A portion of the hard mask layer is etched by an etching gas to form a plurality of first openings in the hard mask layer, each first opening exposing a portion of the top surface of the stacked structure and a portion of the top surface of at least one of the lower electrodes; The etching gas includes a first gas, which includes a nitrogen-containing and / or hydrogen-containing gas to prevent the first gas from reacting with the material of the lower electrode. The hard mask layer includes a first material. Under discharge conditions, the first material reacts with the plasma generated by the ionization of the first gas to generate volatile substances. Neither the volatile substances nor the plasma generated by the ionization of the first gas reacts chemically with the material of the lower electrode.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first gas includes nitrogen and hydrogen gases.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The first gas includes one or more of NH3 or N2H2.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of the hard mask layer includes: A first material is deposited, which covers the top surface of the initial structure to form a first material layer; A second material is deposited, which covers the top surface of the first material layer to form a second material layer; Under discharge conditions, the first material reacts with the plasma generated by the ionization of the first gas to produce volatile substances, and the first material has a higher etching selectivity than the second material.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The etching of a portion of the hard mask layer by etching gas includes: The second material layer is etched with a second gas to form multiple initial openings in the second material layer; The first material layer exposed by the first gas through the initial openings is etched until the top surface of the stacked structure is reached, thus forming the first openings.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: Using the retained hard mask layer as a mask, the top layer of the stacked structure is etched to transfer the pattern of the first opening into the top layer, forming a plurality of capacitor opening holes in the top layer.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The manufacturing method further includes: The remaining hard mask layer is removed by etching with the first gas.

8. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The stacked structure includes alternating sacrificial layers and support layers; The manufacturing method further includes: According to the capacitor opening, the sacrificial layer and part of the support layer of the stacked structure are removed sequentially, and the remaining support layer forms a support structure.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The manufacturing method further includes: A dielectric layer is formed, which covers the lower electrode and the support structure; An upper electrode is formed, which covers the dielectric layer.

10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The provision of the initial structure includes: A substrate is provided, and sacrificial layers and support layers are alternately formed on the substrate to form an initial stacked structure, wherein the top layer of the initial stacked structure is the support layer; A first mask layer is formed on the top surface of the initial stacked structure; The initial stacked structure is etched according to the first mask layer to form a plurality of capacitor holes in the initial stacked structure. The capacitor holes penetrate the initial stacked structure along the stacking direction of the initial stacked structure and expose a portion of the substrate. The lower electrode is formed in the capacitor hole.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The projections of each of the first openings on the substrate and the projections of the capacitor holes on the substrate partially overlap, or the projections of each of the first openings on the substrate and the projections of some of the capacitor holes on the substrate partially overlap.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, There is a partial overlap between the projection of each of the first openings on the substrate and the projections of the three to five capacitor holes on the substrate.

13. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The process of forming the lower electrode in the capacitor hole includes: A deposition electrode material is formed to cover the sidewalls and bottom surface of the capacitor aperture, thus forming the lower electrode.

14. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The process of forming the lower electrode in the capacitor hole includes: A deposition electrode material is used to fill the capacitor hole, forming the lower electrode.

15. A semiconductor structure, characterized in that, The semiconductor structure is fabricated according to the semiconductor structure fabrication method according to any one of claims 1 to 14.

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