Power supply generation circuit in time-interleaved charge pump

Abstract

The present invention provides a time-interleaved charge pump internal power supply generation circuit, comprising a first control signal generation module, a second control signal generation module, a time-interleaved charge pump module, and a voltage follower module. The time-interleaved charge pump internal power supply generation circuit of the present invention utilizes the time-interleaved charge pump module to alternately generate an internal power supply with a stable output greater than the power supply voltage during each cycle, boosting the power supply voltage before output, effectively achieving rail-to-rail input for a subsequent operational amplifier. Feedback provided by the voltage follower module ensures that the internal power supply remains stable and continuous during the alternating switching of the time-interleaved charge pump module, thereby improving the stability of the internal power supply and reducing voltage fluctuations of the internal power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a time-interleaved charge pump internal power supply circuit. BACKGROUND

[0002] In order to achieve rail-to-rail input stage of the operational amplifier, in addition to the structure of parallel connection of PMOS and NMOS and low threshold tube, a power supply higher than the power supply voltage can be used as a separate power supply to achieve the rail-to-rail input stage of the operational amplifier, and the power supply circuit can be realized by using a bootstrap circuit or a charge pump.

[0003] The bootstrap circuit, also known as a voltage boosting circuit, uses bootstrap diodes, bootstrap capacitors and other electronic components to superimpose the discharge voltage of the capacitor and the power supply voltage, thereby increasing the voltage. Some circuits can increase the voltage by several times the power supply voltage. The bootstrap circuit is only a name defined in practice and has no concept in theory. The bootstrap circuit is commonly used in complementary symmetric circuits of type A and type B single power supply. The charge pump is a DC-DC converter that uses capacitors as energy storage elements to generate an output voltage higher than the input voltage or a negative output voltage. The charge pump circuit has high electrical efficiency, about 90-95%, and the circuit is relatively simple. In the past decade, the charge pump has been widely used, and its function has changed from a built-in adjustment single-output IC to a built-in adjustment multi-output IC. The output power and efficiency have also been developed, so that the current charge pump can output a current of up to 250mA with an efficiency of 75%. Charge pumps are mostly used in battery-powered systems such as cellular phones, pagers, Bluetooth systems and portable electronic devices.

[0004] However, there are few related technical solutions at present, and the principles of the few existing technical solutions are relatively complex and have high cost and power consumption, which is not conducive to the large-scale popularization and application of the input stage of the operational amplifier. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a power supply boosting technical solution for boosting the output of the power supply voltage and realizing the rail-to-rail capability of the input stage of the operational amplifier.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by the present application is as follows.

[0007] A time-interleaved charge pump internal power supply circuit, comprising:

[0008] A first control signal generation module generates a plurality of first control signals;

[0009] A second control signal generation module generates a plurality of second control signals;

[0010] a time-interleaved charge pump module, connected to the power supply voltage, each of the first control signals and each of the second control signals, to generate an output internal power supply using a time-interleaved structure, the internal power supply being greater than the power supply voltage;

[0011] a voltage follower module, connected to the time-interleaved charge pump module, to maintain the internal power supply stable and continuous during the alternate switching of the time-interleaved structure.

[0012] Optionally, the first control signal generating module is connected to a clock signal, and generates 7 non-overlapping first control signals according to the clock signal.

[0013] Optionally, the first control signal generating module includes 7 logic gates arranged in parallel, and the 7 logic gates have different time delays.

[0014] Optionally, the second control signal generating module includes a digital power supply generating unit and 4 switch level bootstrap units, the digital power supply generating unit is connected to a band gap reference voltage, the digital power supply generating unit generates an output digital power supply voltage, each of the switch level bootstrap units is connected to the digital power supply voltage and the power supply voltage, each of the switch level bootstrap units generates an output second control signal, and 4 second control signals generated by the 4 switch level bootstrap units are non-overlapping.

[0015] Optionally, the digital power supply generating unit includes an operational amplifier, a first resistor and a second resistor, the non-inverting input terminal of the operational amplifier is connected to the band gap reference voltage, the inverting input terminal of the operational amplifier is connected to ground through the first resistor in series, and the inverting input terminal of the operational amplifier is also connected to the output terminal of the operational amplifier through the second resistor in series, and the output terminal of the operational amplifier outputs the digital power supply voltage.

[0016] Optionally, the switch level bootstrap unit includes a digital switch, a first NMOS transistor, a second NMOS transistor, a first capacitor and a second capacitor, the drain of the first NMOS transistor is connected to the power supply voltage, the source of the first NMOS transistor is connected to one end of the first capacitor, the other end of the first capacitor is connected to the input terminal of the digital switch, the power supply terminal of the digital switch is connected to the digital power supply voltage, the output terminal of the digital switch is connected to one end of the second capacitor, the other end of the second capacitor is connected to the source of the second NMOS transistor, the source of the second NMOS transistor is also connected to the gate of the first NMOS transistor, the gate of the second NMOS transistor is connected to the source of the first NMOS transistor, the drain of the second NMOS transistor is connected to the power supply voltage, and the second capacitor outputs the second control signal from one end of the source of the second NMOS transistor.

[0017] Optionally, the digital switch comprises a NOT gate.

[0018] Optionally, the time-interleaved charge pump module comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a current source, a third capacitor, a fourth capacitor, and a fifth capacitor, a source of the first PMOS transistor is connected to the power supply voltage, a gate of the first PMOS transistor is connected to a drain of the first PMOS transistor, a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, a gate of the second PMOS transistor is connected to a first first control signal, a drain of the second PMOS transistor is connected to ground through the current source in series, a source of the third PMOS transistor is connected to the power supply voltage, a gate of the third PMOS transistor is connected to a drain of the second PMOS transistor, a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor, a gate of the third NMOS transistor is connected to a first second control signal, a source of the third NMOS transistor is connected to a source of the fourth PMOS transistor, a gate of the fourth PMOS transistor is connected to a second second control signal, a drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, a gate of the fourth NMOS transistor is connected to a third second control signal, a source of the fourth NMOS transistor is connected to a source of the fifth PMOS transistor, a gate of the fifth PMOS transistor is connected to a fourth second control signal, a drain of the fifth PMOS transistor is connected to a drain of the fourth PMOS transistor, a source of the sixth PMOS transistor is connected to the power supply voltage, a gate of the sixth PMOS transistor is connected to a bias voltage, a drain of the sixth PMOS transistor is connected to a source of the seventh PMOS transistor, a gate of the seventh PMOS transistor is connected to a second first control signal, a drain of the seventh PMOS transistor is connected to a drain of the fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to a third first control signal, a source of the fifth NMOS transistor is connected to ground, a source of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor, a gate of the eighth PMOS transistor is connected to a fourth first control signal, a drain of the eighth PMOS transistor is connected to a drain of the sixth NMOS transistor, a gate of the sixth NMOS transistor is connected to a fifth first control signal, a source of the sixth NMOS transistor is connected to ground, a drain of the ninth PMOS transistor is connected to the drain of the fifth NMOS transistor, a gate of the ninth PMOS transistor is connected to a sixth first control signal, a drain of the tenth PMOS transistor is connected to the drain of the sixth NMOS transistor, a gate of the tenth PMOS transistor is connected to a seventh first control signal, a source of the tenth PMOS transistor is connected to a source of the ninth PMOS transistor, one end of the third capacitor is connected to a source of the third NMOS transistor, the other end of the third capacitor is connected to a drain of the fifth NMOS transistor,One end of the fourth capacitor is connected to the source of the fourth NMOS tube, the other end of the fourth capacitor is connected to the drain of the sixth NMOS tube, one end of the fifth capacitor is connected to the drain of the fourth PMOS tube, the drain of the fourth PMOS tube outputs the internal power supply, and the other end of the fifth capacitor is connected to the power supply voltage.

[0019] Optionally, the time-interleaved charge pump internal power supply generation circuit further comprises a third resistor, a power supply end of the voltage follower module is connected to the power supply voltage, an input end of the voltage follower module is connected to the drain of the sixth PMOS tube, a feedback end of the voltage follower module is connected to the source of the ninth PMOS tube, and an output end of the voltage follower module follows the output of the internal power supply after the third resistor in series.

[0020] As described above, the time-interleaved charge pump internal power supply generation circuit provided by the application has at least the following beneficial effects:

[0021] By the time-interleaved charge pump module, the internal power supply which is stable and greater than the power supply voltage is alternately generated in each cycle, and the power supply voltage is output after being boosted, so that the rail-to-rail input of the subsequent operational amplifier can be effectively realized; by the voltage follower module, the internal power supply is kept stable and continuous when the time-interleaved charge pump module is alternately switched, so that the stability of the internal power supply is improved, and the voltage fluctuation of the internal power supply is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 FIG. 1 is a circuit structure diagram of a time-interleaved charge pump internal power supply generation circuit in the application.

[0023] Figure 2 FIG. 2 is a structure schematic diagram of a first control signal generation module in the application. Figure 1

[0024] FIG. 3 is a structure schematic diagram of a second control signal generation module in the application. Figure 3 Figure 1 FIG. 4 is a circuit structure diagram of a digital power supply generation unit in the application.

[0025] Figure 4 Figure 1 FIG. 5 is a circuit structure diagram of a switch level bootstrap unit in the application.

[0026] Figure 5 FIG. 6 is a circuit structure diagram of a time-interleaved charge pump module in the application. Figure 1 DETAILED DESCRIPTION

[0027] ​​​Following, the embodiments of the present application are described through specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art according to the disclosure. The present application can also be implemented or applied through other different embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0028] Please refer to Figures 1 to 5 . It is noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and thus only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The shapes, number and proportions of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complicated. The structures, proportions and sizes shown in the diagrams attached to the specification are only used to understand and read the disclosure by those skilled in the art, and do not limit the conditions under which the present application can be implemented. Therefore, any modification of the structure, change of the proportional relationship or adjustment of the size, which does not affect the effects and purposes of the present application, should still fall within the scope of the disclosed technology.

[0029] As shown in Figure 1 , the present application provides a power generation circuit in a time-interleaved charge pump, which comprises:

[0030] a first control signal generation module for generating and outputting first control signals D1-D7;

[0031] a second control signal generation module for generating and outputting second control signals C1-C4;

[0032] a time-interleaved charge pump module connected to the power supply voltage, the first control signals D1-D7 and the second control signals C1-C4, and configured to generate and output an internal power supply V3 using a time-interleaved structure, wherein the internal power supply V3 is greater than the power supply voltage;

[0033] a voltage follower module connected to the time-interleaved charge pump module, and configured to keep the internal power supply V3 stable and continuous during the alternate switching of the time-interleaved structure.

[0034] In detail, as shown in Figures 1 to 2 , the first control signal generation module is connected to a clock signal CLK, and generates and outputs seven non-overlapping first control signals D1-D7 according to the clock signal CLK.

[0035] In an optional embodiment of the present application, the first control signal generating module comprises seven logic gates arranged in parallel, which can be NOR gates, NAND gates or other logic gates. The input ends of the seven logic gates are connected to the clock signal CLK respectively. The output ends of the seven logic gates output one first control signal (square wave) respectively. The time delays of the seven logic gates are different, so that seven non-overlapping first control signals D1-D7 (D1, D2, D3, D4, D5, D6 and D7) are obtained.

[0036] In detail, as shown in Figure 1 , Figures 3-4 , the second control signal generating module comprises a digital power supply generating unit and four switch level bootstrap units. The digital power supply generating unit is connected to the band gap reference voltage V1. The digital power supply generating unit generates an output digital power supply voltage V2. The switch level bootstrap units are connected to the digital power supply voltage V2 and the power supply voltage VDD. Each of the switch level bootstrap units generates one second control signal. The four switch level bootstrap units generate four non-overlapping second control signals C1-C4 (C1, C2, C3 and C4).

[0037] In more detail, as shown in Figure 3 , the digital power supply generating unit comprises an operational amplifier A1, a first resistor R1 and a second resistor R2. The non-inverting input end of the operational amplifier A1 is connected to the band gap reference voltage V1. The inverting input end of the operational amplifier A1 is connected to the ground through the first resistor R1 in series. The inverting input end of the operational amplifier A1 is also connected to the output end of the operational amplifier A1 through the second resistor R2 in series. The output end of the operational amplifier A1 outputs the digital power supply voltage V2.

[0038] In more detail, as shown in Figure 4 , the switch level bootstrap unit comprises a digital switch, a first NMOS transistor N1, a second NMOS transistor N2, a first capacitor C1 and a second capacitor C2. The drain of the first NMOS transistor N1 is connected to the power supply voltage VDD. The source of the first NMOS transistor N1 is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the input end of the digital switch. The power supply end of the digital switch is connected to the digital power supply voltage V2. The enable end of the digital switch is connected to the enable signal ENP. The output end of the digital switch is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the source of the second NMOS transistor N2. The source of the second NMOS transistor N2 is also connected to the gate of the first NMOS transistor N1. The gate of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1. The drain of the second NMOS transistor N2 is connected to the power supply voltage VDD. The second capacitor C2 outputs the second control signal Cj (j is 1-4) from one end of the source of the second NMOS transistor N2.

[0039] The digital switch includes a NOT gate, the input end of which is logically negated with the output end, the low level is 0, and the high level is a digital power supply voltage V2. The digital switch can also include other buffers and delay units, so that the time delay of the digital switch in each switch level bootstrap unit is different, which is not limited herein.

[0040] In more detail, as shown in Figure 4 , the working principle of the single switch level bootstrap unit is as follows:

[0041] When the input end of the digital switch is at a high level, the gate of the first NMOS tube N1 is at a low level, and the source is at a high level, the first NMOS tube N1 is cut off, the gate of the second NMOS tube N2 is at a high level, and the source is at a low level, the second NMOS tube N2 is turned on, and the second capacitor C2 is charged to VDD; when the input end of the digital switch is at a low level, the gate of the first NMOS tube N1 is at a high level, and the source is at a low level, the first NMOS tube N1 is turned on, the gate of the second NMOS tube N2 is at a low level, and the source is at a high level, the second NMOS tube N2 is cut off, and the first capacitor C1 is charged to VDD; at this time, the second capacitor C2 is charged to VDD in the last clock cycle, and the voltage on the second capacitor C2 cannot change abruptly, so when the low end voltage is at a high level (i.e. the digital power supply voltage V2), the high end voltage becomes VDD+V2; therefore, the high end voltage of the second capacitor C2 is VDD or VDD+V2, that is, the second control signal Cj output by the switch level bootstrap unit is a square wave signal of VDD~VDD+V2.

[0042] In more detail, as shown in Figure 1 and Figure 5 , the time-interleaved charge pump module includes a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P 10, current source I1, third capacitor C3, fourth capacitor C4 and fifth capacitor C5, source of first PMOS P1 connects to power voltage VDD, gate of first PMOS P1 connects to drain of first PMOS P1, drain of first PMOS P1 connects to source of second PMOS P2, gate of second PMOS P2 connects to first first control signal D1, drain of second PMOS P2 connects to ground through current source I1 in series, source of third PMOS P3 connects to power voltage VDD, gate of third PMOS P3 connects to drain of second PMOS P2, drain of third PMOS P3 connects to drain of third NMOS N3, gate of third NMOS N3 connects to first second control signal C1, source of third NMOS N3 connects to source of fourth PMOS P4, gate of fourth PMOS P4 connects to second second control signal C2, drain of fourth NMOS N4 connects to drain of third NMOS N3, gate of fourth NMOS N4 connects to third second control signal C3, source of fourth NMOS N4 connects to source of fifth PMOS P5, gate of fifth PMOS P5 connects to fourth second control signal C4, drain of fifth PMOS P5 connects to drain of fourth PMOS P4, source of sixth PMOS P6 connects to power voltage VDD, gate of sixth PMOS P6 connects to bias voltage Vbais, drain of sixth PMOS P6 connects to source of seventh PMOS P7, gate of seventh PMOS P7 connects to second first control signal D2, drain of seventh PMOS P7 connects to drain of fifth NMOS N5, gate of fifth NMOS N5 connects to third first control signal D3, source of fifth NMOS N5 connects to ground, source of eighth PMOS P8 connects to source of seventh PMOS P7, gate of eighth PMOS P8 connects to fourth first control signal D4, drain of eighth PMOS P8 connects to drain of sixth NMOS N6, gate of sixth NMOS N6 connects to fifth first control signal D5, source of sixth NMOS N6 connects to ground, drain of ninth PMOS P9 connects to drain of fifth NMOS N5, gate of ninth PMOS P9 connects to sixth first control signal D6, drain of tenth PMOS P 10 , gate of tenth PMOS P 10 connects to seventh first control signal D7, drain of tenth PMOS P 10The source of the ninth PMOS transistor P9 is connected to the source of the first NMOS transistor Nl, one end of the first capacitor C1 is connected to the source of the second NMOS transistor N2, the other end of the first capacitor C1 is connected to the drain of the third NMOS transistor N3, one end of the second capacitor C2 is connected to the source of the third NMOS transistor N3, the other end of the second capacitor C2 is connected to the drain of the fourth NMOS transistor N4, one end of the third capacitor C3 is connected to the source of the fourth NMOS transistor N4, the other end of the third capacitor C3 is connected to the drain of the fifth NMOS transistor N5, one end of the fourth capacitor C4 is connected to the source of the fifth NMOS transistor N5, the other end of the fourth capacitor C4 is connected to the drain of the sixth NMOS transistor N6, one end of the fifth capacitor C5 is connected to the drain of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6 outputs the internal power supply V3, the other end of the fifth capacitor C5 is connected to the power supply voltage VDD.

[0043] In detail, as shown in Figure 5 , the time-interleaved charge pump internal power supply generating circuit further comprises a third resistor R3, the power supply end of the voltage follower module is connected to the power supply voltage VDD, the input end of the voltage follower module is connected to the drain of the sixth PMOS transistor P6, the feedback end of the voltage follower module is connected to the source of the ninth PMOS transistor P9, and the output end of the voltage follower module is connected to follow the output of the internal power supply V3 after the third resistor R3 is connected in series.

[0044] In more detail, as shown in Figure 5 , the working principle of the time-interleaved charge pump module is as follows:

[0045] 1) On the premise that the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the sixth PMOS transistor P6 are turned on, first turn on the third NMOS transistor N3 and the fifth NMOS transistor N5, and turn off the fourth PMOS transistor P4 and the seventh PMOS transistor P7, so that the third capacitor C3 is charged to VDD; then turn off the third NMOS transistor N3 and the fifth NMOS transistor N5, and turn on the fourth PMOS transistor P4 and the seventh PMOS transistor P7, so that the lower plate potential of the third capacitor C3 becomes V0, the amplitude of the power supply voltage VDD is boosted at the upper plate of the third capacitor C3, and the internal power supply V3 = V0 + VDD is obtained, and the internal power supply V3 is externally output under the control of the fourth PMOS transistor P4;

[0046] 2) Similarly, on the premise that the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the sixth PMOS transistor P6 are turned on, first turn on the fourth NMOS transistor N4 and the sixth NMOS transistor N6, and turn off the fifth PMOS transistor P5 and the eighth PMOS transistor P8, so that the fourth capacitor C4 is charged to VDD; then turn off the fourth NMOS transistor N4 and the sixth NMOS transistor N6, and turn on the fifth PMOS transistor P5 and the eighth PMOS transistor P8, so that the lower plate potential of the fourth capacitor C4 becomes V0, the amplitude of the power supply voltage VDD is boosted at the upper plate of the fourth capacitor C4, and the internal power supply V3 = V0 + VDD is obtained, and the internal power supply V3 is externally output under the control of the fifth PMOS transistor P5;

[0047] 3), the third NMOS tube N3, the fifth NMOS tube N5, the fourth PMOS tube P4, the seventh PMOS tube P7 and the third capacitor C3 constitute half of the time interleaving structure, the fourth NMOS tube N4, the sixth NMOS tube N6, the fifth PMOS tube P5, the eighth PMOS tube P8 and the fourth capacitor C4 constitute the other half of the time interleaving structure, through the time interleaving structure, the power supply voltage VDD is stably and continuously amplified in a clock cycle, the internal power supply V3=V0+VDD is obtained, and is alternately outputted outside under the control of the fourth PMOS tube P4 and the fifth PMOS tube P5;

[0048] 4), the ninth PMOS tube P9 is only temporarily turned on when the fifth NMOS tube N5 and the seventh PMOS tube P7 are switched, and a unit gain feedback is formed with the auxiliary operational amplifier in the voltage follower module, so that the lower plate voltage of the third capacitor C3 is continuous and does not jump. 10 The tenth PMOS tube P Only temporarily turned on when the sixth NMOS tube N6 and the eighth PMOS tube P8 are switched, and a unit gain feedback is formed with the auxiliary operational amplifier in the voltage follower module, so that the lower plate voltage of the fourth capacitor C4 is continuous and does not jump.

[0049] 5), the second NMOS tube N2 controls the current source I1 to gradually turn on and charge the corresponding capacitor (the third capacitor C3 or the fourth capacitor C4) only when any one of the third NMOS tube N3 and the fourth NMOS tube N4 is turned on, and when the third NMOS tube N3 and the fourth NMOS tube N4 are closed at the same time, the current source I1 is also closed, so that the charging current is not too large and large glitches are caused.

[0050] Wherein, the specific value of V0 is determined by the size of the bias voltage Vbais, the parameters of the sixth PMOS tube P6 and the parameters of the seventh PMOS tube P7, which is not limited here.

[0051] It should be noted that the specific device structure of the entire circuit can be realized based on a conventional CMOS process, which will not be described here.

[0052] In summary, the time interleaving charge pump internal power supply generating circuit of the application can alternately generate an internal power supply that is stable and greater than the power supply voltage in each cycle through the time interleaving charge pump module, and the power supply voltage is outputted after being boosted, which can effectively realize the rail-to-rail input of the subsequent operational amplifier; The feedback formed by the voltage follower module keeps the internal power supply stable and continuous when the time interleaving charge pump module is alternately switched, improves the stability of the internal power supply, and reduces the voltage jump of the internal power supply.

[0053] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A time-interleaved charge pump internal power generation circuit, characterized in that: include: A first control signal generating module generates and outputs a plurality of first control signals; A second control signal generating module generates and outputs a plurality of second control signals; a time-interleaved charge pump module, connected to a power supply voltage, each of the first control signals, and each of the second control signals, and generating an output internal power supply using a time-interleaved structure, wherein the internal power supply is greater than the power supply voltage; a voltage follower module connected to the time-interleaved charge pump module to ensure that the internal power supply remains stable and continuous during the alternating switching of the time-interleaved structure; The time-interleaved charge pump module includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a current source, a third capacitor, a fourth capacitor, and a fifth capacitor. The source of the first PMOS transistor is connected to the power supply voltage, the gate of the first PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is connected to the first of the first control signals, and the second The drain of the PMOS tube is connected to ground after being connected in series with the current source, the source of the third PMOS tube is connected to the power supply voltage, the gate of the third PMOS tube is connected to the drain of the second PMOS tube, the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the first second control signal, the source of the third NMOS tube is connected to the source of the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the second second control signal, the drain of the fourth NMOS tube is connected to the drain of the third NMOS tube, the gate of the fourth NMOS tube is connected to the third second control signal, the source of the fourth NMOS tube is connected to the source of the fifth PMOS tube, and the The gate of the fifth PMOS tube is connected to the fourth second control signal, the drain of the fifth PMOS tube is connected to the drain of the fourth PMOS tube, the source of the sixth PMOS tube is connected to the power supply voltage, the gate of the sixth PMOS tube is connected to the bias voltage, the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the seventh PMOS tube is connected to the second first control signal, the drain of the seventh PMOS tube is connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is connected to the third first control signal, the source of the fifth NMOS tube is grounded, the source of the eighth PMOS tube is connected to the source of the seventh PMOS tube, and the gate of the eighth PMOS tube is connected to the fourth a first control signal, the drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the fifth first control signal, the source of the sixth NMOS transistor is grounded, the drain of the ninth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the ninth PMOS transistor is connected to the sixth first control signal, the drain of the tenth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the tenth PMOS transistor is connected to the seventh first control signal, the source of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor, one end of the third capacitor is connected to the source of the third NMOS transistor, and the other end of the third capacitor is connected to the drain of the fifth NMOS transistor.One end of the fourth capacitor is connected to the source of the fourth NMOS transistor, and the other end of the fourth capacitor is connected to the drain of the sixth NMOS transistor. One end of the fifth capacitor is connected to the drain of the fourth PMOS transistor, the drain of the fourth PMOS transistor outputs the internal power supply, and the other end of the fifth capacitor is connected to the power supply voltage.

2. The time-interleaved charge pump internal power generation circuit according to claim 1, wherein: The first control signal generating module receives a clock signal and generates and outputs seven non-overlapping first control signals according to the clock signal.

3. The time-interleaved charge pump internal power generation circuit according to claim 2, wherein: The first control signal generating module includes 7 logic gates arranged in parallel, and the 7 logic gates have different time delays.

4. The time-interleaved charge pump internal power generation circuit according to claim 2, wherein: The second control signal generating module includes a digital power supply generating unit and four switching level bootstrap units. The digital power supply generating unit is connected to a bandgap reference voltage. The digital power supply generating unit generates and outputs a digital power supply voltage. The switching level bootstrap unit is connected to the digital power supply voltage and the power supply voltage. Each of the switching level bootstrap units generates and outputs one second control signal, and the four second control signals generated and output by the four switching level bootstrap units do not overlap.

5. The time-interleaved charge pump internal power generation circuit according to claim 4, wherein: The digital power generation unit includes an operational amplifier, a first resistor, and a second resistor. The non-inverting input of the operational amplifier is connected to the bandgap reference voltage, the inverting input of the operational amplifier is connected to ground via the first resistor connected in series, and the inverting input of the operational amplifier is further connected to the output of the operational amplifier via the second resistor connected in series. The output of the operational amplifier outputs the digital power voltage.

6. The time-interleaved charge pump internal power generation circuit according to claim 5, wherein: The switch level bootstrap unit includes a digital switch, a first NMOS transistor, a second NMOS transistor, a first capacitor, and a second capacitor. The drain of the first NMOS transistor is connected to the power supply voltage, the source of the first NMOS transistor is connected to one end of the first capacitor, the other end of the first capacitor is connected to the input end of the digital switch, the power supply end of the digital switch is connected to the digital power supply voltage, the output end of the digital switch is connected to one end of the second capacitor, the other end of the second capacitor is connected to the source of the second NMOS transistor, the source of the second NMOS transistor is also connected to the gate of the first NMOS transistor, the gate of the second NMOS transistor is connected to the source of the first NMOS transistor, the drain of the second NMOS transistor is connected to the power supply voltage, and the second capacitor is connected to one end of the source of the second NMOS transistor to output the second control signal.

7. The time-interleaved charge pump internal power generation circuit according to claim 6, wherein: The digital switch includes a NOT gate.

8. The time-interleaved charge pump internal power generation circuit according to claim 1, wherein: The power supply generating circuit in the time-interleaved charge pump also includes a third resistor, the power supply terminal of the voltage follower module is connected to the power supply voltage, the input terminal of the voltage follower module is connected to the drain of the sixth PMOS tube, the feedback terminal of the voltage follower module is connected to the source of the ninth PMOS tube, and the output terminal of the voltage follower module follows the output of the internal power supply after being connected in series with the third resistor.

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