Method and control circuit for reducing the switching regulator, and switching regulator circuit

Abstract

The present disclosure relates to reducing spurious noise by monotonic frequency stepping and compensating for error amplifier output under peak current mode switching regulators. Described herein is a switching regulator that can provide high current while operating at low noise and low spurs. The switching regulator can operate at varying switching frequencies. Spurs at the varying switching frequencies can be reduced by compensating an error amplifier that controls the switching frequency.

Description

[0001] Claiming priority

[0002] This patent application claims priority to U.S. Provisional Patent Application Serial No. 63 / 75,667, filed September 8, 2020, entitled “Reducing Stray Noise by Monotonic Frequency Stepping and Compensating the Output of an Error Amplifier in a Peak Current Mode Switching Regulator,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to power management, and more particularly to switching regulators (also known as switch-mode power converters) with reduced parasitic noise. Background Technology

[0004] Some applications (such as RF applications) require low noise and low spurious emissions from their power supply voltages while providing high current for high performance. A switching regulator is a type of power supply. A switching regulator can increase (e.g., a boost converter) or decrease (e.g., a buck converter) the input voltage of a power supply to the required voltage suitable for connecting a load device. For example, a switching regulator may include, among other things, two switches that alternately turn on and off to produce an output voltage at the desired voltage level. Switching occurs at the switching frequency. However, switching regulators with a fixed switching frequency can result in high spurious emissions at the switching frequency and its harmonics, leading to poor performance. Summary of the Invention

[0005] In one aspect, this disclosure relates to a method for spurious attenuation in a switching regulator, the method comprising: receiving an input signal at a switching regulator including a pair of switching devices; changing the switching frequency of the pair of switching devices; adjusting a compensation voltage to stabilize the compensation voltage by means of an increment value of the compensation voltage in response to the change in the switching frequency; and converting the input signal into an output voltage.

[0006] In one aspect, this disclosure relates to a switching regulator circuit comprising: a pair of switching devices receiving an input voltage; an inductor coupled to the pair of switching devices; a capacitor coupled to the inductor; an output node defining an output voltage; and control circuitry including an error amplifier and a summing node, subtracting an increment value from the output of the error amplifier to generate a compensation voltage, wherein the control circuitry adjusts the switching frequency of the pair of switching devices based on the compensation voltage.

[0007] In one aspect, the disclosure relates to a control circuit for reducing spurs in a switching regulator, the control circuit comprising: an error amplifier receiving an output voltage of the switching regulator; a summing node subtracting an increment value from an output of the error amplifier, thereby generating a compensation voltage; and a logic circuit generating a control signal to adjust a switching frequency of a pair of switching devices in the switching regulator based on the compensation voltage. BRIEF DESCRIPTION OF DRAWINGS

[0008] The various drawings of the attached drawings only show example embodiments of the disclosure and should not be considered limiting the scope thereof.

[0009] Figure 1 A spread spectrum with a triangular waveform associated with a switching regulator is illustrated.

[0010] Figure 2 An example portion of a switching regulator is illustrated.

[0011] Figure 3 Example waveforms of a compensation voltage and a switching frequency are illustrated.

[0012] Figure 4 Example waveforms of an increment compensation voltage and a switching frequency are illustrated.

[0013] Figure 5 Example waveforms of a switching frequency, a compensation voltage, and an output voltage are illustrated. DETAILED DESCRIPTION

[0014] Accordingly, the inventors recognized a need for a switching regulator that can provide high current while operating with low noise and low spurs. The switching regulator can operate at varying switching frequencies. Spurs at the varying switching frequencies can be reduced by compensating an amplifier that controls the switching frequency.

[0015] A method of spur attenuation in a switching regulator is described. The method comprises: receiving an input signal at a switching regulator, the switching regulator comprising a pair of switching devices; varying a switching frequency of the pair of switching devices; adjusting a compensation voltage by an increment value of the compensation voltage in response to the variation of the switching frequency to stabilize the compensation voltage; and converting the input signal to an output voltage.

[0016] A switching regulator circuit is also described. The switching regulator circuit comprises: a pair of switching devices receiving an input voltage; an inductor coupled to the pair of switching devices; a capacitor coupled to the inductor; an output node defining an output voltage; and a control circuit. The control circuit comprises: an error amplifier; and a summing node subtracting an increment value from an output of the error amplifier, thereby generating a compensation voltage. Based on the compensation voltage, the control circuit can adjust a switching frequency of the pair of switching devices.

[0017] The present disclosure also describes a control circuit for reducing spurs in a switching regulator. The control circuit includes an error amplifier that receives an output voltage of the switching regulator, a summing node that subtracts an increment value from an output of the error amplifier to produce a compensation voltage, and a logic circuit that generates a control signal based on the compensation voltage to adjust a switching frequency of a pair of switching devices in the switching regulator.

[0018] Figure 1 Spread spectrum with a triangular waveform associated with a switching regulator is illustrated. The triangular wave can have a switching frequency (f SW ) and a sweep frequency (f SF ). Monotonically and periodically varying the switching frequency (f SW ) can reduce spurs seen at the switching frequency (f SW ). But this reduction can come at the cost of increasing spurs at the sweep frequency (f SF ) in peak current mode of the switching regulator. This is because, for a peak current mode switching regulator, two negative loops are provided: 1) a current loop to regulate a coil current equal to a load current, and 2) a voltage loop to regulate an output voltage V OUT to a reference voltage. When the switching frequency (f SW ) changes and the load current is constant, the voltage loop can change a compensation voltage (Vcomp) to regulate the coil current. Since V OUT is in the voltage loop, V OUT is modulated with the sweep frequency. Thus, spurs at the sweep frequency (f SF ) can be induced.

[0019] As described herein, this spur can be reduced by compensating Vcomp by AVcomp in response to the switching frequency (f SW ) changing. Thus, the voltage loop can not change Vcomp, and thus V OUT may not be modulated with the sweep frequency (f SF ). Thus, spurs at the sweep frequency (f SF ) can be reduced or eliminated.

[0020] Figure 2 An example portion of a switching regulator 200 is illustrated. The switching regulator 200 can include a pair of switching devices 202, 204, an inductor 206 (L), and a capacitor 208 (Cout). The switching regulator 200 can also include a control circuit 210 to control a switching frequency (e.g., duty cycle) of the switching devices 202, 204. The control circuit 210 can include a resistor 212 (Ri), an error amplifier 214, a summing node 216, a comparator 218, and one or more logic circuits 220 (e.g., D flip-flops).

[0021] Switching devices 202, 204 can be provided as N-channel field effect transistors ("FETs"), P-channel FETs, metal oxide semiconductor FETs (MOSFETs), or combinations, etc. Input voltage V IN may be applied to the input of switching device 202. V IN may be a voltage at a first voltage level. The output of switching device 202 can be coupled to inductor L 106 and switching device 204, which can also be coupled to ground. Inductor L 206 can be coupled to capacitor 208, defining an output node for output voltage V OUT . The output node is also provided as a load resistor (Rload) at the output node.

[0022] The timing of switching devices 202, 204 can be controlled by control circuit 210, as described in more detail below. Control circuit 210 can alternately turn on and off switching devices 202, 204. For example, control circuit 210 can output a pulse width modulated signal to control when switching device 202 is turned on and off. Control circuit 210 can invert this pulse width modulated signal so that switching device 204 is turned on and off at opposite times from switching device 202. In other words, when switching device 202 is on, switching device 204 is off, and vice versa. The fast on / off duty cycle of switching devices 202, 204 can be used to control the value of V OUT . Switching devices 202, 204 can be provided as complementary pairs of transistor devices, for example, switching device 202 can be provided as a P-channel FET and switching device 204 can be provided as an N-channel FET, in which case control circuit 210 can not need to invert the control signal to alternate the timing of the switching devices.

[0023] Switching devices 202, 204 can generate a waveform and can be coupled to inductor L 206. Coil current Icoil can flow through inductor L 106. Inductor L 206 can be coupled to capacitor (Cout) 208, defining an output node for output voltage V OUT .

[0024] Control circuit 210 can be coupled to inductor L 206. An error amplifier can receive V OUT and reference voltage V REF as inputs. Error amplifier 214 can amplify V REF using reference voltage V OUT . The output of error amplifier 214 can be coupled to summing node 216, whose output is Vcomp. ΔVcomp can be coupled to summing node 216 as a negative input. Thus, Vcomp can be the difference between the output of the error amplifier and ΔVcomp.

[0025] The output of summing node 216 can be coupled to comparator 218, which can also be coupled to resistor Ri 212. Comparator 218 can compare Vcomp and Vcoil (Icoil * Ri). The output of comparator 216 can be provided as an input to logic gate 220. Based on the output of comparator 218 and the clock signal, the duty cycle (switching frequency) can be set by logic gate 220 (e.g., a D flip-flop).

[0026] Figure 3 The figure illustrates the relationship between Vcomp and the change in switching frequency. When the switching frequency (f...)... SW When it changes (e.g., from f) SW (n-1) to f SW ΔVcomp(n) may change ΔVcomp(n). Then, as described above, ΔVcomp can be subtracted from the output of the error amplifier.

[0027] ΔVcomp can be defined as:

[0028]

[0029] ΔVcomp=ΔVcomp0+ΔVcomp1+…+ΔVcompn

[0030] Figure 4 The diagram illustrates the relationship between ΔVcomp and the switching frequency (fSW). Figure 5 The diagram illustrates the switching frequency (f) using the technology described herein. SW Example waveforms for Vcomp and Vout are shown. As illustrated, Vcomp can be stabilized based on continuous ΔVcomp adjustments, as described in this article. This can lead to a reduction or elimination of low-frequency spurious signals.

[0031] Various annotations

[0032] Each of the above non-limiting aspects may exist independently or may be combined with one or more of the other aspects or other topics described in this document in various permutations or combinations.

[0033] The above detailed description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These implementations are generally also referred to as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples that provide only those elements shown or described. Furthermore, the inventors also contemplate examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described, or with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0034] If the use of terms in this document and any document incorporated by reference is inconsistent with the use of those terms in the present document, the use in the present document is intended as the controlling use.

[0035] In this document, the terms“a” or“an” are used, as is common in patent documents, to include one or more, independent of any other instances or usages of“at least one” or“one or more”. In this document, the term“or” is used to refer to a nonexclusive or, such that“A or B” includes“A but not B,”“B but not A,” and“A and B,” unless otherwise indicated. In this document, the terms“including” and“comprising” are used as the plain-English equivalents of the respective terms“including” and“comprising.” Also, in the following claims, the terms“including” and“comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms“first,”“second,”“third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0036] Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer- readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level languages code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, in an example, the code can be tangibly embodied in one or more volatile or non-volatile, tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disk drives, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, RAM, ROM, etc.

[0037] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other implementations can be utilized, such as would be apparent to one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to allow a quick determination of the disclosure's purpose. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together or described in a single implementation for the purpose of streamlining the disclosure. This should not be interpreted as intending that an unclaimed disclosure feature is essential to any claim. Rather, inventive subject matter can reside in less than all features of a specific disclosed implementation. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate implementation, and the scope of the application should be determined not with reference to the Abstract, but rather with reference to the claims and the full range of equivalents to which such claims are entitled.

Claims

1. A method for reducing spurs in a switching regulator, the method comprising: receiving an input signal at a switching regulator, the switching regulator comprising a pair of switching devices; converting the input signal to an output voltage based on a compensation voltage at a first time; changing a switching frequency of the pair of switching devices; in response to changing the switching frequency, adjusting the compensation voltage by: amplifying a difference between the output voltage and a reference voltage at the first time, thereby producing an error amplifier output; and subtracting an incremental value of the compensation voltage from the error amplifier output at the first time and a second time to stabilize an adjusted compensation voltage; and converting the input signal to the output voltage based on the adjusted compensation voltage at the second time.

2. The method of claim 1, further comprising: changing the switching frequency based on the adjusted compensation voltage.

3. The method of claim 1, further comprising: comparing the adjusted compensation voltage to a coil voltage; and changing the switching frequency by comparing the adjusted compensation voltage to the coil voltage.

4. The method of claim 3, wherein the coil voltage is associated with an inductance of the switching regulator.

5. The method of claim 1, wherein the adjusting of the compensation voltage is continuous.

6. A switching regulator circuit, comprising: a pair of switching devices that receive an input voltage and produce an output voltage based on a compensation voltage at a first time; an inductor coupled to the pair of switching devices; a capacitor coupled to the inductor that defines an output node of the output voltage; and a control circuit comprising: an error amplifier that amplifies a difference between the output voltage and a reference voltage at the first time, and a summing node that subtracts an incremental value of the compensation voltage from an output of the error amplifier at the first time and a second time, thereby producing an adjusted compensation voltage, wherein the control circuit adjusts a switching frequency of the pair of switching devices based on the compensation voltage, wherein the pair of switching devices converts the input voltage to the output voltage based on the adjusted compensation voltage at the second time.

7. The switching regulator circuit of claim 6, further comprising: a comparator that compares the compensation voltage to a coil voltage of the inductor.

8. The switching regulator circuit of claim 7, further comprising: a resistor that produces the coil voltage.

9. The switching regulator circuit of claim 6, wherein a logic gate controls adjusting the switching frequency.

10. The switching regulator circuit of claim 9, wherein the logic gate is a D flip-flop.

11. The switching regulator circuit of claim 9, wherein the logic gate receives a clock input.

12. The switching regulator circuit of claim 6, wherein the compensation voltage is adjusted in response to a change in the switching frequency.

13. A control circuit for reducing spurs in a switching regulator, the control circuit comprising: an error amplifier that receives an output voltage of the switching regulator and amplifies a difference between the output voltage and a reference voltage at a first time; ​ ​ ​ ​ a summing node that subtracts an incremental value of the compensation voltage from the output of the error amplifier at the first time and the second time, thereby generating an adjusted compensation voltage; and a logic gate that generates a control signal to adjust a switching frequency of a pair of switching devices in a switching regulator based on the compensation voltage, and controls the switching regulator to convert an input voltage to the output voltage based on the adjusted compensation voltage at the second time.

14. The control circuit of claim 13, further comprising: a comparator that compares the compensation voltage to a coil voltage associated with an inductor of the switching regulator.

15. The control circuit of claim 14, further comprising: a resistor that generates the coil voltage.

16. The control circuit of claim 13, wherein the logic gate is a D flip-flop.

17. The control circuit of claim 13, wherein the logic gate receives a clock input.

18. The control circuit of claim 13, wherein the compensation voltage is adjusted in response to a change in the switching frequency.

19. The control circuit of claim 13, wherein the compensation voltage is adjusted in a feedback loop.

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